1224110Sjchandra/*- 2224110Sjchandra * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3224110Sjchandra * reserved. 4224110Sjchandra * 5224110Sjchandra * Redistribution and use in source and binary forms, with or without 6224110Sjchandra * modification, are permitted provided that the following conditions are 7224110Sjchandra * met: 8224110Sjchandra * 9224110Sjchandra * 1. Redistributions of source code must retain the above copyright 10224110Sjchandra * notice, this list of conditions and the following disclaimer. 11224110Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 12224110Sjchandra * notice, this list of conditions and the following disclaimer in 13224110Sjchandra * the documentation and/or other materials provided with the 14224110Sjchandra * distribution. 15224110Sjchandra * 16224110Sjchandra * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17224110Sjchandra * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18224110Sjchandra * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19224110Sjchandra * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20224110Sjchandra * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21224110Sjchandra * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22224110Sjchandra * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23224110Sjchandra * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24224110Sjchandra * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25224110Sjchandra * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26224110Sjchandra * THE POSSIBILITY OF SUCH DAMAGE. 27224110Sjchandra * 28225394Sjchandra * NETLOGIC_BSD 29224110Sjchandra * $FreeBSD: releng/10.2/sys/mips/nlm/hal/cpucontrol.h 228271 2011-12-05 02:56:08Z jchandra $ 30225394Sjchandra */ 31224110Sjchandra 32225394Sjchandra#ifndef __NLM_HAL_CPUCONTROL_H__ 33227722Sjchandra#define __NLM_HAL_CPUCONTROL_H__ 34224110Sjchandra 35227722Sjchandra#define CPU_BLOCKID_IFU 0 36227722Sjchandra#define CPU_BLOCKID_ICU 1 37227722Sjchandra#define CPU_BLOCKID_IEU 2 38227722Sjchandra#define CPU_BLOCKID_LSU 3 39227722Sjchandra#define CPU_BLOCKID_MMU 4 40227722Sjchandra#define CPU_BLOCKID_PRF 5 41227722Sjchandra#define CPU_BLOCKID_SCH 7 42227722Sjchandra#define CPU_BLOCKID_SCU 8 43227722Sjchandra#define CPU_BLOCKID_FPU 9 44227722Sjchandra#define CPU_BLOCKID_MAP 10 45224110Sjchandra 46227722Sjchandra#define LSU_DEFEATURE 0x304 47228271Sjchandra#define LSU_DEBUG_ADDR 0x305 48228271Sjchandra#define LSU_DEBUG_DATA0 0x306 49227722Sjchandra#define LSU_CERRLOG_REGID 0x09 50227722Sjchandra#define SCHED_DEFEATURE 0x700 51224110Sjchandra 52225394Sjchandra/* Offsets of interest from the 'MAP' Block */ 53227722Sjchandra#define MAP_THREADMODE 0x00 54227722Sjchandra#define MAP_EXT_EBASE_ENABLE 0x04 55227722Sjchandra#define MAP_CCDI_CONFIG 0x08 56227722Sjchandra#define MAP_THRD0_CCDI_STATUS 0x0c 57227722Sjchandra#define MAP_THRD1_CCDI_STATUS 0x10 58227722Sjchandra#define MAP_THRD2_CCDI_STATUS 0x14 59227722Sjchandra#define MAP_THRD3_CCDI_STATUS 0x18 60227722Sjchandra#define MAP_THRD0_DEBUG_MODE 0x1c 61227722Sjchandra#define MAP_THRD1_DEBUG_MODE 0x20 62227722Sjchandra#define MAP_THRD2_DEBUG_MODE 0x24 63227722Sjchandra#define MAP_THRD3_DEBUG_MODE 0x28 64227722Sjchandra#define MAP_MISC_STATE 0x60 65227722Sjchandra#define MAP_DEBUG_READ_CTL 0x64 66227722Sjchandra#define MAP_DEBUG_READ_REG0 0x68 67227722Sjchandra#define MAP_DEBUG_READ_REG1 0x6c 68224110Sjchandra 69227722Sjchandra#define MMU_SETUP 0x400 70227722Sjchandra#define MMU_LFSRSEED 0x401 71227722Sjchandra#define MMU_HPW_NUM_PAGE_LVL 0x410 72227722Sjchandra#define MMU_PGWKR_PGDBASE 0x411 73227722Sjchandra#define MMU_PGWKR_PGDSHFT 0x412 74227722Sjchandra#define MMU_PGWKR_PGDMASK 0x413 75227722Sjchandra#define MMU_PGWKR_PUDSHFT 0x414 76227722Sjchandra#define MMU_PGWKR_PUDMASK 0x415 77227722Sjchandra#define MMU_PGWKR_PMDSHFT 0x416 78227722Sjchandra#define MMU_PGWKR_PMDMASK 0x417 79227722Sjchandra#define MMU_PGWKR_PTESHFT 0x418 80227722Sjchandra#define MMU_PGWKR_PTEMASK 0x419 81224110Sjchandra 82224110Sjchandra 83225394Sjchandra#if !defined(LOCORE) && !defined(__ASSEMBLY__) 84225394Sjchandra#if defined(__mips_n64) || defined(__mips_n32) 85225394Sjchandrastatic __inline uint64_t 86225394Sjchandranlm_mfcr(uint32_t reg) 87225394Sjchandra{ 88225394Sjchandra uint64_t res; 89224110Sjchandra 90225394Sjchandra __asm__ __volatile__( 91225394Sjchandra ".set push\n\t" 92225394Sjchandra ".set noreorder\n\t" 93225394Sjchandra "move $9, %1\n\t" 94225394Sjchandra ".word 0x71280018\n\t" /* mfcr $8, $9 */ 95225394Sjchandra "move %0, $8\n\t" 96225394Sjchandra ".set pop\n" 97225394Sjchandra : "=r" (res) : "r"(reg) 98225394Sjchandra : "$8", "$9" 99225394Sjchandra ); 100225394Sjchandra return (res); 101225394Sjchandra} 102224110Sjchandra 103225394Sjchandrastatic __inline void 104225394Sjchandranlm_mtcr(uint32_t reg, uint64_t value) 105225394Sjchandra{ 106225394Sjchandra __asm__ __volatile__( 107225394Sjchandra ".set push\n\t" 108225394Sjchandra ".set noreorder\n\t" 109225394Sjchandra "move $8, %0\n" 110225394Sjchandra "move $9, %1\n" 111225394Sjchandra ".word 0x71280019\n" /* mtcr $8, $9 */ 112225394Sjchandra ".set pop\n" 113225394Sjchandra : 114225394Sjchandra : "r" (value), "r" (reg) 115225394Sjchandra : "$8", "$9" 116225394Sjchandra ); 117225394Sjchandra} 118225394Sjchandra 119225394Sjchandra#else /* !(defined(__mips_n64) || defined(__mips_n32)) */ 120225394Sjchandra 121225394Sjchandrastatic __inline__ uint64_t 122225394Sjchandranlm_mfcr(uint32_t reg) 123225394Sjchandra{ 124225394Sjchandra uint32_t hi, lo; 125225394Sjchandra 126225394Sjchandra __asm__ __volatile__ ( 127225394Sjchandra ".set push\n" 128225394Sjchandra ".set mips64\n" 129225394Sjchandra "move $8, %2\n" 130225394Sjchandra ".word 0x71090018\n" 131225394Sjchandra "nop \n" 132225394Sjchandra "dsra32 %0, $9, 0\n" 133225394Sjchandra "sll %1, $9, 0\n" 134225394Sjchandra ".set pop\n" 135225394Sjchandra : "=r"(hi), "=r"(lo) 136225394Sjchandra : "r"(reg) : "$8", "$9"); 137225394Sjchandra 138225394Sjchandra return (((uint64_t)hi) << 32) | lo; 139225394Sjchandra} 140225394Sjchandra 141225394Sjchandrastatic __inline__ void 142225394Sjchandranlm_mtcr(uint32_t reg, uint64_t val) 143225394Sjchandra{ 144225394Sjchandra uint32_t hi, lo; 145225394Sjchandra 146225394Sjchandra hi = val >> 32; 147225394Sjchandra lo = val & 0xffffffff; 148225394Sjchandra 149225394Sjchandra __asm__ __volatile__ ( 150225394Sjchandra ".set push\n" 151225394Sjchandra ".set mips64\n" 152225394Sjchandra "move $9, %0\n" 153225394Sjchandra "dsll32 $9, %1, 0\n" 154225394Sjchandra "dsll32 $8, %0, 0\n" 155225394Sjchandra "dsrl32 $9, $9, 0\n" 156225394Sjchandra "or $9, $9, $8\n" 157225394Sjchandra "move $8, %2\n" 158225394Sjchandra ".word 0x71090019\n" 159225394Sjchandra "nop \n" 160225394Sjchandra ".set pop\n" 161225394Sjchandra : :"r"(hi), "r"(lo), "r"(reg) 162225394Sjchandra : "$8", "$9"); 163225394Sjchandra} 164225394Sjchandra#endif /* (defined(__mips_n64) || defined(__mips_n32)) */ 165225394Sjchandra 166225394Sjchandra/* hashindex_en = 1 to enable hash mode, hashindex_en=0 to disable 167225394Sjchandra * global_mode = 1 to enable global mode, global_mode=0 to disable 168225394Sjchandra * clk_gating = 0 to enable clock gating, clk_gating=1 to disable 169225394Sjchandra */ 170225394Sjchandrastatic __inline__ void nlm_mmu_setup(int hashindex_en, int global_mode, 171225394Sjchandra int clk_gating) 172225394Sjchandra{ 173225394Sjchandra uint32_t mmusetup = 0; 174225394Sjchandra 175225394Sjchandra mmusetup |= (hashindex_en << 13); 176225394Sjchandra mmusetup |= (clk_gating << 3); 177225394Sjchandra mmusetup |= (global_mode << 0); 178225394Sjchandra nlm_mtcr(MMU_SETUP, mmusetup); 179225394Sjchandra} 180225394Sjchandra 181225394Sjchandrastatic __inline__ void nlm_mmu_lfsr_seed (int thr0_seed, int thr1_seed, 182225394Sjchandra int thr2_seed, int thr3_seed) 183225394Sjchandra{ 184225394Sjchandra uint32_t seed = nlm_mfcr(MMU_LFSRSEED); 185225394Sjchandra 186225394Sjchandra seed |= ((thr3_seed & 0x7f) << 23); 187225394Sjchandra seed |= ((thr2_seed & 0x7f) << 16); 188225394Sjchandra seed |= ((thr1_seed & 0x7f) << 7); 189225394Sjchandra seed |= ((thr0_seed & 0x7f) << 0); 190225394Sjchandra nlm_mtcr(MMU_LFSRSEED, seed); 191225394Sjchandra} 192225394Sjchandra 193225394Sjchandra#endif /* __ASSEMBLY__ */ 194224110Sjchandra#endif /* __NLM_CPUCONTROL_H__ */ 195