bridge.h revision 224110 
1/*-
2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
3 * reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in
13 *    the documentation and/or other materials provided with the
14 *    distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/mips/nlm/hal/bridge.h 224110 2011-07-16 19:35:44Z jchandra $
29 * NETLOGIC_BSD */
30
31#ifndef __NLM_BRIDGE_H__
32#define __NLM_BRIDGE_H__
33
34/**
35* @file_name mio.h
36* @author Netlogic Microsystems
37* @brief Basic definitions of XLP memory and io subsystem
38*/
39
40/* BRIDGE specific registers */
41#define XLP_BRIDGE_MODE_REG			0x40
42#define XLP_BRIDGE_PCI_CFG_BASE_REG		0x41
43#define XLP_BRIDGE_PCI_CFG_LIMIT_REG		0x42
44#define XLP_BRIDGE_PCIE_CFG_BASE_REG		0x43
45#define XLP_BRIDGE_PCIE_CFG_LIMIT_REG		0x44
46#define XLP_BRIDGE_BUSNUM_BAR0_REG		0x45
47#define XLP_BRIDGE_BUSNUM_BAR1_REG		0x46
48#define XLP_BRIDGE_BUSNUM_BAR2_REG		0x47
49#define XLP_BRIDGE_BUSNUM_BAR3_REG		0x48
50#define XLP_BRIDGE_BUSNUM_BAR4_REG		0x49
51#define XLP_BRIDGE_BUSNUM_BAR5_REG		0x4a
52#define XLP_BRIDGE_BUSNUM_BAR6_REG		0x4b
53#define XLP_BRIDGE_FLASH_BAR0_REG		0x4c
54#define XLP_BRIDGE_FLASH_BAR1_REG		0x4d
55#define XLP_BRIDGE_FLASH_BAR2_REG		0x4e
56#define XLP_BRIDGE_FLASH_BAR3_REG		0x4f
57#define XLP_BRIDGE_FLASH_LIMIT0_REG		0x50
58#define XLP_BRIDGE_FLASH_LIMIT1_REG		0x51
59#define XLP_BRIDGE_FLASH_LIMIT2_REG		0x52
60#define XLP_BRIDGE_FLASH_LIMIT3_REG		0x53
61
62#define XLP_BRIDGE_DRAM_BAR_REG(i)		(0x54 + (i))
63#define XLP_BRIDGE_DRAM_BAR0_REG		0x54
64#define XLP_BRIDGE_DRAM_BAR1_REG		0x55
65#define XLP_BRIDGE_DRAM_BAR2_REG		0x56
66#define XLP_BRIDGE_DRAM_BAR3_REG		0x57
67#define XLP_BRIDGE_DRAM_BAR4_REG		0x58
68#define XLP_BRIDGE_DRAM_BAR5_REG		0x59
69#define XLP_BRIDGE_DRAM_BAR6_REG		0x5a
70#define XLP_BRIDGE_DRAM_BAR7_REG		0x5b
71
72#define XLP_BRIDGE_DRAM_LIMIT_REG(i)		(0x5c + (i))
73#define XLP_BRIDGE_DRAM_LIMIT0_REG		0x5c
74#define XLP_BRIDGE_DRAM_LIMIT1_REG		0x5d
75#define XLP_BRIDGE_DRAM_LIMIT2_REG		0x5e
76#define XLP_BRIDGE_DRAM_LIMIT3_REG		0x5f
77#define XLP_BRIDGE_DRAM_LIMIT4_REG		0x60
78#define XLP_BRIDGE_DRAM_LIMIT5_REG		0x61
79#define XLP_BRIDGE_DRAM_LIMIT6_REG		0x62
80#define XLP_BRIDGE_DRAM_LIMIT7_REG		0x63
81
82#define XLP_BRIDGE_DRAM_NODE_TRANSLN0_REG	0x64
83#define XLP_BRIDGE_DRAM_NODE_TRANSLN1_REG	0x65
84#define XLP_BRIDGE_DRAM_NODE_TRANSLN2_REG	0x66
85#define XLP_BRIDGE_DRAM_NODE_TRANSLN3_REG	0x67
86#define XLP_BRIDGE_DRAM_NODE_TRANSLN4_REG	0x68
87#define XLP_BRIDGE_DRAM_NODE_TRANSLN5_REG	0x69
88#define XLP_BRIDGE_DRAM_NODE_TRANSLN6_REG	0x6a
89#define XLP_BRIDGE_DRAM_NODE_TRANSLN7_REG	0x6b
90#define XLP_BRIDGE_DRAM_CHNL_TRANSLN0_REG	0x6c
91#define XLP_BRIDGE_DRAM_CHNL_TRANSLN1_REG	0x6d
92#define XLP_BRIDGE_DRAM_CHNL_TRANSLN2_REG	0x6e
93#define XLP_BRIDGE_DRAM_CHNL_TRANSLN3_REG	0x6f
94#define XLP_BRIDGE_DRAM_CHNL_TRANSLN4_REG	0x70
95#define XLP_BRIDGE_DRAM_CHNL_TRANSLN5_REG	0x71
96#define XLP_BRIDGE_DRAM_CHNL_TRANSLN6_REG	0x72
97#define XLP_BRIDGE_DRAM_CHNL_TRANSLN7_REG	0x73
98#define XLP_BRIDGE_PCIEMEM_BASE0_REG		0x74
99#define XLP_BRIDGE_PCIEMEM_BASE1_REG		0x75
100#define XLP_BRIDGE_PCIEMEM_BASE2_REG		0x76
101#define XLP_BRIDGE_PCIEMEM_BASE3_REG		0x77
102#define XLP_BRIDGE_PCIEMEM_LIMIT0_REG		0x78
103#define XLP_BRIDGE_PCIEMEM_LIMIT1_REG		0x79
104#define XLP_BRIDGE_PCIEMEM_LIMIT2_REG		0x7a
105#define XLP_BRIDGE_PCIEMEM_LIMIT3_REG		0x7b
106#define XLP_BRIDGE_PCIEIO_BASE0_REG		0x7c
107#define XLP_BRIDGE_PCIEIO_BASE1_REG		0x7d
108#define XLP_BRIDGE_PCIEIO_BASE2_REG		0x7e
109#define XLP_BRIDGE_PCIEIO_BASE3_REG		0x7f
110#define XLP_BRIDGE_PCIEIO_LIMIT0_REG		0x80
111#define XLP_BRIDGE_PCIEIO_LIMIT1_REG		0x81
112#define XLP_BRIDGE_PCIEIO_LIMIT2_REG		0x82
113#define XLP_BRIDGE_PCIEIO_LIMIT3_REG		0x83
114#define XLP_BRIDGE_PCIEMEM_BASE4_REG		0x84
115#define XLP_BRIDGE_PCIEMEM_BASE5_REG		0x85
116#define XLP_BRIDGE_PCIEMEM_BASE6_REG		0x86
117#define XLP_BRIDGE_PCIEMEM_LIMIT4_REG		0x87
118#define XLP_BRIDGE_PCIEMEM_LIMIT5_REG		0x88
119#define XLP_BRIDGE_PCIEMEM_LIMIT6_REG		0x89
120#define XLP_BRIDGE_PCIEIO_BASE4_REG		0x8a
121#define XLP_BRIDGE_PCIEIO_BASE5_REG		0x8b
122#define XLP_BRIDGE_PCIEIO_BASE6_REG		0x8c
123#define XLP_BRIDGE_PCIEIO_LIMIT4_REG		0x8d
124#define XLP_BRIDGE_PCIEIO_LIMIT5_REG		0x8e
125#define XLP_BRIDGE_PCIEIO_LIMIT6_REG		0x8f
126#define XLP_BRIDGE_NBU_EVENT_CNT_CTL_REG	0x90
127#define XLP_BRIDGE_EVNTCTR1_LOW_REG		0x91
128#define XLP_BRIDGE_EVNTCTR1_HI_REG		0x92
129#define XLP_BRIDGE_EVNT_CNT_CTL2_REG		0x93
130#define XLP_BRIDGE_EVNTCTR2_LOW_REG		0x94
131#define XLP_BRIDGE_EVNTCTR2_HI_REG		0x95
132#define XLP_BRIDGE_TRACEBUF_MATCH_REG0		0x96
133#define XLP_BRIDGE_TRACEBUF_MATCH_REG1		0x97
134#define XLP_BRIDGE_TRACEBUF_MATCH_LOW_REG	0x98
135#define XLP_BRIDGE_TRACEBUF_MATCH_HI_REG	0x99
136#define XLP_BRIDGE_TRACEBUF_CTRL_REG		0x9a
137#define XLP_BRIDGE_TRACEBUF_INIT_REG		0x9b
138#define XLP_BRIDGE_TRACEBUF_ACCESS_REG		0x9c
139#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG0	0x9d
140#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG1	0x9d
141#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG2	0x9f
142#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG3	0xa0
143#define XLP_BRIDGE_TRACEBUF_STATUS_REG		0xa1
144#define XLP_BRIDGE_ADDRESS_ERROR0_REG		0xa2
145#define XLP_BRIDGE_ADDRESS_ERROR1_REG		0xa3
146#define XLP_BRIDGE_ADDRESS_ERROR2_REG		0xa4
147#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR0_REG	0xa5
148#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR1_REG	0xa6
149#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR2_REG	0xa7
150#define XLP_BRIDGE_LINE_FLUSH_REG0		0xa8
151#define XLP_BRIDGE_LINE_FLUSH_REG1		0xa9
152#define XLP_BRIDGE_NODE_ID_REG			0xaa
153#define XLP_BRIDGE_ERROR_INTERRUPT_EN_REG	0xab
154#define XLP_BRIDGE_PCIE0_WEIGHT_REG		0x300
155#define XLP_BRIDGE_PCIE1_WEIGHT_REG		0x301
156#define XLP_BRIDGE_PCIE2_WEIGHT_REG		0x302
157#define XLP_BRIDGE_PCIE3_WEIGHT_REG		0x303
158#define XLP_BRIDGE_USB_WEIGHT_REG		0x304
159#define XLP_BRIDGE_NET_WEIGHT_REG		0x305
160#define XLP_BRIDGE_POE_WEIGHT_REG		0x306
161#define XLP_BRIDGE_CMS_WEIGHT_REG		0x307
162#define XLP_BRIDGE_DMAENG_WEIGHT_REG		0x308
163#define XLP_BRIDGE_SEC_WEIGHT_REG		0x309
164#define XLP_BRIDGE_COMP_WEIGHT_REG		0x30a
165#define XLP_BRIDGE_GIO_WEIGHT_REG		0x30b
166#define XLP_BRIDGE_FLASH_WEIGHT_REG		0x30c
167
168#if !defined(LOCORE) && !defined(__ASSEMBLY__)
169
170#define nlm_rdreg_bridge(b, r)		nlm_read_reg_kseg(b, r)
171#define nlm_wreg_bridge(b, r, v)	nlm_write_reg_kseg(b, r, v)
172#define	nlm_pcibase_bridge(node)	nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
173#define	nlm_regbase_bridge(node)	nlm_pcibase_bridge(node)
174
175#endif
176
177#endif
178