bridge.h revision 225394
1224110Sjchandra/*- 2224110Sjchandra * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3224110Sjchandra * reserved. 4224110Sjchandra * 5224110Sjchandra * Redistribution and use in source and binary forms, with or without 6224110Sjchandra * modification, are permitted provided that the following conditions are 7224110Sjchandra * met: 8224110Sjchandra * 9224110Sjchandra * 1. Redistributions of source code must retain the above copyright 10224110Sjchandra * notice, this list of conditions and the following disclaimer. 11224110Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 12224110Sjchandra * notice, this list of conditions and the following disclaimer in 13224110Sjchandra * the documentation and/or other materials provided with the 14224110Sjchandra * distribution. 15224110Sjchandra * 16224110Sjchandra * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17224110Sjchandra * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18224110Sjchandra * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19224110Sjchandra * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20224110Sjchandra * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21224110Sjchandra * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22224110Sjchandra * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23224110Sjchandra * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24224110Sjchandra * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25224110Sjchandra * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26224110Sjchandra * THE POSSIBILITY OF SUCH DAMAGE. 27224110Sjchandra * 28225394Sjchandra * NETLOGIC_BSD 29224110Sjchandra * $FreeBSD: head/sys/mips/nlm/hal/bridge.h 225394 2011-09-05 10:45:29Z jchandra $ 30225394Sjchandra */ 31224110Sjchandra 32225394Sjchandra#ifndef __NLM_HAL_BRIDGE_H__ 33225394Sjchandra#define __NLM_HAL_BRIDGE_H__ 34224110Sjchandra 35224110Sjchandra/** 36224110Sjchandra* @file_name mio.h 37224110Sjchandra* @author Netlogic Microsystems 38224110Sjchandra* @brief Basic definitions of XLP memory and io subsystem 39224110Sjchandra*/ 40224110Sjchandra 41225394Sjchandra/* 42225394Sjchandra * BRIDGE specific registers 43225394Sjchandra * 44225394Sjchandra * These registers start after the PCIe header, which has 0x40 45225394Sjchandra * standard entries 46225394Sjchandra */ 47225394Sjchandra#define BRIDGE_MODE 0x00 48225394Sjchandra#define BRIDGE_PCI_CFG_BASE 0x01 49225394Sjchandra#define BRIDGE_PCI_CFG_LIMIT 0x02 50225394Sjchandra#define BRIDGE_PCIE_CFG_BASE 0x03 51225394Sjchandra#define BRIDGE_PCIE_CFG_LIMIT 0x04 52225394Sjchandra#define BRIDGE_BUSNUM_BAR0 0x05 53225394Sjchandra#define BRIDGE_BUSNUM_BAR1 0x06 54225394Sjchandra#define BRIDGE_BUSNUM_BAR2 0x07 55225394Sjchandra#define BRIDGE_BUSNUM_BAR3 0x08 56225394Sjchandra#define BRIDGE_BUSNUM_BAR4 0x09 57225394Sjchandra#define BRIDGE_BUSNUM_BAR5 0x0a 58225394Sjchandra#define BRIDGE_BUSNUM_BAR6 0x0b 59225394Sjchandra#define BRIDGE_FLASH_BAR0 0x0c 60225394Sjchandra#define BRIDGE_FLASH_BAR1 0x0d 61225394Sjchandra#define BRIDGE_FLASH_BAR2 0x0e 62225394Sjchandra#define BRIDGE_FLASH_BAR3 0x0f 63225394Sjchandra#define BRIDGE_FLASH_LIMIT0 0x10 64225394Sjchandra#define BRIDGE_FLASH_LIMIT1 0x11 65225394Sjchandra#define BRIDGE_FLASH_LIMIT2 0x12 66225394Sjchandra#define BRIDGE_FLASH_LIMIT3 0x13 67224110Sjchandra 68225394Sjchandra#define BRIDGE_DRAM_BAR(i) (0x14 + (i)) 69225394Sjchandra#define BRIDGE_DRAM_BAR0 0x14 70225394Sjchandra#define BRIDGE_DRAM_BAR1 0x15 71225394Sjchandra#define BRIDGE_DRAM_BAR2 0x16 72225394Sjchandra#define BRIDGE_DRAM_BAR3 0x17 73225394Sjchandra#define BRIDGE_DRAM_BAR4 0x18 74225394Sjchandra#define BRIDGE_DRAM_BAR5 0x19 75225394Sjchandra#define BRIDGE_DRAM_BAR6 0x1a 76225394Sjchandra#define BRIDGE_DRAM_BAR7 0x1b 77224110Sjchandra 78225394Sjchandra#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) 79225394Sjchandra#define BRIDGE_DRAM_LIMIT0 0x1c 80225394Sjchandra#define BRIDGE_DRAM_LIMIT1 0x1d 81225394Sjchandra#define BRIDGE_DRAM_LIMIT2 0x1e 82225394Sjchandra#define BRIDGE_DRAM_LIMIT3 0x1f 83225394Sjchandra#define BRIDGE_DRAM_LIMIT4 0x20 84225394Sjchandra#define BRIDGE_DRAM_LIMIT5 0x21 85225394Sjchandra#define BRIDGE_DRAM_LIMIT6 0x22 86225394Sjchandra#define BRIDGE_DRAM_LIMIT7 0x23 87224110Sjchandra 88225394Sjchandra#define BRIDGE_DRAM_NODE_TRANSLN0 0x24 89225394Sjchandra#define BRIDGE_DRAM_NODE_TRANSLN1 0x25 90225394Sjchandra#define BRIDGE_DRAM_NODE_TRANSLN2 0x26 91225394Sjchandra#define BRIDGE_DRAM_NODE_TRANSLN3 0x27 92225394Sjchandra#define BRIDGE_DRAM_NODE_TRANSLN4 0x28 93225394Sjchandra#define BRIDGE_DRAM_NODE_TRANSLN5 0x29 94225394Sjchandra#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a 95225394Sjchandra#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b 96225394Sjchandra#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c 97225394Sjchandra#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d 98225394Sjchandra#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e 99225394Sjchandra#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f 100225394Sjchandra#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30 101225394Sjchandra#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 102225394Sjchandra#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 103225394Sjchandra#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 104225394Sjchandra#define BRIDGE_PCIEMEM_BASE0 0x34 105225394Sjchandra#define BRIDGE_PCIEMEM_BASE1 0x35 106225394Sjchandra#define BRIDGE_PCIEMEM_BASE2 0x36 107225394Sjchandra#define BRIDGE_PCIEMEM_BASE3 0x37 108225394Sjchandra#define BRIDGE_PCIEMEM_LIMIT0 0x38 109225394Sjchandra#define BRIDGE_PCIEMEM_LIMIT1 0x39 110225394Sjchandra#define BRIDGE_PCIEMEM_LIMIT2 0x3a 111225394Sjchandra#define BRIDGE_PCIEMEM_LIMIT3 0x3b 112225394Sjchandra#define BRIDGE_PCIEIO_BASE0 0x3c 113225394Sjchandra#define BRIDGE_PCIEIO_BASE1 0x3d 114225394Sjchandra#define BRIDGE_PCIEIO_BASE2 0x3e 115225394Sjchandra#define BRIDGE_PCIEIO_BASE3 0x3f 116225394Sjchandra#define BRIDGE_PCIEIO_LIMIT0 0x40 117225394Sjchandra#define BRIDGE_PCIEIO_LIMIT1 0x41 118225394Sjchandra#define BRIDGE_PCIEIO_LIMIT2 0x42 119225394Sjchandra#define BRIDGE_PCIEIO_LIMIT3 0x43 120225394Sjchandra#define BRIDGE_PCIEMEM_BASE4 0x44 121225394Sjchandra#define BRIDGE_PCIEMEM_BASE5 0x45 122225394Sjchandra#define BRIDGE_PCIEMEM_BASE6 0x46 123225394Sjchandra#define BRIDGE_PCIEMEM_LIMIT4 0x47 124225394Sjchandra#define BRIDGE_PCIEMEM_LIMIT5 0x48 125225394Sjchandra#define BRIDGE_PCIEMEM_LIMIT6 0x49 126225394Sjchandra#define BRIDGE_PCIEIO_BASE4 0x4a 127225394Sjchandra#define BRIDGE_PCIEIO_BASE5 0x4b 128225394Sjchandra#define BRIDGE_PCIEIO_BASE6 0x4c 129225394Sjchandra#define BRIDGE_PCIEIO_LIMIT4 0x4d 130225394Sjchandra#define BRIDGE_PCIEIO_LIMIT5 0x4e 131225394Sjchandra#define BRIDGE_PCIEIO_LIMIT6 0x4f 132225394Sjchandra#define BRIDGE_NBU_EVENT_CNT_CTL 0x50 133225394Sjchandra#define BRIDGE_EVNTCTR1_LOW 0x51 134225394Sjchandra#define BRIDGE_EVNTCTR1_HI 0x52 135225394Sjchandra#define BRIDGE_EVNT_CNT_CTL2 0x53 136225394Sjchandra#define BRIDGE_EVNTCTR2_LOW 0x54 137225394Sjchandra#define BRIDGE_EVNTCTR2_HI 0x55 138225394Sjchandra#define BRIDGE_TRACEBUF_MATCH0 0x56 139225394Sjchandra#define BRIDGE_TRACEBUF_MATCH1 0x57 140225394Sjchandra#define BRIDGE_TRACEBUF_MATCH_LOW 0x58 141225394Sjchandra#define BRIDGE_TRACEBUF_MATCH_HI 0x59 142225394Sjchandra#define BRIDGE_TRACEBUF_CTRL 0x5a 143225394Sjchandra#define BRIDGE_TRACEBUF_INIT 0x5b 144225394Sjchandra#define BRIDGE_TRACEBUF_ACCESS 0x5c 145225394Sjchandra#define BRIDGE_TRACEBUF_READ_DATA0 0x5d 146225394Sjchandra#define BRIDGE_TRACEBUF_READ_DATA1 0x5d 147225394Sjchandra#define BRIDGE_TRACEBUF_READ_DATA2 0x5f 148225394Sjchandra#define BRIDGE_TRACEBUF_READ_DATA3 0x60 149225394Sjchandra#define BRIDGE_TRACEBUF_STATUS 0x61 150225394Sjchandra#define BRIDGE_ADDRESS_ERROR0 0x62 151225394Sjchandra#define BRIDGE_ADDRESS_ERROR1 0x63 152225394Sjchandra#define BRIDGE_ADDRESS_ERROR2 0x64 153225394Sjchandra#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65 154225394Sjchandra#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66 155225394Sjchandra#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67 156225394Sjchandra#define BRIDGE_LINE_FLUSH0 0x68 157225394Sjchandra#define BRIDGE_LINE_FLUSH1 0x69 158225394Sjchandra#define BRIDGE_NODE_ID 0x6a 159225394Sjchandra#define BRIDGE_ERROR_INTERRUPT_EN 0x6b 160225394Sjchandra#define BRIDGE_PCIE0_WEIGHT 0x2c0 161225394Sjchandra#define BRIDGE_PCIE1_WEIGHT 0x2c1 162225394Sjchandra#define BRIDGE_PCIE2_WEIGHT 0x2c2 163225394Sjchandra#define BRIDGE_PCIE3_WEIGHT 0x2c3 164225394Sjchandra#define BRIDGE_USB_WEIGHT 0x2c4 165225394Sjchandra#define BRIDGE_NET_WEIGHT 0x2c5 166225394Sjchandra#define BRIDGE_POE_WEIGHT 0x2c6 167225394Sjchandra#define BRIDGE_CMS_WEIGHT 0x2c7 168225394Sjchandra#define BRIDGE_DMAENG_WEIGHT 0x2c8 169225394Sjchandra#define BRIDGE_SEC_WEIGHT 0x2c9 170225394Sjchandra#define BRIDGE_COMP_WEIGHT 0x2ca 171225394Sjchandra#define BRIDGE_GIO_WEIGHT 0x2cb 172225394Sjchandra#define BRIDGE_FLASH_WEIGHT 0x2cc 173224110Sjchandra 174224110Sjchandra#if !defined(LOCORE) && !defined(__ASSEMBLY__) 175224110Sjchandra 176225394Sjchandra#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) 177225394Sjchandra#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) 178225394Sjchandra#define nlm_get_bridge_pcibase(node) \ 179225394Sjchandra nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) 180225394Sjchandra#define nlm_get_bridge_regbase(node) \ 181225394Sjchandra (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) 182224110Sjchandra 183224110Sjchandra#endif 184224110Sjchandra#endif 185