1178172Simp/* $OpenBSD: mips_opcode.h,v 1.2 1999/01/27 04:46:05 imp Exp $ */ 2178172Simp 3178172Simp/*- 4178172Simp * Copyright (c) 1992, 1993 5178172Simp * The Regents of the University of California. All rights reserved. 6178172Simp * 7178172Simp * This code is derived from software contributed to Berkeley by 8178172Simp * Ralph Campbell. 9178172Simp * 10178172Simp * Redistribution and use in source and binary forms, with or without 11178172Simp * modification, are permitted provided that the following conditions 12178172Simp * are met: 13178172Simp * 1. Redistributions of source code must retain the above copyright 14178172Simp * notice, this list of conditions and the following disclaimer. 15178172Simp * 2. Redistributions in binary form must reproduce the above copyright 16178172Simp * notice, this list of conditions and the following disclaimer in the 17178172Simp * documentation and/or other materials provided with the distribution. 18178172Simp * 4. Neither the name of the University nor the names of its contributors 19178172Simp * may be used to endorse or promote products derived from this software 20178172Simp * without specific prior written permission. 21178172Simp * 22178172Simp * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23178172Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24178172Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25178172Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26178172Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27178172Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28178172Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29178172Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30178172Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31178172Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32178172Simp * SUCH DAMAGE. 33178172Simp * 34178172Simp * from: @(#)mips_opcode.h 8.1 (Berkeley) 6/10/93 35178172Simp * JNPR: mips_opcode.h,v 1.1 2006/08/07 05:38:57 katta 36178172Simp * $FreeBSD: releng/10.2/sys/mips/include/mips_opcode.h 231312 2012-02-09 22:17:13Z gonzo $ 37178172Simp */ 38178172Simp 39178172Simp#ifndef _MACHINE_MIPS_OPCODE_H_ 40178172Simp#define _MACHINE_MIPS_OPCODE_H_ 41178172Simp 42178172Simp/* 43178172Simp * Define the instruction formats and opcode values for the 44178172Simp * MIPS instruction set. 45178172Simp */ 46178172Simp#include <machine/endian.h> 47178172Simp 48178172Simp/* 49178172Simp * Define the instruction formats. 50178172Simp */ 51178172Simptypedef union { 52178172Simp unsigned word; 53178172Simp 54178172Simp#if BYTE_ORDER == BIG_ENDIAN 55178172Simp struct { 56178172Simp unsigned op: 6; 57178172Simp unsigned rs: 5; 58178172Simp unsigned rt: 5; 59178172Simp unsigned imm: 16; 60178172Simp } IType; 61178172Simp 62178172Simp struct { 63178172Simp unsigned op: 6; 64178172Simp unsigned target: 26; 65178172Simp } JType; 66178172Simp 67178172Simp struct { 68178172Simp unsigned op: 6; 69178172Simp unsigned rs: 5; 70178172Simp unsigned rt: 5; 71178172Simp unsigned rd: 5; 72178172Simp unsigned shamt: 5; 73178172Simp unsigned func: 6; 74178172Simp } RType; 75178172Simp 76178172Simp struct { 77178172Simp unsigned op: 6; /* always '0x11' */ 78178172Simp unsigned : 1; /* always '1' */ 79178172Simp unsigned fmt: 4; 80178172Simp unsigned ft: 5; 81178172Simp unsigned fs: 5; 82178172Simp unsigned fd: 5; 83178172Simp unsigned func: 6; 84178172Simp } FRType; 85178172Simp#endif 86178172Simp#if BYTE_ORDER == LITTLE_ENDIAN 87178172Simp struct { 88178172Simp unsigned imm: 16; 89178172Simp unsigned rt: 5; 90178172Simp unsigned rs: 5; 91178172Simp unsigned op: 6; 92178172Simp } IType; 93178172Simp 94178172Simp struct { 95178172Simp unsigned target: 26; 96178172Simp unsigned op: 6; 97178172Simp } JType; 98178172Simp 99178172Simp struct { 100178172Simp unsigned func: 6; 101178172Simp unsigned shamt: 5; 102178172Simp unsigned rd: 5; 103178172Simp unsigned rt: 5; 104178172Simp unsigned rs: 5; 105178172Simp unsigned op: 6; 106178172Simp } RType; 107178172Simp 108178172Simp struct { 109178172Simp unsigned func: 6; 110178172Simp unsigned fd: 5; 111178172Simp unsigned fs: 5; 112178172Simp unsigned ft: 5; 113178172Simp unsigned fmt: 4; 114178172Simp unsigned : 1; /* always '1' */ 115178172Simp unsigned op: 6; /* always '0x11' */ 116178172Simp } FRType; 117178172Simp#endif 118178172Simp} InstFmt; 119178172Simp 120178172Simp/* instruction field decoding macros */ 121178172Simp#define MIPS_INST_OPCODE(val) (val >> 26) 122178172Simp#define MIPS_INST_RS(val) ((val & 0x03e00000) >> 21) 123178172Simp#define MIPS_INST_RT(val) ((val & 0x001f0000) >> 16) 124178172Simp#define MIPS_INST_IMM(val) ((val & 0x0000ffff)) 125178172Simp 126178172Simp#define MIPS_INST_RD(val) ((val & 0x0000f800) >> 11) 127178172Simp#define MIPS_INST_SA(val) ((val & 0x000007c0) >> 6) 128178172Simp#define MIPS_INST_FUNC(val) (val & 0x0000003f) 129178172Simp 130178172Simp#define MIPS_INST_INDEX(val) (val & 0x03ffffff) 131178172Simp 132178172Simp/* 133178172Simp * the mips opcode and function table use a 3bit row and 3bit col 134178172Simp * number we define the following macro for easy transcribing 135178172Simp */ 136178172Simp 137178172Simp#define MIPS_OPCODE(r, c) (((r & 0x07) << 3) | (c & 0x07)) 138178172Simp 139178172Simp 140178172Simp/* 141178172Simp * Values for the 'op' field. 142178172Simp */ 143178172Simp#define OP_SPECIAL 000 144178172Simp#define OP_BCOND 001 145178172Simp#define OP_J 002 146178172Simp#define OP_JAL 003 147178172Simp#define OP_BEQ 004 148178172Simp#define OP_BNE 005 149178172Simp#define OP_BLEZ 006 150178172Simp#define OP_BGTZ 007 151178172Simp 152178172Simp#define OP_REGIMM OP_BCOND 153178172Simp 154178172Simp#define OP_ADDI 010 155178172Simp#define OP_ADDIU 011 156178172Simp#define OP_SLTI 012 157178172Simp#define OP_SLTIU 013 158178172Simp#define OP_ANDI 014 159178172Simp#define OP_ORI 015 160178172Simp#define OP_XORI 016 161178172Simp#define OP_LUI 017 162178172Simp 163178172Simp#define OP_COP0 020 164178172Simp#define OP_COP1 021 165178172Simp#define OP_COP2 022 166178172Simp#define OP_COP3 023 167178172Simp#define OP_BEQL 024 168178172Simp#define OP_BNEL 025 169178172Simp#define OP_BLEZL 026 170178172Simp#define OP_BGTZL 027 171178172Simp 172178172Simp#define OP_COP1X OP_COP3 173178172Simp 174178172Simp#define OP_DADDI 030 175178172Simp#define OP_DADDIU 031 176178172Simp#define OP_LDL 032 177178172Simp#define OP_LDR 033 178178172Simp 179231312Sgonzo#define OP_SPECIAL2 034 180231312Sgonzo#define OP_JALX 035 181231312Sgonzo 182231312Sgonzo#define OP_SPECIAL3 037 183231312Sgonzo 184178172Simp#define OP_LB 040 185178172Simp#define OP_LH 041 186178172Simp#define OP_LWL 042 187178172Simp#define OP_LW 043 188178172Simp#define OP_LBU 044 189178172Simp#define OP_LHU 045 190178172Simp#define OP_LWR 046 191178172Simp#define OP_LWU 047 192178172Simp 193178172Simp#define OP_SB 050 194178172Simp#define OP_SH 051 195178172Simp#define OP_SWL 052 196178172Simp#define OP_SW 053 197178172Simp#define OP_SDL 054 198178172Simp#define OP_SDR 055 199178172Simp#define OP_SWR 056 200178172Simp#define OP_CACHE 057 201178172Simp 202178172Simp#define OP_LL 060 203178172Simp#define OP_LWC1 061 204178172Simp#define OP_LWC2 062 205178172Simp#define OP_LWC3 063 206178172Simp#define OP_LLD 064 207178172Simp#define OP_LDC1 065 208178172Simp#define OP_LDC2 066 209178172Simp#define OP_LD 067 210178172Simp 211178172Simp#define OP_PREF OP_LWC3 212178172Simp 213178172Simp#define OP_SC 070 214178172Simp#define OP_SWC1 071 215178172Simp#define OP_SWC2 072 216178172Simp#define OP_SWC3 073 217178172Simp#define OP_SCD 074 218178172Simp#define OP_SDC1 075 219178172Simp#define OP_SDC2 076 220178172Simp#define OP_SD 077 221178172Simp 222178172Simp/* 223178172Simp * Values for the 'func' field when 'op' == OP_SPECIAL. 224178172Simp */ 225178172Simp#define OP_SLL 000 226178172Simp#define OP_MOVCI 001 227178172Simp#define OP_SRL 002 228178172Simp#define OP_SRA 003 229178172Simp#define OP_SLLV 004 230178172Simp#define OP_SRLV 006 231178172Simp#define OP_SRAV 007 232178172Simp 233178172Simp#define OP_F_SLL OP_SLL 234178172Simp#define OP_F_MOVCI OP_MOVCI 235178172Simp#define OP_F_SRL OP_SRL 236178172Simp#define OP_F_SRA OP_SRA 237178172Simp#define OP_F_SLLV OP_SLLV 238178172Simp#define OP_F_SRLV OP_SRLV 239178172Simp#define OP_F_SRAV OP_SRAV 240178172Simp 241178172Simp#define OP_JR 010 242178172Simp#define OP_JALR 011 243178172Simp#define OP_MOVZ 012 244178172Simp#define OP_MOVN 013 245178172Simp#define OP_SYSCALL 014 246178172Simp#define OP_BREAK 015 247178172Simp#define OP_SYNC 017 248178172Simp 249178172Simp#define OP_F_JR OP_JR 250178172Simp#define OP_F_JALR OP_JALR 251178172Simp#define OP_F_MOVZ OP_MOVZ 252178172Simp#define OP_F_MOVN OP_MOVN 253178172Simp#define OP_F_SYSCALL OP_SYSCALL 254178172Simp#define OP_F_BREAK OP_BREAK 255178172Simp#define OP_F_SYNC OP_SYNC 256178172Simp 257178172Simp#define OP_MFHI 020 258178172Simp#define OP_MTHI 021 259178172Simp#define OP_MFLO 022 260178172Simp#define OP_MTLO 023 261178172Simp#define OP_DSLLV 024 262178172Simp#define OP_DSRLV 026 263178172Simp#define OP_DSRAV 027 264178172Simp 265178172Simp#define OP_F_MFHI OP_MFHI 266178172Simp#define OP_F_MTHI OP_MTHI 267178172Simp#define OP_F_MFLO OP_MFLO 268178172Simp#define OP_F_MTLO OP_MTLO 269178172Simp#define OP_F_DSLLV OP_DSLLV 270178172Simp#define OP_F_DSRLV OP_DSRLV 271178172Simp#define OP_F_DSRAV OP_DSRAV 272178172Simp 273178172Simp#define OP_MULT 030 274178172Simp#define OP_MULTU 031 275178172Simp#define OP_DIV 032 276178172Simp#define OP_DIVU 033 277178172Simp#define OP_DMULT 034 278178172Simp#define OP_DMULTU 035 279178172Simp#define OP_DDIV 036 280178172Simp#define OP_DDIVU 037 281178172Simp 282178172Simp#define OP_F_MULT OP_MULT 283178172Simp#define OP_F_MULTU OP_MULTU 284178172Simp#define OP_F_DIV OP_DIV 285178172Simp#define OP_F_DIVU OP_DIVU 286178172Simp#define OP_F_DMULT OP_DMULT 287178172Simp#define OP_F_DMULTU OP_DMULTU 288178172Simp#define OP_F_DDIV OP_DDIV 289178172Simp#define OP_F_DDIVU OP_DDIVU 290178172Simp 291178172Simp#define OP_ADD 040 292178172Simp#define OP_ADDU 041 293178172Simp#define OP_SUB 042 294178172Simp#define OP_SUBU 043 295178172Simp#define OP_AND 044 296178172Simp#define OP_OR 045 297178172Simp#define OP_XOR 046 298178172Simp#define OP_NOR 047 299178172Simp 300178172Simp#define OP_F_ADD OP_ADD 301178172Simp#define OP_F_ADDU OP_ADDU 302178172Simp#define OP_F_SUB OP_SUB 303178172Simp#define OP_F_SUBU OP_SUBU 304178172Simp#define OP_F_AND OP_AND 305178172Simp#define OP_F_OR OP_OR 306178172Simp#define OP_F_XOR OP_XOR 307178172Simp#define OP_F_NOR OP_NOR 308178172Simp 309178172Simp#define OP_SLT 052 310178172Simp#define OP_SLTU 053 311178172Simp#define OP_DADD 054 312178172Simp#define OP_DADDU 055 313178172Simp#define OP_DSUB 056 314178172Simp#define OP_DSUBU 057 315178172Simp 316178172Simp#define OP_F_SLT OP_SLT 317178172Simp#define OP_F_SLTU OP_SLTU 318178172Simp#define OP_F_DADD OP_DADD 319178172Simp#define OP_F_DADDU OP_DADDU 320178172Simp#define OP_F_DSUB OP_DSUB 321178172Simp#define OP_F_DSUBU OP_DSUBU 322178172Simp 323178172Simp#define OP_TGE 060 324178172Simp#define OP_TGEU 061 325178172Simp#define OP_TLT 062 326178172Simp#define OP_TLTU 063 327178172Simp#define OP_TEQ 064 328178172Simp#define OP_TNE 066 329178172Simp 330178172Simp#define OP_F_TGE OP_TGE 331178172Simp#define OP_F_TGEU OP_TGEU 332178172Simp#define OP_F_TLT OP_TLT 333178172Simp#define OP_F_TLTU OP_TLTU 334178172Simp#define OP_F_TEQ OP_TEQ 335178172Simp#define OP_F_TNE OP_TNE 336178172Simp 337178172Simp#define OP_DSLL 070 338178172Simp#define OP_DSRL 072 339178172Simp#define OP_DSRA 073 340178172Simp#define OP_DSLL32 074 341178172Simp#define OP_DSRL32 076 342178172Simp#define OP_DSRA32 077 343178172Simp 344178172Simp#define OP_F_DSLL OP_DSLL 345178172Simp#define OP_F_DSRL OP_DSRL 346178172Simp#define OP_F_DSRA OP_DSRA 347178172Simp#define OP_F_DSLL32 OP_DSLL32 348178172Simp#define OP_F_DSRL32 OP_DSRL32 349178172Simp#define OP_F_DSRA32 OP_DSRA32 350178172Simp 351178172Simp/* 352178172Simp * The REGIMM - register immediate instructions are further 353178172Simp * decoded using this table that has 2bit row numbers, hence 354178172Simp * a need for a new helper macro. 355178172Simp */ 356178172Simp 357178172Simp#define MIPS_ROP(r, c) ((r & 0x03) << 3) | (c & 0x07) 358178172Simp 359178172Simp/* 360178172Simp * Values for the 'func' field when 'op' == OP_BCOND. 361178172Simp */ 362178172Simp#define OP_BLTZ 000 363178172Simp#define OP_BGEZ 001 364178172Simp#define OP_BLTZL 002 365178172Simp#define OP_BGEZL 003 366178172Simp 367178172Simp#define OP_R_BLTZ OP_BLTZ 368178172Simp#define OP_R_BGEZ OP_BGEZ 369178172Simp#define OP_R_BLTZL OP_BLTZL 370178172Simp#define OP_R_BGEZL OP_BGEZL 371178172Simp 372178172Simp#define OP_TGEI 010 373178172Simp#define OP_TGEIU 011 374178172Simp#define OP_TLTI 012 375178172Simp#define OP_TLTIU 013 376178172Simp#define OP_TEQI 014 377178172Simp#define OP_TNEI 016 378178172Simp 379178172Simp#define OP_R_TGEI OP_TGEI 380178172Simp#define OP_R_TGEIU OP_TGEIU 381178172Simp#define OP_R_TLTI OP_TLTI 382178172Simp#define OP_R_TLTIU OP_TLTIU 383178172Simp#define OP_R_TEQI OP_TEQI 384178172Simp#define OP_R_TNEI OP_TNEI 385178172Simp 386178172Simp#define OP_BLTZAL 020 387178172Simp#define OP_BGEZAL 021 388178172Simp#define OP_BLTZALL 022 389178172Simp#define OP_BGEZALL 023 390178172Simp 391178172Simp#define OP_R_BLTZAL OP_BLTZAL 392178172Simp#define OP_R_BGEZAL OP_BGEZAL 393178172Simp#define OP_R_BLTZALL OP_BLTZALL 394178172Simp#define OP_R_BGEZALL OP_BGEZALL 395178172Simp 396178172Simp/* 397231312Sgonzo * Values for the 'func' field when 'op' == OP_SPECIAL3. 398231312Sgonzo */ 399231312Sgonzo#define OP_RDHWR 073 400231312Sgonzo 401231312Sgonzo/* 402178172Simp * Values for the 'rs' field when 'op' == OP_COPz. 403178172Simp */ 404178172Simp#define OP_MF 000 405178172Simp#define OP_DMF 001 406178172Simp#define OP_MT 004 407178172Simp#define OP_DMT 005 408178172Simp#define OP_BCx 010 409178172Simp#define OP_BCy 014 410178172Simp#define OP_CF 002 411178172Simp#define OP_CT 006 412178172Simp 413178172Simp/* 414178172Simp * Values for the 'rt' field when 'op' == OP_COPz. 415178172Simp */ 416178172Simp#define COPz_BC_TF_MASK 0x01 417178172Simp#define COPz_BC_TRUE 0x01 418178172Simp#define COPz_BC_FALSE 0x00 419178172Simp#define COPz_BCL_TF_MASK 0x02 420178172Simp#define COPz_BCL_TRUE 0x02 421178172Simp#define COPz_BCL_FALSE 0x00 422178172Simp 423178172Simp#endif /* !_MACHINE_MIPS_OPCODE_H_ */ 424