1117397Skan/*- 2117397Skan * Copyright (c) 2003 Marcel Moolenaar 3117397Skan * All rights reserved. 4117397Skan * 5117397Skan * Redistribution and use in source and binary forms, with or without 6117397Skan * modification, are permitted provided that the following conditions 7117397Skan * are met: 8117397Skan * 9117397Skan * 1. Redistributions of source code must retain the above copyright 10117397Skan * notice, this list of conditions and the following disclaimer. 11117397Skan * 2. Redistributions in binary form must reproduce the above copyright 12117397Skan * notice, this list of conditions and the following disclaimer in the 13117397Skan * documentation and/or other materials provided with the distribution. 14117397Skan * 15117397Skan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16117397Skan * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17117397Skan * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18169691Skan * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19117397Skan * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20117397Skan * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21117397Skan * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22117397Skan * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23117397Skan * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24117397Skan * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25117397Skan */ 26117397Skan 27117397Skan/* 28117397Skan * uart_dev_oct16550.c 29117397Skan * 30117397Skan * Derived from uart_dev_ns8250.c 31117397Skan * 32117397Skan * Redistribution and use in source and binary forms, with or without 33117397Skan * modification, are permitted provided that the following conditions 34117397Skan * are met: 35117397Skan * 36169691Skan * 1. Redistributions of source code must retain the above copyright 37169691Skan * notice, this list of conditions and the following disclaimer. 38169691Skan * 2. Redistributions in binary form must reproduce the above copyright 39117397Skan * notice, this list of conditions and the following disclaimer in the 40117397Skan * documentation and/or other materials provided with the distribution. 41117397Skan * 42117397Skan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 43117397Skan * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 44117397Skan * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 45117397Skan * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 46117397Skan * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 47117397Skan * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 48117397Skan * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 49117397Skan * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 50117397Skan * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 51117397Skan * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 52117397Skan * 53117397Skan * 54117397Skan */ 55117397Skan 56117397Skan 57117397Skan#include <sys/cdefs.h> 58117397Skan__FBSDID("$FreeBSD: releng/10.2/sys/mips/cavium/uart_dev_oct16550.c 262649 2014-03-01 04:16:54Z imp $"); 59117397Skan 60169691Skan#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/bus.h> 63#include <sys/conf.h> 64#include <machine/bus.h> 65#include <machine/pcpu.h> 66 67#include <dev/uart/uart.h> 68#include <dev/uart/uart_cpu.h> 69#include <dev/uart/uart_bus.h> 70 71#include <dev/ic/ns16550.h> 72 73#include <mips/cavium/octeon_pcmap_regs.h> 74 75#include <contrib/octeon-sdk/cvmx.h> 76 77#include "uart_if.h" 78 79/* 80 * Clear pending interrupts. THRE is cleared by reading IIR. Data 81 * that may have been received gets lost here. 82 */ 83static void 84oct16550_clrint (struct uart_bas *bas) 85{ 86 uint8_t iir; 87 88 iir = uart_getreg(bas, REG_IIR); 89 while ((iir & IIR_NOPEND) == 0) { 90 iir &= IIR_IMASK; 91 if (iir == IIR_RLS) 92 (void)uart_getreg(bas, REG_LSR); 93 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 94 (void)uart_getreg(bas, REG_DATA); 95 else if (iir == IIR_MLSC) 96 (void)uart_getreg(bas, REG_MSR); 97 else if (iir == IIR_BUSY) 98 (void) uart_getreg(bas, REG_USR); 99 uart_barrier(bas); 100 iir = uart_getreg(bas, REG_IIR); 101 } 102} 103 104static int delay_changed = 1; 105 106static int 107oct16550_delay (struct uart_bas *bas) 108{ 109 int divisor; 110 u_char lcr; 111 static int delay = 0; 112 113 if (!delay_changed) return delay; 114 delay_changed = 0; 115 lcr = uart_getreg(bas, REG_LCR); 116 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 117 uart_barrier(bas); 118 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 119 uart_barrier(bas); 120 uart_setreg(bas, REG_LCR, lcr); 121 uart_barrier(bas); 122 123 if(!bas->rclk) 124 return 10; /* return an approx delay value */ 125 126 /* 1/10th the time to transmit 1 character (estimate). */ 127 if (divisor <= 134) 128 return (16000000 * divisor / bas->rclk); 129 return (16000 * divisor / (bas->rclk / 1000)); 130 131} 132 133static int 134oct16550_divisor (int rclk, int baudrate) 135{ 136 int actual_baud, divisor; 137 int error; 138 139 if (baudrate == 0) 140 return (0); 141 142 divisor = (rclk / (baudrate << 3) + 1) >> 1; 143 if (divisor == 0 || divisor >= 65536) 144 return (0); 145 actual_baud = rclk / (divisor << 4); 146 147 /* 10 times error in percent: */ 148 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 149 150 /* 3.0% maximum error tolerance: */ 151 if (error < -30 || error > 30) 152 return (0); 153 154 return (divisor); 155} 156 157static int 158oct16550_drain (struct uart_bas *bas, int what) 159{ 160 int delay, limit; 161 162 delay = oct16550_delay(bas); 163 164 if (what & UART_DRAIN_TRANSMITTER) { 165 /* 166 * Pick an arbitrary high limit to avoid getting stuck in 167 * an infinite loop when the hardware is broken. Make the 168 * limit high enough to handle large FIFOs. 169 */ 170 limit = 10*10*10*1024; 171 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 172 DELAY(delay); 173 if (limit == 0) { 174 /* printf("oct16550: transmitter appears stuck... "); */ 175 return (0); 176 } 177 } 178 179 if (what & UART_DRAIN_RECEIVER) { 180 /* 181 * Pick an arbitrary high limit to avoid getting stuck in 182 * an infinite loop when the hardware is broken. Make the 183 * limit high enough to handle large FIFOs and integrated 184 * UARTs. The HP rx2600 for example has 3 UARTs on the 185 * management board that tend to get a lot of data send 186 * to it when the UART is first activated. 187 */ 188 limit=10*4096; 189 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 190 (void)uart_getreg(bas, REG_DATA); 191 uart_barrier(bas); 192 DELAY(delay << 2); 193 } 194 if (limit == 0) { 195 /* printf("oct16550: receiver appears broken... "); */ 196 return (EIO); 197 } 198 } 199 200 return (0); 201} 202 203/* 204 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 205 * drained. WARNING: this function clobbers the FIFO setting! 206 */ 207static void 208oct16550_flush (struct uart_bas *bas, int what) 209{ 210 uint8_t fcr; 211 212 fcr = FCR_ENABLE; 213 if (what & UART_FLUSH_TRANSMITTER) 214 fcr |= FCR_XMT_RST; 215 if (what & UART_FLUSH_RECEIVER) 216 fcr |= FCR_RCV_RST; 217 uart_setreg(bas, REG_FCR, fcr); 218 uart_barrier(bas); 219} 220 221static int 222oct16550_param (struct uart_bas *bas, int baudrate, int databits, int stopbits, 223 int parity) 224{ 225 int divisor; 226 uint8_t lcr; 227 228 lcr = 0; 229 if (databits >= 8) 230 lcr |= LCR_8BITS; 231 else if (databits == 7) 232 lcr |= LCR_7BITS; 233 else if (databits == 6) 234 lcr |= LCR_6BITS; 235 else 236 lcr |= LCR_5BITS; 237 if (stopbits > 1) 238 lcr |= LCR_STOPB; 239 lcr |= parity << 3; 240 241 /* Set baudrate. */ 242 if (baudrate > 0) { 243 divisor = oct16550_divisor(bas->rclk, baudrate); 244 if (divisor == 0) 245 return (EINVAL); 246 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 247 uart_barrier(bas); 248 uart_setreg(bas, REG_DLL, divisor & 0xff); 249 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 250 uart_barrier(bas); 251 delay_changed = 1; 252 } 253 254 /* Set LCR and clear DLAB. */ 255 uart_setreg(bas, REG_LCR, lcr); 256 uart_barrier(bas); 257 return (0); 258} 259 260/* 261 * Low-level UART interface. 262 */ 263static int oct16550_probe(struct uart_bas *bas); 264static void oct16550_init(struct uart_bas *bas, int, int, int, int); 265static void oct16550_term(struct uart_bas *bas); 266static void oct16550_putc(struct uart_bas *bas, int); 267static int oct16550_rxready(struct uart_bas *bas); 268static int oct16550_getc(struct uart_bas *bas, struct mtx *); 269 270struct uart_ops uart_oct16550_ops = { 271 .probe = oct16550_probe, 272 .init = oct16550_init, 273 .term = oct16550_term, 274 .putc = oct16550_putc, 275 .rxready = oct16550_rxready, 276 .getc = oct16550_getc, 277}; 278 279static int 280oct16550_probe (struct uart_bas *bas) 281{ 282 u_char val; 283 284 /* Check known 0 bits that don't depend on DLAB. */ 285 val = uart_getreg(bas, REG_IIR); 286 if (val & 0x30) 287 return (ENXIO); 288 val = uart_getreg(bas, REG_MCR); 289 if (val & 0xc0) 290 return (ENXIO); 291 val = uart_getreg(bas, REG_USR); 292 if (val & 0xe0) 293 return (ENXIO); 294 return (0); 295} 296 297static void 298oct16550_init (struct uart_bas *bas, int baudrate, int databits, int stopbits, 299 int parity) 300{ 301 u_char ier; 302 303 oct16550_param(bas, baudrate, databits, stopbits, parity); 304 305 /* Disable all interrupt sources. */ 306 ier = uart_getreg(bas, REG_IER) & 0x0; 307 uart_setreg(bas, REG_IER, ier); 308 uart_barrier(bas); 309 310 /* Disable the FIFO (if present). */ 311// uart_setreg(bas, REG_FCR, 0); 312 uart_barrier(bas); 313 314 /* Set RTS & DTR. */ 315 uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR); 316 uart_barrier(bas); 317 318 oct16550_clrint(bas); 319} 320 321static void 322oct16550_term (struct uart_bas *bas) 323{ 324 325 /* Clear RTS & DTR. */ 326 uart_setreg(bas, REG_MCR, 0); 327 uart_barrier(bas); 328} 329 330static inline void oct16550_wait_txhr_empty (struct uart_bas *bas, int limit, int delay) 331{ 332 while (((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) && 333 ((uart_getreg(bas, REG_USR) & USR_TXFIFO_NOTFULL) == 0)) 334 DELAY(delay); 335} 336 337static void 338oct16550_putc (struct uart_bas *bas, int c) 339{ 340 int delay; 341 342 /* 1/10th the time to transmit 1 character (estimate). */ 343 delay = oct16550_delay(bas); 344 oct16550_wait_txhr_empty(bas, 100, delay); 345 uart_setreg(bas, REG_DATA, c); 346 uart_barrier(bas); 347 oct16550_wait_txhr_empty(bas, 100, delay); 348} 349 350static int 351oct16550_rxready (struct uart_bas *bas) 352{ 353 354 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 355} 356 357static int 358oct16550_getc (struct uart_bas *bas, struct mtx *hwmtx) 359{ 360 int c, delay; 361 362 uart_lock(hwmtx); 363 364 /* 1/10th the time to transmit 1 character (estimate). */ 365 delay = oct16550_delay(bas); 366 367 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 368 uart_unlock(hwmtx); 369 DELAY(delay); 370 uart_lock(hwmtx); 371 } 372 373 c = uart_getreg(bas, REG_DATA); 374 375 uart_unlock(hwmtx); 376 377 return (c); 378} 379 380/* 381 * High-level UART interface. 382 */ 383struct oct16550_softc { 384 struct uart_softc base; 385 uint8_t fcr; 386 uint8_t ier; 387 uint8_t mcr; 388}; 389 390static int oct16550_bus_attach(struct uart_softc *); 391static int oct16550_bus_detach(struct uart_softc *); 392static int oct16550_bus_flush(struct uart_softc *, int); 393static int oct16550_bus_getsig(struct uart_softc *); 394static int oct16550_bus_ioctl(struct uart_softc *, int, intptr_t); 395static int oct16550_bus_ipend(struct uart_softc *); 396static int oct16550_bus_param(struct uart_softc *, int, int, int, int); 397static int oct16550_bus_probe(struct uart_softc *); 398static int oct16550_bus_receive(struct uart_softc *); 399static int oct16550_bus_setsig(struct uart_softc *, int); 400static int oct16550_bus_transmit(struct uart_softc *); 401static void oct16550_bus_grab(struct uart_softc *); 402static void oct16550_bus_ungrab(struct uart_softc *); 403 404static kobj_method_t oct16550_methods[] = { 405 KOBJMETHOD(uart_attach, oct16550_bus_attach), 406 KOBJMETHOD(uart_detach, oct16550_bus_detach), 407 KOBJMETHOD(uart_flush, oct16550_bus_flush), 408 KOBJMETHOD(uart_getsig, oct16550_bus_getsig), 409 KOBJMETHOD(uart_ioctl, oct16550_bus_ioctl), 410 KOBJMETHOD(uart_ipend, oct16550_bus_ipend), 411 KOBJMETHOD(uart_param, oct16550_bus_param), 412 KOBJMETHOD(uart_probe, oct16550_bus_probe), 413 KOBJMETHOD(uart_receive, oct16550_bus_receive), 414 KOBJMETHOD(uart_setsig, oct16550_bus_setsig), 415 KOBJMETHOD(uart_transmit, oct16550_bus_transmit), 416 KOBJMETHOD(uart_grab, oct16550_bus_grab), 417 KOBJMETHOD(uart_ungrab, oct16550_bus_ungrab), 418 { 0, 0 } 419}; 420 421struct uart_class uart_oct16550_class = { 422 "oct16550 class", 423 oct16550_methods, 424 sizeof(struct oct16550_softc), 425 .uc_ops = &uart_oct16550_ops, 426 .uc_range = 8 << 3, 427 .uc_rclk = 0 428}; 429 430#define SIGCHG(c, i, s, d) \ 431 if (c) { \ 432 i |= (i & s) ? s : s | d; \ 433 } else { \ 434 i = (i & s) ? (i & ~s) | d : i; \ 435 } 436 437static int 438oct16550_bus_attach (struct uart_softc *sc) 439{ 440 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc; 441 struct uart_bas *bas; 442 int unit; 443 444 unit = device_get_unit(sc->sc_dev); 445 bas = &sc->sc_bas; 446 447 oct16550_drain(bas, UART_DRAIN_TRANSMITTER); 448 oct16550->mcr = uart_getreg(bas, REG_MCR); 449 oct16550->fcr = FCR_ENABLE | FCR_RX_HIGH; 450 uart_setreg(bas, REG_FCR, oct16550->fcr); 451 uart_barrier(bas); 452 oct16550_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 453 454 if (oct16550->mcr & MCR_DTR) 455 sc->sc_hwsig |= SER_DTR; 456 if (oct16550->mcr & MCR_RTS) 457 sc->sc_hwsig |= SER_RTS; 458 oct16550_bus_getsig(sc); 459 460 oct16550_clrint(bas); 461 oct16550->ier = uart_getreg(bas, REG_IER) & 0xf0; 462 oct16550->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY; 463 uart_setreg(bas, REG_IER, oct16550->ier); 464 uart_barrier(bas); 465 466 return (0); 467} 468 469static int 470oct16550_bus_detach (struct uart_softc *sc) 471{ 472 struct uart_bas *bas; 473 u_char ier; 474 475 bas = &sc->sc_bas; 476 ier = uart_getreg(bas, REG_IER) & 0xf0; 477 uart_setreg(bas, REG_IER, ier); 478 uart_barrier(bas); 479 oct16550_clrint(bas); 480 return (0); 481} 482 483static int 484oct16550_bus_flush (struct uart_softc *sc, int what) 485{ 486 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc; 487 struct uart_bas *bas; 488 int error; 489 490 bas = &sc->sc_bas; 491 uart_lock(sc->sc_hwmtx); 492 if (sc->sc_rxfifosz > 1) { 493 oct16550_flush(bas, what); 494 uart_setreg(bas, REG_FCR, oct16550->fcr); 495 uart_barrier(bas); 496 error = 0; 497 } else 498 error = oct16550_drain(bas, what); 499 uart_unlock(sc->sc_hwmtx); 500 return (error); 501} 502 503static int 504oct16550_bus_getsig (struct uart_softc *sc) 505{ 506 uint32_t new, old, sig; 507 uint8_t msr; 508 509 do { 510 old = sc->sc_hwsig; 511 sig = old; 512 uart_lock(sc->sc_hwmtx); 513 msr = uart_getreg(&sc->sc_bas, REG_MSR); 514 uart_unlock(sc->sc_hwmtx); 515 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 516 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 517 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 518 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 519 new = sig & ~SER_MASK_DELTA; 520 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 521 return (sig); 522} 523 524static int 525oct16550_bus_ioctl (struct uart_softc *sc, int request, intptr_t data) 526{ 527 struct uart_bas *bas; 528 int baudrate, divisor, error; 529 uint8_t efr, lcr; 530 531 bas = &sc->sc_bas; 532 error = 0; 533 uart_lock(sc->sc_hwmtx); 534 switch (request) { 535 case UART_IOCTL_BREAK: 536 lcr = uart_getreg(bas, REG_LCR); 537 if (data) 538 lcr |= LCR_SBREAK; 539 else 540 lcr &= ~LCR_SBREAK; 541 uart_setreg(bas, REG_LCR, lcr); 542 uart_barrier(bas); 543 break; 544 case UART_IOCTL_IFLOW: 545 lcr = uart_getreg(bas, REG_LCR); 546 uart_barrier(bas); 547 uart_setreg(bas, REG_LCR, 0xbf); 548 uart_barrier(bas); 549 efr = uart_getreg(bas, REG_EFR); 550 if (data) 551 efr |= EFR_RTS; 552 else 553 efr &= ~EFR_RTS; 554 uart_setreg(bas, REG_EFR, efr); 555 uart_barrier(bas); 556 uart_setreg(bas, REG_LCR, lcr); 557 uart_barrier(bas); 558 break; 559 case UART_IOCTL_OFLOW: 560 lcr = uart_getreg(bas, REG_LCR); 561 uart_barrier(bas); 562 uart_setreg(bas, REG_LCR, 0xbf); 563 uart_barrier(bas); 564 efr = uart_getreg(bas, REG_EFR); 565 if (data) 566 efr |= EFR_CTS; 567 else 568 efr &= ~EFR_CTS; 569 uart_setreg(bas, REG_EFR, efr); 570 uart_barrier(bas); 571 uart_setreg(bas, REG_LCR, lcr); 572 uart_barrier(bas); 573 break; 574 case UART_IOCTL_BAUD: 575 lcr = uart_getreg(bas, REG_LCR); 576 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 577 uart_barrier(bas); 578 divisor = uart_getreg(bas, REG_DLL) | 579 (uart_getreg(bas, REG_DLH) << 8); 580 uart_barrier(bas); 581 uart_setreg(bas, REG_LCR, lcr); 582 uart_barrier(bas); 583 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 584 delay_changed = 1; 585 if (baudrate > 0) 586 *(int*)data = baudrate; 587 else 588 error = ENXIO; 589 break; 590 default: 591 error = EINVAL; 592 break; 593 } 594 uart_unlock(sc->sc_hwmtx); 595 return (error); 596} 597 598 599static int 600oct16550_bus_ipend(struct uart_softc *sc) 601{ 602 struct uart_bas *bas; 603 int ipend = 0; 604 uint8_t iir, lsr; 605 606 bas = &sc->sc_bas; 607 uart_lock(sc->sc_hwmtx); 608 609 iir = uart_getreg(bas, REG_IIR) & IIR_IMASK; 610 if (iir != IIR_NOPEND) { 611 612 if (iir == IIR_RLS) { 613 lsr = uart_getreg(bas, REG_LSR); 614 if (lsr & LSR_OE) 615 ipend |= SER_INT_OVERRUN; 616 if (lsr & LSR_BI) 617 ipend |= SER_INT_BREAK; 618 if (lsr & LSR_RXRDY) 619 ipend |= SER_INT_RXREADY; 620 621 } else if (iir == IIR_RXRDY) { 622 ipend |= SER_INT_RXREADY; 623 624 } else if (iir == IIR_RXTOUT) { 625 ipend |= SER_INT_RXREADY; 626 627 } else if (iir == IIR_TXRDY) { 628 ipend |= SER_INT_TXIDLE; 629 630 } else if (iir == IIR_MLSC) { 631 ipend |= SER_INT_SIGCHG; 632 633 } else if (iir == IIR_BUSY) { 634 (void) uart_getreg(bas, REG_USR); 635 } 636 } 637 uart_unlock(sc->sc_hwmtx); 638 639 return (ipend); 640} 641 642static int 643oct16550_bus_param (struct uart_softc *sc, int baudrate, int databits, 644 int stopbits, int parity) 645{ 646 struct uart_bas *bas; 647 int error; 648 649 bas = &sc->sc_bas; 650 uart_lock(sc->sc_hwmtx); 651 error = oct16550_param(bas, baudrate, databits, stopbits, parity); 652 uart_unlock(sc->sc_hwmtx); 653 return (error); 654} 655 656static int 657oct16550_bus_probe (struct uart_softc *sc) 658{ 659 struct uart_bas *bas; 660 int error; 661 662 bas = &sc->sc_bas; 663 bas->rclk = uart_oct16550_class.uc_rclk = cvmx_clock_get_rate(CVMX_CLOCK_SCLK); 664 665 error = oct16550_probe(bas); 666 if (error) { 667 return (error); 668 } 669 670 uart_setreg(bas, REG_MCR, (MCR_DTR | MCR_RTS)); 671 672 /* 673 * Enable FIFOs. And check that the UART has them. If not, we're 674 * done. Since this is the first time we enable the FIFOs, we reset 675 * them. 676 */ 677 oct16550_drain(bas, UART_DRAIN_TRANSMITTER); 678#define ENABLE_OCTEON_FIFO 1 679#ifdef ENABLE_OCTEON_FIFO 680 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 681#endif 682 uart_barrier(bas); 683 684 oct16550_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 685 686 if (device_get_unit(sc->sc_dev)) { 687 device_set_desc(sc->sc_dev, "Octeon-16550 channel 1"); 688 } else { 689 device_set_desc(sc->sc_dev, "Octeon-16550 channel 0"); 690 } 691#ifdef ENABLE_OCTEON_FIFO 692 sc->sc_rxfifosz = 64; 693 sc->sc_txfifosz = 64; 694#else 695 sc->sc_rxfifosz = 1; 696 sc->sc_txfifosz = 1; 697#endif 698 699 700#if 0 701 /* 702 * XXX there are some issues related to hardware flow control and 703 * it's likely that uart(4) is the cause. This basicly needs more 704 * investigation, but we avoid using for hardware flow control 705 * until then. 706 */ 707 /* 16650s or higher have automatic flow control. */ 708 if (sc->sc_rxfifosz > 16) { 709 sc->sc_hwiflow = 1; 710 sc->sc_hwoflow = 1; 711 } 712#endif 713 714 return (0); 715} 716 717static int 718oct16550_bus_receive (struct uart_softc *sc) 719{ 720 struct uart_bas *bas; 721 int xc; 722 uint8_t lsr; 723 724 bas = &sc->sc_bas; 725 uart_lock(sc->sc_hwmtx); 726 lsr = uart_getreg(bas, REG_LSR); 727 728 while (lsr & LSR_RXRDY) { 729 if (uart_rx_full(sc)) { 730 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 731 break; 732 } 733 xc = uart_getreg(bas, REG_DATA); 734 if (lsr & LSR_FE) 735 xc |= UART_STAT_FRAMERR; 736 if (lsr & LSR_PE) 737 xc |= UART_STAT_PARERR; 738 uart_rx_put(sc, xc); 739 lsr = uart_getreg(bas, REG_LSR); 740 } 741 /* Discard everything left in the Rx FIFO. */ 742 /* 743 * First do a dummy read/discard anyway, in case the UART was lying to us. 744 * This problem was seen on board, when IIR said RBR, but LSR said no RXRDY 745 * Results in a stuck ipend loop. 746 */ 747 (void)uart_getreg(bas, REG_DATA); 748 while (lsr & LSR_RXRDY) { 749 (void)uart_getreg(bas, REG_DATA); 750 uart_barrier(bas); 751 lsr = uart_getreg(bas, REG_LSR); 752 } 753 uart_unlock(sc->sc_hwmtx); 754 return (0); 755} 756 757static int 758oct16550_bus_setsig (struct uart_softc *sc, int sig) 759{ 760 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc; 761 struct uart_bas *bas; 762 uint32_t new, old; 763 764 bas = &sc->sc_bas; 765 do { 766 old = sc->sc_hwsig; 767 new = old; 768 if (sig & SER_DDTR) { 769 SIGCHG(sig & SER_DTR, new, SER_DTR, 770 SER_DDTR); 771 } 772 if (sig & SER_DRTS) { 773 SIGCHG(sig & SER_RTS, new, SER_RTS, 774 SER_DRTS); 775 } 776 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 777 uart_lock(sc->sc_hwmtx); 778 oct16550->mcr &= ~(MCR_DTR|MCR_RTS); 779 if (new & SER_DTR) 780 oct16550->mcr |= MCR_DTR; 781 if (new & SER_RTS) 782 oct16550->mcr |= MCR_RTS; 783 uart_setreg(bas, REG_MCR, oct16550->mcr); 784 uart_barrier(bas); 785 uart_unlock(sc->sc_hwmtx); 786 return (0); 787} 788 789static int 790oct16550_bus_transmit (struct uart_softc *sc) 791{ 792 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc; 793 struct uart_bas *bas; 794 int i; 795 796 bas = &sc->sc_bas; 797 uart_lock(sc->sc_hwmtx); 798#ifdef NO_UART_INTERRUPTS 799 for (i = 0; i < sc->sc_txdatasz; i++) { 800 oct16550_putc(bas, sc->sc_txbuf[i]); 801 } 802#else 803 804 oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas)); 805 uart_setreg(bas, REG_IER, oct16550->ier | IER_ETXRDY); 806 uart_barrier(bas); 807 808 for (i = 0; i < sc->sc_txdatasz; i++) { 809 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 810 uart_barrier(bas); 811 } 812 sc->sc_txbusy = 1; 813#endif 814 uart_unlock(sc->sc_hwmtx); 815 return (0); 816} 817 818static void 819oct16550_bus_grab(struct uart_softc *sc) 820{ 821 struct uart_bas *bas = &sc->sc_bas; 822 823 /* 824 * turn off all interrupts to enter polling mode. Leave the 825 * saved mask alone. We'll restore whatever it was in ungrab. 826 * All pending interupt signals are reset when IER is set to 0. 827 */ 828 uart_lock(sc->sc_hwmtx); 829 uart_setreg(bas, REG_IER, 0); 830 uart_barrier(bas); 831 uart_unlock(sc->sc_hwmtx); 832} 833 834static void 835oct16550_bus_ungrab(struct uart_softc *sc) 836{ 837 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc; 838 struct uart_bas *bas = &sc->sc_bas; 839 840 /* 841 * Restore previous interrupt mask 842 */ 843 uart_lock(sc->sc_hwmtx); 844 uart_setreg(bas, REG_IER, oct16550->ier); 845 uart_barrier(bas); 846 uart_unlock(sc->sc_hwmtx); 847} 848