1213762Sjmallett/*- 2213762Sjmallett * Copyright (c) 2010 Juli Mallett <jmallett@FreeBSD.org> 3213762Sjmallett * All rights reserved. 4213762Sjmallett * 5213762Sjmallett * Redistribution and use in source and binary forms, with or without 6213762Sjmallett * modification, are permitted provided that the following conditions 7213762Sjmallett * are met: 8213762Sjmallett * 1. Redistributions of source code must retain the above copyright 9213762Sjmallett * notice, this list of conditions and the following disclaimer. 10213762Sjmallett * 2. Redistributions in binary form must reproduce the above copyright 11213762Sjmallett * notice, this list of conditions and the following disclaimer in the 12213762Sjmallett * documentation and/or other materials provided with the distribution. 13213762Sjmallett * 14213762Sjmallett * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15213762Sjmallett * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16213762Sjmallett * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17213762Sjmallett * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18213762Sjmallett * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19213762Sjmallett * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20213762Sjmallett * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21213762Sjmallett * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22213762Sjmallett * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23213762Sjmallett * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24213762Sjmallett * SUCH DAMAGE. 25213762Sjmallett * 26213762Sjmallett * $FreeBSD: releng/10.2/sys/mips/cavium/octe/mv88e61xxphyreg.h 213762 2010-10-13 09:17:44Z jmallett $ 27213762Sjmallett */ 28213762Sjmallett 29213762Sjmallett/* 30213762Sjmallett * Register definitions for Marvell MV88E61XX 31213762Sjmallett * 32213762Sjmallett * Note that names and definitions were gleaned from Linux and U-Boot patches 33213762Sjmallett * released by Marvell, often by looking at contextual use of the registers 34213762Sjmallett * involved, and may not be representative of the full functionality of those 35213762Sjmallett * registers and are certainly not an exhaustive enumeration of registers. 36213762Sjmallett * 37213762Sjmallett * For an exhaustive enumeration of registers, check out the QD-DSDT package 38213762Sjmallett * included in the Marvell ARM Feroceon Board Support Package for Linux. 39213762Sjmallett */ 40213762Sjmallett 41213762Sjmallett#ifndef _MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_ 42213762Sjmallett#define _MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_ 43213762Sjmallett 44213762Sjmallett/* 45213762Sjmallett * Port addresses & per-port registers. 46213762Sjmallett */ 47213762Sjmallett#define MV88E61XX_PORT(x) (0x10 + (x)) 48213762Sjmallett#define MV88E61XX_HOST_PORT (5) 49213762Sjmallett#define MV88E61XX_PORTS (6) 50213762Sjmallett 51213762Sjmallett#define MV88E61XX_PORT_STATUS (0x00) 52213762Sjmallett#define MV88E61XX_PORT_FORCE_MAC (0x01) 53213762Sjmallett#define MV88E61XX_PORT_PAUSE_CONTROL (0x02) 54213762Sjmallett#define MV88E61XX_PORT_REVISION (0x03) 55213762Sjmallett#define MV88E61XX_PORT_CONTROL (0x04) 56213762Sjmallett#define MV88E61XX_PORT_CONTROL2 (0x05) 57213762Sjmallett#define MV88E61XX_PORT_VLAN_MAP (0x06) 58213762Sjmallett#define MV88E61XX_PORT_VLAN (0x07) 59213762Sjmallett#define MV88E61XX_PORT_FILTER (0x08) 60213762Sjmallett#define MV88E61XX_PORT_EGRESS_CONTROL (0x09) 61213762Sjmallett#define MV88E61XX_PORT_EGRESS_CONTROL2 (0x0a) 62213762Sjmallett#define MV88E61XX_PORT_PORT_LEARN (0x0b) 63213762Sjmallett#define MV88E61XX_PORT_ATU_CONTROL (0x0c) 64213762Sjmallett#define MV88E61XX_PORT_PRIORITY_CONTROL (0x0d) 65213762Sjmallett#define MV88E61XX_PORT_ETHER_PROTO (0x0f) 66213762Sjmallett#define MV88E61XX_PORT_PROVIDER_PROTO (0x1a) 67213762Sjmallett#define MV88E61XX_PORT_PRIORITY_MAP (0x18) 68213762Sjmallett#define MV88E61XX_PORT_PRIORITY_MAP2 (0x19) 69213762Sjmallett 70213762Sjmallett/* 71213762Sjmallett * Fields and values in each register. 72213762Sjmallett */ 73213762Sjmallett#define MV88E61XX_PORT_STATUS_MEDIA (0x0300) 74213762Sjmallett#define MV88E61XX_PORT_STATUS_MEDIA_10M (0x0000) 75213762Sjmallett#define MV88E61XX_PORT_STATUS_MEDIA_100M (0x0100) 76213762Sjmallett#define MV88E61XX_PORT_STATUS_MEDIA_1G (0x0200) 77213762Sjmallett#define MV88E61XX_PORT_STATUS_DUPLEX (0x0400) 78213762Sjmallett#define MV88E61XX_PORT_STATUS_LINK (0x0800) 79213762Sjmallett#define MV88E61XX_PORT_STATUS_FC (0x8000) 80213762Sjmallett 81213762Sjmallett#define MV88E61XX_PORT_CONTROL_DOUBLE_TAG (0x0200) 82213762Sjmallett 83213762Sjmallett#define MV88E61XX_PORT_FILTER_MAP_DEST (0x0080) 84213762Sjmallett#define MV88E61XX_PORT_FILTER_DISCARD_UNTAGGED (0x0100) 85213762Sjmallett#define MV88E61XX_PORT_FILTER_DISCARD_TAGGED (0x0200) 86213762Sjmallett#define MV88E61XX_PORT_FILTER_8021Q_MODE (0x0c00) 87213762Sjmallett#define MV88E61XX_PORT_FILTER_8021Q_DISABLED (0x0000) 88213762Sjmallett#define MV88E61XX_PORT_FILTER_8021Q_FALLBACK (0x0400) 89213762Sjmallett#define MV88E61XX_PORT_FILTER_8021Q_CHECK (0x0800) 90213762Sjmallett#define MV88E61XX_PORT_FILTER_8021Q_SECURE (0x0c00) 91213762Sjmallett 92213762Sjmallett/* 93213762Sjmallett * Global address & global registers. 94213762Sjmallett */ 95213762Sjmallett#define MV88E61XX_GLOBAL (0x1b) 96213762Sjmallett 97213762Sjmallett#define MV88E61XX_GLOBAL_STATUS (0x00) 98213762Sjmallett#define MV88E61XX_GLOBAL_CONTROL (0x04) 99213762Sjmallett#define MV88E61XX_GLOBAL_VTU_OP (0x05) 100213762Sjmallett#define MV88E61XX_GLOBAL_VTU_VID (0x06) 101213762Sjmallett#define MV88E61XX_GLOBAL_VTU_DATA_P0P3 (0x07) 102213762Sjmallett#define MV88E61XX_GLOBAL_VTU_DATA_P4P5 (0x08) 103213762Sjmallett#define MV88E61XX_GLOBAL_ATU_CONTROL (0x0a) 104213762Sjmallett#define MV88E61XX_GLOBAL_PRIORITY_MAP (0x18) 105213762Sjmallett#define MV88E61XX_GLOBAL_MONITOR (0x1a) 106213762Sjmallett#define MV88E61XX_GLOBAL_REMOTE_MGMT (0x1c) 107213762Sjmallett#define MV88E61XX_GLOBAL_STATS (0x1d) 108213762Sjmallett 109213762Sjmallett/* 110213762Sjmallett * Fields and values in each register. 111213762Sjmallett */ 112213762Sjmallett#define MV88E61XX_GLOBAL_VTU_OP_BUSY (0x8000) 113213762Sjmallett#define MV88E61XX_GLOBAL_VTU_OP_OP (0x7000) 114213762Sjmallett#define MV88E61XX_GLOBAL_VTU_OP_OP_FLUSH (0x1000) 115213762Sjmallett#define MV88E61XX_GLOBAL_VTU_OP_OP_VTU_LOAD (0x3000) 116213762Sjmallett 117213762Sjmallett#define MV88E61XX_GLOBAL_VTU_VID_VALID (0x1000) 118213762Sjmallett 119213762Sjmallett/* 120213762Sjmallett * Second global address & second global registers. 121213762Sjmallett */ 122213762Sjmallett#define MV88E61XX_GLOBAL2 (0x1c) 123213762Sjmallett 124213762Sjmallett#define MV88E61XX_GLOBAL2_MANAGE_2X (0x02) 125213762Sjmallett#define MV88E61XX_GLOBAL2_MANAGE_0X (0x03) 126213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2 (0x05) 127213762Sjmallett#define MV88E61XX_GLOBAL2_TRUNK_MASK (0x07) 128213762Sjmallett#define MV88E61XX_GLOBAL2_TRUNK_MAP (0x08) 129213762Sjmallett#define MV88E61XX_GLOBAL2_RATELIMIT (0x09) 130213762Sjmallett#define MV88E61XX_GLOBAL2_VLAN_CONTROL (0x0b) 131213762Sjmallett#define MV88E61XX_GLOBAL2_MAC_ADDRESS (0x0d) 132213762Sjmallett 133213762Sjmallett/* 134213762Sjmallett * Fields and values in each register. 135213762Sjmallett */ 136213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_DOUBLE_USE (0x8000) 137213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_LOOP_PREVENT (0x4000) 138213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_FLOW_MESSAGE (0x2000) 139213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_FLOOD_BC (0x1000) 140213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_REMOVE_PTAG (0x0800) 141213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_AGE_INT (0x0400) 142213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_FLOW_TAG (0x0200) 143213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_ALWAYS_VTU (0x0100) 144213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_FORCE_FC_PRI (0x0080) 145213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_FC_PRI (0x0070) 146213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_MGMT_TO_HOST (0x0008) 147213762Sjmallett#define MV88E61XX_GLOBAL2_CONTROL2_MGMT_PRI (0x0007) 148213762Sjmallett 149213762Sjmallett#endif /* !_MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_ */ 150