if_argevar.h revision 199234 
1/*-
2 * Copyright (c) 2009, Oleksandr Tymoshenko
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice unmodified, this list of conditions, and the following
10 *    disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#ifndef __IF_ARGEVAR_H__
29#define __IF_ARGEVAR_H__
30
31#define	ARGE_NPHY		32
32#define	ARGE_TX_RING_COUNT	128
33#define	ARGE_RX_RING_COUNT	128
34#define	ARGE_RX_DMA_SIZE	ARGE_RX_RING_COUNT * sizeof(struct arge_desc)
35#define	ARGE_TX_DMA_SIZE	ARGE_TX_RING_COUNT * sizeof(struct arge_desc)
36#define	ARGE_MAXFRAGS		8
37#define ARGE_RING_ALIGN		sizeof(struct arge_desc)
38#define ARGE_RX_ALIGN		sizeof(uint32_t)
39#define ARGE_MAXFRAGS		8
40#define	ARGE_TX_RING_ADDR(sc, i)	\
41    ((sc)->arge_rdata.arge_tx_ring_paddr + sizeof(struct arge_desc) * (i))
42#define	ARGE_RX_RING_ADDR(sc, i)	\
43    ((sc)->arge_rdata.arge_rx_ring_paddr + sizeof(struct arge_desc) * (i))
44#define	ARGE_INC(x,y)		(x) = (((x) + 1) % y)
45
46
47#define	ARGE_MII_TIMEOUT	1000
48
49#define	ARGE_LOCK(_sc)		mtx_lock(&(_sc)->arge_mtx)
50#define	ARGE_UNLOCK(_sc)	mtx_unlock(&(_sc)->arge_mtx)
51#define	ARGE_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->arge_mtx, MA_OWNED)
52
53/*
54 * register space access macros
55 */
56#define ARGE_WRITE(sc, reg, val)	do {	\
57		bus_write_4(sc->arge_res, (reg), (val)); \
58	} while (0)
59
60#define ARGE_READ(sc, reg)	 bus_read_4(sc->arge_res, (reg))
61
62#define ARGE_SET_BITS(sc, reg, bits)	\
63	ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) | (bits))
64
65#define ARGE_CLEAR_BITS(sc, reg, bits)	\
66	ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) & ~(bits))
67
68/*
69 * MII registers access macros
70 */
71#define ARGE_MII_READ(reg) \
72        *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((AR71XX_MII_BASE + reg)))
73
74#define ARGE_MII_WRITE(reg, val) \
75        *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((AR71XX_MII_BASE + reg))) = (val)
76
77
78#define ARGE_DESC_EMPTY		(1 << 31)
79#define ARGE_DESC_MORE		(1 << 24)
80#define ARGE_DESC_SIZE_MASK	((1 << 12) - 1)
81#define	ARGE_DMASIZE(len)	((len) & ARGE_DESC_SIZE_MASK)
82struct arge_desc {
83	uint32_t	packet_addr;
84	uint32_t	packet_ctrl;
85	uint32_t	next_desc;
86	uint32_t	padding;
87};
88
89struct arge_txdesc {
90	struct mbuf	*tx_m;
91	bus_dmamap_t	tx_dmamap;
92};
93
94struct arge_rxdesc {
95	struct mbuf		*rx_m;
96	bus_dmamap_t		rx_dmamap;
97	struct arge_desc	*desc;
98};
99
100struct arge_chain_data {
101	bus_dma_tag_t		arge_parent_tag;
102	bus_dma_tag_t		arge_tx_tag;
103	struct arge_txdesc	arge_txdesc[ARGE_TX_RING_COUNT];
104	bus_dma_tag_t		arge_rx_tag;
105	struct arge_rxdesc	arge_rxdesc[ARGE_RX_RING_COUNT];
106	bus_dma_tag_t		arge_tx_ring_tag;
107	bus_dma_tag_t		arge_rx_ring_tag;
108	bus_dmamap_t		arge_tx_ring_map;
109	bus_dmamap_t		arge_rx_ring_map;
110	bus_dmamap_t		arge_rx_sparemap;
111	int			arge_tx_pkts;
112	int			arge_tx_prod;
113	int			arge_tx_cons;
114	int			arge_tx_cnt;
115	int			arge_rx_cons;
116};
117
118struct arge_ring_data {
119	struct arge_desc	*arge_rx_ring;
120	struct arge_desc	*arge_tx_ring;
121	bus_addr_t		arge_rx_ring_paddr;
122	bus_addr_t		arge_tx_ring_paddr;
123};
124
125struct arge_softc {
126	struct ifnet		*arge_ifp;	/* interface info */
127	device_t		arge_dev;
128	struct ifmedia		arge_ifmedia;
129	/*
130	 * Media & duples settings for multiPHY MAC
131	 */
132	uint32_t		arge_media_type;
133	uint32_t		arge_duplex_mode;
134	struct resource		*arge_res;
135	int			arge_rid;
136	struct resource		*arge_irq;
137	void			*arge_intrhand;
138	device_t		arge_miibus;
139	bus_dma_tag_t		arge_parent_tag;
140	bus_dma_tag_t		arge_tag;
141	struct mtx		arge_mtx;
142	struct callout		arge_stat_callout;
143	struct task		arge_link_task;
144	struct arge_chain_data	arge_cdata;
145	struct arge_ring_data	arge_rdata;
146	int			arge_link_status;
147	int			arge_detach;
148	uint32_t		arge_intr_status;
149	int			arge_mac_unit;
150	int			arge_phymask;
151	uint32_t		arge_ddr_flush_reg;
152	uint32_t		arge_pll_reg;
153	uint32_t		arge_pll_reg_shift;
154	int			arge_if_flags;
155};
156
157#endif /* __IF_ARGEVAR_H__ */
158