aureg.h revision 202032
1219820Sjeff/* $NetBSD: aureg.h,v 1.18 2006/10/02 06:44:00 gdamore Exp $ */ 2219820Sjeff 3219820Sjeff/* 4219820Sjeff * Copyright 2002 Wasabi Systems, Inc. 5293151Shselasky * All rights reserved. 6219820Sjeff * 7219820Sjeff * Written by Simon Burge for Wasabi Systems, Inc. 8219820Sjeff * 9219820Sjeff * Redistribution and use in source and binary forms, with or without 10219820Sjeff * modification, are permitted provided that the following conditions 11219820Sjeff * are met: 12219820Sjeff * 1. Redistributions of source code must retain the above copyright 13219820Sjeff * notice, this list of conditions and the following disclaimer. 14219820Sjeff * 2. Redistributions in binary form must reproduce the above copyright 15219820Sjeff * notice, this list of conditions and the following disclaimer in the 16219820Sjeff * documentation and/or other materials provided with the distribution. 17219820Sjeff * 3. All advertising materials mentioning features or use of this software 18219820Sjeff * must display the following acknowledgement: 19219820Sjeff * This product includes software developed for the NetBSD Project by 20219820Sjeff * Wasabi Systems, Inc. 21219820Sjeff * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22219820Sjeff * or promote products derived from this software without specific prior 23219820Sjeff * written permission. 24219820Sjeff * 25219820Sjeff * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26219820Sjeff * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27219820Sjeff * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28219820Sjeff * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29219820Sjeff * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30219820Sjeff * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31219820Sjeff * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32219820Sjeff * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33219820Sjeff * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34219820Sjeff * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35219820Sjeff * POSSIBILITY OF SUCH DAMAGE. 36219820Sjeff */ 37293151Shselasky 38293151Shselasky#ifndef _MIPS_ALCHEMY_AUREG_H 39219820Sjeff#define _MIPS_ALCHEMY_AUREG_H 40219820Sjeff 41219820Sjeff/************************************************************************/ 42219820Sjeff/******************** AC97 Controller registers *********************/ 43293151Shselasky/************************************************************************/ 44219820Sjeff#define AC97_BASE 0x10000000 45219820Sjeff 46219820Sjeff/************************************************************************/ 47219820Sjeff/*********************** USB Host registers *************************/ 48219820Sjeff/************************************************************************/ 49219820Sjeff#define USBH_BASE 0x10100000 50219820Sjeff#define AU1550_USBH_BASE 0x14020000 51219820Sjeff 52293151Shselasky#define USBH_ENABLE 0x7fffc 53293151Shselasky#define USBH_SIZE 0x100000 54219820Sjeff 55219820Sjeff#define AU1550_USBH_ENABLE 0x7ffc 56219820Sjeff#define AU1550_USBH_SIZE 0x60000 57219820Sjeff 58219820Sjeff/************************************************************************/ 59293151Shselasky/********************** USB Device registers ************************/ 60293151Shselasky/************************************************************************/ 61293151Shselasky#define USBD_BASE 0x10200000 62293151Shselasky 63293151Shselasky/************************************************************************/ 64293151Shselasky/************************* IRDA registers ***************************/ 65219820Sjeff/************************************************************************/ 66219820Sjeff#define IRDA_BASE 0x10300000 67219820Sjeff 68219820Sjeff/************************************************************************/ 69219820Sjeff/****************** Interrupt Controller registers ******************/ 70219820Sjeff/************************************************************************/ 71219820Sjeff 72219820Sjeff#define IC0_BASE 0x10400000 73219820Sjeff#define IC1_BASE 0x11800000 74219820Sjeff 75219820Sjeff/* 76293151Shselasky * The *_READ registers read the current value of the register 77219820Sjeff * The *_SET registers set to 1 all bits that are written 1 78219820Sjeff * The *_CLEAR registers clear to zero all bits that are written as 1 79219820Sjeff */ 80219820Sjeff#define IC_CONFIG0_READ 0x40 /* See table below */ 81219820Sjeff#define IC_CONFIG0_SET 0x40 82314667Savg#define IC_CONFIG0_CLEAR 0x44 83219820Sjeff 84219820Sjeff#define IC_CONFIG1_READ 0x48 /* See table below */ 85293151Shselasky#define IC_CONFIG1_SET 0x48 86219820Sjeff#define IC_CONFIG1_CLEAR 0x4c 87219820Sjeff 88219820Sjeff#define IC_CONFIG2_READ 0x50 /* See table below */ 89219820Sjeff#define IC_CONFIG2_SET 0x50 90219820Sjeff#define IC_CONFIG2_CLEAR 0x54 91219820Sjeff 92219820Sjeff#define IC_REQUEST0_INT 0x54 /* Show active interrupts on request 0 */ 93219820Sjeff 94219820Sjeff#define IC_SOURCE_READ 0x58 /* Interrupt source */ 95293151Shselasky#define IC_SOURCE_SET 0x58 /* 0 - test bit used as source */ 96293151Shselasky#define IC_SOURCE_CLEAR 0x5c /* 1 - peripheral/GPIO used as source */ 97271127Shselasky 98293151Shselasky#define IC_REQUEST1_INT 0x5c /* Show active interrupts on request 1 */ 99293151Shselasky 100293151Shselasky#define IC_ASSIGN_REQUEST_READ 0x60 /* Assigns the interrupt to one of the */ 101293151Shselasky#define IC_ASSIGN_REQUEST_SET 0x60 /* CPU requests (0 - assign to request 1, */ 102293151Shselasky#define IC_ASSIGN_REQUEST_CLEAR 0x64 /* 1 - assign to request 0) */ 103293151Shselasky 104271127Shselasky#define IC_WAKEUP_READ 0x68 /* Controls whether the interrupt can */ 105219820Sjeff#define IC_WAKEUP_SET 0x68 /* cause a wakeup from IDLE */ 106219820Sjeff#define IC_WAKEUP_CLEAR 0x6c 107219820Sjeff 108219820Sjeff#define IC_MASK_READ 0x70 /* Enables/Disables the interrupt */ 109219820Sjeff#define IC_MASK_SET 0x70 110219820Sjeff#define IC_MASK_CLEAR 0x74 111219820Sjeff 112219820Sjeff#define IC_RISING_EDGE 0x78 /* Check/clear rising edge */ 113293151Shselasky 114293151Shselasky#define IC_FALLING_EDGE 0x7c /* Check/clear falling edge */ 115293151Shselasky 116293151Shselasky#define IC_TEST_BIT 0x80 /* single bit source select */ 117293151Shselasky 118293151Shselasky/* 119293151Shselasky * Interrupt Configuration Register Functions 120293151Shselasky * 121293151Shselasky * Cfg2[n] Cfg1[n] Cfg0[n] Function 122293151Shselasky * 0 0 0 Interrupts Disabled 123219820Sjeff * 0 0 1 Rising Edge Enabled 124219820Sjeff * 0 1 0 Falling Edge Enabled 125219820Sjeff * 0 1 1 Rising and Falling Edge Enabled 126293151Shselasky * 1 0 0 Interrupts Disabled 127293151Shselasky * 1 0 1 High Level Enabled 128293151Shselasky * 1 1 0 Low Level Enabled 129255932Salfred * 1 1 1 Both Levels and Both Edges Enabled 130293151Shselasky */ 131255932Salfred 132293151Shselasky/************************************************************************/ 133293151Shselasky/************* Programable Serial Controller registers **************/ 134293151Shselasky/************************************************************************/ 135219820Sjeff 136219820Sjeff#define PSC0_BASE 0x11A00000 137219820Sjeff#define PSC1_BASE 0x11B00000 138293151Shselasky#define PSC2_BASE 0x10A00000 139219820Sjeff#define PSC3_BASE 0x10B00000 140219820Sjeff 141293151Shselasky 142219820Sjeff/************************************************************************/ 143293151Shselasky/********************** Ethernet MAC registers **********************/ 144293151Shselasky/************************************************************************/ 145219820Sjeff 146293151Shselasky#define MAC0_BASE 0x10500000 147293151Shselasky#define MAC1_BASE 0x10510000 148293151Shselasky#define MACx_SIZE 0x28 149219820Sjeff 150219820Sjeff#define AU1500_MAC0_BASE 0x11500000 /* Grr, different on Au1500 */ 151219820Sjeff#define AU1500_MAC1_BASE 0x11510000 /* Grr, different on Au1500 */ 152219820Sjeff 153219820Sjeff#define MAC0_ENABLE 0x10520000 154219820Sjeff#define MAC1_ENABLE 0x10520004 155219820Sjeff#define MACENx_SIZE 0x04 156221055Sjeff 157293151Shselasky#define AU1500_MAC0_ENABLE 0x11520000 /* Grr, different on Au1500 */ 158219820Sjeff#define AU1500_MAC1_ENABLE 0x11520004 /* Grr, different on Au1500 */ 159219820Sjeff 160221055Sjeff#define MAC0_DMA_BASE 0x14004000 161219820Sjeff#define MAC1_DMA_BASE 0x14004200 162219820Sjeff#define MACx_DMA_SIZE 0x140 163293151Shselasky 164293151Shselasky/************************************************************************/ 165293151Shselasky/********************** Static Bus registers ************************/ 166293151Shselasky/************************************************************************/ 167293151Shselasky#define STATIC_BUS_BASE 0x14001000 168293151Shselasky 169293151Shselasky/************************************************************************/ 170293151Shselasky/******************** Secure Digital registers **********************/ 171219820Sjeff/************************************************************************/ 172219820Sjeff#define SD0_BASE 0x10600000 173219820Sjeff#define SD1_BASE 0x10680000 174219820Sjeff 175219820Sjeff/************************************************************************/ 176219820Sjeff/************************* I^2S registers ***************************/ 177219820Sjeff/************************************************************************/ 178219820Sjeff#define I2S_BASE 0x11000000 179219820Sjeff 180219820Sjeff/************************************************************************/ 181219820Sjeff/************************** UART registers **************************/ 182219820Sjeff/************************************************************************/ 183219820Sjeff 184219820Sjeff#define UART0_BASE 0x11100000 185219820Sjeff#define UART1_BASE 0x11200000 186219820Sjeff#define UART2_BASE 0x11300000 187219820Sjeff#define UART3_BASE 0x11400000 188250374Sdelphij 189250374Sdelphij/************************************************************************/ 190250374Sdelphij/************************* SSI registers ****************************/ 191219820Sjeff/************************************************************************/ 192219820Sjeff#define SSI0_BASE 0x11600000 193219820Sjeff#define SSI1_BASE 0x11680000 194255932Salfred 195255932Salfred/************************************************************************/ 196255932Salfred/************************ GPIO2 registers ***************************/ 197255932Salfred/************************************************************************/ 198255932Salfred#define GPIO_BASE 0x11900100 199255932Salfred 200255932Salfred/************************************************************************/ 201255932Salfred/************************ GPIO2 registers ***************************/ 202255932Salfred/************************************************************************/ 203255932Salfred#define GPIO2_BASE 0x11700000 204255932Salfred 205271127Shselasky/************************************************************************/ 206271127Shselasky/************************* PCI registers ****************************/ 207293151Shselasky/************************************************************************/ 208271127Shselasky#define PCI_BASE 0x14005000 209271127Shselasky#define PCI_HEADER 0x14005100 210271127Shselasky#define PCI_MEM_BASE 0x400000000ULL 211271127Shselasky#define PCI_IO_BASE 0x500000000ULL 212271127Shselasky#define PCI_CONFIG_BASE 0x600000000ULL 213271127Shselasky 214219820Sjeff/************************************************************************/ 215/*********************** PCMCIA registers ***************************/ 216/************************************************************************/ 217#define PCMCIA_BASE 0xF00000000ULL 218 219/************************************************************************/ 220/****************** Programmable Counter registers ******************/ 221/************************************************************************/ 222 223#define SYS_BASE 0x11900000 224 225#define PC_BASE SYS_BASE 226 227#define PC_TRIM0 0x00 /* PC0 Divide (16 bits) */ 228#define PC_COUNTER_WRITE0 0x04 /* set PC0 */ 229#define PC_MATCH0_0 0x08 /* match counter & interrupt */ 230#define PC_MATCH1_0 0x0c /* match counter & interrupt */ 231#define PC_MATCH2_0 0x10 /* match counter & interrupt */ 232#define PC_COUNTER_CONTROL 0x14 /* Programmable Counter Control */ 233#define CC_E1S 0x00800000 /* Enable PC1 write status */ 234#define CC_T1S 0x00100000 /* Trim PC1 write status */ 235#define CC_M21 0x00080000 /* Match 2 of PC1 write status */ 236#define CC_M11 0x00040000 /* Match 1 of PC1 write status */ 237#define CC_M01 0x00020000 /* Match 0 of PC1 write status */ 238#define CC_C1S 0x00010000 /* PC1 write status */ 239#define CC_BP 0x00004000 /* Bypass OSC (use GPIO1) */ 240#define CC_EN1 0x00002000 /* Enable PC1 */ 241#define CC_BT1 0x00001000 /* Bypass Trim on PC1 */ 242#define CC_EN0 0x00000800 /* Enable PC0 */ 243#define CC_BT0 0x00000400 /* Bypass Trim on PC0 */ 244#define CC_EO 0x00000100 /* Enable Oscillator */ 245#define CC_E0S 0x00000080 /* Enable PC0 write status */ 246#define CC_32S 0x00000020 /* 32.768kHz OSC status */ 247#define CC_T0S 0x00000010 /* Trim PC0 write status */ 248#define CC_M20 0x00000008 /* Match 2 of PC0 write status */ 249#define CC_M10 0x00000004 /* Match 1 of PC0 write status */ 250#define CC_M00 0x00000002 /* Match 0 of PC0 write status */ 251#define CC_C0S 0x00000001 /* PC0 write status */ 252#define PC_COUNTER_READ_0 0x40 /* get PC0 */ 253#define PC_TRIM1 0x44 /* PC1 Divide (16 bits) */ 254#define PC_COUNTER_WRITE1 0x48 /* set PC1 */ 255#define PC_MATCH0_1 0x4c /* match counter & interrupt */ 256#define PC_MATCH1_1 0x50 /* match counter & interrupt */ 257#define PC_MATCH2_1 0x54 /* match counter & interrupt */ 258#define PC_COUNTER_READ_1 0x58 /* get PC1 */ 259 260#define PC_SIZE 0x5c /* size of register set */ 261#define PC_RATE 32768 /* counter rate is 32.768kHz */ 262 263/************************************************************************/ 264/******************* Frequency Generator Registers ******************/ 265/************************************************************************/ 266 267#define SYS_FREQCTRL0 (SYS_BASE + 0x20) 268#define SFC_FRDIV2(f) (f<<22) /* 29:22. Freq Divider 2 */ 269#define SFC_FE2 (1<<21) /* Freq generator output enable 2 */ 270#define SFC_FS2 (1<<20) /* Freq generator source 2 */ 271#define SFC_FRDIV1(f) (f<<12) /* 19:12. Freq Divider 1 */ 272#define SFC_FE1 (1<<11) /* Freq generator output enable 1 */ 273#define SFC_FS1 (1<<10) /* Freq generator source 1 */ 274#define SFC_FRDIV0(f) (f<<2) /* 9:2. Freq Divider 0 */ 275#define SFC_FE0 2 /* Freq generator output enable 0 */ 276#define SFC_FS0 1 /* Freq generator source 0 */ 277 278#define SYS_FREQCTRL1 (SYS_BASE + 0x24) 279#define SFC_FRDIV5(f) (f<<22) /* 29:22. Freq Divider 5 */ 280#define SFC_FE5 (1<<21) /* Freq generator output enable 5 */ 281#define SFC_FS5 (1<<20) /* Freq generator source 5 */ 282#define SFC_FRDIV4(f) (f<<12) /* 19:12. Freq Divider 4 */ 283#define SFC_FE4 (1<<11) /* Freq generator output enable 4 */ 284#define SFC_FS4 (1<<10) /* Freq generator source 4 */ 285#define SFC_FRDIV3(f) (f<<2) /* 9:2. Freq Divider 3 */ 286#define SFC_FE3 2 /* Freq generator output enable 3 */ 287#define SFC_FS3 1 /* Freq generator source 3 */ 288 289/************************************************************************/ 290/****************** Clock Source Control Registers ******************/ 291/************************************************************************/ 292 293#define SYS_CLKSRC (SYS_BASE + 0x28) 294#define SCS_ME1(n) (n<<27) /* EXTCLK1 Clock Mux input select */ 295#define SCS_ME0(n) (n<<22) /* EXTCLK0 Clock Mux input select */ 296#define SCS_MPC(n) (n<<17) /* PCI clock mux input select */ 297#define SCS_MUH(n) (n<<12) /* USB Host clock mux input select */ 298#define SCS_MUD(n) (n<<7) /* USB Device clock mux input select */ 299#define SCS_MEx_AUX 0x1 /* Aux clock */ 300#define SCS_MEx_FREQ0 0x2 /* FREQ0 */ 301#define SCS_MEx_FREQ1 0x3 /* FREQ1 */ 302#define SCS_MEx_FREQ2 0x4 /* FREQ2 */ 303#define SCS_MEx_FREQ3 0x5 /* FREQ3 */ 304#define SCS_MEx_FREQ4 0x6 /* FREQ4 */ 305#define SCS_MEx_FREQ5 0x7 /* FREQ5 */ 306#define SCS_DE1 (1<<26) /* EXTCLK1 clock divider select */ 307#define SCS_CE1 (1<<25) /* EXTCLK1 clock select */ 308#define SCS_DE0 (1<<21) /* EXTCLK0 clock divider select */ 309#define SCS_CE0 (1<<20) /* EXTCLK0 clock select */ 310#define SCS_DPC (1<<16) /* PCI clock divider select */ 311#define SCS_CPC (1<<15) /* PCI clock select */ 312#define SCS_DUH (1<<11) /* USB Host clock divider select */ 313#define SCS_CUH (1<<10) /* USB Host clock select */ 314#define SCS_DUD (1<<6) /* USB Device clock divider select */ 315#define SCS_CUD (1<<5) /* USB Device clock select */ 316/* 317 * Au1550 bits, needed for PSCs. Note that some bits collide with 318 * earlier parts. On Au1550, USB clocks (both device and host) are 319 * shared with PSC2, and must be configured for 48MHz. DBAU1550 YAMON 320 * does this by default. Also, EXTCLK0 is shared with PSC3. DBAU1550 321 * YAMON does not configure any clocks besides PSC2. 322 */ 323#define SCS_MP3(n) (n<<22) /* psc3_intclock mux */ 324#define SCS_DP3 (1<<21) /* psc3_intclock divider */ 325#define SCS_CP3 (1<<20) /* psc3_intclock select */ 326#define SCS_MP1(n) (n<<12) /* psc1_intclock mux */ 327#define SCS_DP1 (1<<11) /* psc1_intclock divider */ 328#define SCS_CP1 (1<<10) /* psc1_intclock select */ 329#define SCS_MP0(n) (n<<7) /* psc0_intclock mux */ 330#define SCS_DP0 (1<<6) /* psc0_intclock divider */ 331#define SCS_CP0 (1<<5) /* psc0_intclock seelct */ 332#define SCS_MP2(n) (n<<2) /* psc2_intclock mux */ 333#define SCS_DP2 (1<<1) /* psc2_intclock divider */ 334#define SCS_CP2 (1<<0) /* psc2_intclock select */ 335 336/************************************************************************/ 337/*************************** PIN Function *****************************/ 338/************************************************************************/ 339 340#define SYS_PINFUNC (SYS_BASE + 0x2c) 341#define SPF_PSC3_MASK (7<<20) 342#define SPF_PSC3_AC97 (0<<17) /* select AC97/SPI */ 343#define SPF_PSC3_I2S (1<<17) /* select I2S */ 344#define SPF_PSC3_SMBUS (3<<17) /* select SMbus */ 345#define SPF_PSC3_GPIO (7<<17) /* select gpio215:211 */ 346#define SPF_PSC2_MASK (7<<17) 347#define SPF_PSC2_AC97 (0<<17) /* select AC97/SPI */ 348#define SPF_PSC2_I2S (1<<17) /* select I2S */ 349#define SPF_PSC2_SMBUS (3<<17) /* select SMbus */ 350#define SPF_PSC2_GPIO (7<<17) /* select gpio210:206*/ 351#define SPF_CS (1<<16) /* extclk0 or 32kHz osc */ 352#define SPF_USB (1<<15) /* host or device usb otg */ 353#define SPF_U3T (1<<14) /* uart3 tx or gpio23 */ 354#define SPF_U1R (1<<13) /* uart1 rx or gpio22 */ 355#define SPF_U1T (1<<12) /* uart1 tx or gpio21 */ 356#define SPF_EX1 (1<<10) /* gpio3 or extclk1 */ 357#define SPF_EX0 (1<<9) /* gpio2 or extclk0/32kHz osc*/ 358#define SPF_U3 (1<<7) /* gpio14:9 or uart3 */ 359#define SPF_MBSa (1<<5) /* must be set */ 360#define SPF_NI2 (1<<4) /* enet1 or gpio28:24 */ 361#define SPF_U0 (1<<3) /* uart0 or gpio20 */ 362#define SPF_MBSb (1<<2) /* must be set */ 363#define SPF_S1 (1<<1) /* gpio17 or psc1_sync1 */ 364#define SPF_S0 (1<<0) /* gpio16 or psc0_sync1 */ 365 366/************************************************************************/ 367/*************************** PLL Control *****************************/ 368/************************************************************************/ 369 370#define SYS_CPUPLL (SYS_BASE + 0x60) 371#define SYS_AUXPLL (SYS_BASE + 0x64) 372 373#endif /* _MIPS_ALCHEMY_AUREG_H */ 374