cpufunc.h revision 84581
1230557Sjimharris/*- 2230557Sjimharris * Copyright (c) 1998 Doug Rabson 3230557Sjimharris * All rights reserved. 4230557Sjimharris * 5230557Sjimharris * Redistribution and use in source and binary forms, with or without 6230557Sjimharris * modification, are permitted provided that the following conditions 7230557Sjimharris * are met: 8230557Sjimharris * 1. Redistributions of source code must retain the above copyright 9230557Sjimharris * notice, this list of conditions and the following disclaimer. 10230557Sjimharris * 2. Redistributions in binary form must reproduce the above copyright 11230557Sjimharris * notice, this list of conditions and the following disclaimer in the 12230557Sjimharris * documentation and/or other materials provided with the distribution. 13230557Sjimharris * 14230557Sjimharris * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15230557Sjimharris * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16230557Sjimharris * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17230557Sjimharris * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18230557Sjimharris * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19230557Sjimharris * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20230557Sjimharris * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21230557Sjimharris * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22230557Sjimharris * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23230557Sjimharris * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24230557Sjimharris * SUCH DAMAGE. 25230557Sjimharris * 26230557Sjimharris * $FreeBSD: head/sys/ia64/include/cpufunc.h 84581 2001-10-06 09:31:43Z marcel $ 27230557Sjimharris */ 28230557Sjimharris 29230557Sjimharris#ifndef _MACHINE_CPUFUNC_H_ 30230557Sjimharris#define _MACHINE_CPUFUNC_H_ 31230557Sjimharris 32230557Sjimharris#ifdef _KERNEL 33230557Sjimharris 34230557Sjimharris#include <sys/types.h> 35230557Sjimharris#include <machine/ia64_cpu.h> 36230557Sjimharris 37230557Sjimharris#ifdef __GNUC__ 38230557Sjimharris 39230557Sjimharrisstatic __inline void 40230557Sjimharrisbreakpoint(void) 41230557Sjimharris{ 42230557Sjimharris __asm __volatile("break 0x80100"); /* XXX use linux value */ 43230557Sjimharris} 44230557Sjimharris 45230557Sjimharris#endif 46230557Sjimharris 47230557Sjimharrisextern u_int64_t ia64_port_base; 48230557Sjimharris 49230557Sjimharrisstatic __inline volatile void * 50230557Sjimharrisia64_port_address(u_int port) 51230557Sjimharris{ 52230557Sjimharris return (volatile void *)(ia64_port_base 53230557Sjimharris | ((port >> 2) << 12) 54230557Sjimharris | (port & ((1 << 12) - 1))); 55230557Sjimharris} 56230557Sjimharris 57230557Sjimharrisstatic __inline volatile void * 58230557Sjimharrisia64_memory_address(u_int64_t addr) 59230557Sjimharris{ 60230557Sjimharris return (volatile void *) IA64_PHYS_TO_RR6(addr); 61230557Sjimharris} 62230557Sjimharris 63230557Sjimharrisstatic __inline u_int8_t 64230557Sjimharrisinb(u_int port) 65230557Sjimharris{ 66230557Sjimharris volatile u_int8_t *p = ia64_port_address(port); 67230557Sjimharris u_int8_t v = *p; 68230557Sjimharris ia64_mf_a(); 69230557Sjimharris ia64_mf(); 70230557Sjimharris return v; 71230557Sjimharris} 72230557Sjimharris 73230557Sjimharrisstatic __inline u_int16_t 74230557Sjimharrisinw(u_int port) 75230557Sjimharris{ 76230557Sjimharris volatile u_int16_t *p = ia64_port_address(port); 77230557Sjimharris u_int16_t v = *p; 78230557Sjimharris ia64_mf_a(); 79230557Sjimharris ia64_mf(); 80230557Sjimharris return v; 81230557Sjimharris} 82230557Sjimharris 83230557Sjimharrisstatic __inline u_int32_t 84230557Sjimharrisinl(u_int port) 85230557Sjimharris{ 86230557Sjimharris volatile u_int32_t *p = ia64_port_address(port); 87230557Sjimharris u_int32_t v = *p; 88230557Sjimharris ia64_mf_a(); 89230557Sjimharris ia64_mf(); 90230557Sjimharris return v; 91230557Sjimharris} 92230557Sjimharris 93230557Sjimharrisstatic __inline void 94230557Sjimharrisinsb(u_int port, void *addr, size_t count) 95230557Sjimharris{ 96230557Sjimharris u_int8_t *p = addr; 97230557Sjimharris while (count--) 98230557Sjimharris *p++ = inb(port); 99230557Sjimharris} 100230557Sjimharris 101230557Sjimharrisstatic __inline void 102230557Sjimharrisinsw(u_int port, void *addr, size_t count) 103230557Sjimharris{ 104230557Sjimharris u_int16_t *p = addr; 105230557Sjimharris while (count--) 106230557Sjimharris *p++ = inw(port); 107230557Sjimharris} 108230557Sjimharris 109230557Sjimharrisstatic __inline void 110230557Sjimharrisinsl(u_int port, void *addr, size_t count) 111230557Sjimharris{ 112230557Sjimharris u_int32_t *p = addr; 113230557Sjimharris while (count--) 114230557Sjimharris *p++ = inl(port); 115230557Sjimharris} 116230557Sjimharris 117230557Sjimharrisstatic __inline void 118230557Sjimharrisoutb(u_int port, u_int8_t data) 119230557Sjimharris{ 120230557Sjimharris volatile u_int8_t *p = ia64_port_address(port); 121230557Sjimharris *p = data; 122230557Sjimharris ia64_mf_a(); 123230557Sjimharris ia64_mf(); 124230557Sjimharris} 125230557Sjimharris 126230557Sjimharrisstatic __inline void 127230557Sjimharrisoutw(u_int port, u_int16_t data) 128230557Sjimharris{ 129230557Sjimharris volatile u_int16_t *p = ia64_port_address(port); 130230557Sjimharris *p = data; 131230557Sjimharris ia64_mf_a(); 132230557Sjimharris ia64_mf(); 133230557Sjimharris} 134230557Sjimharris 135230557Sjimharrisstatic __inline void 136outl(u_int port, u_int32_t data) 137{ 138 volatile u_int32_t *p = ia64_port_address(port); 139 *p = data; 140 ia64_mf_a(); 141 ia64_mf(); 142} 143 144static __inline void 145outsb(u_int port, const void *addr, size_t count) 146{ 147 const u_int8_t *p = addr; 148 while (count--) 149 outb(port, *p++); 150} 151 152static __inline void 153outsw(u_int port, const void *addr, size_t count) 154{ 155 const u_int16_t *p = addr; 156 while (count--) 157 outw(port, *p++); 158} 159 160static __inline void 161outsl(u_int port, const void *addr, size_t count) 162{ 163 const u_int32_t *p = addr; 164 while (count--) 165 outl(port, *p++); 166} 167 168static __inline u_int8_t 169readb(u_int addr) 170{ 171 volatile u_int8_t *p = ia64_memory_address(addr); 172 u_int8_t v = *p; 173 ia64_mf_a(); 174 ia64_mf(); 175 return v; 176} 177 178static __inline u_int16_t 179readw(u_int addr) 180{ 181 volatile u_int16_t *p = ia64_memory_address(addr); 182 u_int16_t v = *p; 183 ia64_mf_a(); 184 ia64_mf(); 185 return v; 186} 187 188static __inline u_int32_t 189readl(u_int addr) 190{ 191 volatile u_int32_t *p = ia64_memory_address(addr); 192 u_int32_t v = *p; 193 ia64_mf_a(); 194 ia64_mf(); 195 return v; 196} 197 198static __inline void 199writeb(u_int addr, u_int8_t data) 200{ 201 volatile u_int8_t *p = ia64_memory_address(addr); 202 *p = data; 203 ia64_mf_a(); 204 ia64_mf(); 205} 206 207static __inline void 208writew(u_int addr, u_int16_t data) 209{ 210 volatile u_int16_t *p = ia64_memory_address(addr); 211 *p = data; 212 ia64_mf_a(); 213 ia64_mf(); 214} 215 216static __inline void 217writel(u_int addr, u_int32_t data) 218{ 219 volatile u_int32_t *p = ia64_memory_address(addr); 220 *p = data; 221 ia64_mf_a(); 222 ia64_mf(); 223} 224 225static __inline void 226memcpy_fromio(u_int8_t *addr, size_t ofs, size_t count) 227{ 228 volatile u_int8_t *p = ia64_memory_address(ofs); 229 while (count--) 230 *addr++ = *p++; 231} 232 233static __inline void 234memcpy_io(size_t dst, size_t src, size_t count) 235{ 236 volatile u_int8_t *dp = ia64_memory_address(dst); 237 volatile u_int8_t *sp = ia64_memory_address(src); 238 while (count--) 239 *dp++ = *sp++; 240} 241 242static __inline void 243memcpy_toio(size_t ofs, u_int8_t *addr, size_t count) 244{ 245 volatile u_int8_t *p = ia64_memory_address(ofs); 246 while (count--) 247 *p++ = *addr++; 248} 249 250static __inline void 251memset_io(size_t ofs, u_int8_t value, size_t count) 252{ 253 volatile u_int8_t *p = ia64_memory_address(ofs); 254 while (count--) 255 *p++ = value; 256} 257 258static __inline void 259memsetw(u_int16_t *addr, int val, size_t size) 260{ 261 while (size--) 262 *addr++ = val; 263} 264 265static __inline void 266memsetw_io(size_t ofs, u_int16_t value, size_t count) 267{ 268 volatile u_int16_t *p = ia64_memory_address(ofs); 269 while (count--) 270 *p++ = value; 271} 272 273static __inline void 274disable_intr(void) 275{ 276 __asm __volatile ("rsm psr.i;;"); 277} 278 279static __inline void 280enable_intr(void) 281{ 282 __asm __volatile (";; ssm psr.i;; srlz.d"); 283} 284 285static __inline critical_t 286critical_enter(void) 287{ 288 critical_t psr; 289 290 __asm __volatile ("mov %0=psr;;" : "=r" (psr)); 291 disable_intr(); 292 return (psr); 293} 294 295static __inline void 296critical_exit(critical_t psr) 297{ 298 __asm __volatile ("mov psr.l=%0;; srlz.d" :: "r" (psr)); 299} 300 301#endif /* _KERNEL */ 302 303#endif /* !_MACHINE_CPUFUNC_H_ */ 304