cpufunc.h revision 83836 
1/*-
2 * Copyright (c) 1998 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/ia64/include/cpufunc.h 83836 2001-09-22 19:51:18Z dfr $
27 */
28
29#ifndef _MACHINE_CPUFUNC_H_
30#define _MACHINE_CPUFUNC_H_
31
32#ifdef _KERNEL
33
34#include <sys/types.h>
35#include <machine/ia64_cpu.h>
36
37#ifdef __GNUC__
38
39static __inline void
40breakpoint(void)
41{
42	__asm __volatile("break 0x80100"); /* XXX use linux value */
43}
44
45#endif
46
47extern u_int64_t	ia64_port_base;
48
49static __inline volatile void *
50ia64_port_address(u_int port)
51{
52    return (volatile void *)(ia64_port_base
53			     | ((port >> 2) << 12)
54			     | (port & ((1 << 12) - 1)));
55}
56
57static __inline volatile void *
58ia64_memory_address(u_int addr)
59{
60    return (volatile void *) IA64_PHYS_TO_RR6(addr);;
61}
62
63static __inline u_int8_t
64inb(u_int port)
65{
66	volatile u_int8_t *p = ia64_port_address(port);
67	u_int8_t v = *p;
68	ia64_mf_a();
69	ia64_mf();
70	return v;
71}
72
73static __inline u_int16_t
74inw(u_int port)
75{
76	volatile u_int16_t *p = ia64_port_address(port);
77	u_int16_t v = *p;
78	ia64_mf_a();
79	ia64_mf();
80	return v;
81}
82
83static __inline u_int32_t
84inl(u_int port)
85{
86	volatile u_int32_t *p = ia64_port_address(port);
87	u_int32_t v = *p;
88	ia64_mf_a();
89	ia64_mf();
90	return v;
91}
92
93static __inline void
94insb(u_int port, void *addr, size_t count)
95{
96	u_int8_t *p = addr;
97	while (count--)
98		*p++ = inb(port);
99}
100
101static __inline void
102insw(u_int port, void *addr, size_t count)
103{
104	u_int16_t *p = addr;
105	while (count--)
106		*p++ = inw(port);
107}
108
109static __inline void
110insl(u_int port, void *addr, size_t count)
111{
112	u_int32_t *p = addr;
113	while (count--)
114		*p++ = inl(port);
115}
116
117static __inline void
118outb(u_int port, u_int8_t data)
119{
120	volatile u_int8_t *p = ia64_port_address(port);
121	*p = data;
122	ia64_mf_a();
123	ia64_mf();
124}
125
126static __inline void
127outw(u_int port, u_int16_t data)
128{
129	volatile u_int16_t *p = ia64_port_address(port);
130	*p = data;
131	ia64_mf_a();
132	ia64_mf();
133}
134
135static __inline void
136outl(u_int port, u_int32_t data)
137{
138	volatile u_int32_t *p = ia64_port_address(port);
139	*p = data;
140	ia64_mf_a();
141	ia64_mf();
142}
143
144static __inline void
145outsb(u_int port, const void *addr, size_t count)
146{
147	const u_int8_t *p = addr;
148	while (count--)
149		outb(port, *p++);
150}
151
152static __inline void
153outsw(u_int port, const void *addr, size_t count)
154{
155	const u_int16_t *p = addr;
156	while (count--)
157		outw(port, *p++);
158}
159
160static __inline void
161outsl(u_int port, const void *addr, size_t count)
162{
163	const u_int32_t *p = addr;
164	while (count--)
165		outl(port, *p++);
166}
167
168static __inline u_int8_t
169readb(u_int addr)
170{
171	volatile u_int8_t *p = ia64_memory_address(addr);
172	u_int8_t v = *p;
173	ia64_mf_a();
174	ia64_mf();
175	return v;
176}
177
178static __inline u_int16_t
179readw(u_int addr)
180{
181	volatile u_int16_t *p = ia64_memory_address(addr);
182	u_int16_t v = *p;
183	ia64_mf_a();
184	ia64_mf();
185	return v;
186}
187
188static __inline u_int32_t
189readl(u_int addr)
190{
191	volatile u_int32_t *p = ia64_memory_address(addr);
192	u_int32_t v = *p;
193	ia64_mf_a();
194	ia64_mf();
195	return v;
196}
197
198static __inline void
199writeb(u_int addr, u_int8_t data)
200{
201	volatile u_int8_t *p = ia64_memory_address(addr);
202	*p = data;
203	ia64_mf_a();
204	ia64_mf();
205}
206
207static __inline void
208writew(u_int addr, u_int16_t data)
209{
210	volatile u_int16_t *p = ia64_memory_address(addr);
211	*p = data;
212	ia64_mf_a();
213	ia64_mf();
214}
215
216static __inline void
217writel(u_int addr, u_int32_t data)
218{
219	volatile u_int32_t *p = ia64_memory_address(addr);
220	*p = data;
221	ia64_mf_a();
222	ia64_mf();
223}
224
225static __inline void
226disable_intr(void)
227{
228	__asm __volatile ("rsm psr.i;;");
229}
230
231static __inline void
232enable_intr(void)
233{
234	__asm __volatile (";; ssm psr.i;; srlz.d");
235}
236
237static __inline critical_t
238critical_enter(void)
239{
240	critical_t psr;
241
242	__asm __volatile ("mov %0=psr;;" : "=r" (psr));
243	disable_intr();
244	return (psr);
245}
246
247static __inline void
248critical_exit(critical_t psr)
249{
250	__asm __volatile ("mov psr.l=%0;; srlz.d" :: "r" (psr));
251}
252
253#endif /* _KERNEL */
254
255#endif /* !_MACHINE_CPUFUNC_H_ */
256