pmap.c revision 240126
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 240126 2012-09-05 06:02:54Z alc $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_smp.h" 109#include "opt_xbox.h" 110 111#include <sys/param.h> 112#include <sys/systm.h> 113#include <sys/kernel.h> 114#include <sys/ktr.h> 115#include <sys/lock.h> 116#include <sys/malloc.h> 117#include <sys/mman.h> 118#include <sys/msgbuf.h> 119#include <sys/mutex.h> 120#include <sys/proc.h> 121#include <sys/sf_buf.h> 122#include <sys/sx.h> 123#include <sys/vmmeter.h> 124#include <sys/sched.h> 125#include <sys/sysctl.h> 126#ifdef SMP 127#include <sys/smp.h> 128#else 129#include <sys/cpuset.h> 130#endif 131 132#include <vm/vm.h> 133#include <vm/vm_param.h> 134#include <vm/vm_kern.h> 135#include <vm/vm_page.h> 136#include <vm/vm_map.h> 137#include <vm/vm_object.h> 138#include <vm/vm_extern.h> 139#include <vm/vm_pageout.h> 140#include <vm/vm_pager.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/cputypes.h> 145#include <machine/md_var.h> 146#include <machine/pcb.h> 147#include <machine/specialreg.h> 148#ifdef SMP 149#include <machine/smp.h> 150#endif 151 152#ifdef XBOX 153#include <machine/xbox.h> 154#endif 155 156#include <xen/interface/xen.h> 157#include <xen/hypervisor.h> 158#include <machine/xen/hypercall.h> 159#include <machine/xen/xenvar.h> 160#include <machine/xen/xenfunc.h> 161 162#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 163#define CPU_ENABLE_SSE 164#endif 165 166#ifndef PMAP_SHPGPERPROC 167#define PMAP_SHPGPERPROC 200 168#endif 169 170#define DIAGNOSTIC 171 172#if !defined(DIAGNOSTIC) 173#ifdef __GNUC_GNU_INLINE__ 174#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 175#else 176#define PMAP_INLINE extern inline 177#endif 178#else 179#define PMAP_INLINE 180#endif 181 182#ifdef PV_STATS 183#define PV_STAT(x) do { x ; } while (0) 184#else 185#define PV_STAT(x) do { } while (0) 186#endif 187 188/* 189 * Get PDEs and PTEs for user/kernel address space 190 */ 191#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 192#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 193 194#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 195#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 196#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 197#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 198#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 199 200#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 201 202#define HAMFISTED_LOCKING 203#ifdef HAMFISTED_LOCKING 204static struct mtx createdelete_lock; 205#endif 206 207struct pmap kernel_pmap_store; 208LIST_HEAD(pmaplist, pmap); 209static struct pmaplist allpmaps; 210static struct mtx allpmaps_lock; 211 212vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 213vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 214int pgeflag = 0; /* PG_G or-in */ 215int pseflag = 0; /* PG_PS or-in */ 216 217int nkpt; 218vm_offset_t kernel_vm_end; 219extern u_int32_t KERNend; 220 221#ifdef PAE 222pt_entry_t pg_nx; 223#endif 224 225static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 226 227static int pat_works; /* Is page attribute table sane? */ 228 229/* 230 * Data for the pv entry allocation mechanism 231 */ 232static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 233static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 234static int shpgperproc = PMAP_SHPGPERPROC; 235 236struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 237int pv_maxchunks; /* How many chunks we have KVA for */ 238vm_offset_t pv_vafree; /* freelist stored in the PTE */ 239 240/* 241 * All those kernel PT submaps that BSD is so fond of 242 */ 243struct sysmaps { 244 struct mtx lock; 245 pt_entry_t *CMAP1; 246 pt_entry_t *CMAP2; 247 caddr_t CADDR1; 248 caddr_t CADDR2; 249}; 250static struct sysmaps sysmaps_pcpu[MAXCPU]; 251static pt_entry_t *CMAP3; 252caddr_t ptvmmap = 0; 253static caddr_t CADDR3; 254struct msgbuf *msgbufp = 0; 255 256/* 257 * Crashdump maps. 258 */ 259static caddr_t crashdumpmap; 260 261static pt_entry_t *PMAP1 = 0, *PMAP2; 262static pt_entry_t *PADDR1 = 0, *PADDR2; 263#ifdef SMP 264static int PMAP1cpu; 265static int PMAP1changedcpu; 266SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 267 &PMAP1changedcpu, 0, 268 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 269#endif 270static int PMAP1changed; 271SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 272 &PMAP1changed, 0, 273 "Number of times pmap_pte_quick changed PMAP1"); 274static int PMAP1unchanged; 275SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 276 &PMAP1unchanged, 0, 277 "Number of times pmap_pte_quick didn't change PMAP1"); 278static struct mtx PMAP2mutex; 279 280static void free_pv_chunk(struct pv_chunk *pc); 281static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 282static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 283static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 284static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 285 vm_offset_t va); 286 287static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 288 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 289static void pmap_flush_page(vm_page_t m); 290static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 291static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 292 vm_page_t *free); 293static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 294 vm_page_t *free); 295static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 296 vm_offset_t va); 297static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 298 vm_page_t m); 299 300static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 301 302static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags); 303static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free); 304static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 305static void pmap_pte_release(pt_entry_t *pte); 306static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 307static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 308 309static __inline void pagezero(void *page); 310 311CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 312CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 313 314/* 315 * If you get an error here, then you set KVA_PAGES wrong! See the 316 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 317 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 318 */ 319CTASSERT(KERNBASE % (1 << 24) == 0); 320 321void 322pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 323{ 324 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 325 326 switch (type) { 327 case SH_PD_SET_VA: 328#if 0 329 xen_queue_pt_update(shadow_pdir_ma, 330 xpmap_ptom(val & ~(PG_RW))); 331#endif 332 xen_queue_pt_update(pdir_ma, 333 xpmap_ptom(val)); 334 break; 335 case SH_PD_SET_VA_MA: 336#if 0 337 xen_queue_pt_update(shadow_pdir_ma, 338 val & ~(PG_RW)); 339#endif 340 xen_queue_pt_update(pdir_ma, val); 341 break; 342 case SH_PD_SET_VA_CLEAR: 343#if 0 344 xen_queue_pt_update(shadow_pdir_ma, 0); 345#endif 346 xen_queue_pt_update(pdir_ma, 0); 347 break; 348 } 349} 350 351/* 352 * Bootstrap the system enough to run with virtual memory. 353 * 354 * On the i386 this is called after mapping has already been enabled 355 * and just syncs the pmap module with what has already been done. 356 * [We can't call it easily with mapping off since the kernel is not 357 * mapped with PA == VA, hence we would have to relocate every address 358 * from the linked base (virtual) address "KERNBASE" to the actual 359 * (physical) address starting relative to 0] 360 */ 361void 362pmap_bootstrap(vm_paddr_t firstaddr) 363{ 364 vm_offset_t va; 365 pt_entry_t *pte, *unused; 366 struct sysmaps *sysmaps; 367 int i; 368 369 /* 370 * Initialize the first available kernel virtual address. However, 371 * using "firstaddr" may waste a few pages of the kernel virtual 372 * address space, because locore may not have mapped every physical 373 * page that it allocated. Preferably, locore would provide a first 374 * unused virtual address in addition to "firstaddr". 375 */ 376 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 377 378 virtual_end = VM_MAX_KERNEL_ADDRESS; 379 380 /* 381 * Initialize the kernel pmap (which is statically allocated). 382 */ 383 PMAP_LOCK_INIT(kernel_pmap); 384 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 385#ifdef PAE 386 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 387#endif 388 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 389 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 390 LIST_INIT(&allpmaps); 391 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 392 mtx_lock_spin(&allpmaps_lock); 393 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 394 mtx_unlock_spin(&allpmaps_lock); 395 if (nkpt == 0) 396 nkpt = NKPT; 397 398 /* 399 * Reserve some special page table entries/VA space for temporary 400 * mapping of pages. 401 */ 402#define SYSMAP(c, p, v, n) \ 403 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 404 405 va = virtual_avail; 406 pte = vtopte(va); 407 408 /* 409 * CMAP1/CMAP2 are used for zeroing and copying pages. 410 * CMAP3 is used for the idle process page zeroing. 411 */ 412 for (i = 0; i < MAXCPU; i++) { 413 sysmaps = &sysmaps_pcpu[i]; 414 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 415 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 416 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 417 PT_SET_MA(sysmaps->CADDR1, 0); 418 PT_SET_MA(sysmaps->CADDR2, 0); 419 } 420 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 421 PT_SET_MA(CADDR3, 0); 422 423 /* 424 * Crashdump maps. 425 */ 426 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 427 428 /* 429 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 430 */ 431 SYSMAP(caddr_t, unused, ptvmmap, 1) 432 433 /* 434 * msgbufp is used to map the system message buffer. 435 */ 436 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 437 438 /* 439 * ptemap is used for pmap_pte_quick 440 */ 441 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 442 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 443 444 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 445 446 virtual_avail = va; 447 448 /* 449 * Leave in place an identity mapping (virt == phys) for the low 1 MB 450 * physical memory region that is used by the ACPI wakeup code. This 451 * mapping must not have PG_G set. 452 */ 453#ifndef XEN 454 /* 455 * leave here deliberately to show that this is not supported 456 */ 457#ifdef XBOX 458 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 459 * an early stadium, we cannot yet neatly map video memory ... :-( 460 * Better fixes are very welcome! */ 461 if (!arch_i386_is_xbox) 462#endif 463 for (i = 1; i < NKPT; i++) 464 PTD[i] = 0; 465 466 /* Initialize the PAT MSR if present. */ 467 pmap_init_pat(); 468 469 /* Turn on PG_G on kernel page(s) */ 470 pmap_set_pg(); 471#endif 472 473#ifdef HAMFISTED_LOCKING 474 mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF); 475#endif 476} 477 478/* 479 * Setup the PAT MSR. 480 */ 481void 482pmap_init_pat(void) 483{ 484 uint64_t pat_msr; 485 486 /* Bail if this CPU doesn't implement PAT. */ 487 if (!(cpu_feature & CPUID_PAT)) 488 return; 489 490 if (cpu_vendor_id != CPU_VENDOR_INTEL || 491 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 492 /* 493 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 494 * Program 4 and 5 as WP and WC. 495 * Leave 6 and 7 as UC and UC-. 496 */ 497 pat_msr = rdmsr(MSR_PAT); 498 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 499 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 500 PAT_VALUE(5, PAT_WRITE_COMBINING); 501 pat_works = 1; 502 } else { 503 /* 504 * Due to some Intel errata, we can only safely use the lower 4 505 * PAT entries. Thus, just replace PAT Index 2 with WC instead 506 * of UC-. 507 * 508 * Intel Pentium III Processor Specification Update 509 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 510 * or Mode C Paging) 511 * 512 * Intel Pentium IV Processor Specification Update 513 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 514 */ 515 pat_msr = rdmsr(MSR_PAT); 516 pat_msr &= ~PAT_MASK(2); 517 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 518 pat_works = 0; 519 } 520 wrmsr(MSR_PAT, pat_msr); 521} 522 523/* 524 * Initialize a vm_page's machine-dependent fields. 525 */ 526void 527pmap_page_init(vm_page_t m) 528{ 529 530 TAILQ_INIT(&m->md.pv_list); 531 m->md.pat_mode = PAT_WRITE_BACK; 532} 533 534/* 535 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 536 * Requirements: 537 * - Must deal with pages in order to ensure that none of the PG_* bits 538 * are ever set, PG_V in particular. 539 * - Assumes we can write to ptes without pte_store() atomic ops, even 540 * on PAE systems. This should be ok. 541 * - Assumes nothing will ever test these addresses for 0 to indicate 542 * no mapping instead of correctly checking PG_V. 543 * - Assumes a vm_offset_t will fit in a pte (true for i386). 544 * Because PG_V is never set, there can be no mappings to invalidate. 545 */ 546static int ptelist_count = 0; 547static vm_offset_t 548pmap_ptelist_alloc(vm_offset_t *head) 549{ 550 vm_offset_t va; 551 vm_offset_t *phead = (vm_offset_t *)*head; 552 553 if (ptelist_count == 0) { 554 printf("out of memory!!!!!!\n"); 555 return (0); /* Out of memory */ 556 } 557 ptelist_count--; 558 va = phead[ptelist_count]; 559 return (va); 560} 561 562static void 563pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 564{ 565 vm_offset_t *phead = (vm_offset_t *)*head; 566 567 phead[ptelist_count++] = va; 568} 569 570static void 571pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 572{ 573 int i, nstackpages; 574 vm_offset_t va; 575 vm_page_t m; 576 577 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 578 for (i = 0; i < nstackpages; i++) { 579 va = (vm_offset_t)base + i * PAGE_SIZE; 580 m = vm_page_alloc(NULL, i, 581 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 582 VM_ALLOC_ZERO); 583 pmap_qenter(va, &m, 1); 584 } 585 586 *head = (vm_offset_t)base; 587 for (i = npages - 1; i >= nstackpages; i--) { 588 va = (vm_offset_t)base + i * PAGE_SIZE; 589 pmap_ptelist_free(head, va); 590 } 591} 592 593 594/* 595 * Initialize the pmap module. 596 * Called by vm_init, to initialize any structures that the pmap 597 * system needs to map virtual memory. 598 */ 599void 600pmap_init(void) 601{ 602 603 /* 604 * Initialize the address space (zone) for the pv entries. Set a 605 * high water mark so that the system can recover from excessive 606 * numbers of pv entries. 607 */ 608 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 609 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 610 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 611 pv_entry_max = roundup(pv_entry_max, _NPCPV); 612 pv_entry_high_water = 9 * (pv_entry_max / 10); 613 614 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 615 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 616 PAGE_SIZE * pv_maxchunks); 617 if (pv_chunkbase == NULL) 618 panic("pmap_init: not enough kvm for pv chunks"); 619 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 620} 621 622 623SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 624 "Max number of PV entries"); 625SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 626 "Page share factor per proc"); 627 628static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 629 "2/4MB page mapping counters"); 630 631static u_long pmap_pde_mappings; 632SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 633 &pmap_pde_mappings, 0, "2/4MB page mappings"); 634 635/*************************************************** 636 * Low level helper routines..... 637 ***************************************************/ 638 639/* 640 * Determine the appropriate bits to set in a PTE or PDE for a specified 641 * caching mode. 642 */ 643int 644pmap_cache_bits(int mode, boolean_t is_pde) 645{ 646 int pat_flag, pat_index, cache_bits; 647 648 /* The PAT bit is different for PTE's and PDE's. */ 649 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 650 651 /* If we don't support PAT, map extended modes to older ones. */ 652 if (!(cpu_feature & CPUID_PAT)) { 653 switch (mode) { 654 case PAT_UNCACHEABLE: 655 case PAT_WRITE_THROUGH: 656 case PAT_WRITE_BACK: 657 break; 658 case PAT_UNCACHED: 659 case PAT_WRITE_COMBINING: 660 case PAT_WRITE_PROTECTED: 661 mode = PAT_UNCACHEABLE; 662 break; 663 } 664 } 665 666 /* Map the caching mode to a PAT index. */ 667 if (pat_works) { 668 switch (mode) { 669 case PAT_UNCACHEABLE: 670 pat_index = 3; 671 break; 672 case PAT_WRITE_THROUGH: 673 pat_index = 1; 674 break; 675 case PAT_WRITE_BACK: 676 pat_index = 0; 677 break; 678 case PAT_UNCACHED: 679 pat_index = 2; 680 break; 681 case PAT_WRITE_COMBINING: 682 pat_index = 5; 683 break; 684 case PAT_WRITE_PROTECTED: 685 pat_index = 4; 686 break; 687 default: 688 panic("Unknown caching mode %d\n", mode); 689 } 690 } else { 691 switch (mode) { 692 case PAT_UNCACHED: 693 case PAT_UNCACHEABLE: 694 case PAT_WRITE_PROTECTED: 695 pat_index = 3; 696 break; 697 case PAT_WRITE_THROUGH: 698 pat_index = 1; 699 break; 700 case PAT_WRITE_BACK: 701 pat_index = 0; 702 break; 703 case PAT_WRITE_COMBINING: 704 pat_index = 2; 705 break; 706 default: 707 panic("Unknown caching mode %d\n", mode); 708 } 709 } 710 711 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 712 cache_bits = 0; 713 if (pat_index & 0x4) 714 cache_bits |= pat_flag; 715 if (pat_index & 0x2) 716 cache_bits |= PG_NC_PCD; 717 if (pat_index & 0x1) 718 cache_bits |= PG_NC_PWT; 719 return (cache_bits); 720} 721#ifdef SMP 722/* 723 * For SMP, these functions have to use the IPI mechanism for coherence. 724 * 725 * N.B.: Before calling any of the following TLB invalidation functions, 726 * the calling processor must ensure that all stores updating a non- 727 * kernel page table are globally performed. Otherwise, another 728 * processor could cache an old, pre-update entry without being 729 * invalidated. This can happen one of two ways: (1) The pmap becomes 730 * active on another processor after its pm_active field is checked by 731 * one of the following functions but before a store updating the page 732 * table is globally performed. (2) The pmap becomes active on another 733 * processor before its pm_active field is checked but due to 734 * speculative loads one of the following functions stills reads the 735 * pmap as inactive on the other processor. 736 * 737 * The kernel page table is exempt because its pm_active field is 738 * immutable. The kernel page table is always active on every 739 * processor. 740 */ 741void 742pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 743{ 744 cpuset_t other_cpus; 745 u_int cpuid; 746 747 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 748 pmap, va); 749 750 sched_pin(); 751 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 752 invlpg(va); 753 smp_invlpg(va); 754 } else { 755 cpuid = PCPU_GET(cpuid); 756 other_cpus = all_cpus; 757 CPU_CLR(cpuid, &other_cpus); 758 if (CPU_ISSET(cpuid, &pmap->pm_active)) 759 invlpg(va); 760 CPU_AND(&other_cpus, &pmap->pm_active); 761 if (!CPU_EMPTY(&other_cpus)) 762 smp_masked_invlpg(other_cpus, va); 763 } 764 sched_unpin(); 765 PT_UPDATES_FLUSH(); 766} 767 768void 769pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 770{ 771 cpuset_t other_cpus; 772 vm_offset_t addr; 773 u_int cpuid; 774 775 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 776 pmap, sva, eva); 777 778 sched_pin(); 779 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 780 for (addr = sva; addr < eva; addr += PAGE_SIZE) 781 invlpg(addr); 782 smp_invlpg_range(sva, eva); 783 } else { 784 cpuid = PCPU_GET(cpuid); 785 other_cpus = all_cpus; 786 CPU_CLR(cpuid, &other_cpus); 787 if (CPU_ISSET(cpuid, &pmap->pm_active)) 788 for (addr = sva; addr < eva; addr += PAGE_SIZE) 789 invlpg(addr); 790 CPU_AND(&other_cpus, &pmap->pm_active); 791 if (!CPU_EMPTY(&other_cpus)) 792 smp_masked_invlpg_range(other_cpus, sva, eva); 793 } 794 sched_unpin(); 795 PT_UPDATES_FLUSH(); 796} 797 798void 799pmap_invalidate_all(pmap_t pmap) 800{ 801 cpuset_t other_cpus; 802 u_int cpuid; 803 804 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 805 806 sched_pin(); 807 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 808 invltlb(); 809 smp_invltlb(); 810 } else { 811 cpuid = PCPU_GET(cpuid); 812 other_cpus = all_cpus; 813 CPU_CLR(cpuid, &other_cpus); 814 if (CPU_ISSET(cpuid, &pmap->pm_active)) 815 invltlb(); 816 CPU_AND(&other_cpus, &pmap->pm_active); 817 if (!CPU_EMPTY(&other_cpus)) 818 smp_masked_invltlb(other_cpus); 819 } 820 sched_unpin(); 821} 822 823void 824pmap_invalidate_cache(void) 825{ 826 827 sched_pin(); 828 wbinvd(); 829 smp_cache_flush(); 830 sched_unpin(); 831} 832#else /* !SMP */ 833/* 834 * Normal, non-SMP, 486+ invalidation functions. 835 * We inline these within pmap.c for speed. 836 */ 837PMAP_INLINE void 838pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 839{ 840 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 841 pmap, va); 842 843 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 844 invlpg(va); 845 PT_UPDATES_FLUSH(); 846} 847 848PMAP_INLINE void 849pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 850{ 851 vm_offset_t addr; 852 853 if (eva - sva > PAGE_SIZE) 854 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 855 pmap, sva, eva); 856 857 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 858 for (addr = sva; addr < eva; addr += PAGE_SIZE) 859 invlpg(addr); 860 PT_UPDATES_FLUSH(); 861} 862 863PMAP_INLINE void 864pmap_invalidate_all(pmap_t pmap) 865{ 866 867 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 868 869 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 870 invltlb(); 871} 872 873PMAP_INLINE void 874pmap_invalidate_cache(void) 875{ 876 877 wbinvd(); 878} 879#endif /* !SMP */ 880 881#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 882 883void 884pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 885{ 886 887 KASSERT((sva & PAGE_MASK) == 0, 888 ("pmap_invalidate_cache_range: sva not page-aligned")); 889 KASSERT((eva & PAGE_MASK) == 0, 890 ("pmap_invalidate_cache_range: eva not page-aligned")); 891 892 if (cpu_feature & CPUID_SS) 893 ; /* If "Self Snoop" is supported, do nothing. */ 894 else if ((cpu_feature & CPUID_CLFSH) != 0 && 895 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 896 897 /* 898 * Otherwise, do per-cache line flush. Use the mfence 899 * instruction to insure that previous stores are 900 * included in the write-back. The processor 901 * propagates flush to other processors in the cache 902 * coherence domain. 903 */ 904 mfence(); 905 for (; sva < eva; sva += cpu_clflush_line_size) 906 clflush(sva); 907 mfence(); 908 } else { 909 910 /* 911 * No targeted cache flush methods are supported by CPU, 912 * or the supplied range is bigger than 2MB. 913 * Globally invalidate cache. 914 */ 915 pmap_invalidate_cache(); 916 } 917} 918 919void 920pmap_invalidate_cache_pages(vm_page_t *pages, int count) 921{ 922 int i; 923 924 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 925 (cpu_feature & CPUID_CLFSH) == 0) { 926 pmap_invalidate_cache(); 927 } else { 928 for (i = 0; i < count; i++) 929 pmap_flush_page(pages[i]); 930 } 931} 932 933/* 934 * Are we current address space or kernel? N.B. We return FALSE when 935 * a pmap's page table is in use because a kernel thread is borrowing 936 * it. The borrowed page table can change spontaneously, making any 937 * dependence on its continued use subject to a race condition. 938 */ 939static __inline int 940pmap_is_current(pmap_t pmap) 941{ 942 943 return (pmap == kernel_pmap || 944 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 945 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 946} 947 948/* 949 * If the given pmap is not the current or kernel pmap, the returned pte must 950 * be released by passing it to pmap_pte_release(). 951 */ 952pt_entry_t * 953pmap_pte(pmap_t pmap, vm_offset_t va) 954{ 955 pd_entry_t newpf; 956 pd_entry_t *pde; 957 958 pde = pmap_pde(pmap, va); 959 if (*pde & PG_PS) 960 return (pde); 961 if (*pde != 0) { 962 /* are we current address space or kernel? */ 963 if (pmap_is_current(pmap)) 964 return (vtopte(va)); 965 mtx_lock(&PMAP2mutex); 966 newpf = *pde & PG_FRAME; 967 if ((*PMAP2 & PG_FRAME) != newpf) { 968 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 969 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 970 pmap, va, (*PMAP2 & 0xffffffff)); 971 } 972 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 973 } 974 return (NULL); 975} 976 977/* 978 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 979 * being NULL. 980 */ 981static __inline void 982pmap_pte_release(pt_entry_t *pte) 983{ 984 985 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 986 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 987 *PMAP2); 988 vm_page_lock_queues(); 989 PT_SET_VA(PMAP2, 0, TRUE); 990 vm_page_unlock_queues(); 991 mtx_unlock(&PMAP2mutex); 992 } 993} 994 995static __inline void 996invlcaddr(void *caddr) 997{ 998 999 invlpg((u_int)caddr); 1000 PT_UPDATES_FLUSH(); 1001} 1002 1003/* 1004 * Super fast pmap_pte routine best used when scanning 1005 * the pv lists. This eliminates many coarse-grained 1006 * invltlb calls. Note that many of the pv list 1007 * scans are across different pmaps. It is very wasteful 1008 * to do an entire invltlb for checking a single mapping. 1009 * 1010 * If the given pmap is not the current pmap, vm_page_queue_mtx 1011 * must be held and curthread pinned to a CPU. 1012 */ 1013static pt_entry_t * 1014pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1015{ 1016 pd_entry_t newpf; 1017 pd_entry_t *pde; 1018 1019 pde = pmap_pde(pmap, va); 1020 if (*pde & PG_PS) 1021 return (pde); 1022 if (*pde != 0) { 1023 /* are we current address space or kernel? */ 1024 if (pmap_is_current(pmap)) 1025 return (vtopte(va)); 1026 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1027 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1028 newpf = *pde & PG_FRAME; 1029 if ((*PMAP1 & PG_FRAME) != newpf) { 1030 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1031 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1032 pmap, va, (u_long)*PMAP1); 1033 1034#ifdef SMP 1035 PMAP1cpu = PCPU_GET(cpuid); 1036#endif 1037 PMAP1changed++; 1038 } else 1039#ifdef SMP 1040 if (PMAP1cpu != PCPU_GET(cpuid)) { 1041 PMAP1cpu = PCPU_GET(cpuid); 1042 invlcaddr(PADDR1); 1043 PMAP1changedcpu++; 1044 } else 1045#endif 1046 PMAP1unchanged++; 1047 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1048 } 1049 return (0); 1050} 1051 1052/* 1053 * Routine: pmap_extract 1054 * Function: 1055 * Extract the physical page address associated 1056 * with the given map/virtual_address pair. 1057 */ 1058vm_paddr_t 1059pmap_extract(pmap_t pmap, vm_offset_t va) 1060{ 1061 vm_paddr_t rtval; 1062 pt_entry_t *pte; 1063 pd_entry_t pde; 1064 pt_entry_t pteval; 1065 1066 rtval = 0; 1067 PMAP_LOCK(pmap); 1068 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1069 if (pde != 0) { 1070 if ((pde & PG_PS) != 0) { 1071 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1072 PMAP_UNLOCK(pmap); 1073 return rtval; 1074 } 1075 pte = pmap_pte(pmap, va); 1076 pteval = *pte ? xpmap_mtop(*pte) : 0; 1077 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1078 pmap_pte_release(pte); 1079 } 1080 PMAP_UNLOCK(pmap); 1081 return (rtval); 1082} 1083 1084/* 1085 * Routine: pmap_extract_ma 1086 * Function: 1087 * Like pmap_extract, but returns machine address 1088 */ 1089vm_paddr_t 1090pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1091{ 1092 vm_paddr_t rtval; 1093 pt_entry_t *pte; 1094 pd_entry_t pde; 1095 1096 rtval = 0; 1097 PMAP_LOCK(pmap); 1098 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1099 if (pde != 0) { 1100 if ((pde & PG_PS) != 0) { 1101 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1102 PMAP_UNLOCK(pmap); 1103 return rtval; 1104 } 1105 pte = pmap_pte(pmap, va); 1106 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1107 pmap_pte_release(pte); 1108 } 1109 PMAP_UNLOCK(pmap); 1110 return (rtval); 1111} 1112 1113/* 1114 * Routine: pmap_extract_and_hold 1115 * Function: 1116 * Atomically extract and hold the physical page 1117 * with the given pmap and virtual address pair 1118 * if that mapping permits the given protection. 1119 */ 1120vm_page_t 1121pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1122{ 1123 pd_entry_t pde; 1124 pt_entry_t pte, *ptep; 1125 vm_page_t m; 1126 vm_paddr_t pa; 1127 1128 pa = 0; 1129 m = NULL; 1130 PMAP_LOCK(pmap); 1131retry: 1132 pde = PT_GET(pmap_pde(pmap, va)); 1133 if (pde != 0) { 1134 if (pde & PG_PS) { 1135 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1136 if (vm_page_pa_tryrelock(pmap, (pde & 1137 PG_PS_FRAME) | (va & PDRMASK), &pa)) 1138 goto retry; 1139 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1140 (va & PDRMASK)); 1141 vm_page_hold(m); 1142 } 1143 } else { 1144 ptep = pmap_pte(pmap, va); 1145 pte = PT_GET(ptep); 1146 pmap_pte_release(ptep); 1147 if (pte != 0 && 1148 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1149 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1150 &pa)) 1151 goto retry; 1152 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1153 vm_page_hold(m); 1154 } 1155 } 1156 } 1157 PA_UNLOCK_COND(pa); 1158 PMAP_UNLOCK(pmap); 1159 return (m); 1160} 1161 1162/*************************************************** 1163 * Low level mapping routines..... 1164 ***************************************************/ 1165 1166/* 1167 * Add a wired page to the kva. 1168 * Note: not SMP coherent. 1169 * 1170 * This function may be used before pmap_bootstrap() is called. 1171 */ 1172void 1173pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1174{ 1175 1176 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1177} 1178 1179void 1180pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1181{ 1182 pt_entry_t *pte; 1183 1184 pte = vtopte(va); 1185 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1186} 1187 1188static __inline void 1189pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1190{ 1191 1192 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1193} 1194 1195/* 1196 * Remove a page from the kernel pagetables. 1197 * Note: not SMP coherent. 1198 * 1199 * This function may be used before pmap_bootstrap() is called. 1200 */ 1201PMAP_INLINE void 1202pmap_kremove(vm_offset_t va) 1203{ 1204 pt_entry_t *pte; 1205 1206 pte = vtopte(va); 1207 PT_CLEAR_VA(pte, FALSE); 1208} 1209 1210/* 1211 * Used to map a range of physical addresses into kernel 1212 * virtual address space. 1213 * 1214 * The value passed in '*virt' is a suggested virtual address for 1215 * the mapping. Architectures which can support a direct-mapped 1216 * physical to virtual region can return the appropriate address 1217 * within that region, leaving '*virt' unchanged. Other 1218 * architectures should map the pages starting at '*virt' and 1219 * update '*virt' with the first usable address after the mapped 1220 * region. 1221 */ 1222vm_offset_t 1223pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1224{ 1225 vm_offset_t va, sva; 1226 1227 va = sva = *virt; 1228 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1229 va, start, end, prot); 1230 while (start < end) { 1231 pmap_kenter(va, start); 1232 va += PAGE_SIZE; 1233 start += PAGE_SIZE; 1234 } 1235 pmap_invalidate_range(kernel_pmap, sva, va); 1236 *virt = va; 1237 return (sva); 1238} 1239 1240 1241/* 1242 * Add a list of wired pages to the kva 1243 * this routine is only used for temporary 1244 * kernel mappings that do not need to have 1245 * page modification or references recorded. 1246 * Note that old mappings are simply written 1247 * over. The page *must* be wired. 1248 * Note: SMP coherent. Uses a ranged shootdown IPI. 1249 */ 1250void 1251pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1252{ 1253 pt_entry_t *endpte, *pte; 1254 vm_paddr_t pa; 1255 vm_offset_t va = sva; 1256 int mclcount = 0; 1257 multicall_entry_t mcl[16]; 1258 multicall_entry_t *mclp = mcl; 1259 int error; 1260 1261 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1262 pte = vtopte(sva); 1263 endpte = pte + count; 1264 while (pte < endpte) { 1265 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1266 1267 mclp->op = __HYPERVISOR_update_va_mapping; 1268 mclp->args[0] = va; 1269 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1270 mclp->args[2] = (uint32_t)(pa >> 32); 1271 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1272 1273 va += PAGE_SIZE; 1274 pte++; 1275 ma++; 1276 mclp++; 1277 mclcount++; 1278 if (mclcount == 16) { 1279 error = HYPERVISOR_multicall(mcl, mclcount); 1280 mclp = mcl; 1281 mclcount = 0; 1282 KASSERT(error == 0, ("bad multicall %d", error)); 1283 } 1284 } 1285 if (mclcount) { 1286 error = HYPERVISOR_multicall(mcl, mclcount); 1287 KASSERT(error == 0, ("bad multicall %d", error)); 1288 } 1289 1290#ifdef INVARIANTS 1291 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1292 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1293#endif 1294} 1295 1296/* 1297 * This routine tears out page mappings from the 1298 * kernel -- it is meant only for temporary mappings. 1299 * Note: SMP coherent. Uses a ranged shootdown IPI. 1300 */ 1301void 1302pmap_qremove(vm_offset_t sva, int count) 1303{ 1304 vm_offset_t va; 1305 1306 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1307 va = sva; 1308 vm_page_lock_queues(); 1309 critical_enter(); 1310 while (count-- > 0) { 1311 pmap_kremove(va); 1312 va += PAGE_SIZE; 1313 } 1314 PT_UPDATES_FLUSH(); 1315 pmap_invalidate_range(kernel_pmap, sva, va); 1316 critical_exit(); 1317 vm_page_unlock_queues(); 1318} 1319 1320/*************************************************** 1321 * Page table page management routines..... 1322 ***************************************************/ 1323static __inline void 1324pmap_free_zero_pages(vm_page_t free) 1325{ 1326 vm_page_t m; 1327 1328 while (free != NULL) { 1329 m = free; 1330 free = m->right; 1331 vm_page_free_zero(m); 1332 } 1333} 1334 1335/* 1336 * Decrements a page table page's wire count, which is used to record the 1337 * number of valid page table entries within the page. If the wire count 1338 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1339 * page table page was unmapped and FALSE otherwise. 1340 */ 1341static inline boolean_t 1342pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1343{ 1344 1345 --m->wire_count; 1346 if (m->wire_count == 0) { 1347 _pmap_unwire_ptp(pmap, m, free); 1348 return (TRUE); 1349 } else 1350 return (FALSE); 1351} 1352 1353static void 1354_pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1355{ 1356 vm_offset_t pteva; 1357 1358 PT_UPDATES_FLUSH(); 1359 /* 1360 * unmap the page table page 1361 */ 1362 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1363 /* 1364 * page *might* contain residual mapping :-/ 1365 */ 1366 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1367 pmap_zero_page(m); 1368 --pmap->pm_stats.resident_count; 1369 1370 /* 1371 * This is a release store so that the ordinary store unmapping 1372 * the page table page is globally performed before TLB shoot- 1373 * down is begun. 1374 */ 1375 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1376 1377 /* 1378 * Do an invltlb to make the invalidated mapping 1379 * take effect immediately. 1380 */ 1381 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1382 pmap_invalidate_page(pmap, pteva); 1383 1384 /* 1385 * Put page on a list so that it is released after 1386 * *ALL* TLB shootdown is done 1387 */ 1388 m->right = *free; 1389 *free = m; 1390} 1391 1392/* 1393 * After removing a page table entry, this routine is used to 1394 * conditionally free the page, and manage the hold/wire counts. 1395 */ 1396static int 1397pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1398{ 1399 pd_entry_t ptepde; 1400 vm_page_t mpte; 1401 1402 if (va >= VM_MAXUSER_ADDRESS) 1403 return (0); 1404 ptepde = PT_GET(pmap_pde(pmap, va)); 1405 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1406 return (pmap_unwire_ptp(pmap, mpte, free)); 1407} 1408 1409/* 1410 * Initialize the pmap for the swapper process. 1411 */ 1412void 1413pmap_pinit0(pmap_t pmap) 1414{ 1415 1416 PMAP_LOCK_INIT(pmap); 1417 /* 1418 * Since the page table directory is shared with the kernel pmap, 1419 * which is already included in the list "allpmaps", this pmap does 1420 * not need to be inserted into that list. 1421 */ 1422 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1423#ifdef PAE 1424 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1425#endif 1426 CPU_ZERO(&pmap->pm_active); 1427 PCPU_SET(curpmap, pmap); 1428 TAILQ_INIT(&pmap->pm_pvchunk); 1429 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1430} 1431 1432/* 1433 * Initialize a preallocated and zeroed pmap structure, 1434 * such as one in a vmspace structure. 1435 */ 1436int 1437pmap_pinit(pmap_t pmap) 1438{ 1439 vm_page_t m, ptdpg[NPGPTD + 1]; 1440 int npgptd = NPGPTD + 1; 1441 int i; 1442 1443#ifdef HAMFISTED_LOCKING 1444 mtx_lock(&createdelete_lock); 1445#endif 1446 1447 PMAP_LOCK_INIT(pmap); 1448 1449 /* 1450 * No need to allocate page table space yet but we do need a valid 1451 * page directory table. 1452 */ 1453 if (pmap->pm_pdir == NULL) { 1454 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1455 NBPTD); 1456 if (pmap->pm_pdir == NULL) { 1457 PMAP_LOCK_DESTROY(pmap); 1458#ifdef HAMFISTED_LOCKING 1459 mtx_unlock(&createdelete_lock); 1460#endif 1461 return (0); 1462 } 1463#ifdef PAE 1464 pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1465#endif 1466 } 1467 1468 /* 1469 * allocate the page directory page(s) 1470 */ 1471 for (i = 0; i < npgptd;) { 1472 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1473 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1474 if (m == NULL) 1475 VM_WAIT; 1476 else { 1477 ptdpg[i++] = m; 1478 } 1479 } 1480 1481 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1482 1483 for (i = 0; i < NPGPTD; i++) 1484 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1485 pagezero(pmap->pm_pdir + (i * NPDEPG)); 1486 1487 mtx_lock_spin(&allpmaps_lock); 1488 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1489 /* Copy the kernel page table directory entries. */ 1490 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1491 mtx_unlock_spin(&allpmaps_lock); 1492 1493#ifdef PAE 1494 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1495 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1496 bzero(pmap->pm_pdpt, PAGE_SIZE); 1497 for (i = 0; i < NPGPTD; i++) { 1498 vm_paddr_t ma; 1499 1500 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1501 pmap->pm_pdpt[i] = ma | PG_V; 1502 1503 } 1504#endif 1505 for (i = 0; i < NPGPTD; i++) { 1506 pt_entry_t *pd; 1507 vm_paddr_t ma; 1508 1509 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1510 pd = pmap->pm_pdir + (i * NPDEPG); 1511 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1512#if 0 1513 xen_pgd_pin(ma); 1514#endif 1515 } 1516 1517#ifdef PAE 1518 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1519#endif 1520 vm_page_lock_queues(); 1521 xen_flush_queue(); 1522 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1523 for (i = 0; i < NPGPTD; i++) { 1524 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1525 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1526 } 1527 xen_flush_queue(); 1528 vm_page_unlock_queues(); 1529 CPU_ZERO(&pmap->pm_active); 1530 TAILQ_INIT(&pmap->pm_pvchunk); 1531 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1532 1533#ifdef HAMFISTED_LOCKING 1534 mtx_unlock(&createdelete_lock); 1535#endif 1536 return (1); 1537} 1538 1539/* 1540 * this routine is called if the page table page is not 1541 * mapped correctly. 1542 */ 1543static vm_page_t 1544_pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags) 1545{ 1546 vm_paddr_t ptema; 1547 vm_page_t m; 1548 1549 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1550 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1551 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1552 1553 /* 1554 * Allocate a page table page. 1555 */ 1556 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1557 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1558 if (flags & M_WAITOK) { 1559 PMAP_UNLOCK(pmap); 1560 vm_page_unlock_queues(); 1561 VM_WAIT; 1562 vm_page_lock_queues(); 1563 PMAP_LOCK(pmap); 1564 } 1565 1566 /* 1567 * Indicate the need to retry. While waiting, the page table 1568 * page may have been allocated. 1569 */ 1570 return (NULL); 1571 } 1572 if ((m->flags & PG_ZERO) == 0) 1573 pmap_zero_page(m); 1574 1575 /* 1576 * Map the pagetable page into the process address space, if 1577 * it isn't already there. 1578 */ 1579 1580 pmap->pm_stats.resident_count++; 1581 1582 ptema = VM_PAGE_TO_MACH(m); 1583 xen_pt_pin(ptema); 1584 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1585 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1586 1587 KASSERT(pmap->pm_pdir[ptepindex], 1588 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1589 return (m); 1590} 1591 1592static vm_page_t 1593pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1594{ 1595 u_int ptepindex; 1596 pd_entry_t ptema; 1597 vm_page_t m; 1598 1599 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1600 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1601 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1602 1603 /* 1604 * Calculate pagetable page index 1605 */ 1606 ptepindex = va >> PDRSHIFT; 1607retry: 1608 /* 1609 * Get the page directory entry 1610 */ 1611 ptema = pmap->pm_pdir[ptepindex]; 1612 1613 /* 1614 * This supports switching from a 4MB page to a 1615 * normal 4K page. 1616 */ 1617 if (ptema & PG_PS) { 1618 /* 1619 * XXX 1620 */ 1621 pmap->pm_pdir[ptepindex] = 0; 1622 ptema = 0; 1623 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1624 pmap_invalidate_all(kernel_pmap); 1625 } 1626 1627 /* 1628 * If the page table page is mapped, we just increment the 1629 * hold count, and activate it. 1630 */ 1631 if (ptema & PG_V) { 1632 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1633 m->wire_count++; 1634 } else { 1635 /* 1636 * Here if the pte page isn't mapped, or if it has 1637 * been deallocated. 1638 */ 1639 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1640 pmap, va, flags); 1641 m = _pmap_allocpte(pmap, ptepindex, flags); 1642 if (m == NULL && (flags & M_WAITOK)) 1643 goto retry; 1644 1645 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1646 } 1647 return (m); 1648} 1649 1650 1651/*************************************************** 1652* Pmap allocation/deallocation routines. 1653 ***************************************************/ 1654 1655#ifdef SMP 1656/* 1657 * Deal with a SMP shootdown of other users of the pmap that we are 1658 * trying to dispose of. This can be a bit hairy. 1659 */ 1660static cpuset_t *lazymask; 1661static u_int lazyptd; 1662static volatile u_int lazywait; 1663 1664void pmap_lazyfix_action(void); 1665 1666void 1667pmap_lazyfix_action(void) 1668{ 1669 1670#ifdef COUNT_IPIS 1671 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1672#endif 1673 if (rcr3() == lazyptd) 1674 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1675 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1676 atomic_store_rel_int(&lazywait, 1); 1677} 1678 1679static void 1680pmap_lazyfix_self(u_int cpuid) 1681{ 1682 1683 if (rcr3() == lazyptd) 1684 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1685 CPU_CLR_ATOMIC(cpuid, lazymask); 1686} 1687 1688 1689static void 1690pmap_lazyfix(pmap_t pmap) 1691{ 1692 cpuset_t mymask, mask; 1693 u_int cpuid, spins; 1694 int lsb; 1695 1696 mask = pmap->pm_active; 1697 while (!CPU_EMPTY(&mask)) { 1698 spins = 50000000; 1699 1700 /* Find least significant set bit. */ 1701 lsb = cpusetobj_ffs(&mask); 1702 MPASS(lsb != 0); 1703 lsb--; 1704 CPU_SETOF(lsb, &mask); 1705 mtx_lock_spin(&smp_ipi_mtx); 1706#ifdef PAE 1707 lazyptd = vtophys(pmap->pm_pdpt); 1708#else 1709 lazyptd = vtophys(pmap->pm_pdir); 1710#endif 1711 cpuid = PCPU_GET(cpuid); 1712 1713 /* Use a cpuset just for having an easy check. */ 1714 CPU_SETOF(cpuid, &mymask); 1715 if (!CPU_CMP(&mask, &mymask)) { 1716 lazymask = &pmap->pm_active; 1717 pmap_lazyfix_self(cpuid); 1718 } else { 1719 atomic_store_rel_int((u_int *)&lazymask, 1720 (u_int)&pmap->pm_active); 1721 atomic_store_rel_int(&lazywait, 0); 1722 ipi_selected(mask, IPI_LAZYPMAP); 1723 while (lazywait == 0) { 1724 ia32_pause(); 1725 if (--spins == 0) 1726 break; 1727 } 1728 } 1729 mtx_unlock_spin(&smp_ipi_mtx); 1730 if (spins == 0) 1731 printf("pmap_lazyfix: spun for 50000000\n"); 1732 mask = pmap->pm_active; 1733 } 1734} 1735 1736#else /* SMP */ 1737 1738/* 1739 * Cleaning up on uniprocessor is easy. For various reasons, we're 1740 * unlikely to have to even execute this code, including the fact 1741 * that the cleanup is deferred until the parent does a wait(2), which 1742 * means that another userland process has run. 1743 */ 1744static void 1745pmap_lazyfix(pmap_t pmap) 1746{ 1747 u_int cr3; 1748 1749 cr3 = vtophys(pmap->pm_pdir); 1750 if (cr3 == rcr3()) { 1751 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1752 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 1753 } 1754} 1755#endif /* SMP */ 1756 1757/* 1758 * Release any resources held by the given physical map. 1759 * Called when a pmap initialized by pmap_pinit is being released. 1760 * Should only be called if the map contains no valid mappings. 1761 */ 1762void 1763pmap_release(pmap_t pmap) 1764{ 1765 vm_page_t m, ptdpg[2*NPGPTD+1]; 1766 vm_paddr_t ma; 1767 int i; 1768#ifdef PAE 1769 int npgptd = NPGPTD + 1; 1770#else 1771 int npgptd = NPGPTD; 1772#endif 1773 1774 KASSERT(pmap->pm_stats.resident_count == 0, 1775 ("pmap_release: pmap resident count %ld != 0", 1776 pmap->pm_stats.resident_count)); 1777 PT_UPDATES_FLUSH(); 1778 1779#ifdef HAMFISTED_LOCKING 1780 mtx_lock(&createdelete_lock); 1781#endif 1782 1783 pmap_lazyfix(pmap); 1784 mtx_lock_spin(&allpmaps_lock); 1785 LIST_REMOVE(pmap, pm_list); 1786 mtx_unlock_spin(&allpmaps_lock); 1787 1788 for (i = 0; i < NPGPTD; i++) 1789 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1790 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1791#ifdef PAE 1792 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1793#endif 1794 1795 for (i = 0; i < npgptd; i++) { 1796 m = ptdpg[i]; 1797 ma = VM_PAGE_TO_MACH(m); 1798 /* unpinning L1 and L2 treated the same */ 1799#if 0 1800 xen_pgd_unpin(ma); 1801#else 1802 if (i == NPGPTD) 1803 xen_pgd_unpin(ma); 1804#endif 1805#ifdef PAE 1806 if (i < NPGPTD) 1807 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1808 ("pmap_release: got wrong ptd page")); 1809#endif 1810 m->wire_count--; 1811 atomic_subtract_int(&cnt.v_wire_count, 1); 1812 vm_page_free(m); 1813 } 1814#ifdef PAE 1815 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1816#endif 1817 PMAP_LOCK_DESTROY(pmap); 1818 1819#ifdef HAMFISTED_LOCKING 1820 mtx_unlock(&createdelete_lock); 1821#endif 1822} 1823 1824static int 1825kvm_size(SYSCTL_HANDLER_ARGS) 1826{ 1827 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1828 1829 return (sysctl_handle_long(oidp, &ksize, 0, req)); 1830} 1831SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1832 0, 0, kvm_size, "IU", "Size of KVM"); 1833 1834static int 1835kvm_free(SYSCTL_HANDLER_ARGS) 1836{ 1837 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1838 1839 return (sysctl_handle_long(oidp, &kfree, 0, req)); 1840} 1841SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1842 0, 0, kvm_free, "IU", "Amount of KVM free"); 1843 1844/* 1845 * grow the number of kernel page table entries, if needed 1846 */ 1847void 1848pmap_growkernel(vm_offset_t addr) 1849{ 1850 struct pmap *pmap; 1851 vm_paddr_t ptppaddr; 1852 vm_page_t nkpg; 1853 pd_entry_t newpdir; 1854 1855 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1856 if (kernel_vm_end == 0) { 1857 kernel_vm_end = KERNBASE; 1858 nkpt = 0; 1859 while (pdir_pde(PTD, kernel_vm_end)) { 1860 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1861 nkpt++; 1862 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1863 kernel_vm_end = kernel_map->max_offset; 1864 break; 1865 } 1866 } 1867 } 1868 addr = roundup2(addr, NBPDR); 1869 if (addr - 1 >= kernel_map->max_offset) 1870 addr = kernel_map->max_offset; 1871 while (kernel_vm_end < addr) { 1872 if (pdir_pde(PTD, kernel_vm_end)) { 1873 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1874 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1875 kernel_vm_end = kernel_map->max_offset; 1876 break; 1877 } 1878 continue; 1879 } 1880 1881 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1882 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1883 VM_ALLOC_ZERO); 1884 if (nkpg == NULL) 1885 panic("pmap_growkernel: no memory to grow kernel"); 1886 1887 nkpt++; 1888 1889 if ((nkpg->flags & PG_ZERO) == 0) 1890 pmap_zero_page(nkpg); 1891 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1892 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1893 vm_page_lock_queues(); 1894 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1895 mtx_lock_spin(&allpmaps_lock); 1896 LIST_FOREACH(pmap, &allpmaps, pm_list) 1897 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1898 1899 mtx_unlock_spin(&allpmaps_lock); 1900 vm_page_unlock_queues(); 1901 1902 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1903 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1904 kernel_vm_end = kernel_map->max_offset; 1905 break; 1906 } 1907 } 1908} 1909 1910 1911/*************************************************** 1912 * page management routines. 1913 ***************************************************/ 1914 1915CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1916CTASSERT(_NPCM == 11); 1917CTASSERT(_NPCPV == 336); 1918 1919static __inline struct pv_chunk * 1920pv_to_chunk(pv_entry_t pv) 1921{ 1922 1923 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1924} 1925 1926#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1927 1928#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1929#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1930 1931static const uint32_t pc_freemask[_NPCM] = { 1932 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1933 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1934 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1935 PC_FREE0_9, PC_FREE10 1936}; 1937 1938SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1939 "Current number of pv entries"); 1940 1941#ifdef PV_STATS 1942static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1943 1944SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1945 "Current number of pv entry chunks"); 1946SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1947 "Current number of pv entry chunks allocated"); 1948SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1949 "Current number of pv entry chunks frees"); 1950SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1951 "Number of times tried to get a chunk page but failed."); 1952 1953static long pv_entry_frees, pv_entry_allocs; 1954static int pv_entry_spare; 1955 1956SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1957 "Current number of pv entry frees"); 1958SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1959 "Current number of pv entry allocs"); 1960SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1961 "Current number of spare pv entries"); 1962#endif 1963 1964/* 1965 * We are in a serious low memory condition. Resort to 1966 * drastic measures to free some pages so we can allocate 1967 * another pv entry chunk. 1968 */ 1969static vm_page_t 1970pmap_pv_reclaim(pmap_t locked_pmap) 1971{ 1972 struct pch newtail; 1973 struct pv_chunk *pc; 1974 pmap_t pmap; 1975 pt_entry_t *pte, tpte; 1976 pv_entry_t pv; 1977 vm_offset_t va; 1978 vm_page_t free, m, m_pc; 1979 uint32_t inuse; 1980 int bit, field, freed; 1981 1982 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1983 pmap = NULL; 1984 free = m_pc = NULL; 1985 TAILQ_INIT(&newtail); 1986 sched_pin(); 1987 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 1988 free == NULL)) { 1989 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1990 if (pmap != pc->pc_pmap) { 1991 if (pmap != NULL) { 1992 pmap_invalidate_all(pmap); 1993 if (pmap != locked_pmap) 1994 PMAP_UNLOCK(pmap); 1995 } 1996 pmap = pc->pc_pmap; 1997 /* Avoid deadlock and lock recursion. */ 1998 if (pmap > locked_pmap) 1999 PMAP_LOCK(pmap); 2000 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 2001 pmap = NULL; 2002 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2003 continue; 2004 } 2005 } 2006 2007 /* 2008 * Destroy every non-wired, 4 KB page mapping in the chunk. 2009 */ 2010 freed = 0; 2011 for (field = 0; field < _NPCM; field++) { 2012 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2013 inuse != 0; inuse &= ~(1UL << bit)) { 2014 bit = bsfl(inuse); 2015 pv = &pc->pc_pventry[field * 32 + bit]; 2016 va = pv->pv_va; 2017 pte = pmap_pte_quick(pmap, va); 2018 if ((*pte & PG_W) != 0) 2019 continue; 2020 tpte = pte_load_clear(pte); 2021 if ((tpte & PG_G) != 0) 2022 pmap_invalidate_page(pmap, va); 2023 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2024 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2025 vm_page_dirty(m); 2026 if ((tpte & PG_A) != 0) 2027 vm_page_aflag_set(m, PGA_REFERENCED); 2028 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2029 if (TAILQ_EMPTY(&m->md.pv_list)) 2030 vm_page_aflag_clear(m, PGA_WRITEABLE); 2031 pc->pc_map[field] |= 1UL << bit; 2032 pmap_unuse_pt(pmap, va, &free); 2033 freed++; 2034 } 2035 } 2036 if (freed == 0) { 2037 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2038 continue; 2039 } 2040 /* Every freed mapping is for a 4 KB page. */ 2041 pmap->pm_stats.resident_count -= freed; 2042 PV_STAT(pv_entry_frees += freed); 2043 PV_STAT(pv_entry_spare += freed); 2044 pv_entry_count -= freed; 2045 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2046 for (field = 0; field < _NPCM; field++) 2047 if (pc->pc_map[field] != pc_freemask[field]) { 2048 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2049 pc_list); 2050 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2051 2052 /* 2053 * One freed pv entry in locked_pmap is 2054 * sufficient. 2055 */ 2056 if (pmap == locked_pmap) 2057 goto out; 2058 break; 2059 } 2060 if (field == _NPCM) { 2061 PV_STAT(pv_entry_spare -= _NPCPV); 2062 PV_STAT(pc_chunk_count--); 2063 PV_STAT(pc_chunk_frees++); 2064 /* Entire chunk is free; return it. */ 2065 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2066 pmap_qremove((vm_offset_t)pc, 1); 2067 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2068 break; 2069 } 2070 } 2071out: 2072 sched_unpin(); 2073 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 2074 if (pmap != NULL) { 2075 pmap_invalidate_all(pmap); 2076 if (pmap != locked_pmap) 2077 PMAP_UNLOCK(pmap); 2078 } 2079 if (m_pc == NULL && pv_vafree != 0 && free != NULL) { 2080 m_pc = free; 2081 free = m_pc->right; 2082 /* Recycle a freed page table page. */ 2083 m_pc->wire_count = 1; 2084 atomic_add_int(&cnt.v_wire_count, 1); 2085 } 2086 pmap_free_zero_pages(free); 2087 return (m_pc); 2088} 2089 2090/* 2091 * free the pv_entry back to the free list 2092 */ 2093static void 2094free_pv_entry(pmap_t pmap, pv_entry_t pv) 2095{ 2096 struct pv_chunk *pc; 2097 int idx, field, bit; 2098 2099 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2100 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2101 PV_STAT(pv_entry_frees++); 2102 PV_STAT(pv_entry_spare++); 2103 pv_entry_count--; 2104 pc = pv_to_chunk(pv); 2105 idx = pv - &pc->pc_pventry[0]; 2106 field = idx / 32; 2107 bit = idx % 32; 2108 pc->pc_map[field] |= 1ul << bit; 2109 for (idx = 0; idx < _NPCM; idx++) 2110 if (pc->pc_map[idx] != pc_freemask[idx]) { 2111 /* 2112 * 98% of the time, pc is already at the head of the 2113 * list. If it isn't already, move it to the head. 2114 */ 2115 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 2116 pc)) { 2117 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2118 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2119 pc_list); 2120 } 2121 return; 2122 } 2123 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2124 free_pv_chunk(pc); 2125} 2126 2127static void 2128free_pv_chunk(struct pv_chunk *pc) 2129{ 2130 vm_page_t m; 2131 2132 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2133 PV_STAT(pv_entry_spare -= _NPCPV); 2134 PV_STAT(pc_chunk_count--); 2135 PV_STAT(pc_chunk_frees++); 2136 /* entire chunk is free, return it */ 2137 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2138 pmap_qremove((vm_offset_t)pc, 1); 2139 vm_page_unwire(m, 0); 2140 vm_page_free(m); 2141 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2142} 2143 2144/* 2145 * get a new pv_entry, allocating a block from the system 2146 * when needed. 2147 */ 2148static pv_entry_t 2149get_pv_entry(pmap_t pmap, boolean_t try) 2150{ 2151 static const struct timeval printinterval = { 60, 0 }; 2152 static struct timeval lastprint; 2153 int bit, field; 2154 pv_entry_t pv; 2155 struct pv_chunk *pc; 2156 vm_page_t m; 2157 2158 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2159 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2160 PV_STAT(pv_entry_allocs++); 2161 pv_entry_count++; 2162 if (pv_entry_count > pv_entry_high_water) 2163 if (ratecheck(&lastprint, &printinterval)) 2164 printf("Approaching the limit on PV entries, consider " 2165 "increasing either the vm.pmap.shpgperproc or the " 2166 "vm.pmap.pv_entry_max tunable.\n"); 2167retry: 2168 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2169 if (pc != NULL) { 2170 for (field = 0; field < _NPCM; field++) { 2171 if (pc->pc_map[field]) { 2172 bit = bsfl(pc->pc_map[field]); 2173 break; 2174 } 2175 } 2176 if (field < _NPCM) { 2177 pv = &pc->pc_pventry[field * 32 + bit]; 2178 pc->pc_map[field] &= ~(1ul << bit); 2179 /* If this was the last item, move it to tail */ 2180 for (field = 0; field < _NPCM; field++) 2181 if (pc->pc_map[field] != 0) { 2182 PV_STAT(pv_entry_spare--); 2183 return (pv); /* not full, return */ 2184 } 2185 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2186 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2187 PV_STAT(pv_entry_spare--); 2188 return (pv); 2189 } 2190 } 2191 /* 2192 * Access to the ptelist "pv_vafree" is synchronized by the page 2193 * queues lock. If "pv_vafree" is currently non-empty, it will 2194 * remain non-empty until pmap_ptelist_alloc() completes. 2195 */ 2196 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2197 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2198 if (try) { 2199 pv_entry_count--; 2200 PV_STAT(pc_chunk_tryfail++); 2201 return (NULL); 2202 } 2203 m = pmap_pv_reclaim(pmap); 2204 if (m == NULL) 2205 goto retry; 2206 } 2207 PV_STAT(pc_chunk_count++); 2208 PV_STAT(pc_chunk_allocs++); 2209 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2210 pmap_qenter((vm_offset_t)pc, &m, 1); 2211 if ((m->flags & PG_ZERO) == 0) 2212 pagezero(pc); 2213 pc->pc_pmap = pmap; 2214 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2215 for (field = 1; field < _NPCM; field++) 2216 pc->pc_map[field] = pc_freemask[field]; 2217 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2218 pv = &pc->pc_pventry[0]; 2219 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2220 PV_STAT(pv_entry_spare += _NPCPV - 1); 2221 return (pv); 2222} 2223 2224static __inline pv_entry_t 2225pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2226{ 2227 pv_entry_t pv; 2228 2229 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2230 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2231 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2232 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2233 break; 2234 } 2235 } 2236 return (pv); 2237} 2238 2239static void 2240pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2241{ 2242 pv_entry_t pv; 2243 2244 pv = pmap_pvh_remove(pvh, pmap, va); 2245 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2246 free_pv_entry(pmap, pv); 2247} 2248 2249static void 2250pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2251{ 2252 2253 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2254 pmap_pvh_free(&m->md, pmap, va); 2255 if (TAILQ_EMPTY(&m->md.pv_list)) 2256 vm_page_aflag_clear(m, PGA_WRITEABLE); 2257} 2258 2259/* 2260 * Conditionally create a pv entry. 2261 */ 2262static boolean_t 2263pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2264{ 2265 pv_entry_t pv; 2266 2267 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2268 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2269 if (pv_entry_count < pv_entry_high_water && 2270 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2271 pv->pv_va = va; 2272 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2273 return (TRUE); 2274 } else 2275 return (FALSE); 2276} 2277 2278/* 2279 * pmap_remove_pte: do the things to unmap a page in a process 2280 */ 2281static int 2282pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2283{ 2284 pt_entry_t oldpte; 2285 vm_page_t m; 2286 2287 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2288 pmap, (u_long)*ptq, va); 2289 2290 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2291 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2292 oldpte = *ptq; 2293 PT_SET_VA_MA(ptq, 0, TRUE); 2294 if (oldpte & PG_W) 2295 pmap->pm_stats.wired_count -= 1; 2296 /* 2297 * Machines that don't support invlpg, also don't support 2298 * PG_G. 2299 */ 2300 if (oldpte & PG_G) 2301 pmap_invalidate_page(kernel_pmap, va); 2302 pmap->pm_stats.resident_count -= 1; 2303 if (oldpte & PG_MANAGED) { 2304 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2305 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2306 vm_page_dirty(m); 2307 if (oldpte & PG_A) 2308 vm_page_aflag_set(m, PGA_REFERENCED); 2309 pmap_remove_entry(pmap, m, va); 2310 } 2311 return (pmap_unuse_pt(pmap, va, free)); 2312} 2313 2314/* 2315 * Remove a single page from a process address space 2316 */ 2317static void 2318pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2319{ 2320 pt_entry_t *pte; 2321 2322 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2323 pmap, va); 2324 2325 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2326 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2327 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2328 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2329 return; 2330 pmap_remove_pte(pmap, pte, va, free); 2331 pmap_invalidate_page(pmap, va); 2332 if (*PMAP1) 2333 PT_SET_MA(PADDR1, 0); 2334 2335} 2336 2337/* 2338 * Remove the given range of addresses from the specified map. 2339 * 2340 * It is assumed that the start and end are properly 2341 * rounded to the page size. 2342 */ 2343void 2344pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2345{ 2346 vm_offset_t pdnxt; 2347 pd_entry_t ptpaddr; 2348 pt_entry_t *pte; 2349 vm_page_t free = NULL; 2350 int anyvalid; 2351 2352 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2353 pmap, sva, eva); 2354 2355 /* 2356 * Perform an unsynchronized read. This is, however, safe. 2357 */ 2358 if (pmap->pm_stats.resident_count == 0) 2359 return; 2360 2361 anyvalid = 0; 2362 2363 vm_page_lock_queues(); 2364 sched_pin(); 2365 PMAP_LOCK(pmap); 2366 2367 /* 2368 * special handling of removing one page. a very 2369 * common operation and easy to short circuit some 2370 * code. 2371 */ 2372 if ((sva + PAGE_SIZE == eva) && 2373 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2374 pmap_remove_page(pmap, sva, &free); 2375 goto out; 2376 } 2377 2378 for (; sva < eva; sva = pdnxt) { 2379 u_int pdirindex; 2380 2381 /* 2382 * Calculate index for next page table. 2383 */ 2384 pdnxt = (sva + NBPDR) & ~PDRMASK; 2385 if (pdnxt < sva) 2386 pdnxt = eva; 2387 if (pmap->pm_stats.resident_count == 0) 2388 break; 2389 2390 pdirindex = sva >> PDRSHIFT; 2391 ptpaddr = pmap->pm_pdir[pdirindex]; 2392 2393 /* 2394 * Weed out invalid mappings. Note: we assume that the page 2395 * directory table is always allocated, and in kernel virtual. 2396 */ 2397 if (ptpaddr == 0) 2398 continue; 2399 2400 /* 2401 * Check for large page. 2402 */ 2403 if ((ptpaddr & PG_PS) != 0) { 2404 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2405 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2406 anyvalid = 1; 2407 continue; 2408 } 2409 2410 /* 2411 * Limit our scan to either the end of the va represented 2412 * by the current page table page, or to the end of the 2413 * range being removed. 2414 */ 2415 if (pdnxt > eva) 2416 pdnxt = eva; 2417 2418 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2419 sva += PAGE_SIZE) { 2420 if ((*pte & PG_V) == 0) 2421 continue; 2422 2423 /* 2424 * The TLB entry for a PG_G mapping is invalidated 2425 * by pmap_remove_pte(). 2426 */ 2427 if ((*pte & PG_G) == 0) 2428 anyvalid = 1; 2429 if (pmap_remove_pte(pmap, pte, sva, &free)) 2430 break; 2431 } 2432 } 2433 PT_UPDATES_FLUSH(); 2434 if (*PMAP1) 2435 PT_SET_VA_MA(PMAP1, 0, TRUE); 2436out: 2437 if (anyvalid) 2438 pmap_invalidate_all(pmap); 2439 sched_unpin(); 2440 vm_page_unlock_queues(); 2441 PMAP_UNLOCK(pmap); 2442 pmap_free_zero_pages(free); 2443} 2444 2445/* 2446 * Routine: pmap_remove_all 2447 * Function: 2448 * Removes this physical page from 2449 * all physical maps in which it resides. 2450 * Reflects back modify bits to the pager. 2451 * 2452 * Notes: 2453 * Original versions of this routine were very 2454 * inefficient because they iteratively called 2455 * pmap_remove (slow...) 2456 */ 2457 2458void 2459pmap_remove_all(vm_page_t m) 2460{ 2461 pv_entry_t pv; 2462 pmap_t pmap; 2463 pt_entry_t *pte, tpte; 2464 vm_page_t free; 2465 2466 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2467 ("pmap_remove_all: page %p is not managed", m)); 2468 free = NULL; 2469 vm_page_lock_queues(); 2470 sched_pin(); 2471 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2472 pmap = PV_PMAP(pv); 2473 PMAP_LOCK(pmap); 2474 pmap->pm_stats.resident_count--; 2475 pte = pmap_pte_quick(pmap, pv->pv_va); 2476 tpte = *pte; 2477 PT_SET_VA_MA(pte, 0, TRUE); 2478 if (tpte & PG_W) 2479 pmap->pm_stats.wired_count--; 2480 if (tpte & PG_A) 2481 vm_page_aflag_set(m, PGA_REFERENCED); 2482 2483 /* 2484 * Update the vm_page_t clean and reference bits. 2485 */ 2486 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2487 vm_page_dirty(m); 2488 pmap_unuse_pt(pmap, pv->pv_va, &free); 2489 pmap_invalidate_page(pmap, pv->pv_va); 2490 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2491 free_pv_entry(pmap, pv); 2492 PMAP_UNLOCK(pmap); 2493 } 2494 vm_page_aflag_clear(m, PGA_WRITEABLE); 2495 PT_UPDATES_FLUSH(); 2496 if (*PMAP1) 2497 PT_SET_MA(PADDR1, 0); 2498 sched_unpin(); 2499 vm_page_unlock_queues(); 2500 pmap_free_zero_pages(free); 2501} 2502 2503/* 2504 * Set the physical protection on the 2505 * specified range of this map as requested. 2506 */ 2507void 2508pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2509{ 2510 vm_offset_t pdnxt; 2511 pd_entry_t ptpaddr; 2512 pt_entry_t *pte; 2513 int anychanged; 2514 2515 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2516 pmap, sva, eva, prot); 2517 2518 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2519 pmap_remove(pmap, sva, eva); 2520 return; 2521 } 2522 2523#ifdef PAE 2524 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2525 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2526 return; 2527#else 2528 if (prot & VM_PROT_WRITE) 2529 return; 2530#endif 2531 2532 anychanged = 0; 2533 2534 vm_page_lock_queues(); 2535 sched_pin(); 2536 PMAP_LOCK(pmap); 2537 for (; sva < eva; sva = pdnxt) { 2538 pt_entry_t obits, pbits; 2539 u_int pdirindex; 2540 2541 pdnxt = (sva + NBPDR) & ~PDRMASK; 2542 if (pdnxt < sva) 2543 pdnxt = eva; 2544 2545 pdirindex = sva >> PDRSHIFT; 2546 ptpaddr = pmap->pm_pdir[pdirindex]; 2547 2548 /* 2549 * Weed out invalid mappings. Note: we assume that the page 2550 * directory table is always allocated, and in kernel virtual. 2551 */ 2552 if (ptpaddr == 0) 2553 continue; 2554 2555 /* 2556 * Check for large page. 2557 */ 2558 if ((ptpaddr & PG_PS) != 0) { 2559 if ((prot & VM_PROT_WRITE) == 0) 2560 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2561#ifdef PAE 2562 if ((prot & VM_PROT_EXECUTE) == 0) 2563 pmap->pm_pdir[pdirindex] |= pg_nx; 2564#endif 2565 anychanged = 1; 2566 continue; 2567 } 2568 2569 if (pdnxt > eva) 2570 pdnxt = eva; 2571 2572 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2573 sva += PAGE_SIZE) { 2574 vm_page_t m; 2575 2576retry: 2577 /* 2578 * Regardless of whether a pte is 32 or 64 bits in 2579 * size, PG_RW, PG_A, and PG_M are among the least 2580 * significant 32 bits. 2581 */ 2582 obits = pbits = *pte; 2583 if ((pbits & PG_V) == 0) 2584 continue; 2585 2586 if ((prot & VM_PROT_WRITE) == 0) { 2587 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2588 (PG_MANAGED | PG_M | PG_RW)) { 2589 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2590 PG_FRAME); 2591 vm_page_dirty(m); 2592 } 2593 pbits &= ~(PG_RW | PG_M); 2594 } 2595#ifdef PAE 2596 if ((prot & VM_PROT_EXECUTE) == 0) 2597 pbits |= pg_nx; 2598#endif 2599 2600 if (pbits != obits) { 2601 obits = *pte; 2602 PT_SET_VA_MA(pte, pbits, TRUE); 2603 if (*pte != pbits) 2604 goto retry; 2605 if (obits & PG_G) 2606 pmap_invalidate_page(pmap, sva); 2607 else 2608 anychanged = 1; 2609 } 2610 } 2611 } 2612 PT_UPDATES_FLUSH(); 2613 if (*PMAP1) 2614 PT_SET_VA_MA(PMAP1, 0, TRUE); 2615 if (anychanged) 2616 pmap_invalidate_all(pmap); 2617 sched_unpin(); 2618 vm_page_unlock_queues(); 2619 PMAP_UNLOCK(pmap); 2620} 2621 2622/* 2623 * Insert the given physical page (p) at 2624 * the specified virtual address (v) in the 2625 * target physical map with the protection requested. 2626 * 2627 * If specified, the page will be wired down, meaning 2628 * that the related pte can not be reclaimed. 2629 * 2630 * NB: This is the only routine which MAY NOT lazy-evaluate 2631 * or lose information. That is, this routine must actually 2632 * insert this page into the given map NOW. 2633 */ 2634void 2635pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2636 vm_prot_t prot, boolean_t wired) 2637{ 2638 pd_entry_t *pde; 2639 pt_entry_t *pte; 2640 pt_entry_t newpte, origpte; 2641 pv_entry_t pv; 2642 vm_paddr_t opa, pa; 2643 vm_page_t mpte, om; 2644 boolean_t invlva; 2645 2646 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2647 pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2648 va = trunc_page(va); 2649 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2650 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2651 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2652 va)); 2653 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 2654 VM_OBJECT_LOCKED(m->object), 2655 ("pmap_enter: page %p is not busy", m)); 2656 2657 mpte = NULL; 2658 2659 vm_page_lock_queues(); 2660 PMAP_LOCK(pmap); 2661 sched_pin(); 2662 2663 /* 2664 * In the case that a page table page is not 2665 * resident, we are creating it here. 2666 */ 2667 if (va < VM_MAXUSER_ADDRESS) { 2668 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2669 } 2670 2671 pde = pmap_pde(pmap, va); 2672 if ((*pde & PG_PS) != 0) 2673 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2674 pte = pmap_pte_quick(pmap, va); 2675 2676 /* 2677 * Page Directory table entry not valid, we need a new PT page 2678 */ 2679 if (pte == NULL) { 2680 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2681 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2682 } 2683 2684 pa = VM_PAGE_TO_PHYS(m); 2685 om = NULL; 2686 opa = origpte = 0; 2687 2688#if 0 2689 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2690 pte, *pte)); 2691#endif 2692 origpte = *pte; 2693 if (origpte) 2694 origpte = xpmap_mtop(origpte); 2695 opa = origpte & PG_FRAME; 2696 2697 /* 2698 * Mapping has not changed, must be protection or wiring change. 2699 */ 2700 if (origpte && (opa == pa)) { 2701 /* 2702 * Wiring change, just update stats. We don't worry about 2703 * wiring PT pages as they remain resident as long as there 2704 * are valid mappings in them. Hence, if a user page is wired, 2705 * the PT page will be also. 2706 */ 2707 if (wired && ((origpte & PG_W) == 0)) 2708 pmap->pm_stats.wired_count++; 2709 else if (!wired && (origpte & PG_W)) 2710 pmap->pm_stats.wired_count--; 2711 2712 /* 2713 * Remove extra pte reference 2714 */ 2715 if (mpte) 2716 mpte->wire_count--; 2717 2718 if (origpte & PG_MANAGED) { 2719 om = m; 2720 pa |= PG_MANAGED; 2721 } 2722 goto validate; 2723 } 2724 2725 pv = NULL; 2726 2727 /* 2728 * Mapping has changed, invalidate old range and fall through to 2729 * handle validating new mapping. 2730 */ 2731 if (opa) { 2732 if (origpte & PG_W) 2733 pmap->pm_stats.wired_count--; 2734 if (origpte & PG_MANAGED) { 2735 om = PHYS_TO_VM_PAGE(opa); 2736 pv = pmap_pvh_remove(&om->md, pmap, va); 2737 } else if (va < VM_MAXUSER_ADDRESS) 2738 printf("va=0x%x is unmanaged :-( \n", va); 2739 2740 if (mpte != NULL) { 2741 mpte->wire_count--; 2742 KASSERT(mpte->wire_count > 0, 2743 ("pmap_enter: missing reference to page table page," 2744 " va: 0x%x", va)); 2745 } 2746 } else 2747 pmap->pm_stats.resident_count++; 2748 2749 /* 2750 * Enter on the PV list if part of our managed memory. 2751 */ 2752 if ((m->oflags & VPO_UNMANAGED) == 0) { 2753 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2754 ("pmap_enter: managed mapping within the clean submap")); 2755 if (pv == NULL) 2756 pv = get_pv_entry(pmap, FALSE); 2757 pv->pv_va = va; 2758 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2759 pa |= PG_MANAGED; 2760 } else if (pv != NULL) 2761 free_pv_entry(pmap, pv); 2762 2763 /* 2764 * Increment counters 2765 */ 2766 if (wired) 2767 pmap->pm_stats.wired_count++; 2768 2769validate: 2770 /* 2771 * Now validate mapping with desired protection/wiring. 2772 */ 2773 newpte = (pt_entry_t)(pa | PG_V); 2774 if ((prot & VM_PROT_WRITE) != 0) { 2775 newpte |= PG_RW; 2776 if ((newpte & PG_MANAGED) != 0) 2777 vm_page_aflag_set(m, PGA_WRITEABLE); 2778 } 2779#ifdef PAE 2780 if ((prot & VM_PROT_EXECUTE) == 0) 2781 newpte |= pg_nx; 2782#endif 2783 if (wired) 2784 newpte |= PG_W; 2785 if (va < VM_MAXUSER_ADDRESS) 2786 newpte |= PG_U; 2787 if (pmap == kernel_pmap) 2788 newpte |= pgeflag; 2789 2790 critical_enter(); 2791 /* 2792 * if the mapping or permission bits are different, we need 2793 * to update the pte. 2794 */ 2795 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2796 if (origpte) { 2797 invlva = FALSE; 2798 origpte = *pte; 2799 PT_SET_VA(pte, newpte | PG_A, FALSE); 2800 if (origpte & PG_A) { 2801 if (origpte & PG_MANAGED) 2802 vm_page_aflag_set(om, PGA_REFERENCED); 2803 if (opa != VM_PAGE_TO_PHYS(m)) 2804 invlva = TRUE; 2805#ifdef PAE 2806 if ((origpte & PG_NX) == 0 && 2807 (newpte & PG_NX) != 0) 2808 invlva = TRUE; 2809#endif 2810 } 2811 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2812 if ((origpte & PG_MANAGED) != 0) 2813 vm_page_dirty(om); 2814 if ((prot & VM_PROT_WRITE) == 0) 2815 invlva = TRUE; 2816 } 2817 if ((origpte & PG_MANAGED) != 0 && 2818 TAILQ_EMPTY(&om->md.pv_list)) 2819 vm_page_aflag_clear(om, PGA_WRITEABLE); 2820 if (invlva) 2821 pmap_invalidate_page(pmap, va); 2822 } else{ 2823 PT_SET_VA(pte, newpte | PG_A, FALSE); 2824 } 2825 2826 } 2827 PT_UPDATES_FLUSH(); 2828 critical_exit(); 2829 if (*PMAP1) 2830 PT_SET_VA_MA(PMAP1, 0, TRUE); 2831 sched_unpin(); 2832 vm_page_unlock_queues(); 2833 PMAP_UNLOCK(pmap); 2834} 2835 2836/* 2837 * Maps a sequence of resident pages belonging to the same object. 2838 * The sequence begins with the given page m_start. This page is 2839 * mapped at the given virtual address start. Each subsequent page is 2840 * mapped at a virtual address that is offset from start by the same 2841 * amount as the page is offset from m_start within the object. The 2842 * last page in the sequence is the page with the largest offset from 2843 * m_start that can be mapped at a virtual address less than the given 2844 * virtual address end. Not every virtual page between start and end 2845 * is mapped; only those for which a resident page exists with the 2846 * corresponding offset from m_start are mapped. 2847 */ 2848void 2849pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2850 vm_page_t m_start, vm_prot_t prot) 2851{ 2852 vm_page_t m, mpte; 2853 vm_pindex_t diff, psize; 2854 multicall_entry_t mcl[16]; 2855 multicall_entry_t *mclp = mcl; 2856 int error, count = 0; 2857 2858 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2859 psize = atop(end - start); 2860 mpte = NULL; 2861 m = m_start; 2862 vm_page_lock_queues(); 2863 PMAP_LOCK(pmap); 2864 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2865 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2866 prot, mpte); 2867 m = TAILQ_NEXT(m, listq); 2868 if (count == 16) { 2869 error = HYPERVISOR_multicall(mcl, count); 2870 KASSERT(error == 0, ("bad multicall %d", error)); 2871 mclp = mcl; 2872 count = 0; 2873 } 2874 } 2875 if (count) { 2876 error = HYPERVISOR_multicall(mcl, count); 2877 KASSERT(error == 0, ("bad multicall %d", error)); 2878 } 2879 vm_page_unlock_queues(); 2880 PMAP_UNLOCK(pmap); 2881} 2882 2883/* 2884 * this code makes some *MAJOR* assumptions: 2885 * 1. Current pmap & pmap exists. 2886 * 2. Not wired. 2887 * 3. Read access. 2888 * 4. No page table pages. 2889 * but is *MUCH* faster than pmap_enter... 2890 */ 2891 2892void 2893pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2894{ 2895 multicall_entry_t mcl, *mclp; 2896 int count = 0; 2897 mclp = &mcl; 2898 2899 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2900 pmap, va, m, prot); 2901 2902 vm_page_lock_queues(); 2903 PMAP_LOCK(pmap); 2904 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2905 if (count) 2906 HYPERVISOR_multicall(&mcl, count); 2907 vm_page_unlock_queues(); 2908 PMAP_UNLOCK(pmap); 2909} 2910 2911#ifdef notyet 2912void 2913pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2914{ 2915 int i, error, index = 0; 2916 multicall_entry_t mcl[16]; 2917 multicall_entry_t *mclp = mcl; 2918 2919 PMAP_LOCK(pmap); 2920 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2921 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2922 continue; 2923 2924 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2925 if (index == 16) { 2926 error = HYPERVISOR_multicall(mcl, index); 2927 mclp = mcl; 2928 index = 0; 2929 KASSERT(error == 0, ("bad multicall %d", error)); 2930 } 2931 } 2932 if (index) { 2933 error = HYPERVISOR_multicall(mcl, index); 2934 KASSERT(error == 0, ("bad multicall %d", error)); 2935 } 2936 2937 PMAP_UNLOCK(pmap); 2938} 2939#endif 2940 2941static vm_page_t 2942pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2943 vm_prot_t prot, vm_page_t mpte) 2944{ 2945 pt_entry_t *pte; 2946 vm_paddr_t pa; 2947 vm_page_t free; 2948 multicall_entry_t *mcl = *mclpp; 2949 2950 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2951 (m->oflags & VPO_UNMANAGED) != 0, 2952 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2953 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2954 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2955 2956 /* 2957 * In the case that a page table page is not 2958 * resident, we are creating it here. 2959 */ 2960 if (va < VM_MAXUSER_ADDRESS) { 2961 u_int ptepindex; 2962 pd_entry_t ptema; 2963 2964 /* 2965 * Calculate pagetable page index 2966 */ 2967 ptepindex = va >> PDRSHIFT; 2968 if (mpte && (mpte->pindex == ptepindex)) { 2969 mpte->wire_count++; 2970 } else { 2971 /* 2972 * Get the page directory entry 2973 */ 2974 ptema = pmap->pm_pdir[ptepindex]; 2975 2976 /* 2977 * If the page table page is mapped, we just increment 2978 * the hold count, and activate it. 2979 */ 2980 if (ptema & PG_V) { 2981 if (ptema & PG_PS) 2982 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2983 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2984 mpte->wire_count++; 2985 } else { 2986 mpte = _pmap_allocpte(pmap, ptepindex, 2987 M_NOWAIT); 2988 if (mpte == NULL) 2989 return (mpte); 2990 } 2991 } 2992 } else { 2993 mpte = NULL; 2994 } 2995 2996 /* 2997 * This call to vtopte makes the assumption that we are 2998 * entering the page into the current pmap. In order to support 2999 * quick entry into any pmap, one would likely use pmap_pte_quick. 3000 * But that isn't as quick as vtopte. 3001 */ 3002 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 3003 pte = vtopte(va); 3004 if (*pte & PG_V) { 3005 if (mpte != NULL) { 3006 mpte->wire_count--; 3007 mpte = NULL; 3008 } 3009 return (mpte); 3010 } 3011 3012 /* 3013 * Enter on the PV list if part of our managed memory. 3014 */ 3015 if ((m->oflags & VPO_UNMANAGED) == 0 && 3016 !pmap_try_insert_pv_entry(pmap, va, m)) { 3017 if (mpte != NULL) { 3018 free = NULL; 3019 if (pmap_unwire_ptp(pmap, mpte, &free)) { 3020 pmap_invalidate_page(pmap, va); 3021 pmap_free_zero_pages(free); 3022 } 3023 3024 mpte = NULL; 3025 } 3026 return (mpte); 3027 } 3028 3029 /* 3030 * Increment counters 3031 */ 3032 pmap->pm_stats.resident_count++; 3033 3034 pa = VM_PAGE_TO_PHYS(m); 3035#ifdef PAE 3036 if ((prot & VM_PROT_EXECUTE) == 0) 3037 pa |= pg_nx; 3038#endif 3039 3040#if 0 3041 /* 3042 * Now validate mapping with RO protection 3043 */ 3044 if ((m->oflags & VPO_UNMANAGED) != 0) 3045 pte_store(pte, pa | PG_V | PG_U); 3046 else 3047 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3048#else 3049 /* 3050 * Now validate mapping with RO protection 3051 */ 3052 if ((m->oflags & VPO_UNMANAGED) != 0) 3053 pa = xpmap_ptom(pa | PG_V | PG_U); 3054 else 3055 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3056 3057 mcl->op = __HYPERVISOR_update_va_mapping; 3058 mcl->args[0] = va; 3059 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3060 mcl->args[2] = (uint32_t)(pa >> 32); 3061 mcl->args[3] = 0; 3062 *mclpp = mcl + 1; 3063 *count = *count + 1; 3064#endif 3065 return (mpte); 3066} 3067 3068/* 3069 * Make a temporary mapping for a physical address. This is only intended 3070 * to be used for panic dumps. 3071 */ 3072void * 3073pmap_kenter_temporary(vm_paddr_t pa, int i) 3074{ 3075 vm_offset_t va; 3076 vm_paddr_t ma = xpmap_ptom(pa); 3077 3078 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3079 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3080 invlpg(va); 3081 return ((void *)crashdumpmap); 3082} 3083 3084/* 3085 * This code maps large physical mmap regions into the 3086 * processor address space. Note that some shortcuts 3087 * are taken, but the code works. 3088 */ 3089void 3090pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3091 vm_pindex_t pindex, vm_size_t size) 3092{ 3093 pd_entry_t *pde; 3094 vm_paddr_t pa, ptepa; 3095 vm_page_t p; 3096 int pat_mode; 3097 3098 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3099 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3100 ("pmap_object_init_pt: non-device object")); 3101 if (pseflag && 3102 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3103 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3104 return; 3105 p = vm_page_lookup(object, pindex); 3106 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3107 ("pmap_object_init_pt: invalid page %p", p)); 3108 pat_mode = p->md.pat_mode; 3109 3110 /* 3111 * Abort the mapping if the first page is not physically 3112 * aligned to a 2/4MB page boundary. 3113 */ 3114 ptepa = VM_PAGE_TO_PHYS(p); 3115 if (ptepa & (NBPDR - 1)) 3116 return; 3117 3118 /* 3119 * Skip the first page. Abort the mapping if the rest of 3120 * the pages are not physically contiguous or have differing 3121 * memory attributes. 3122 */ 3123 p = TAILQ_NEXT(p, listq); 3124 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3125 pa += PAGE_SIZE) { 3126 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3127 ("pmap_object_init_pt: invalid page %p", p)); 3128 if (pa != VM_PAGE_TO_PHYS(p) || 3129 pat_mode != p->md.pat_mode) 3130 return; 3131 p = TAILQ_NEXT(p, listq); 3132 } 3133 3134 /* 3135 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3136 * "size" is a multiple of 2/4M, adding the PAT setting to 3137 * "pa" will not affect the termination of this loop. 3138 */ 3139 PMAP_LOCK(pmap); 3140 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3141 size; pa += NBPDR) { 3142 pde = pmap_pde(pmap, addr); 3143 if (*pde == 0) { 3144 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3145 PG_U | PG_RW | PG_V); 3146 pmap->pm_stats.resident_count += NBPDR / 3147 PAGE_SIZE; 3148 pmap_pde_mappings++; 3149 } 3150 /* Else continue on if the PDE is already valid. */ 3151 addr += NBPDR; 3152 } 3153 PMAP_UNLOCK(pmap); 3154 } 3155} 3156 3157/* 3158 * Routine: pmap_change_wiring 3159 * Function: Change the wiring attribute for a map/virtual-address 3160 * pair. 3161 * In/out conditions: 3162 * The mapping must already exist in the pmap. 3163 */ 3164void 3165pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3166{ 3167 pt_entry_t *pte; 3168 3169 vm_page_lock_queues(); 3170 PMAP_LOCK(pmap); 3171 pte = pmap_pte(pmap, va); 3172 3173 if (wired && !pmap_pte_w(pte)) { 3174 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3175 pmap->pm_stats.wired_count++; 3176 } else if (!wired && pmap_pte_w(pte)) { 3177 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3178 pmap->pm_stats.wired_count--; 3179 } 3180 3181 /* 3182 * Wiring is not a hardware characteristic so there is no need to 3183 * invalidate TLB. 3184 */ 3185 pmap_pte_release(pte); 3186 PMAP_UNLOCK(pmap); 3187 vm_page_unlock_queues(); 3188} 3189 3190 3191 3192/* 3193 * Copy the range specified by src_addr/len 3194 * from the source map to the range dst_addr/len 3195 * in the destination map. 3196 * 3197 * This routine is only advisory and need not do anything. 3198 */ 3199 3200void 3201pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3202 vm_offset_t src_addr) 3203{ 3204 vm_page_t free; 3205 vm_offset_t addr; 3206 vm_offset_t end_addr = src_addr + len; 3207 vm_offset_t pdnxt; 3208 3209 if (dst_addr != src_addr) 3210 return; 3211 3212 if (!pmap_is_current(src_pmap)) { 3213 CTR2(KTR_PMAP, 3214 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3215 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3216 3217 return; 3218 } 3219 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3220 dst_pmap, src_pmap, dst_addr, len, src_addr); 3221 3222#ifdef HAMFISTED_LOCKING 3223 mtx_lock(&createdelete_lock); 3224#endif 3225 3226 vm_page_lock_queues(); 3227 if (dst_pmap < src_pmap) { 3228 PMAP_LOCK(dst_pmap); 3229 PMAP_LOCK(src_pmap); 3230 } else { 3231 PMAP_LOCK(src_pmap); 3232 PMAP_LOCK(dst_pmap); 3233 } 3234 sched_pin(); 3235 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3236 pt_entry_t *src_pte, *dst_pte; 3237 vm_page_t dstmpte, srcmpte; 3238 pd_entry_t srcptepaddr; 3239 u_int ptepindex; 3240 3241 KASSERT(addr < UPT_MIN_ADDRESS, 3242 ("pmap_copy: invalid to pmap_copy page tables")); 3243 3244 pdnxt = (addr + NBPDR) & ~PDRMASK; 3245 if (pdnxt < addr) 3246 pdnxt = end_addr; 3247 ptepindex = addr >> PDRSHIFT; 3248 3249 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3250 if (srcptepaddr == 0) 3251 continue; 3252 3253 if (srcptepaddr & PG_PS) { 3254 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3255 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3256 dst_pmap->pm_stats.resident_count += 3257 NBPDR / PAGE_SIZE; 3258 } 3259 continue; 3260 } 3261 3262 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3263 KASSERT(srcmpte->wire_count > 0, 3264 ("pmap_copy: source page table page is unused")); 3265 3266 if (pdnxt > end_addr) 3267 pdnxt = end_addr; 3268 3269 src_pte = vtopte(addr); 3270 while (addr < pdnxt) { 3271 pt_entry_t ptetemp; 3272 ptetemp = *src_pte; 3273 /* 3274 * we only virtual copy managed pages 3275 */ 3276 if ((ptetemp & PG_MANAGED) != 0) { 3277 dstmpte = pmap_allocpte(dst_pmap, addr, 3278 M_NOWAIT); 3279 if (dstmpte == NULL) 3280 goto out; 3281 dst_pte = pmap_pte_quick(dst_pmap, addr); 3282 if (*dst_pte == 0 && 3283 pmap_try_insert_pv_entry(dst_pmap, addr, 3284 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3285 /* 3286 * Clear the wired, modified, and 3287 * accessed (referenced) bits 3288 * during the copy. 3289 */ 3290 KASSERT(ptetemp != 0, ("src_pte not set")); 3291 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3292 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3293 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3294 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3295 dst_pmap->pm_stats.resident_count++; 3296 } else { 3297 free = NULL; 3298 if (pmap_unwire_ptp(dst_pmap, dstmpte, 3299 &free)) { 3300 pmap_invalidate_page(dst_pmap, 3301 addr); 3302 pmap_free_zero_pages(free); 3303 } 3304 goto out; 3305 } 3306 if (dstmpte->wire_count >= srcmpte->wire_count) 3307 break; 3308 } 3309 addr += PAGE_SIZE; 3310 src_pte++; 3311 } 3312 } 3313out: 3314 PT_UPDATES_FLUSH(); 3315 sched_unpin(); 3316 vm_page_unlock_queues(); 3317 PMAP_UNLOCK(src_pmap); 3318 PMAP_UNLOCK(dst_pmap); 3319 3320#ifdef HAMFISTED_LOCKING 3321 mtx_unlock(&createdelete_lock); 3322#endif 3323} 3324 3325static __inline void 3326pagezero(void *page) 3327{ 3328#if defined(I686_CPU) 3329 if (cpu_class == CPUCLASS_686) { 3330#if defined(CPU_ENABLE_SSE) 3331 if (cpu_feature & CPUID_SSE2) 3332 sse2_pagezero(page); 3333 else 3334#endif 3335 i686_pagezero(page); 3336 } else 3337#endif 3338 bzero(page, PAGE_SIZE); 3339} 3340 3341/* 3342 * pmap_zero_page zeros the specified hardware page by mapping 3343 * the page into KVM and using bzero to clear its contents. 3344 */ 3345void 3346pmap_zero_page(vm_page_t m) 3347{ 3348 struct sysmaps *sysmaps; 3349 3350 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3351 mtx_lock(&sysmaps->lock); 3352 if (*sysmaps->CMAP2) 3353 panic("pmap_zero_page: CMAP2 busy"); 3354 sched_pin(); 3355 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3356 pagezero(sysmaps->CADDR2); 3357 PT_SET_MA(sysmaps->CADDR2, 0); 3358 sched_unpin(); 3359 mtx_unlock(&sysmaps->lock); 3360} 3361 3362/* 3363 * pmap_zero_page_area zeros the specified hardware page by mapping 3364 * the page into KVM and using bzero to clear its contents. 3365 * 3366 * off and size may not cover an area beyond a single hardware page. 3367 */ 3368void 3369pmap_zero_page_area(vm_page_t m, int off, int size) 3370{ 3371 struct sysmaps *sysmaps; 3372 3373 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3374 mtx_lock(&sysmaps->lock); 3375 if (*sysmaps->CMAP2) 3376 panic("pmap_zero_page_area: CMAP2 busy"); 3377 sched_pin(); 3378 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3379 3380 if (off == 0 && size == PAGE_SIZE) 3381 pagezero(sysmaps->CADDR2); 3382 else 3383 bzero((char *)sysmaps->CADDR2 + off, size); 3384 PT_SET_MA(sysmaps->CADDR2, 0); 3385 sched_unpin(); 3386 mtx_unlock(&sysmaps->lock); 3387} 3388 3389/* 3390 * pmap_zero_page_idle zeros the specified hardware page by mapping 3391 * the page into KVM and using bzero to clear its contents. This 3392 * is intended to be called from the vm_pagezero process only and 3393 * outside of Giant. 3394 */ 3395void 3396pmap_zero_page_idle(vm_page_t m) 3397{ 3398 3399 if (*CMAP3) 3400 panic("pmap_zero_page_idle: CMAP3 busy"); 3401 sched_pin(); 3402 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3403 pagezero(CADDR3); 3404 PT_SET_MA(CADDR3, 0); 3405 sched_unpin(); 3406} 3407 3408/* 3409 * pmap_copy_page copies the specified (machine independent) 3410 * page by mapping the page into virtual memory and using 3411 * bcopy to copy the page, one machine dependent page at a 3412 * time. 3413 */ 3414void 3415pmap_copy_page(vm_page_t src, vm_page_t dst) 3416{ 3417 struct sysmaps *sysmaps; 3418 3419 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3420 mtx_lock(&sysmaps->lock); 3421 if (*sysmaps->CMAP1) 3422 panic("pmap_copy_page: CMAP1 busy"); 3423 if (*sysmaps->CMAP2) 3424 panic("pmap_copy_page: CMAP2 busy"); 3425 sched_pin(); 3426 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3427 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3428 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3429 PT_SET_MA(sysmaps->CADDR1, 0); 3430 PT_SET_MA(sysmaps->CADDR2, 0); 3431 sched_unpin(); 3432 mtx_unlock(&sysmaps->lock); 3433} 3434 3435/* 3436 * Returns true if the pmap's pv is one of the first 3437 * 16 pvs linked to from this page. This count may 3438 * be changed upwards or downwards in the future; it 3439 * is only necessary that true be returned for a small 3440 * subset of pmaps for proper page aging. 3441 */ 3442boolean_t 3443pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3444{ 3445 pv_entry_t pv; 3446 int loops = 0; 3447 boolean_t rv; 3448 3449 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3450 ("pmap_page_exists_quick: page %p is not managed", m)); 3451 rv = FALSE; 3452 vm_page_lock_queues(); 3453 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3454 if (PV_PMAP(pv) == pmap) { 3455 rv = TRUE; 3456 break; 3457 } 3458 loops++; 3459 if (loops >= 16) 3460 break; 3461 } 3462 vm_page_unlock_queues(); 3463 return (rv); 3464} 3465 3466/* 3467 * pmap_page_wired_mappings: 3468 * 3469 * Return the number of managed mappings to the given physical page 3470 * that are wired. 3471 */ 3472int 3473pmap_page_wired_mappings(vm_page_t m) 3474{ 3475 pv_entry_t pv; 3476 pt_entry_t *pte; 3477 pmap_t pmap; 3478 int count; 3479 3480 count = 0; 3481 if ((m->oflags & VPO_UNMANAGED) != 0) 3482 return (count); 3483 vm_page_lock_queues(); 3484 sched_pin(); 3485 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3486 pmap = PV_PMAP(pv); 3487 PMAP_LOCK(pmap); 3488 pte = pmap_pte_quick(pmap, pv->pv_va); 3489 if ((*pte & PG_W) != 0) 3490 count++; 3491 PMAP_UNLOCK(pmap); 3492 } 3493 sched_unpin(); 3494 vm_page_unlock_queues(); 3495 return (count); 3496} 3497 3498/* 3499 * Returns TRUE if the given page is mapped. Otherwise, returns FALSE. 3500 */ 3501boolean_t 3502pmap_page_is_mapped(vm_page_t m) 3503{ 3504 3505 if ((m->oflags & VPO_UNMANAGED) != 0) 3506 return (FALSE); 3507 return (!TAILQ_EMPTY(&m->md.pv_list)); 3508} 3509 3510/* 3511 * Remove all pages from specified address space 3512 * this aids process exit speeds. Also, this code 3513 * is special cased for current process only, but 3514 * can have the more generic (and slightly slower) 3515 * mode enabled. This is much faster than pmap_remove 3516 * in the case of running down an entire address space. 3517 */ 3518void 3519pmap_remove_pages(pmap_t pmap) 3520{ 3521 pt_entry_t *pte, tpte; 3522 vm_page_t m, free = NULL; 3523 pv_entry_t pv; 3524 struct pv_chunk *pc, *npc; 3525 int field, idx; 3526 int32_t bit; 3527 uint32_t inuse, bitmask; 3528 int allfree; 3529 3530 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3531 3532 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3533 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3534 return; 3535 } 3536 vm_page_lock_queues(); 3537 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3538 PMAP_LOCK(pmap); 3539 sched_pin(); 3540 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3541 allfree = 1; 3542 for (field = 0; field < _NPCM; field++) { 3543 inuse = ~pc->pc_map[field] & pc_freemask[field]; 3544 while (inuse != 0) { 3545 bit = bsfl(inuse); 3546 bitmask = 1UL << bit; 3547 idx = field * 32 + bit; 3548 pv = &pc->pc_pventry[idx]; 3549 inuse &= ~bitmask; 3550 3551 pte = vtopte(pv->pv_va); 3552 tpte = *pte ? xpmap_mtop(*pte) : 0; 3553 3554 if (tpte == 0) { 3555 printf( 3556 "TPTE at %p IS ZERO @ VA %08x\n", 3557 pte, pv->pv_va); 3558 panic("bad pte"); 3559 } 3560 3561/* 3562 * We cannot remove wired pages from a process' mapping at this time 3563 */ 3564 if (tpte & PG_W) { 3565 allfree = 0; 3566 continue; 3567 } 3568 3569 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3570 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3571 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3572 m, (uintmax_t)m->phys_addr, 3573 (uintmax_t)tpte)); 3574 3575 KASSERT(m < &vm_page_array[vm_page_array_size], 3576 ("pmap_remove_pages: bad tpte %#jx", 3577 (uintmax_t)tpte)); 3578 3579 3580 PT_CLEAR_VA(pte, FALSE); 3581 3582 /* 3583 * Update the vm_page_t clean/reference bits. 3584 */ 3585 if (tpte & PG_M) 3586 vm_page_dirty(m); 3587 3588 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3589 if (TAILQ_EMPTY(&m->md.pv_list)) 3590 vm_page_aflag_clear(m, PGA_WRITEABLE); 3591 3592 pmap_unuse_pt(pmap, pv->pv_va, &free); 3593 3594 /* Mark free */ 3595 PV_STAT(pv_entry_frees++); 3596 PV_STAT(pv_entry_spare++); 3597 pv_entry_count--; 3598 pc->pc_map[field] |= bitmask; 3599 pmap->pm_stats.resident_count--; 3600 } 3601 } 3602 PT_UPDATES_FLUSH(); 3603 if (allfree) { 3604 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3605 free_pv_chunk(pc); 3606 } 3607 } 3608 PT_UPDATES_FLUSH(); 3609 if (*PMAP1) 3610 PT_SET_MA(PADDR1, 0); 3611 3612 sched_unpin(); 3613 pmap_invalidate_all(pmap); 3614 vm_page_unlock_queues(); 3615 PMAP_UNLOCK(pmap); 3616 pmap_free_zero_pages(free); 3617} 3618 3619/* 3620 * pmap_is_modified: 3621 * 3622 * Return whether or not the specified physical page was modified 3623 * in any physical maps. 3624 */ 3625boolean_t 3626pmap_is_modified(vm_page_t m) 3627{ 3628 pv_entry_t pv; 3629 pt_entry_t *pte; 3630 pmap_t pmap; 3631 boolean_t rv; 3632 3633 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3634 ("pmap_is_modified: page %p is not managed", m)); 3635 rv = FALSE; 3636 3637 /* 3638 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 3639 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3640 * is clear, no PTEs can have PG_M set. 3641 */ 3642 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3643 if ((m->oflags & VPO_BUSY) == 0 && 3644 (m->aflags & PGA_WRITEABLE) == 0) 3645 return (rv); 3646 vm_page_lock_queues(); 3647 sched_pin(); 3648 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3649 pmap = PV_PMAP(pv); 3650 PMAP_LOCK(pmap); 3651 pte = pmap_pte_quick(pmap, pv->pv_va); 3652 rv = (*pte & PG_M) != 0; 3653 PMAP_UNLOCK(pmap); 3654 if (rv) 3655 break; 3656 } 3657 if (*PMAP1) 3658 PT_SET_MA(PADDR1, 0); 3659 sched_unpin(); 3660 vm_page_unlock_queues(); 3661 return (rv); 3662} 3663 3664/* 3665 * pmap_is_prefaultable: 3666 * 3667 * Return whether or not the specified virtual address is elgible 3668 * for prefault. 3669 */ 3670static boolean_t 3671pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3672{ 3673 pt_entry_t *pte; 3674 boolean_t rv = FALSE; 3675 3676 return (rv); 3677 3678 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3679 pte = vtopte(addr); 3680 rv = (*pte == 0); 3681 } 3682 return (rv); 3683} 3684 3685boolean_t 3686pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3687{ 3688 boolean_t rv; 3689 3690 PMAP_LOCK(pmap); 3691 rv = pmap_is_prefaultable_locked(pmap, addr); 3692 PMAP_UNLOCK(pmap); 3693 return (rv); 3694} 3695 3696boolean_t 3697pmap_is_referenced(vm_page_t m) 3698{ 3699 pv_entry_t pv; 3700 pt_entry_t *pte; 3701 pmap_t pmap; 3702 boolean_t rv; 3703 3704 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3705 ("pmap_is_referenced: page %p is not managed", m)); 3706 rv = FALSE; 3707 vm_page_lock_queues(); 3708 sched_pin(); 3709 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3710 pmap = PV_PMAP(pv); 3711 PMAP_LOCK(pmap); 3712 pte = pmap_pte_quick(pmap, pv->pv_va); 3713 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3714 PMAP_UNLOCK(pmap); 3715 if (rv) 3716 break; 3717 } 3718 if (*PMAP1) 3719 PT_SET_MA(PADDR1, 0); 3720 sched_unpin(); 3721 vm_page_unlock_queues(); 3722 return (rv); 3723} 3724 3725void 3726pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3727{ 3728 int i, npages = round_page(len) >> PAGE_SHIFT; 3729 for (i = 0; i < npages; i++) { 3730 pt_entry_t *pte; 3731 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3732 vm_page_lock_queues(); 3733 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3734 vm_page_unlock_queues(); 3735 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3736 pmap_pte_release(pte); 3737 } 3738} 3739 3740void 3741pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3742{ 3743 int i, npages = round_page(len) >> PAGE_SHIFT; 3744 for (i = 0; i < npages; i++) { 3745 pt_entry_t *pte; 3746 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3747 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3748 vm_page_lock_queues(); 3749 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3750 vm_page_unlock_queues(); 3751 pmap_pte_release(pte); 3752 } 3753} 3754 3755/* 3756 * Clear the write and modified bits in each of the given page's mappings. 3757 */ 3758void 3759pmap_remove_write(vm_page_t m) 3760{ 3761 pv_entry_t pv; 3762 pmap_t pmap; 3763 pt_entry_t oldpte, *pte; 3764 3765 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3766 ("pmap_remove_write: page %p is not managed", m)); 3767 3768 /* 3769 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 3770 * another thread while the object is locked. Thus, if PGA_WRITEABLE 3771 * is clear, no page table entries need updating. 3772 */ 3773 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3774 if ((m->oflags & VPO_BUSY) == 0 && 3775 (m->aflags & PGA_WRITEABLE) == 0) 3776 return; 3777 vm_page_lock_queues(); 3778 sched_pin(); 3779 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3780 pmap = PV_PMAP(pv); 3781 PMAP_LOCK(pmap); 3782 pte = pmap_pte_quick(pmap, pv->pv_va); 3783retry: 3784 oldpte = *pte; 3785 if ((oldpte & PG_RW) != 0) { 3786 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3787 3788 /* 3789 * Regardless of whether a pte is 32 or 64 bits 3790 * in size, PG_RW and PG_M are among the least 3791 * significant 32 bits. 3792 */ 3793 PT_SET_VA_MA(pte, newpte, TRUE); 3794 if (*pte != newpte) 3795 goto retry; 3796 3797 if ((oldpte & PG_M) != 0) 3798 vm_page_dirty(m); 3799 pmap_invalidate_page(pmap, pv->pv_va); 3800 } 3801 PMAP_UNLOCK(pmap); 3802 } 3803 vm_page_aflag_clear(m, PGA_WRITEABLE); 3804 PT_UPDATES_FLUSH(); 3805 if (*PMAP1) 3806 PT_SET_MA(PADDR1, 0); 3807 sched_unpin(); 3808 vm_page_unlock_queues(); 3809} 3810 3811/* 3812 * pmap_ts_referenced: 3813 * 3814 * Return a count of reference bits for a page, clearing those bits. 3815 * It is not necessary for every reference bit to be cleared, but it 3816 * is necessary that 0 only be returned when there are truly no 3817 * reference bits set. 3818 * 3819 * XXX: The exact number of bits to check and clear is a matter that 3820 * should be tested and standardized at some point in the future for 3821 * optimal aging of shared pages. 3822 */ 3823int 3824pmap_ts_referenced(vm_page_t m) 3825{ 3826 pv_entry_t pv, pvf, pvn; 3827 pmap_t pmap; 3828 pt_entry_t *pte; 3829 int rtval = 0; 3830 3831 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3832 ("pmap_ts_referenced: page %p is not managed", m)); 3833 vm_page_lock_queues(); 3834 sched_pin(); 3835 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3836 pvf = pv; 3837 do { 3838 pvn = TAILQ_NEXT(pv, pv_list); 3839 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3840 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3841 pmap = PV_PMAP(pv); 3842 PMAP_LOCK(pmap); 3843 pte = pmap_pte_quick(pmap, pv->pv_va); 3844 if ((*pte & PG_A) != 0) { 3845 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3846 pmap_invalidate_page(pmap, pv->pv_va); 3847 rtval++; 3848 if (rtval > 4) 3849 pvn = NULL; 3850 } 3851 PMAP_UNLOCK(pmap); 3852 } while ((pv = pvn) != NULL && pv != pvf); 3853 } 3854 PT_UPDATES_FLUSH(); 3855 if (*PMAP1) 3856 PT_SET_MA(PADDR1, 0); 3857 sched_unpin(); 3858 vm_page_unlock_queues(); 3859 return (rtval); 3860} 3861 3862/* 3863 * Clear the modify bits on the specified physical page. 3864 */ 3865void 3866pmap_clear_modify(vm_page_t m) 3867{ 3868 pv_entry_t pv; 3869 pmap_t pmap; 3870 pt_entry_t *pte; 3871 3872 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3873 ("pmap_clear_modify: page %p is not managed", m)); 3874 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3875 KASSERT((m->oflags & VPO_BUSY) == 0, 3876 ("pmap_clear_modify: page %p is busy", m)); 3877 3878 /* 3879 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 3880 * If the object containing the page is locked and the page is not 3881 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 3882 */ 3883 if ((m->aflags & PGA_WRITEABLE) == 0) 3884 return; 3885 vm_page_lock_queues(); 3886 sched_pin(); 3887 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3888 pmap = PV_PMAP(pv); 3889 PMAP_LOCK(pmap); 3890 pte = pmap_pte_quick(pmap, pv->pv_va); 3891 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3892 /* 3893 * Regardless of whether a pte is 32 or 64 bits 3894 * in size, PG_M is among the least significant 3895 * 32 bits. 3896 */ 3897 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3898 pmap_invalidate_page(pmap, pv->pv_va); 3899 } 3900 PMAP_UNLOCK(pmap); 3901 } 3902 sched_unpin(); 3903 vm_page_unlock_queues(); 3904} 3905 3906/* 3907 * pmap_clear_reference: 3908 * 3909 * Clear the reference bit on the specified physical page. 3910 */ 3911void 3912pmap_clear_reference(vm_page_t m) 3913{ 3914 pv_entry_t pv; 3915 pmap_t pmap; 3916 pt_entry_t *pte; 3917 3918 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3919 ("pmap_clear_reference: page %p is not managed", m)); 3920 vm_page_lock_queues(); 3921 sched_pin(); 3922 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3923 pmap = PV_PMAP(pv); 3924 PMAP_LOCK(pmap); 3925 pte = pmap_pte_quick(pmap, pv->pv_va); 3926 if ((*pte & PG_A) != 0) { 3927 /* 3928 * Regardless of whether a pte is 32 or 64 bits 3929 * in size, PG_A is among the least significant 3930 * 32 bits. 3931 */ 3932 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3933 pmap_invalidate_page(pmap, pv->pv_va); 3934 } 3935 PMAP_UNLOCK(pmap); 3936 } 3937 sched_unpin(); 3938 vm_page_unlock_queues(); 3939} 3940 3941/* 3942 * Miscellaneous support routines follow 3943 */ 3944 3945/* 3946 * Map a set of physical memory pages into the kernel virtual 3947 * address space. Return a pointer to where it is mapped. This 3948 * routine is intended to be used for mapping device memory, 3949 * NOT real memory. 3950 */ 3951void * 3952pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 3953{ 3954 vm_offset_t va, offset; 3955 vm_size_t tmpsize; 3956 3957 offset = pa & PAGE_MASK; 3958 size = roundup(offset + size, PAGE_SIZE); 3959 pa = pa & PG_FRAME; 3960 3961 if (pa < KERNLOAD && pa + size <= KERNLOAD) 3962 va = KERNBASE + pa; 3963 else 3964 va = kmem_alloc_nofault(kernel_map, size); 3965 if (!va) 3966 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3967 3968 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 3969 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 3970 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 3971 pmap_invalidate_cache_range(va, va + size); 3972 return ((void *)(va + offset)); 3973} 3974 3975void * 3976pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3977{ 3978 3979 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 3980} 3981 3982void * 3983pmap_mapbios(vm_paddr_t pa, vm_size_t size) 3984{ 3985 3986 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 3987} 3988 3989void 3990pmap_unmapdev(vm_offset_t va, vm_size_t size) 3991{ 3992 vm_offset_t base, offset, tmpva; 3993 3994 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 3995 return; 3996 base = trunc_page(va); 3997 offset = va & PAGE_MASK; 3998 size = roundup(offset + size, PAGE_SIZE); 3999 critical_enter(); 4000 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 4001 pmap_kremove(tmpva); 4002 pmap_invalidate_range(kernel_pmap, va, tmpva); 4003 critical_exit(); 4004 kmem_free(kernel_map, base, size); 4005} 4006 4007/* 4008 * Sets the memory attribute for the specified page. 4009 */ 4010void 4011pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4012{ 4013 4014 m->md.pat_mode = ma; 4015 if ((m->flags & PG_FICTITIOUS) != 0) 4016 return; 4017 4018 /* 4019 * If "m" is a normal page, flush it from the cache. 4020 * See pmap_invalidate_cache_range(). 4021 * 4022 * First, try to find an existing mapping of the page by sf 4023 * buffer. sf_buf_invalidate_cache() modifies mapping and 4024 * flushes the cache. 4025 */ 4026 if (sf_buf_invalidate_cache(m)) 4027 return; 4028 4029 /* 4030 * If page is not mapped by sf buffer, but CPU does not 4031 * support self snoop, map the page transient and do 4032 * invalidation. In the worst case, whole cache is flushed by 4033 * pmap_invalidate_cache_range(). 4034 */ 4035 if ((cpu_feature & CPUID_SS) == 0) 4036 pmap_flush_page(m); 4037} 4038 4039static void 4040pmap_flush_page(vm_page_t m) 4041{ 4042 struct sysmaps *sysmaps; 4043 vm_offset_t sva, eva; 4044 4045 if ((cpu_feature & CPUID_CLFSH) != 0) { 4046 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4047 mtx_lock(&sysmaps->lock); 4048 if (*sysmaps->CMAP2) 4049 panic("pmap_flush_page: CMAP2 busy"); 4050 sched_pin(); 4051 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 4052 VM_PAGE_TO_MACH(m) | PG_A | PG_M | 4053 pmap_cache_bits(m->md.pat_mode, 0)); 4054 invlcaddr(sysmaps->CADDR2); 4055 sva = (vm_offset_t)sysmaps->CADDR2; 4056 eva = sva + PAGE_SIZE; 4057 4058 /* 4059 * Use mfence despite the ordering implied by 4060 * mtx_{un,}lock() because clflush is not guaranteed 4061 * to be ordered by any other instruction. 4062 */ 4063 mfence(); 4064 for (; sva < eva; sva += cpu_clflush_line_size) 4065 clflush(sva); 4066 mfence(); 4067 PT_SET_MA(sysmaps->CADDR2, 0); 4068 sched_unpin(); 4069 mtx_unlock(&sysmaps->lock); 4070 } else 4071 pmap_invalidate_cache(); 4072} 4073 4074/* 4075 * Changes the specified virtual address range's memory type to that given by 4076 * the parameter "mode". The specified virtual address range must be 4077 * completely contained within either the kernel map. 4078 * 4079 * Returns zero if the change completed successfully, and either EINVAL or 4080 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4081 * of the virtual address range was not mapped, and ENOMEM is returned if 4082 * there was insufficient memory available to complete the change. 4083 */ 4084int 4085pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4086{ 4087 vm_offset_t base, offset, tmpva; 4088 pt_entry_t *pte; 4089 u_int opte, npte; 4090 pd_entry_t *pde; 4091 boolean_t changed; 4092 4093 base = trunc_page(va); 4094 offset = va & PAGE_MASK; 4095 size = roundup(offset + size, PAGE_SIZE); 4096 4097 /* Only supported on kernel virtual addresses. */ 4098 if (base <= VM_MAXUSER_ADDRESS) 4099 return (EINVAL); 4100 4101 /* 4MB pages and pages that aren't mapped aren't supported. */ 4102 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4103 pde = pmap_pde(kernel_pmap, tmpva); 4104 if (*pde & PG_PS) 4105 return (EINVAL); 4106 if ((*pde & PG_V) == 0) 4107 return (EINVAL); 4108 pte = vtopte(va); 4109 if ((*pte & PG_V) == 0) 4110 return (EINVAL); 4111 } 4112 4113 changed = FALSE; 4114 4115 /* 4116 * Ok, all the pages exist and are 4k, so run through them updating 4117 * their cache mode. 4118 */ 4119 for (tmpva = base; size > 0; ) { 4120 pte = vtopte(tmpva); 4121 4122 /* 4123 * The cache mode bits are all in the low 32-bits of the 4124 * PTE, so we can just spin on updating the low 32-bits. 4125 */ 4126 do { 4127 opte = *(u_int *)pte; 4128 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4129 npte |= pmap_cache_bits(mode, 0); 4130 PT_SET_VA_MA(pte, npte, TRUE); 4131 } while (npte != opte && (*pte != npte)); 4132 if (npte != opte) 4133 changed = TRUE; 4134 tmpva += PAGE_SIZE; 4135 size -= PAGE_SIZE; 4136 } 4137 4138 /* 4139 * Flush CPU caches to make sure any data isn't cached that 4140 * shouldn't be, etc. 4141 */ 4142 if (changed) { 4143 pmap_invalidate_range(kernel_pmap, base, tmpva); 4144 pmap_invalidate_cache_range(base, tmpva); 4145 } 4146 return (0); 4147} 4148 4149/* 4150 * perform the pmap work for mincore 4151 */ 4152int 4153pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4154{ 4155 pt_entry_t *ptep, pte; 4156 vm_paddr_t pa; 4157 int val; 4158 4159 PMAP_LOCK(pmap); 4160retry: 4161 ptep = pmap_pte(pmap, addr); 4162 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4163 pmap_pte_release(ptep); 4164 val = 0; 4165 if ((pte & PG_V) != 0) { 4166 val |= MINCORE_INCORE; 4167 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4168 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4169 if ((pte & PG_A) != 0) 4170 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4171 } 4172 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4173 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4174 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4175 pa = pte & PG_FRAME; 4176 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4177 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4178 goto retry; 4179 } else 4180 PA_UNLOCK_COND(*locked_pa); 4181 PMAP_UNLOCK(pmap); 4182 return (val); 4183} 4184 4185void 4186pmap_activate(struct thread *td) 4187{ 4188 pmap_t pmap, oldpmap; 4189 u_int cpuid; 4190 u_int32_t cr3; 4191 4192 critical_enter(); 4193 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4194 oldpmap = PCPU_GET(curpmap); 4195 cpuid = PCPU_GET(cpuid); 4196#if defined(SMP) 4197 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 4198 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 4199#else 4200 CPU_CLR(cpuid, &oldpmap->pm_active); 4201 CPU_SET(cpuid, &pmap->pm_active); 4202#endif 4203#ifdef PAE 4204 cr3 = vtophys(pmap->pm_pdpt); 4205#else 4206 cr3 = vtophys(pmap->pm_pdir); 4207#endif 4208 /* 4209 * pmap_activate is for the current thread on the current cpu 4210 */ 4211 td->td_pcb->pcb_cr3 = cr3; 4212 PT_UPDATES_FLUSH(); 4213 load_cr3(cr3); 4214 PCPU_SET(curpmap, pmap); 4215 critical_exit(); 4216} 4217 4218void 4219pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4220{ 4221} 4222 4223/* 4224 * Increase the starting virtual address of the given mapping if a 4225 * different alignment might result in more superpage mappings. 4226 */ 4227void 4228pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4229 vm_offset_t *addr, vm_size_t size) 4230{ 4231 vm_offset_t superpage_offset; 4232 4233 if (size < NBPDR) 4234 return; 4235 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4236 offset += ptoa(object->pg_color); 4237 superpage_offset = offset & PDRMASK; 4238 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4239 (*addr & PDRMASK) == superpage_offset) 4240 return; 4241 if ((*addr & PDRMASK) < superpage_offset) 4242 *addr = (*addr & ~PDRMASK) + superpage_offset; 4243 else 4244 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4245} 4246 4247void 4248pmap_suspend() 4249{ 4250 pmap_t pmap; 4251 int i, pdir, offset; 4252 vm_paddr_t pdirma; 4253 mmu_update_t mu[4]; 4254 4255 /* 4256 * We need to remove the recursive mapping structure from all 4257 * our pmaps so that Xen doesn't get confused when it restores 4258 * the page tables. The recursive map lives at page directory 4259 * index PTDPTDI. We assume that the suspend code has stopped 4260 * the other vcpus (if any). 4261 */ 4262 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4263 for (i = 0; i < 4; i++) { 4264 /* 4265 * Figure out which page directory (L2) page 4266 * contains this bit of the recursive map and 4267 * the offset within that page of the map 4268 * entry 4269 */ 4270 pdir = (PTDPTDI + i) / NPDEPG; 4271 offset = (PTDPTDI + i) % NPDEPG; 4272 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4273 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4274 mu[i].val = 0; 4275 } 4276 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4277 } 4278} 4279 4280void 4281pmap_resume() 4282{ 4283 pmap_t pmap; 4284 int i, pdir, offset; 4285 vm_paddr_t pdirma; 4286 mmu_update_t mu[4]; 4287 4288 /* 4289 * Restore the recursive map that we removed on suspend. 4290 */ 4291 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4292 for (i = 0; i < 4; i++) { 4293 /* 4294 * Figure out which page directory (L2) page 4295 * contains this bit of the recursive map and 4296 * the offset within that page of the map 4297 * entry 4298 */ 4299 pdir = (PTDPTDI + i) / NPDEPG; 4300 offset = (PTDPTDI + i) % NPDEPG; 4301 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4302 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4303 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4304 } 4305 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4306 } 4307} 4308 4309#if defined(PMAP_DEBUG) 4310pmap_pid_dump(int pid) 4311{ 4312 pmap_t pmap; 4313 struct proc *p; 4314 int npte = 0; 4315 int index; 4316 4317 sx_slock(&allproc_lock); 4318 FOREACH_PROC_IN_SYSTEM(p) { 4319 if (p->p_pid != pid) 4320 continue; 4321 4322 if (p->p_vmspace) { 4323 int i,j; 4324 index = 0; 4325 pmap = vmspace_pmap(p->p_vmspace); 4326 for (i = 0; i < NPDEPTD; i++) { 4327 pd_entry_t *pde; 4328 pt_entry_t *pte; 4329 vm_offset_t base = i << PDRSHIFT; 4330 4331 pde = &pmap->pm_pdir[i]; 4332 if (pde && pmap_pde_v(pde)) { 4333 for (j = 0; j < NPTEPG; j++) { 4334 vm_offset_t va = base + (j << PAGE_SHIFT); 4335 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4336 if (index) { 4337 index = 0; 4338 printf("\n"); 4339 } 4340 sx_sunlock(&allproc_lock); 4341 return (npte); 4342 } 4343 pte = pmap_pte(pmap, va); 4344 if (pte && pmap_pte_v(pte)) { 4345 pt_entry_t pa; 4346 vm_page_t m; 4347 pa = PT_GET(pte); 4348 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4349 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4350 va, pa, m->hold_count, m->wire_count, m->flags); 4351 npte++; 4352 index++; 4353 if (index >= 2) { 4354 index = 0; 4355 printf("\n"); 4356 } else { 4357 printf(" "); 4358 } 4359 } 4360 } 4361 } 4362 } 4363 } 4364 } 4365 sx_sunlock(&allproc_lock); 4366 return (npte); 4367} 4368#endif 4369 4370#if defined(DEBUG) 4371 4372static void pads(pmap_t pm); 4373void pmap_pvdump(vm_paddr_t pa); 4374 4375/* print address space of pmap*/ 4376static void 4377pads(pmap_t pm) 4378{ 4379 int i, j; 4380 vm_paddr_t va; 4381 pt_entry_t *ptep; 4382 4383 if (pm == kernel_pmap) 4384 return; 4385 for (i = 0; i < NPDEPTD; i++) 4386 if (pm->pm_pdir[i]) 4387 for (j = 0; j < NPTEPG; j++) { 4388 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4389 if (pm == kernel_pmap && va < KERNBASE) 4390 continue; 4391 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4392 continue; 4393 ptep = pmap_pte(pm, va); 4394 if (pmap_pte_v(ptep)) 4395 printf("%x:%x ", va, *ptep); 4396 }; 4397 4398} 4399 4400void 4401pmap_pvdump(vm_paddr_t pa) 4402{ 4403 pv_entry_t pv; 4404 pmap_t pmap; 4405 vm_page_t m; 4406 4407 printf("pa %x", pa); 4408 m = PHYS_TO_VM_PAGE(pa); 4409 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4410 pmap = PV_PMAP(pv); 4411 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4412 pads(pmap); 4413 } 4414 printf(" "); 4415} 4416#endif 4417