pmap.c revision 229007
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 229007 2011-12-30 18:16:15Z alc $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_smp.h" 109#include "opt_xbox.h" 110 111#include <sys/param.h> 112#include <sys/systm.h> 113#include <sys/kernel.h> 114#include <sys/ktr.h> 115#include <sys/lock.h> 116#include <sys/malloc.h> 117#include <sys/mman.h> 118#include <sys/msgbuf.h> 119#include <sys/mutex.h> 120#include <sys/proc.h> 121#include <sys/sf_buf.h> 122#include <sys/sx.h> 123#include <sys/vmmeter.h> 124#include <sys/sched.h> 125#include <sys/sysctl.h> 126#ifdef SMP 127#include <sys/smp.h> 128#else 129#include <sys/cpuset.h> 130#endif 131 132#include <vm/vm.h> 133#include <vm/vm_param.h> 134#include <vm/vm_kern.h> 135#include <vm/vm_page.h> 136#include <vm/vm_map.h> 137#include <vm/vm_object.h> 138#include <vm/vm_extern.h> 139#include <vm/vm_pageout.h> 140#include <vm/vm_pager.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/cputypes.h> 145#include <machine/md_var.h> 146#include <machine/pcb.h> 147#include <machine/specialreg.h> 148#ifdef SMP 149#include <machine/smp.h> 150#endif 151 152#ifdef XBOX 153#include <machine/xbox.h> 154#endif 155 156#include <xen/interface/xen.h> 157#include <xen/hypervisor.h> 158#include <machine/xen/hypercall.h> 159#include <machine/xen/xenvar.h> 160#include <machine/xen/xenfunc.h> 161 162#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 163#define CPU_ENABLE_SSE 164#endif 165 166#ifndef PMAP_SHPGPERPROC 167#define PMAP_SHPGPERPROC 200 168#endif 169 170#define DIAGNOSTIC 171 172#if !defined(DIAGNOSTIC) 173#ifdef __GNUC_GNU_INLINE__ 174#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 175#else 176#define PMAP_INLINE extern inline 177#endif 178#else 179#define PMAP_INLINE 180#endif 181 182#define PV_STATS 183#ifdef PV_STATS 184#define PV_STAT(x) do { x ; } while (0) 185#else 186#define PV_STAT(x) do { } while (0) 187#endif 188 189/* 190 * Get PDEs and PTEs for user/kernel address space 191 */ 192#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 193#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 194 195#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 196#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 197#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 198#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 199#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 200 201#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 202 203#define HAMFISTED_LOCKING 204#ifdef HAMFISTED_LOCKING 205static struct mtx createdelete_lock; 206#endif 207 208struct pmap kernel_pmap_store; 209LIST_HEAD(pmaplist, pmap); 210static struct pmaplist allpmaps; 211static struct mtx allpmaps_lock; 212 213vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 214vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 215int pgeflag = 0; /* PG_G or-in */ 216int pseflag = 0; /* PG_PS or-in */ 217 218int nkpt; 219vm_offset_t kernel_vm_end; 220extern u_int32_t KERNend; 221 222#ifdef PAE 223pt_entry_t pg_nx; 224#endif 225 226static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 227 228static int pat_works; /* Is page attribute table sane? */ 229 230/* 231 * Data for the pv entry allocation mechanism 232 */ 233static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 234static int shpgperproc = PMAP_SHPGPERPROC; 235 236struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 237int pv_maxchunks; /* How many chunks we have KVA for */ 238vm_offset_t pv_vafree; /* freelist stored in the PTE */ 239 240/* 241 * All those kernel PT submaps that BSD is so fond of 242 */ 243struct sysmaps { 244 struct mtx lock; 245 pt_entry_t *CMAP1; 246 pt_entry_t *CMAP2; 247 caddr_t CADDR1; 248 caddr_t CADDR2; 249}; 250static struct sysmaps sysmaps_pcpu[MAXCPU]; 251static pt_entry_t *CMAP3; 252caddr_t ptvmmap = 0; 253static caddr_t CADDR3; 254struct msgbuf *msgbufp = 0; 255 256/* 257 * Crashdump maps. 258 */ 259static caddr_t crashdumpmap; 260 261static pt_entry_t *PMAP1 = 0, *PMAP2; 262static pt_entry_t *PADDR1 = 0, *PADDR2; 263#ifdef SMP 264static int PMAP1cpu; 265static int PMAP1changedcpu; 266SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 267 &PMAP1changedcpu, 0, 268 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 269#endif 270static int PMAP1changed; 271SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 272 &PMAP1changed, 0, 273 "Number of times pmap_pte_quick changed PMAP1"); 274static int PMAP1unchanged; 275SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 276 &PMAP1unchanged, 0, 277 "Number of times pmap_pte_quick didn't change PMAP1"); 278static struct mtx PMAP2mutex; 279 280static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 281static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 282static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 283static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 284 vm_offset_t va); 285 286static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 287 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 288static void pmap_flush_page(vm_page_t m); 289static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 290static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 291 vm_page_t *free); 292static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 293 vm_page_t *free); 294static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 295 vm_offset_t va); 296static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 297 vm_page_t m); 298 299static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 300 301static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags); 302static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 303static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 304static void pmap_pte_release(pt_entry_t *pte); 305static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 306static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 307 308static __inline void pagezero(void *page); 309 310CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 311CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 312 313/* 314 * If you get an error here, then you set KVA_PAGES wrong! See the 315 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 316 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 317 */ 318CTASSERT(KERNBASE % (1 << 24) == 0); 319 320void 321pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 322{ 323 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 324 325 switch (type) { 326 case SH_PD_SET_VA: 327#if 0 328 xen_queue_pt_update(shadow_pdir_ma, 329 xpmap_ptom(val & ~(PG_RW))); 330#endif 331 xen_queue_pt_update(pdir_ma, 332 xpmap_ptom(val)); 333 break; 334 case SH_PD_SET_VA_MA: 335#if 0 336 xen_queue_pt_update(shadow_pdir_ma, 337 val & ~(PG_RW)); 338#endif 339 xen_queue_pt_update(pdir_ma, val); 340 break; 341 case SH_PD_SET_VA_CLEAR: 342#if 0 343 xen_queue_pt_update(shadow_pdir_ma, 0); 344#endif 345 xen_queue_pt_update(pdir_ma, 0); 346 break; 347 } 348} 349 350/* 351 * Bootstrap the system enough to run with virtual memory. 352 * 353 * On the i386 this is called after mapping has already been enabled 354 * and just syncs the pmap module with what has already been done. 355 * [We can't call it easily with mapping off since the kernel is not 356 * mapped with PA == VA, hence we would have to relocate every address 357 * from the linked base (virtual) address "KERNBASE" to the actual 358 * (physical) address starting relative to 0] 359 */ 360void 361pmap_bootstrap(vm_paddr_t firstaddr) 362{ 363 vm_offset_t va; 364 pt_entry_t *pte, *unused; 365 struct sysmaps *sysmaps; 366 int i; 367 368 /* 369 * Initialize the first available kernel virtual address. However, 370 * using "firstaddr" may waste a few pages of the kernel virtual 371 * address space, because locore may not have mapped every physical 372 * page that it allocated. Preferably, locore would provide a first 373 * unused virtual address in addition to "firstaddr". 374 */ 375 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 376 377 virtual_end = VM_MAX_KERNEL_ADDRESS; 378 379 /* 380 * Initialize the kernel pmap (which is statically allocated). 381 */ 382 PMAP_LOCK_INIT(kernel_pmap); 383 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 384#ifdef PAE 385 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 386#endif 387 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 388 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 389 LIST_INIT(&allpmaps); 390 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 391 mtx_lock_spin(&allpmaps_lock); 392 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 393 mtx_unlock_spin(&allpmaps_lock); 394 if (nkpt == 0) 395 nkpt = NKPT; 396 397 /* 398 * Reserve some special page table entries/VA space for temporary 399 * mapping of pages. 400 */ 401#define SYSMAP(c, p, v, n) \ 402 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 403 404 va = virtual_avail; 405 pte = vtopte(va); 406 407 /* 408 * CMAP1/CMAP2 are used for zeroing and copying pages. 409 * CMAP3 is used for the idle process page zeroing. 410 */ 411 for (i = 0; i < MAXCPU; i++) { 412 sysmaps = &sysmaps_pcpu[i]; 413 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 414 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 415 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 416 PT_SET_MA(sysmaps->CADDR1, 0); 417 PT_SET_MA(sysmaps->CADDR2, 0); 418 } 419 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 420 PT_SET_MA(CADDR3, 0); 421 422 /* 423 * Crashdump maps. 424 */ 425 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 426 427 /* 428 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 429 */ 430 SYSMAP(caddr_t, unused, ptvmmap, 1) 431 432 /* 433 * msgbufp is used to map the system message buffer. 434 */ 435 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 436 437 /* 438 * ptemap is used for pmap_pte_quick 439 */ 440 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 441 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 442 443 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 444 445 virtual_avail = va; 446 447 /* 448 * Leave in place an identity mapping (virt == phys) for the low 1 MB 449 * physical memory region that is used by the ACPI wakeup code. This 450 * mapping must not have PG_G set. 451 */ 452#ifndef XEN 453 /* 454 * leave here deliberately to show that this is not supported 455 */ 456#ifdef XBOX 457 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 458 * an early stadium, we cannot yet neatly map video memory ... :-( 459 * Better fixes are very welcome! */ 460 if (!arch_i386_is_xbox) 461#endif 462 for (i = 1; i < NKPT; i++) 463 PTD[i] = 0; 464 465 /* Initialize the PAT MSR if present. */ 466 pmap_init_pat(); 467 468 /* Turn on PG_G on kernel page(s) */ 469 pmap_set_pg(); 470#endif 471 472#ifdef HAMFISTED_LOCKING 473 mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF); 474#endif 475} 476 477/* 478 * Setup the PAT MSR. 479 */ 480void 481pmap_init_pat(void) 482{ 483 uint64_t pat_msr; 484 485 /* Bail if this CPU doesn't implement PAT. */ 486 if (!(cpu_feature & CPUID_PAT)) 487 return; 488 489 if (cpu_vendor_id != CPU_VENDOR_INTEL || 490 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 491 /* 492 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 493 * Program 4 and 5 as WP and WC. 494 * Leave 6 and 7 as UC and UC-. 495 */ 496 pat_msr = rdmsr(MSR_PAT); 497 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 498 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 499 PAT_VALUE(5, PAT_WRITE_COMBINING); 500 pat_works = 1; 501 } else { 502 /* 503 * Due to some Intel errata, we can only safely use the lower 4 504 * PAT entries. Thus, just replace PAT Index 2 with WC instead 505 * of UC-. 506 * 507 * Intel Pentium III Processor Specification Update 508 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 509 * or Mode C Paging) 510 * 511 * Intel Pentium IV Processor Specification Update 512 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 513 */ 514 pat_msr = rdmsr(MSR_PAT); 515 pat_msr &= ~PAT_MASK(2); 516 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 517 pat_works = 0; 518 } 519 wrmsr(MSR_PAT, pat_msr); 520} 521 522/* 523 * Initialize a vm_page's machine-dependent fields. 524 */ 525void 526pmap_page_init(vm_page_t m) 527{ 528 529 TAILQ_INIT(&m->md.pv_list); 530 m->md.pat_mode = PAT_WRITE_BACK; 531} 532 533/* 534 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 535 * Requirements: 536 * - Must deal with pages in order to ensure that none of the PG_* bits 537 * are ever set, PG_V in particular. 538 * - Assumes we can write to ptes without pte_store() atomic ops, even 539 * on PAE systems. This should be ok. 540 * - Assumes nothing will ever test these addresses for 0 to indicate 541 * no mapping instead of correctly checking PG_V. 542 * - Assumes a vm_offset_t will fit in a pte (true for i386). 543 * Because PG_V is never set, there can be no mappings to invalidate. 544 */ 545static int ptelist_count = 0; 546static vm_offset_t 547pmap_ptelist_alloc(vm_offset_t *head) 548{ 549 vm_offset_t va; 550 vm_offset_t *phead = (vm_offset_t *)*head; 551 552 if (ptelist_count == 0) { 553 printf("out of memory!!!!!!\n"); 554 return (0); /* Out of memory */ 555 } 556 ptelist_count--; 557 va = phead[ptelist_count]; 558 return (va); 559} 560 561static void 562pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 563{ 564 vm_offset_t *phead = (vm_offset_t *)*head; 565 566 phead[ptelist_count++] = va; 567} 568 569static void 570pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 571{ 572 int i, nstackpages; 573 vm_offset_t va; 574 vm_page_t m; 575 576 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 577 for (i = 0; i < nstackpages; i++) { 578 va = (vm_offset_t)base + i * PAGE_SIZE; 579 m = vm_page_alloc(NULL, i, 580 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 581 VM_ALLOC_ZERO); 582 pmap_qenter(va, &m, 1); 583 } 584 585 *head = (vm_offset_t)base; 586 for (i = npages - 1; i >= nstackpages; i--) { 587 va = (vm_offset_t)base + i * PAGE_SIZE; 588 pmap_ptelist_free(head, va); 589 } 590} 591 592 593/* 594 * Initialize the pmap module. 595 * Called by vm_init, to initialize any structures that the pmap 596 * system needs to map virtual memory. 597 */ 598void 599pmap_init(void) 600{ 601 602 /* 603 * Initialize the address space (zone) for the pv entries. Set a 604 * high water mark so that the system can recover from excessive 605 * numbers of pv entries. 606 */ 607 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 608 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 609 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 610 pv_entry_max = roundup(pv_entry_max, _NPCPV); 611 pv_entry_high_water = 9 * (pv_entry_max / 10); 612 613 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 614 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 615 PAGE_SIZE * pv_maxchunks); 616 if (pv_chunkbase == NULL) 617 panic("pmap_init: not enough kvm for pv chunks"); 618 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 619} 620 621 622SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 623 "Max number of PV entries"); 624SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 625 "Page share factor per proc"); 626 627static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 628 "2/4MB page mapping counters"); 629 630static u_long pmap_pde_mappings; 631SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 632 &pmap_pde_mappings, 0, "2/4MB page mappings"); 633 634/*************************************************** 635 * Low level helper routines..... 636 ***************************************************/ 637 638/* 639 * Determine the appropriate bits to set in a PTE or PDE for a specified 640 * caching mode. 641 */ 642int 643pmap_cache_bits(int mode, boolean_t is_pde) 644{ 645 int pat_flag, pat_index, cache_bits; 646 647 /* The PAT bit is different for PTE's and PDE's. */ 648 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 649 650 /* If we don't support PAT, map extended modes to older ones. */ 651 if (!(cpu_feature & CPUID_PAT)) { 652 switch (mode) { 653 case PAT_UNCACHEABLE: 654 case PAT_WRITE_THROUGH: 655 case PAT_WRITE_BACK: 656 break; 657 case PAT_UNCACHED: 658 case PAT_WRITE_COMBINING: 659 case PAT_WRITE_PROTECTED: 660 mode = PAT_UNCACHEABLE; 661 break; 662 } 663 } 664 665 /* Map the caching mode to a PAT index. */ 666 if (pat_works) { 667 switch (mode) { 668 case PAT_UNCACHEABLE: 669 pat_index = 3; 670 break; 671 case PAT_WRITE_THROUGH: 672 pat_index = 1; 673 break; 674 case PAT_WRITE_BACK: 675 pat_index = 0; 676 break; 677 case PAT_UNCACHED: 678 pat_index = 2; 679 break; 680 case PAT_WRITE_COMBINING: 681 pat_index = 5; 682 break; 683 case PAT_WRITE_PROTECTED: 684 pat_index = 4; 685 break; 686 default: 687 panic("Unknown caching mode %d\n", mode); 688 } 689 } else { 690 switch (mode) { 691 case PAT_UNCACHED: 692 case PAT_UNCACHEABLE: 693 case PAT_WRITE_PROTECTED: 694 pat_index = 3; 695 break; 696 case PAT_WRITE_THROUGH: 697 pat_index = 1; 698 break; 699 case PAT_WRITE_BACK: 700 pat_index = 0; 701 break; 702 case PAT_WRITE_COMBINING: 703 pat_index = 2; 704 break; 705 default: 706 panic("Unknown caching mode %d\n", mode); 707 } 708 } 709 710 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 711 cache_bits = 0; 712 if (pat_index & 0x4) 713 cache_bits |= pat_flag; 714 if (pat_index & 0x2) 715 cache_bits |= PG_NC_PCD; 716 if (pat_index & 0x1) 717 cache_bits |= PG_NC_PWT; 718 return (cache_bits); 719} 720#ifdef SMP 721/* 722 * For SMP, these functions have to use the IPI mechanism for coherence. 723 * 724 * N.B.: Before calling any of the following TLB invalidation functions, 725 * the calling processor must ensure that all stores updating a non- 726 * kernel page table are globally performed. Otherwise, another 727 * processor could cache an old, pre-update entry without being 728 * invalidated. This can happen one of two ways: (1) The pmap becomes 729 * active on another processor after its pm_active field is checked by 730 * one of the following functions but before a store updating the page 731 * table is globally performed. (2) The pmap becomes active on another 732 * processor before its pm_active field is checked but due to 733 * speculative loads one of the following functions stills reads the 734 * pmap as inactive on the other processor. 735 * 736 * The kernel page table is exempt because its pm_active field is 737 * immutable. The kernel page table is always active on every 738 * processor. 739 */ 740void 741pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 742{ 743 cpuset_t other_cpus; 744 u_int cpuid; 745 746 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 747 pmap, va); 748 749 sched_pin(); 750 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 751 invlpg(va); 752 smp_invlpg(va); 753 } else { 754 cpuid = PCPU_GET(cpuid); 755 other_cpus = all_cpus; 756 CPU_CLR(cpuid, &other_cpus); 757 if (CPU_ISSET(cpuid, &pmap->pm_active)) 758 invlpg(va); 759 CPU_AND(&other_cpus, &pmap->pm_active); 760 if (!CPU_EMPTY(&other_cpus)) 761 smp_masked_invlpg(other_cpus, va); 762 } 763 sched_unpin(); 764 PT_UPDATES_FLUSH(); 765} 766 767void 768pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 769{ 770 cpuset_t other_cpus; 771 vm_offset_t addr; 772 u_int cpuid; 773 774 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 775 pmap, sva, eva); 776 777 sched_pin(); 778 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 779 for (addr = sva; addr < eva; addr += PAGE_SIZE) 780 invlpg(addr); 781 smp_invlpg_range(sva, eva); 782 } else { 783 cpuid = PCPU_GET(cpuid); 784 other_cpus = all_cpus; 785 CPU_CLR(cpuid, &other_cpus); 786 if (CPU_ISSET(cpuid, &pmap->pm_active)) 787 for (addr = sva; addr < eva; addr += PAGE_SIZE) 788 invlpg(addr); 789 CPU_AND(&other_cpus, &pmap->pm_active); 790 if (!CPU_EMPTY(&other_cpus)) 791 smp_masked_invlpg_range(other_cpus, sva, eva); 792 } 793 sched_unpin(); 794 PT_UPDATES_FLUSH(); 795} 796 797void 798pmap_invalidate_all(pmap_t pmap) 799{ 800 cpuset_t other_cpus; 801 u_int cpuid; 802 803 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 804 805 sched_pin(); 806 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 807 invltlb(); 808 smp_invltlb(); 809 } else { 810 cpuid = PCPU_GET(cpuid); 811 other_cpus = all_cpus; 812 CPU_CLR(cpuid, &other_cpus); 813 if (CPU_ISSET(cpuid, &pmap->pm_active)) 814 invltlb(); 815 CPU_AND(&other_cpus, &pmap->pm_active); 816 if (!CPU_EMPTY(&other_cpus)) 817 smp_masked_invltlb(other_cpus); 818 } 819 sched_unpin(); 820} 821 822void 823pmap_invalidate_cache(void) 824{ 825 826 sched_pin(); 827 wbinvd(); 828 smp_cache_flush(); 829 sched_unpin(); 830} 831#else /* !SMP */ 832/* 833 * Normal, non-SMP, 486+ invalidation functions. 834 * We inline these within pmap.c for speed. 835 */ 836PMAP_INLINE void 837pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 838{ 839 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 840 pmap, va); 841 842 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 843 invlpg(va); 844 PT_UPDATES_FLUSH(); 845} 846 847PMAP_INLINE void 848pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 849{ 850 vm_offset_t addr; 851 852 if (eva - sva > PAGE_SIZE) 853 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 854 pmap, sva, eva); 855 856 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 857 for (addr = sva; addr < eva; addr += PAGE_SIZE) 858 invlpg(addr); 859 PT_UPDATES_FLUSH(); 860} 861 862PMAP_INLINE void 863pmap_invalidate_all(pmap_t pmap) 864{ 865 866 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 867 868 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 869 invltlb(); 870} 871 872PMAP_INLINE void 873pmap_invalidate_cache(void) 874{ 875 876 wbinvd(); 877} 878#endif /* !SMP */ 879 880#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 881 882void 883pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 884{ 885 886 KASSERT((sva & PAGE_MASK) == 0, 887 ("pmap_invalidate_cache_range: sva not page-aligned")); 888 KASSERT((eva & PAGE_MASK) == 0, 889 ("pmap_invalidate_cache_range: eva not page-aligned")); 890 891 if (cpu_feature & CPUID_SS) 892 ; /* If "Self Snoop" is supported, do nothing. */ 893 else if ((cpu_feature & CPUID_CLFSH) != 0 && 894 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 895 896 /* 897 * Otherwise, do per-cache line flush. Use the mfence 898 * instruction to insure that previous stores are 899 * included in the write-back. The processor 900 * propagates flush to other processors in the cache 901 * coherence domain. 902 */ 903 mfence(); 904 for (; sva < eva; sva += cpu_clflush_line_size) 905 clflush(sva); 906 mfence(); 907 } else { 908 909 /* 910 * No targeted cache flush methods are supported by CPU, 911 * or the supplied range is bigger than 2MB. 912 * Globally invalidate cache. 913 */ 914 pmap_invalidate_cache(); 915 } 916} 917 918void 919pmap_invalidate_cache_pages(vm_page_t *pages, int count) 920{ 921 int i; 922 923 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 924 (cpu_feature & CPUID_CLFSH) == 0) { 925 pmap_invalidate_cache(); 926 } else { 927 for (i = 0; i < count; i++) 928 pmap_flush_page(pages[i]); 929 } 930} 931 932/* 933 * Are we current address space or kernel? N.B. We return FALSE when 934 * a pmap's page table is in use because a kernel thread is borrowing 935 * it. The borrowed page table can change spontaneously, making any 936 * dependence on its continued use subject to a race condition. 937 */ 938static __inline int 939pmap_is_current(pmap_t pmap) 940{ 941 942 return (pmap == kernel_pmap || 943 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 944 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 945} 946 947/* 948 * If the given pmap is not the current or kernel pmap, the returned pte must 949 * be released by passing it to pmap_pte_release(). 950 */ 951pt_entry_t * 952pmap_pte(pmap_t pmap, vm_offset_t va) 953{ 954 pd_entry_t newpf; 955 pd_entry_t *pde; 956 957 pde = pmap_pde(pmap, va); 958 if (*pde & PG_PS) 959 return (pde); 960 if (*pde != 0) { 961 /* are we current address space or kernel? */ 962 if (pmap_is_current(pmap)) 963 return (vtopte(va)); 964 mtx_lock(&PMAP2mutex); 965 newpf = *pde & PG_FRAME; 966 if ((*PMAP2 & PG_FRAME) != newpf) { 967 vm_page_lock_queues(); 968 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 969 vm_page_unlock_queues(); 970 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 971 pmap, va, (*PMAP2 & 0xffffffff)); 972 } 973 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 974 } 975 return (NULL); 976} 977 978/* 979 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 980 * being NULL. 981 */ 982static __inline void 983pmap_pte_release(pt_entry_t *pte) 984{ 985 986 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 987 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 988 *PMAP2); 989 vm_page_lock_queues(); 990 PT_SET_VA(PMAP2, 0, TRUE); 991 vm_page_unlock_queues(); 992 mtx_unlock(&PMAP2mutex); 993 } 994} 995 996static __inline void 997invlcaddr(void *caddr) 998{ 999 1000 invlpg((u_int)caddr); 1001 PT_UPDATES_FLUSH(); 1002} 1003 1004/* 1005 * Super fast pmap_pte routine best used when scanning 1006 * the pv lists. This eliminates many coarse-grained 1007 * invltlb calls. Note that many of the pv list 1008 * scans are across different pmaps. It is very wasteful 1009 * to do an entire invltlb for checking a single mapping. 1010 * 1011 * If the given pmap is not the current pmap, vm_page_queue_mtx 1012 * must be held and curthread pinned to a CPU. 1013 */ 1014static pt_entry_t * 1015pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1016{ 1017 pd_entry_t newpf; 1018 pd_entry_t *pde; 1019 1020 pde = pmap_pde(pmap, va); 1021 if (*pde & PG_PS) 1022 return (pde); 1023 if (*pde != 0) { 1024 /* are we current address space or kernel? */ 1025 if (pmap_is_current(pmap)) 1026 return (vtopte(va)); 1027 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1028 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1029 newpf = *pde & PG_FRAME; 1030 if ((*PMAP1 & PG_FRAME) != newpf) { 1031 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1032 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1033 pmap, va, (u_long)*PMAP1); 1034 1035#ifdef SMP 1036 PMAP1cpu = PCPU_GET(cpuid); 1037#endif 1038 PMAP1changed++; 1039 } else 1040#ifdef SMP 1041 if (PMAP1cpu != PCPU_GET(cpuid)) { 1042 PMAP1cpu = PCPU_GET(cpuid); 1043 invlcaddr(PADDR1); 1044 PMAP1changedcpu++; 1045 } else 1046#endif 1047 PMAP1unchanged++; 1048 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1049 } 1050 return (0); 1051} 1052 1053/* 1054 * Routine: pmap_extract 1055 * Function: 1056 * Extract the physical page address associated 1057 * with the given map/virtual_address pair. 1058 */ 1059vm_paddr_t 1060pmap_extract(pmap_t pmap, vm_offset_t va) 1061{ 1062 vm_paddr_t rtval; 1063 pt_entry_t *pte; 1064 pd_entry_t pde; 1065 pt_entry_t pteval; 1066 1067 rtval = 0; 1068 PMAP_LOCK(pmap); 1069 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1070 if (pde != 0) { 1071 if ((pde & PG_PS) != 0) { 1072 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1073 PMAP_UNLOCK(pmap); 1074 return rtval; 1075 } 1076 pte = pmap_pte(pmap, va); 1077 pteval = *pte ? xpmap_mtop(*pte) : 0; 1078 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1079 pmap_pte_release(pte); 1080 } 1081 PMAP_UNLOCK(pmap); 1082 return (rtval); 1083} 1084 1085/* 1086 * Routine: pmap_extract_ma 1087 * Function: 1088 * Like pmap_extract, but returns machine address 1089 */ 1090vm_paddr_t 1091pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1092{ 1093 vm_paddr_t rtval; 1094 pt_entry_t *pte; 1095 pd_entry_t pde; 1096 1097 rtval = 0; 1098 PMAP_LOCK(pmap); 1099 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1100 if (pde != 0) { 1101 if ((pde & PG_PS) != 0) { 1102 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1103 PMAP_UNLOCK(pmap); 1104 return rtval; 1105 } 1106 pte = pmap_pte(pmap, va); 1107 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1108 pmap_pte_release(pte); 1109 } 1110 PMAP_UNLOCK(pmap); 1111 return (rtval); 1112} 1113 1114/* 1115 * Routine: pmap_extract_and_hold 1116 * Function: 1117 * Atomically extract and hold the physical page 1118 * with the given pmap and virtual address pair 1119 * if that mapping permits the given protection. 1120 */ 1121vm_page_t 1122pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1123{ 1124 pd_entry_t pde; 1125 pt_entry_t pte, *ptep; 1126 vm_page_t m; 1127 vm_paddr_t pa; 1128 1129 pa = 0; 1130 m = NULL; 1131 PMAP_LOCK(pmap); 1132retry: 1133 pde = PT_GET(pmap_pde(pmap, va)); 1134 if (pde != 0) { 1135 if (pde & PG_PS) { 1136 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1137 if (vm_page_pa_tryrelock(pmap, (pde & 1138 PG_PS_FRAME) | (va & PDRMASK), &pa)) 1139 goto retry; 1140 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1141 (va & PDRMASK)); 1142 vm_page_hold(m); 1143 } 1144 } else { 1145 ptep = pmap_pte(pmap, va); 1146 pte = PT_GET(ptep); 1147 pmap_pte_release(ptep); 1148 if (pte != 0 && 1149 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1150 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1151 &pa)) 1152 goto retry; 1153 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1154 vm_page_hold(m); 1155 } 1156 } 1157 } 1158 PA_UNLOCK_COND(pa); 1159 PMAP_UNLOCK(pmap); 1160 return (m); 1161} 1162 1163/*************************************************** 1164 * Low level mapping routines..... 1165 ***************************************************/ 1166 1167/* 1168 * Add a wired page to the kva. 1169 * Note: not SMP coherent. 1170 * 1171 * This function may be used before pmap_bootstrap() is called. 1172 */ 1173void 1174pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1175{ 1176 1177 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1178} 1179 1180void 1181pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1182{ 1183 pt_entry_t *pte; 1184 1185 pte = vtopte(va); 1186 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1187} 1188 1189static __inline void 1190pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1191{ 1192 1193 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1194} 1195 1196/* 1197 * Remove a page from the kernel pagetables. 1198 * Note: not SMP coherent. 1199 * 1200 * This function may be used before pmap_bootstrap() is called. 1201 */ 1202PMAP_INLINE void 1203pmap_kremove(vm_offset_t va) 1204{ 1205 pt_entry_t *pte; 1206 1207 pte = vtopte(va); 1208 PT_CLEAR_VA(pte, FALSE); 1209} 1210 1211/* 1212 * Used to map a range of physical addresses into kernel 1213 * virtual address space. 1214 * 1215 * The value passed in '*virt' is a suggested virtual address for 1216 * the mapping. Architectures which can support a direct-mapped 1217 * physical to virtual region can return the appropriate address 1218 * within that region, leaving '*virt' unchanged. Other 1219 * architectures should map the pages starting at '*virt' and 1220 * update '*virt' with the first usable address after the mapped 1221 * region. 1222 */ 1223vm_offset_t 1224pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1225{ 1226 vm_offset_t va, sva; 1227 1228 va = sva = *virt; 1229 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1230 va, start, end, prot); 1231 while (start < end) { 1232 pmap_kenter(va, start); 1233 va += PAGE_SIZE; 1234 start += PAGE_SIZE; 1235 } 1236 pmap_invalidate_range(kernel_pmap, sva, va); 1237 *virt = va; 1238 return (sva); 1239} 1240 1241 1242/* 1243 * Add a list of wired pages to the kva 1244 * this routine is only used for temporary 1245 * kernel mappings that do not need to have 1246 * page modification or references recorded. 1247 * Note that old mappings are simply written 1248 * over. The page *must* be wired. 1249 * Note: SMP coherent. Uses a ranged shootdown IPI. 1250 */ 1251void 1252pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1253{ 1254 pt_entry_t *endpte, *pte; 1255 vm_paddr_t pa; 1256 vm_offset_t va = sva; 1257 int mclcount = 0; 1258 multicall_entry_t mcl[16]; 1259 multicall_entry_t *mclp = mcl; 1260 int error; 1261 1262 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1263 pte = vtopte(sva); 1264 endpte = pte + count; 1265 while (pte < endpte) { 1266 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1267 1268 mclp->op = __HYPERVISOR_update_va_mapping; 1269 mclp->args[0] = va; 1270 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1271 mclp->args[2] = (uint32_t)(pa >> 32); 1272 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1273 1274 va += PAGE_SIZE; 1275 pte++; 1276 ma++; 1277 mclp++; 1278 mclcount++; 1279 if (mclcount == 16) { 1280 error = HYPERVISOR_multicall(mcl, mclcount); 1281 mclp = mcl; 1282 mclcount = 0; 1283 KASSERT(error == 0, ("bad multicall %d", error)); 1284 } 1285 } 1286 if (mclcount) { 1287 error = HYPERVISOR_multicall(mcl, mclcount); 1288 KASSERT(error == 0, ("bad multicall %d", error)); 1289 } 1290 1291#ifdef INVARIANTS 1292 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1293 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1294#endif 1295} 1296 1297/* 1298 * This routine tears out page mappings from the 1299 * kernel -- it is meant only for temporary mappings. 1300 * Note: SMP coherent. Uses a ranged shootdown IPI. 1301 */ 1302void 1303pmap_qremove(vm_offset_t sva, int count) 1304{ 1305 vm_offset_t va; 1306 1307 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1308 va = sva; 1309 vm_page_lock_queues(); 1310 critical_enter(); 1311 while (count-- > 0) { 1312 pmap_kremove(va); 1313 va += PAGE_SIZE; 1314 } 1315 PT_UPDATES_FLUSH(); 1316 pmap_invalidate_range(kernel_pmap, sva, va); 1317 critical_exit(); 1318 vm_page_unlock_queues(); 1319} 1320 1321/*************************************************** 1322 * Page table page management routines..... 1323 ***************************************************/ 1324static __inline void 1325pmap_free_zero_pages(vm_page_t free) 1326{ 1327 vm_page_t m; 1328 1329 while (free != NULL) { 1330 m = free; 1331 free = m->right; 1332 vm_page_free_zero(m); 1333 } 1334} 1335 1336/* 1337 * This routine unholds page table pages, and if the hold count 1338 * drops to zero, then it decrements the wire count. 1339 */ 1340static __inline int 1341pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1342{ 1343 1344 --m->wire_count; 1345 if (m->wire_count == 0) 1346 return (_pmap_unwire_pte_hold(pmap, m, free)); 1347 else 1348 return (0); 1349} 1350 1351static int 1352_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1353{ 1354 vm_offset_t pteva; 1355 1356 PT_UPDATES_FLUSH(); 1357 /* 1358 * unmap the page table page 1359 */ 1360 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1361 /* 1362 * page *might* contain residual mapping :-/ 1363 */ 1364 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1365 pmap_zero_page(m); 1366 --pmap->pm_stats.resident_count; 1367 1368 /* 1369 * This is a release store so that the ordinary store unmapping 1370 * the page table page is globally performed before TLB shoot- 1371 * down is begun. 1372 */ 1373 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1374 1375 /* 1376 * Do an invltlb to make the invalidated mapping 1377 * take effect immediately. 1378 */ 1379 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1380 pmap_invalidate_page(pmap, pteva); 1381 1382 /* 1383 * Put page on a list so that it is released after 1384 * *ALL* TLB shootdown is done 1385 */ 1386 m->right = *free; 1387 *free = m; 1388 1389 return (1); 1390} 1391 1392/* 1393 * After removing a page table entry, this routine is used to 1394 * conditionally free the page, and manage the hold/wire counts. 1395 */ 1396static int 1397pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1398{ 1399 pd_entry_t ptepde; 1400 vm_page_t mpte; 1401 1402 if (va >= VM_MAXUSER_ADDRESS) 1403 return (0); 1404 ptepde = PT_GET(pmap_pde(pmap, va)); 1405 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1406 return (pmap_unwire_pte_hold(pmap, mpte, free)); 1407} 1408 1409/* 1410 * Initialize the pmap for the swapper process. 1411 */ 1412void 1413pmap_pinit0(pmap_t pmap) 1414{ 1415 1416 PMAP_LOCK_INIT(pmap); 1417 /* 1418 * Since the page table directory is shared with the kernel pmap, 1419 * which is already included in the list "allpmaps", this pmap does 1420 * not need to be inserted into that list. 1421 */ 1422 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1423#ifdef PAE 1424 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1425#endif 1426 CPU_ZERO(&pmap->pm_active); 1427 PCPU_SET(curpmap, pmap); 1428 TAILQ_INIT(&pmap->pm_pvchunk); 1429 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1430} 1431 1432/* 1433 * Initialize a preallocated and zeroed pmap structure, 1434 * such as one in a vmspace structure. 1435 */ 1436int 1437pmap_pinit(pmap_t pmap) 1438{ 1439 vm_page_t m, ptdpg[NPGPTD + 1]; 1440 int npgptd = NPGPTD + 1; 1441 int i; 1442 1443#ifdef HAMFISTED_LOCKING 1444 mtx_lock(&createdelete_lock); 1445#endif 1446 1447 PMAP_LOCK_INIT(pmap); 1448 1449 /* 1450 * No need to allocate page table space yet but we do need a valid 1451 * page directory table. 1452 */ 1453 if (pmap->pm_pdir == NULL) { 1454 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1455 NBPTD); 1456 if (pmap->pm_pdir == NULL) { 1457 PMAP_LOCK_DESTROY(pmap); 1458#ifdef HAMFISTED_LOCKING 1459 mtx_unlock(&createdelete_lock); 1460#endif 1461 return (0); 1462 } 1463#ifdef PAE 1464 pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1465#endif 1466 } 1467 1468 /* 1469 * allocate the page directory page(s) 1470 */ 1471 for (i = 0; i < npgptd;) { 1472 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1473 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1474 if (m == NULL) 1475 VM_WAIT; 1476 else { 1477 ptdpg[i++] = m; 1478 } 1479 } 1480 1481 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1482 1483 for (i = 0; i < NPGPTD; i++) 1484 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1485 pagezero(pmap->pm_pdir + (i * NPDEPG)); 1486 1487 mtx_lock_spin(&allpmaps_lock); 1488 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1489 /* Copy the kernel page table directory entries. */ 1490 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1491 mtx_unlock_spin(&allpmaps_lock); 1492 1493#ifdef PAE 1494 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1495 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1496 bzero(pmap->pm_pdpt, PAGE_SIZE); 1497 for (i = 0; i < NPGPTD; i++) { 1498 vm_paddr_t ma; 1499 1500 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1501 pmap->pm_pdpt[i] = ma | PG_V; 1502 1503 } 1504#endif 1505 for (i = 0; i < NPGPTD; i++) { 1506 pt_entry_t *pd; 1507 vm_paddr_t ma; 1508 1509 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1510 pd = pmap->pm_pdir + (i * NPDEPG); 1511 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1512#if 0 1513 xen_pgd_pin(ma); 1514#endif 1515 } 1516 1517#ifdef PAE 1518 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1519#endif 1520 vm_page_lock_queues(); 1521 xen_flush_queue(); 1522 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1523 for (i = 0; i < NPGPTD; i++) { 1524 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1525 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1526 } 1527 xen_flush_queue(); 1528 vm_page_unlock_queues(); 1529 CPU_ZERO(&pmap->pm_active); 1530 TAILQ_INIT(&pmap->pm_pvchunk); 1531 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1532 1533#ifdef HAMFISTED_LOCKING 1534 mtx_unlock(&createdelete_lock); 1535#endif 1536 return (1); 1537} 1538 1539/* 1540 * this routine is called if the page table page is not 1541 * mapped correctly. 1542 */ 1543static vm_page_t 1544_pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags) 1545{ 1546 vm_paddr_t ptema; 1547 vm_page_t m; 1548 1549 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1550 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1551 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1552 1553 /* 1554 * Allocate a page table page. 1555 */ 1556 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1557 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1558 if (flags & M_WAITOK) { 1559 PMAP_UNLOCK(pmap); 1560 vm_page_unlock_queues(); 1561 VM_WAIT; 1562 vm_page_lock_queues(); 1563 PMAP_LOCK(pmap); 1564 } 1565 1566 /* 1567 * Indicate the need to retry. While waiting, the page table 1568 * page may have been allocated. 1569 */ 1570 return (NULL); 1571 } 1572 if ((m->flags & PG_ZERO) == 0) 1573 pmap_zero_page(m); 1574 1575 /* 1576 * Map the pagetable page into the process address space, if 1577 * it isn't already there. 1578 */ 1579 1580 pmap->pm_stats.resident_count++; 1581 1582 ptema = VM_PAGE_TO_MACH(m); 1583 xen_pt_pin(ptema); 1584 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1585 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1586 1587 KASSERT(pmap->pm_pdir[ptepindex], 1588 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1589 return (m); 1590} 1591 1592static vm_page_t 1593pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1594{ 1595 u_int ptepindex; 1596 pd_entry_t ptema; 1597 vm_page_t m; 1598 1599 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1600 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1601 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1602 1603 /* 1604 * Calculate pagetable page index 1605 */ 1606 ptepindex = va >> PDRSHIFT; 1607retry: 1608 /* 1609 * Get the page directory entry 1610 */ 1611 ptema = pmap->pm_pdir[ptepindex]; 1612 1613 /* 1614 * This supports switching from a 4MB page to a 1615 * normal 4K page. 1616 */ 1617 if (ptema & PG_PS) { 1618 /* 1619 * XXX 1620 */ 1621 pmap->pm_pdir[ptepindex] = 0; 1622 ptema = 0; 1623 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1624 pmap_invalidate_all(kernel_pmap); 1625 } 1626 1627 /* 1628 * If the page table page is mapped, we just increment the 1629 * hold count, and activate it. 1630 */ 1631 if (ptema & PG_V) { 1632 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1633 m->wire_count++; 1634 } else { 1635 /* 1636 * Here if the pte page isn't mapped, or if it has 1637 * been deallocated. 1638 */ 1639 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1640 pmap, va, flags); 1641 m = _pmap_allocpte(pmap, ptepindex, flags); 1642 if (m == NULL && (flags & M_WAITOK)) 1643 goto retry; 1644 1645 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1646 } 1647 return (m); 1648} 1649 1650 1651/*************************************************** 1652* Pmap allocation/deallocation routines. 1653 ***************************************************/ 1654 1655#ifdef SMP 1656/* 1657 * Deal with a SMP shootdown of other users of the pmap that we are 1658 * trying to dispose of. This can be a bit hairy. 1659 */ 1660static cpuset_t *lazymask; 1661static u_int lazyptd; 1662static volatile u_int lazywait; 1663 1664void pmap_lazyfix_action(void); 1665 1666void 1667pmap_lazyfix_action(void) 1668{ 1669 1670#ifdef COUNT_IPIS 1671 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1672#endif 1673 if (rcr3() == lazyptd) 1674 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1675 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1676 atomic_store_rel_int(&lazywait, 1); 1677} 1678 1679static void 1680pmap_lazyfix_self(u_int cpuid) 1681{ 1682 1683 if (rcr3() == lazyptd) 1684 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1685 CPU_CLR_ATOMIC(cpuid, lazymask); 1686} 1687 1688 1689static void 1690pmap_lazyfix(pmap_t pmap) 1691{ 1692 cpuset_t mymask, mask; 1693 u_int cpuid, spins; 1694 int lsb; 1695 1696 mask = pmap->pm_active; 1697 while (!CPU_EMPTY(&mask)) { 1698 spins = 50000000; 1699 1700 /* Find least significant set bit. */ 1701 lsb = cpusetobj_ffs(&mask); 1702 MPASS(lsb != 0); 1703 lsb--; 1704 CPU_SETOF(lsb, &mask); 1705 mtx_lock_spin(&smp_ipi_mtx); 1706#ifdef PAE 1707 lazyptd = vtophys(pmap->pm_pdpt); 1708#else 1709 lazyptd = vtophys(pmap->pm_pdir); 1710#endif 1711 cpuid = PCPU_GET(cpuid); 1712 1713 /* Use a cpuset just for having an easy check. */ 1714 CPU_SETOF(cpuid, &mymask); 1715 if (!CPU_CMP(&mask, &mymask)) { 1716 lazymask = &pmap->pm_active; 1717 pmap_lazyfix_self(cpuid); 1718 } else { 1719 atomic_store_rel_int((u_int *)&lazymask, 1720 (u_int)&pmap->pm_active); 1721 atomic_store_rel_int(&lazywait, 0); 1722 ipi_selected(mask, IPI_LAZYPMAP); 1723 while (lazywait == 0) { 1724 ia32_pause(); 1725 if (--spins == 0) 1726 break; 1727 } 1728 } 1729 mtx_unlock_spin(&smp_ipi_mtx); 1730 if (spins == 0) 1731 printf("pmap_lazyfix: spun for 50000000\n"); 1732 mask = pmap->pm_active; 1733 } 1734} 1735 1736#else /* SMP */ 1737 1738/* 1739 * Cleaning up on uniprocessor is easy. For various reasons, we're 1740 * unlikely to have to even execute this code, including the fact 1741 * that the cleanup is deferred until the parent does a wait(2), which 1742 * means that another userland process has run. 1743 */ 1744static void 1745pmap_lazyfix(pmap_t pmap) 1746{ 1747 u_int cr3; 1748 1749 cr3 = vtophys(pmap->pm_pdir); 1750 if (cr3 == rcr3()) { 1751 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1752 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 1753 } 1754} 1755#endif /* SMP */ 1756 1757/* 1758 * Release any resources held by the given physical map. 1759 * Called when a pmap initialized by pmap_pinit is being released. 1760 * Should only be called if the map contains no valid mappings. 1761 */ 1762void 1763pmap_release(pmap_t pmap) 1764{ 1765 vm_page_t m, ptdpg[2*NPGPTD+1]; 1766 vm_paddr_t ma; 1767 int i; 1768#ifdef PAE 1769 int npgptd = NPGPTD + 1; 1770#else 1771 int npgptd = NPGPTD; 1772#endif 1773 1774 KASSERT(pmap->pm_stats.resident_count == 0, 1775 ("pmap_release: pmap resident count %ld != 0", 1776 pmap->pm_stats.resident_count)); 1777 PT_UPDATES_FLUSH(); 1778 1779#ifdef HAMFISTED_LOCKING 1780 mtx_lock(&createdelete_lock); 1781#endif 1782 1783 pmap_lazyfix(pmap); 1784 mtx_lock_spin(&allpmaps_lock); 1785 LIST_REMOVE(pmap, pm_list); 1786 mtx_unlock_spin(&allpmaps_lock); 1787 1788 for (i = 0; i < NPGPTD; i++) 1789 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1790 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1791#ifdef PAE 1792 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1793#endif 1794 1795 for (i = 0; i < npgptd; i++) { 1796 m = ptdpg[i]; 1797 ma = VM_PAGE_TO_MACH(m); 1798 /* unpinning L1 and L2 treated the same */ 1799#if 0 1800 xen_pgd_unpin(ma); 1801#else 1802 if (i == NPGPTD) 1803 xen_pgd_unpin(ma); 1804#endif 1805#ifdef PAE 1806 if (i < NPGPTD) 1807 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1808 ("pmap_release: got wrong ptd page")); 1809#endif 1810 m->wire_count--; 1811 atomic_subtract_int(&cnt.v_wire_count, 1); 1812 vm_page_free(m); 1813 } 1814#ifdef PAE 1815 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1816#endif 1817 PMAP_LOCK_DESTROY(pmap); 1818 1819#ifdef HAMFISTED_LOCKING 1820 mtx_unlock(&createdelete_lock); 1821#endif 1822} 1823 1824static int 1825kvm_size(SYSCTL_HANDLER_ARGS) 1826{ 1827 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1828 1829 return (sysctl_handle_long(oidp, &ksize, 0, req)); 1830} 1831SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1832 0, 0, kvm_size, "IU", "Size of KVM"); 1833 1834static int 1835kvm_free(SYSCTL_HANDLER_ARGS) 1836{ 1837 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1838 1839 return (sysctl_handle_long(oidp, &kfree, 0, req)); 1840} 1841SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1842 0, 0, kvm_free, "IU", "Amount of KVM free"); 1843 1844/* 1845 * grow the number of kernel page table entries, if needed 1846 */ 1847void 1848pmap_growkernel(vm_offset_t addr) 1849{ 1850 struct pmap *pmap; 1851 vm_paddr_t ptppaddr; 1852 vm_page_t nkpg; 1853 pd_entry_t newpdir; 1854 1855 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1856 if (kernel_vm_end == 0) { 1857 kernel_vm_end = KERNBASE; 1858 nkpt = 0; 1859 while (pdir_pde(PTD, kernel_vm_end)) { 1860 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1861 nkpt++; 1862 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1863 kernel_vm_end = kernel_map->max_offset; 1864 break; 1865 } 1866 } 1867 } 1868 addr = roundup2(addr, NBPDR); 1869 if (addr - 1 >= kernel_map->max_offset) 1870 addr = kernel_map->max_offset; 1871 while (kernel_vm_end < addr) { 1872 if (pdir_pde(PTD, kernel_vm_end)) { 1873 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1874 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1875 kernel_vm_end = kernel_map->max_offset; 1876 break; 1877 } 1878 continue; 1879 } 1880 1881 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1882 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1883 VM_ALLOC_ZERO); 1884 if (nkpg == NULL) 1885 panic("pmap_growkernel: no memory to grow kernel"); 1886 1887 nkpt++; 1888 1889 if ((nkpg->flags & PG_ZERO) == 0) 1890 pmap_zero_page(nkpg); 1891 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1892 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1893 vm_page_lock_queues(); 1894 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1895 mtx_lock_spin(&allpmaps_lock); 1896 LIST_FOREACH(pmap, &allpmaps, pm_list) 1897 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1898 1899 mtx_unlock_spin(&allpmaps_lock); 1900 vm_page_unlock_queues(); 1901 1902 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1903 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1904 kernel_vm_end = kernel_map->max_offset; 1905 break; 1906 } 1907 } 1908} 1909 1910 1911/*************************************************** 1912 * page management routines. 1913 ***************************************************/ 1914 1915CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1916CTASSERT(_NPCM == 11); 1917 1918static __inline struct pv_chunk * 1919pv_to_chunk(pv_entry_t pv) 1920{ 1921 1922 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1923} 1924 1925#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1926 1927#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1928#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1929 1930static uint32_t pc_freemask[11] = { 1931 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1932 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1933 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1934 PC_FREE0_9, PC_FREE10 1935}; 1936 1937SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1938 "Current number of pv entries"); 1939 1940#ifdef PV_STATS 1941static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1942 1943SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1944 "Current number of pv entry chunks"); 1945SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1946 "Current number of pv entry chunks allocated"); 1947SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1948 "Current number of pv entry chunks frees"); 1949SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1950 "Number of times tried to get a chunk page but failed."); 1951 1952static long pv_entry_frees, pv_entry_allocs; 1953static int pv_entry_spare; 1954 1955SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1956 "Current number of pv entry frees"); 1957SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1958 "Current number of pv entry allocs"); 1959SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1960 "Current number of spare pv entries"); 1961 1962static int pmap_collect_inactive, pmap_collect_active; 1963 1964SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 1965 "Current number times pmap_collect called on inactive queue"); 1966SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 1967 "Current number times pmap_collect called on active queue"); 1968#endif 1969 1970/* 1971 * We are in a serious low memory condition. Resort to 1972 * drastic measures to free some pages so we can allocate 1973 * another pv entry chunk. This is normally called to 1974 * unmap inactive pages, and if necessary, active pages. 1975 */ 1976static void 1977pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 1978{ 1979 pmap_t pmap; 1980 pt_entry_t *pte, tpte; 1981 pv_entry_t next_pv, pv; 1982 vm_offset_t va; 1983 vm_page_t m, free; 1984 1985 sched_pin(); 1986 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1987 if ((m->flags & PG_MARKER) != 0 || m->hold_count || m->busy) 1988 continue; 1989 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1990 va = pv->pv_va; 1991 pmap = PV_PMAP(pv); 1992 /* Avoid deadlock and lock recursion. */ 1993 if (pmap > locked_pmap) 1994 PMAP_LOCK(pmap); 1995 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1996 continue; 1997 pmap->pm_stats.resident_count--; 1998 pte = pmap_pte_quick(pmap, va); 1999 tpte = pte_load_clear(pte); 2000 KASSERT((tpte & PG_W) == 0, 2001 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2002 if (tpte & PG_A) 2003 vm_page_aflag_set(m, PGA_REFERENCED); 2004 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2005 vm_page_dirty(m); 2006 free = NULL; 2007 pmap_unuse_pt(pmap, va, &free); 2008 pmap_invalidate_page(pmap, va); 2009 pmap_free_zero_pages(free); 2010 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2011 free_pv_entry(pmap, pv); 2012 if (pmap != locked_pmap) 2013 PMAP_UNLOCK(pmap); 2014 } 2015 if (TAILQ_EMPTY(&m->md.pv_list)) 2016 vm_page_aflag_clear(m, PGA_WRITEABLE); 2017 } 2018 sched_unpin(); 2019} 2020 2021 2022/* 2023 * free the pv_entry back to the free list 2024 */ 2025static void 2026free_pv_entry(pmap_t pmap, pv_entry_t pv) 2027{ 2028 vm_page_t m; 2029 struct pv_chunk *pc; 2030 int idx, field, bit; 2031 2032 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2033 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2034 PV_STAT(pv_entry_frees++); 2035 PV_STAT(pv_entry_spare++); 2036 pv_entry_count--; 2037 pc = pv_to_chunk(pv); 2038 idx = pv - &pc->pc_pventry[0]; 2039 field = idx / 32; 2040 bit = idx % 32; 2041 pc->pc_map[field] |= 1ul << bit; 2042 /* move to head of list */ 2043 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2044 for (idx = 0; idx < _NPCM; idx++) 2045 if (pc->pc_map[idx] != pc_freemask[idx]) { 2046 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2047 return; 2048 } 2049 PV_STAT(pv_entry_spare -= _NPCPV); 2050 PV_STAT(pc_chunk_count--); 2051 PV_STAT(pc_chunk_frees++); 2052 /* entire chunk is free, return it */ 2053 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2054 pmap_qremove((vm_offset_t)pc, 1); 2055 vm_page_unwire(m, 0); 2056 vm_page_free(m); 2057 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2058} 2059 2060/* 2061 * get a new pv_entry, allocating a block from the system 2062 * when needed. 2063 */ 2064static pv_entry_t 2065get_pv_entry(pmap_t pmap, int try) 2066{ 2067 static const struct timeval printinterval = { 60, 0 }; 2068 static struct timeval lastprint; 2069 struct vpgqueues *pq; 2070 int bit, field; 2071 pv_entry_t pv; 2072 struct pv_chunk *pc; 2073 vm_page_t m; 2074 2075 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2076 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2077 PV_STAT(pv_entry_allocs++); 2078 pv_entry_count++; 2079 if (pv_entry_count > pv_entry_high_water) 2080 if (ratecheck(&lastprint, &printinterval)) 2081 printf("Approaching the limit on PV entries, consider " 2082 "increasing either the vm.pmap.shpgperproc or the " 2083 "vm.pmap.pv_entry_max tunable.\n"); 2084 pq = NULL; 2085retry: 2086 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2087 if (pc != NULL) { 2088 for (field = 0; field < _NPCM; field++) { 2089 if (pc->pc_map[field]) { 2090 bit = bsfl(pc->pc_map[field]); 2091 break; 2092 } 2093 } 2094 if (field < _NPCM) { 2095 pv = &pc->pc_pventry[field * 32 + bit]; 2096 pc->pc_map[field] &= ~(1ul << bit); 2097 /* If this was the last item, move it to tail */ 2098 for (field = 0; field < _NPCM; field++) 2099 if (pc->pc_map[field] != 0) { 2100 PV_STAT(pv_entry_spare--); 2101 return (pv); /* not full, return */ 2102 } 2103 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2104 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2105 PV_STAT(pv_entry_spare--); 2106 return (pv); 2107 } 2108 } 2109 /* 2110 * Access to the ptelist "pv_vafree" is synchronized by the page 2111 * queues lock. If "pv_vafree" is currently non-empty, it will 2112 * remain non-empty until pmap_ptelist_alloc() completes. 2113 */ 2114 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, (pq == 2115 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2116 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2117 if (try) { 2118 pv_entry_count--; 2119 PV_STAT(pc_chunk_tryfail++); 2120 return (NULL); 2121 } 2122 /* 2123 * Reclaim pv entries: At first, destroy mappings to 2124 * inactive pages. After that, if a pv chunk entry 2125 * is still needed, destroy mappings to active pages. 2126 */ 2127 if (pq == NULL) { 2128 PV_STAT(pmap_collect_inactive++); 2129 pq = &vm_page_queues[PQ_INACTIVE]; 2130 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2131 PV_STAT(pmap_collect_active++); 2132 pq = &vm_page_queues[PQ_ACTIVE]; 2133 } else 2134 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2135 pmap_collect(pmap, pq); 2136 goto retry; 2137 } 2138 PV_STAT(pc_chunk_count++); 2139 PV_STAT(pc_chunk_allocs++); 2140 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2141 pmap_qenter((vm_offset_t)pc, &m, 1); 2142 if ((m->flags & PG_ZERO) == 0) 2143 pagezero(pc); 2144 pc->pc_pmap = pmap; 2145 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2146 for (field = 1; field < _NPCM; field++) 2147 pc->pc_map[field] = pc_freemask[field]; 2148 pv = &pc->pc_pventry[0]; 2149 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2150 PV_STAT(pv_entry_spare += _NPCPV - 1); 2151 return (pv); 2152} 2153 2154static __inline pv_entry_t 2155pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2156{ 2157 pv_entry_t pv; 2158 2159 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2160 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2161 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2162 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2163 break; 2164 } 2165 } 2166 return (pv); 2167} 2168 2169static void 2170pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2171{ 2172 pv_entry_t pv; 2173 2174 pv = pmap_pvh_remove(pvh, pmap, va); 2175 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2176 free_pv_entry(pmap, pv); 2177} 2178 2179static void 2180pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2181{ 2182 2183 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2184 pmap_pvh_free(&m->md, pmap, va); 2185 if (TAILQ_EMPTY(&m->md.pv_list)) 2186 vm_page_aflag_clear(m, PGA_WRITEABLE); 2187} 2188 2189/* 2190 * Conditionally create a pv entry. 2191 */ 2192static boolean_t 2193pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2194{ 2195 pv_entry_t pv; 2196 2197 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2198 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2199 if (pv_entry_count < pv_entry_high_water && 2200 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2201 pv->pv_va = va; 2202 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2203 return (TRUE); 2204 } else 2205 return (FALSE); 2206} 2207 2208/* 2209 * pmap_remove_pte: do the things to unmap a page in a process 2210 */ 2211static int 2212pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2213{ 2214 pt_entry_t oldpte; 2215 vm_page_t m; 2216 2217 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2218 pmap, (u_long)*ptq, va); 2219 2220 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2221 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2222 oldpte = *ptq; 2223 PT_SET_VA_MA(ptq, 0, TRUE); 2224 if (oldpte & PG_W) 2225 pmap->pm_stats.wired_count -= 1; 2226 /* 2227 * Machines that don't support invlpg, also don't support 2228 * PG_G. 2229 */ 2230 if (oldpte & PG_G) 2231 pmap_invalidate_page(kernel_pmap, va); 2232 pmap->pm_stats.resident_count -= 1; 2233 if (oldpte & PG_MANAGED) { 2234 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2235 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2236 vm_page_dirty(m); 2237 if (oldpte & PG_A) 2238 vm_page_aflag_set(m, PGA_REFERENCED); 2239 pmap_remove_entry(pmap, m, va); 2240 } 2241 return (pmap_unuse_pt(pmap, va, free)); 2242} 2243 2244/* 2245 * Remove a single page from a process address space 2246 */ 2247static void 2248pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2249{ 2250 pt_entry_t *pte; 2251 2252 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2253 pmap, va); 2254 2255 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2256 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2257 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2258 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2259 return; 2260 pmap_remove_pte(pmap, pte, va, free); 2261 pmap_invalidate_page(pmap, va); 2262 if (*PMAP1) 2263 PT_SET_MA(PADDR1, 0); 2264 2265} 2266 2267/* 2268 * Remove the given range of addresses from the specified map. 2269 * 2270 * It is assumed that the start and end are properly 2271 * rounded to the page size. 2272 */ 2273void 2274pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2275{ 2276 vm_offset_t pdnxt; 2277 pd_entry_t ptpaddr; 2278 pt_entry_t *pte; 2279 vm_page_t free = NULL; 2280 int anyvalid; 2281 2282 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2283 pmap, sva, eva); 2284 2285 /* 2286 * Perform an unsynchronized read. This is, however, safe. 2287 */ 2288 if (pmap->pm_stats.resident_count == 0) 2289 return; 2290 2291 anyvalid = 0; 2292 2293 vm_page_lock_queues(); 2294 sched_pin(); 2295 PMAP_LOCK(pmap); 2296 2297 /* 2298 * special handling of removing one page. a very 2299 * common operation and easy to short circuit some 2300 * code. 2301 */ 2302 if ((sva + PAGE_SIZE == eva) && 2303 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2304 pmap_remove_page(pmap, sva, &free); 2305 goto out; 2306 } 2307 2308 for (; sva < eva; sva = pdnxt) { 2309 u_int pdirindex; 2310 2311 /* 2312 * Calculate index for next page table. 2313 */ 2314 pdnxt = (sva + NBPDR) & ~PDRMASK; 2315 if (pdnxt < sva) 2316 pdnxt = eva; 2317 if (pmap->pm_stats.resident_count == 0) 2318 break; 2319 2320 pdirindex = sva >> PDRSHIFT; 2321 ptpaddr = pmap->pm_pdir[pdirindex]; 2322 2323 /* 2324 * Weed out invalid mappings. Note: we assume that the page 2325 * directory table is always allocated, and in kernel virtual. 2326 */ 2327 if (ptpaddr == 0) 2328 continue; 2329 2330 /* 2331 * Check for large page. 2332 */ 2333 if ((ptpaddr & PG_PS) != 0) { 2334 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2335 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2336 anyvalid = 1; 2337 continue; 2338 } 2339 2340 /* 2341 * Limit our scan to either the end of the va represented 2342 * by the current page table page, or to the end of the 2343 * range being removed. 2344 */ 2345 if (pdnxt > eva) 2346 pdnxt = eva; 2347 2348 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2349 sva += PAGE_SIZE) { 2350 if ((*pte & PG_V) == 0) 2351 continue; 2352 2353 /* 2354 * The TLB entry for a PG_G mapping is invalidated 2355 * by pmap_remove_pte(). 2356 */ 2357 if ((*pte & PG_G) == 0) 2358 anyvalid = 1; 2359 if (pmap_remove_pte(pmap, pte, sva, &free)) 2360 break; 2361 } 2362 } 2363 PT_UPDATES_FLUSH(); 2364 if (*PMAP1) 2365 PT_SET_VA_MA(PMAP1, 0, TRUE); 2366out: 2367 if (anyvalid) 2368 pmap_invalidate_all(pmap); 2369 sched_unpin(); 2370 vm_page_unlock_queues(); 2371 PMAP_UNLOCK(pmap); 2372 pmap_free_zero_pages(free); 2373} 2374 2375/* 2376 * Routine: pmap_remove_all 2377 * Function: 2378 * Removes this physical page from 2379 * all physical maps in which it resides. 2380 * Reflects back modify bits to the pager. 2381 * 2382 * Notes: 2383 * Original versions of this routine were very 2384 * inefficient because they iteratively called 2385 * pmap_remove (slow...) 2386 */ 2387 2388void 2389pmap_remove_all(vm_page_t m) 2390{ 2391 pv_entry_t pv; 2392 pmap_t pmap; 2393 pt_entry_t *pte, tpte; 2394 vm_page_t free; 2395 2396 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2397 ("pmap_remove_all: page %p is not managed", m)); 2398 free = NULL; 2399 vm_page_lock_queues(); 2400 sched_pin(); 2401 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2402 pmap = PV_PMAP(pv); 2403 PMAP_LOCK(pmap); 2404 pmap->pm_stats.resident_count--; 2405 pte = pmap_pte_quick(pmap, pv->pv_va); 2406 tpte = *pte; 2407 PT_SET_VA_MA(pte, 0, TRUE); 2408 if (tpte & PG_W) 2409 pmap->pm_stats.wired_count--; 2410 if (tpte & PG_A) 2411 vm_page_aflag_set(m, PGA_REFERENCED); 2412 2413 /* 2414 * Update the vm_page_t clean and reference bits. 2415 */ 2416 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2417 vm_page_dirty(m); 2418 pmap_unuse_pt(pmap, pv->pv_va, &free); 2419 pmap_invalidate_page(pmap, pv->pv_va); 2420 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2421 free_pv_entry(pmap, pv); 2422 PMAP_UNLOCK(pmap); 2423 } 2424 vm_page_aflag_clear(m, PGA_WRITEABLE); 2425 PT_UPDATES_FLUSH(); 2426 if (*PMAP1) 2427 PT_SET_MA(PADDR1, 0); 2428 sched_unpin(); 2429 vm_page_unlock_queues(); 2430 pmap_free_zero_pages(free); 2431} 2432 2433/* 2434 * Set the physical protection on the 2435 * specified range of this map as requested. 2436 */ 2437void 2438pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2439{ 2440 vm_offset_t pdnxt; 2441 pd_entry_t ptpaddr; 2442 pt_entry_t *pte; 2443 int anychanged; 2444 2445 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2446 pmap, sva, eva, prot); 2447 2448 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2449 pmap_remove(pmap, sva, eva); 2450 return; 2451 } 2452 2453#ifdef PAE 2454 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2455 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2456 return; 2457#else 2458 if (prot & VM_PROT_WRITE) 2459 return; 2460#endif 2461 2462 anychanged = 0; 2463 2464 vm_page_lock_queues(); 2465 sched_pin(); 2466 PMAP_LOCK(pmap); 2467 for (; sva < eva; sva = pdnxt) { 2468 pt_entry_t obits, pbits; 2469 u_int pdirindex; 2470 2471 pdnxt = (sva + NBPDR) & ~PDRMASK; 2472 if (pdnxt < sva) 2473 pdnxt = eva; 2474 2475 pdirindex = sva >> PDRSHIFT; 2476 ptpaddr = pmap->pm_pdir[pdirindex]; 2477 2478 /* 2479 * Weed out invalid mappings. Note: we assume that the page 2480 * directory table is always allocated, and in kernel virtual. 2481 */ 2482 if (ptpaddr == 0) 2483 continue; 2484 2485 /* 2486 * Check for large page. 2487 */ 2488 if ((ptpaddr & PG_PS) != 0) { 2489 if ((prot & VM_PROT_WRITE) == 0) 2490 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2491#ifdef PAE 2492 if ((prot & VM_PROT_EXECUTE) == 0) 2493 pmap->pm_pdir[pdirindex] |= pg_nx; 2494#endif 2495 anychanged = 1; 2496 continue; 2497 } 2498 2499 if (pdnxt > eva) 2500 pdnxt = eva; 2501 2502 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2503 sva += PAGE_SIZE) { 2504 vm_page_t m; 2505 2506retry: 2507 /* 2508 * Regardless of whether a pte is 32 or 64 bits in 2509 * size, PG_RW, PG_A, and PG_M are among the least 2510 * significant 32 bits. 2511 */ 2512 obits = pbits = *pte; 2513 if ((pbits & PG_V) == 0) 2514 continue; 2515 2516 if ((prot & VM_PROT_WRITE) == 0) { 2517 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2518 (PG_MANAGED | PG_M | PG_RW)) { 2519 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2520 PG_FRAME); 2521 vm_page_dirty(m); 2522 } 2523 pbits &= ~(PG_RW | PG_M); 2524 } 2525#ifdef PAE 2526 if ((prot & VM_PROT_EXECUTE) == 0) 2527 pbits |= pg_nx; 2528#endif 2529 2530 if (pbits != obits) { 2531 obits = *pte; 2532 PT_SET_VA_MA(pte, pbits, TRUE); 2533 if (*pte != pbits) 2534 goto retry; 2535 if (obits & PG_G) 2536 pmap_invalidate_page(pmap, sva); 2537 else 2538 anychanged = 1; 2539 } 2540 } 2541 } 2542 PT_UPDATES_FLUSH(); 2543 if (*PMAP1) 2544 PT_SET_VA_MA(PMAP1, 0, TRUE); 2545 if (anychanged) 2546 pmap_invalidate_all(pmap); 2547 sched_unpin(); 2548 vm_page_unlock_queues(); 2549 PMAP_UNLOCK(pmap); 2550} 2551 2552/* 2553 * Insert the given physical page (p) at 2554 * the specified virtual address (v) in the 2555 * target physical map with the protection requested. 2556 * 2557 * If specified, the page will be wired down, meaning 2558 * that the related pte can not be reclaimed. 2559 * 2560 * NB: This is the only routine which MAY NOT lazy-evaluate 2561 * or lose information. That is, this routine must actually 2562 * insert this page into the given map NOW. 2563 */ 2564void 2565pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2566 vm_prot_t prot, boolean_t wired) 2567{ 2568 pd_entry_t *pde; 2569 pt_entry_t *pte; 2570 pt_entry_t newpte, origpte; 2571 pv_entry_t pv; 2572 vm_paddr_t opa, pa; 2573 vm_page_t mpte, om; 2574 boolean_t invlva; 2575 2576 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2577 pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2578 va = trunc_page(va); 2579 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2580 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2581 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2582 va)); 2583 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 2584 VM_OBJECT_LOCKED(m->object), 2585 ("pmap_enter: page %p is not busy", m)); 2586 2587 mpte = NULL; 2588 2589 vm_page_lock_queues(); 2590 PMAP_LOCK(pmap); 2591 sched_pin(); 2592 2593 /* 2594 * In the case that a page table page is not 2595 * resident, we are creating it here. 2596 */ 2597 if (va < VM_MAXUSER_ADDRESS) { 2598 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2599 } 2600 2601 pde = pmap_pde(pmap, va); 2602 if ((*pde & PG_PS) != 0) 2603 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2604 pte = pmap_pte_quick(pmap, va); 2605 2606 /* 2607 * Page Directory table entry not valid, we need a new PT page 2608 */ 2609 if (pte == NULL) { 2610 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2611 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2612 } 2613 2614 pa = VM_PAGE_TO_PHYS(m); 2615 om = NULL; 2616 opa = origpte = 0; 2617 2618#if 0 2619 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2620 pte, *pte)); 2621#endif 2622 origpte = *pte; 2623 if (origpte) 2624 origpte = xpmap_mtop(origpte); 2625 opa = origpte & PG_FRAME; 2626 2627 /* 2628 * Mapping has not changed, must be protection or wiring change. 2629 */ 2630 if (origpte && (opa == pa)) { 2631 /* 2632 * Wiring change, just update stats. We don't worry about 2633 * wiring PT pages as they remain resident as long as there 2634 * are valid mappings in them. Hence, if a user page is wired, 2635 * the PT page will be also. 2636 */ 2637 if (wired && ((origpte & PG_W) == 0)) 2638 pmap->pm_stats.wired_count++; 2639 else if (!wired && (origpte & PG_W)) 2640 pmap->pm_stats.wired_count--; 2641 2642 /* 2643 * Remove extra pte reference 2644 */ 2645 if (mpte) 2646 mpte->wire_count--; 2647 2648 if (origpte & PG_MANAGED) { 2649 om = m; 2650 pa |= PG_MANAGED; 2651 } 2652 goto validate; 2653 } 2654 2655 pv = NULL; 2656 2657 /* 2658 * Mapping has changed, invalidate old range and fall through to 2659 * handle validating new mapping. 2660 */ 2661 if (opa) { 2662 if (origpte & PG_W) 2663 pmap->pm_stats.wired_count--; 2664 if (origpte & PG_MANAGED) { 2665 om = PHYS_TO_VM_PAGE(opa); 2666 pv = pmap_pvh_remove(&om->md, pmap, va); 2667 } else if (va < VM_MAXUSER_ADDRESS) 2668 printf("va=0x%x is unmanaged :-( \n", va); 2669 2670 if (mpte != NULL) { 2671 mpte->wire_count--; 2672 KASSERT(mpte->wire_count > 0, 2673 ("pmap_enter: missing reference to page table page," 2674 " va: 0x%x", va)); 2675 } 2676 } else 2677 pmap->pm_stats.resident_count++; 2678 2679 /* 2680 * Enter on the PV list if part of our managed memory. 2681 */ 2682 if ((m->oflags & VPO_UNMANAGED) == 0) { 2683 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2684 ("pmap_enter: managed mapping within the clean submap")); 2685 if (pv == NULL) 2686 pv = get_pv_entry(pmap, FALSE); 2687 pv->pv_va = va; 2688 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2689 pa |= PG_MANAGED; 2690 } else if (pv != NULL) 2691 free_pv_entry(pmap, pv); 2692 2693 /* 2694 * Increment counters 2695 */ 2696 if (wired) 2697 pmap->pm_stats.wired_count++; 2698 2699validate: 2700 /* 2701 * Now validate mapping with desired protection/wiring. 2702 */ 2703 newpte = (pt_entry_t)(pa | PG_V); 2704 if ((prot & VM_PROT_WRITE) != 0) { 2705 newpte |= PG_RW; 2706 if ((newpte & PG_MANAGED) != 0) 2707 vm_page_aflag_set(m, PGA_WRITEABLE); 2708 } 2709#ifdef PAE 2710 if ((prot & VM_PROT_EXECUTE) == 0) 2711 newpte |= pg_nx; 2712#endif 2713 if (wired) 2714 newpte |= PG_W; 2715 if (va < VM_MAXUSER_ADDRESS) 2716 newpte |= PG_U; 2717 if (pmap == kernel_pmap) 2718 newpte |= pgeflag; 2719 2720 critical_enter(); 2721 /* 2722 * if the mapping or permission bits are different, we need 2723 * to update the pte. 2724 */ 2725 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2726 if (origpte) { 2727 invlva = FALSE; 2728 origpte = *pte; 2729 PT_SET_VA(pte, newpte | PG_A, FALSE); 2730 if (origpte & PG_A) { 2731 if (origpte & PG_MANAGED) 2732 vm_page_aflag_set(om, PGA_REFERENCED); 2733 if (opa != VM_PAGE_TO_PHYS(m)) 2734 invlva = TRUE; 2735#ifdef PAE 2736 if ((origpte & PG_NX) == 0 && 2737 (newpte & PG_NX) != 0) 2738 invlva = TRUE; 2739#endif 2740 } 2741 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2742 if ((origpte & PG_MANAGED) != 0) 2743 vm_page_dirty(om); 2744 if ((prot & VM_PROT_WRITE) == 0) 2745 invlva = TRUE; 2746 } 2747 if ((origpte & PG_MANAGED) != 0 && 2748 TAILQ_EMPTY(&om->md.pv_list)) 2749 vm_page_aflag_clear(om, PGA_WRITEABLE); 2750 if (invlva) 2751 pmap_invalidate_page(pmap, va); 2752 } else{ 2753 PT_SET_VA(pte, newpte | PG_A, FALSE); 2754 } 2755 2756 } 2757 PT_UPDATES_FLUSH(); 2758 critical_exit(); 2759 if (*PMAP1) 2760 PT_SET_VA_MA(PMAP1, 0, TRUE); 2761 sched_unpin(); 2762 vm_page_unlock_queues(); 2763 PMAP_UNLOCK(pmap); 2764} 2765 2766/* 2767 * Maps a sequence of resident pages belonging to the same object. 2768 * The sequence begins with the given page m_start. This page is 2769 * mapped at the given virtual address start. Each subsequent page is 2770 * mapped at a virtual address that is offset from start by the same 2771 * amount as the page is offset from m_start within the object. The 2772 * last page in the sequence is the page with the largest offset from 2773 * m_start that can be mapped at a virtual address less than the given 2774 * virtual address end. Not every virtual page between start and end 2775 * is mapped; only those for which a resident page exists with the 2776 * corresponding offset from m_start are mapped. 2777 */ 2778void 2779pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2780 vm_page_t m_start, vm_prot_t prot) 2781{ 2782 vm_page_t m, mpte; 2783 vm_pindex_t diff, psize; 2784 multicall_entry_t mcl[16]; 2785 multicall_entry_t *mclp = mcl; 2786 int error, count = 0; 2787 2788 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2789 psize = atop(end - start); 2790 mpte = NULL; 2791 m = m_start; 2792 vm_page_lock_queues(); 2793 PMAP_LOCK(pmap); 2794 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2795 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2796 prot, mpte); 2797 m = TAILQ_NEXT(m, listq); 2798 if (count == 16) { 2799 error = HYPERVISOR_multicall(mcl, count); 2800 KASSERT(error == 0, ("bad multicall %d", error)); 2801 mclp = mcl; 2802 count = 0; 2803 } 2804 } 2805 if (count) { 2806 error = HYPERVISOR_multicall(mcl, count); 2807 KASSERT(error == 0, ("bad multicall %d", error)); 2808 } 2809 vm_page_unlock_queues(); 2810 PMAP_UNLOCK(pmap); 2811} 2812 2813/* 2814 * this code makes some *MAJOR* assumptions: 2815 * 1. Current pmap & pmap exists. 2816 * 2. Not wired. 2817 * 3. Read access. 2818 * 4. No page table pages. 2819 * but is *MUCH* faster than pmap_enter... 2820 */ 2821 2822void 2823pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2824{ 2825 multicall_entry_t mcl, *mclp; 2826 int count = 0; 2827 mclp = &mcl; 2828 2829 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2830 pmap, va, m, prot); 2831 2832 vm_page_lock_queues(); 2833 PMAP_LOCK(pmap); 2834 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2835 if (count) 2836 HYPERVISOR_multicall(&mcl, count); 2837 vm_page_unlock_queues(); 2838 PMAP_UNLOCK(pmap); 2839} 2840 2841#ifdef notyet 2842void 2843pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2844{ 2845 int i, error, index = 0; 2846 multicall_entry_t mcl[16]; 2847 multicall_entry_t *mclp = mcl; 2848 2849 PMAP_LOCK(pmap); 2850 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2851 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2852 continue; 2853 2854 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2855 if (index == 16) { 2856 error = HYPERVISOR_multicall(mcl, index); 2857 mclp = mcl; 2858 index = 0; 2859 KASSERT(error == 0, ("bad multicall %d", error)); 2860 } 2861 } 2862 if (index) { 2863 error = HYPERVISOR_multicall(mcl, index); 2864 KASSERT(error == 0, ("bad multicall %d", error)); 2865 } 2866 2867 PMAP_UNLOCK(pmap); 2868} 2869#endif 2870 2871static vm_page_t 2872pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2873 vm_prot_t prot, vm_page_t mpte) 2874{ 2875 pt_entry_t *pte; 2876 vm_paddr_t pa; 2877 vm_page_t free; 2878 multicall_entry_t *mcl = *mclpp; 2879 2880 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2881 (m->oflags & VPO_UNMANAGED) != 0, 2882 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2883 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2884 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2885 2886 /* 2887 * In the case that a page table page is not 2888 * resident, we are creating it here. 2889 */ 2890 if (va < VM_MAXUSER_ADDRESS) { 2891 u_int ptepindex; 2892 pd_entry_t ptema; 2893 2894 /* 2895 * Calculate pagetable page index 2896 */ 2897 ptepindex = va >> PDRSHIFT; 2898 if (mpte && (mpte->pindex == ptepindex)) { 2899 mpte->wire_count++; 2900 } else { 2901 /* 2902 * Get the page directory entry 2903 */ 2904 ptema = pmap->pm_pdir[ptepindex]; 2905 2906 /* 2907 * If the page table page is mapped, we just increment 2908 * the hold count, and activate it. 2909 */ 2910 if (ptema & PG_V) { 2911 if (ptema & PG_PS) 2912 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2913 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2914 mpte->wire_count++; 2915 } else { 2916 mpte = _pmap_allocpte(pmap, ptepindex, 2917 M_NOWAIT); 2918 if (mpte == NULL) 2919 return (mpte); 2920 } 2921 } 2922 } else { 2923 mpte = NULL; 2924 } 2925 2926 /* 2927 * This call to vtopte makes the assumption that we are 2928 * entering the page into the current pmap. In order to support 2929 * quick entry into any pmap, one would likely use pmap_pte_quick. 2930 * But that isn't as quick as vtopte. 2931 */ 2932 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 2933 pte = vtopte(va); 2934 if (*pte & PG_V) { 2935 if (mpte != NULL) { 2936 mpte->wire_count--; 2937 mpte = NULL; 2938 } 2939 return (mpte); 2940 } 2941 2942 /* 2943 * Enter on the PV list if part of our managed memory. 2944 */ 2945 if ((m->oflags & VPO_UNMANAGED) == 0 && 2946 !pmap_try_insert_pv_entry(pmap, va, m)) { 2947 if (mpte != NULL) { 2948 free = NULL; 2949 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 2950 pmap_invalidate_page(pmap, va); 2951 pmap_free_zero_pages(free); 2952 } 2953 2954 mpte = NULL; 2955 } 2956 return (mpte); 2957 } 2958 2959 /* 2960 * Increment counters 2961 */ 2962 pmap->pm_stats.resident_count++; 2963 2964 pa = VM_PAGE_TO_PHYS(m); 2965#ifdef PAE 2966 if ((prot & VM_PROT_EXECUTE) == 0) 2967 pa |= pg_nx; 2968#endif 2969 2970#if 0 2971 /* 2972 * Now validate mapping with RO protection 2973 */ 2974 if ((m->oflags & VPO_UNMANAGED) != 0) 2975 pte_store(pte, pa | PG_V | PG_U); 2976 else 2977 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 2978#else 2979 /* 2980 * Now validate mapping with RO protection 2981 */ 2982 if ((m->oflags & VPO_UNMANAGED) != 0) 2983 pa = xpmap_ptom(pa | PG_V | PG_U); 2984 else 2985 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 2986 2987 mcl->op = __HYPERVISOR_update_va_mapping; 2988 mcl->args[0] = va; 2989 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 2990 mcl->args[2] = (uint32_t)(pa >> 32); 2991 mcl->args[3] = 0; 2992 *mclpp = mcl + 1; 2993 *count = *count + 1; 2994#endif 2995 return (mpte); 2996} 2997 2998/* 2999 * Make a temporary mapping for a physical address. This is only intended 3000 * to be used for panic dumps. 3001 */ 3002void * 3003pmap_kenter_temporary(vm_paddr_t pa, int i) 3004{ 3005 vm_offset_t va; 3006 vm_paddr_t ma = xpmap_ptom(pa); 3007 3008 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3009 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3010 invlpg(va); 3011 return ((void *)crashdumpmap); 3012} 3013 3014/* 3015 * This code maps large physical mmap regions into the 3016 * processor address space. Note that some shortcuts 3017 * are taken, but the code works. 3018 */ 3019void 3020pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3021 vm_pindex_t pindex, vm_size_t size) 3022{ 3023 pd_entry_t *pde; 3024 vm_paddr_t pa, ptepa; 3025 vm_page_t p; 3026 int pat_mode; 3027 3028 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3029 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3030 ("pmap_object_init_pt: non-device object")); 3031 if (pseflag && 3032 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3033 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3034 return; 3035 p = vm_page_lookup(object, pindex); 3036 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3037 ("pmap_object_init_pt: invalid page %p", p)); 3038 pat_mode = p->md.pat_mode; 3039 3040 /* 3041 * Abort the mapping if the first page is not physically 3042 * aligned to a 2/4MB page boundary. 3043 */ 3044 ptepa = VM_PAGE_TO_PHYS(p); 3045 if (ptepa & (NBPDR - 1)) 3046 return; 3047 3048 /* 3049 * Skip the first page. Abort the mapping if the rest of 3050 * the pages are not physically contiguous or have differing 3051 * memory attributes. 3052 */ 3053 p = TAILQ_NEXT(p, listq); 3054 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3055 pa += PAGE_SIZE) { 3056 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3057 ("pmap_object_init_pt: invalid page %p", p)); 3058 if (pa != VM_PAGE_TO_PHYS(p) || 3059 pat_mode != p->md.pat_mode) 3060 return; 3061 p = TAILQ_NEXT(p, listq); 3062 } 3063 3064 /* 3065 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3066 * "size" is a multiple of 2/4M, adding the PAT setting to 3067 * "pa" will not affect the termination of this loop. 3068 */ 3069 PMAP_LOCK(pmap); 3070 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3071 size; pa += NBPDR) { 3072 pde = pmap_pde(pmap, addr); 3073 if (*pde == 0) { 3074 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3075 PG_U | PG_RW | PG_V); 3076 pmap->pm_stats.resident_count += NBPDR / 3077 PAGE_SIZE; 3078 pmap_pde_mappings++; 3079 } 3080 /* Else continue on if the PDE is already valid. */ 3081 addr += NBPDR; 3082 } 3083 PMAP_UNLOCK(pmap); 3084 } 3085} 3086 3087/* 3088 * Routine: pmap_change_wiring 3089 * Function: Change the wiring attribute for a map/virtual-address 3090 * pair. 3091 * In/out conditions: 3092 * The mapping must already exist in the pmap. 3093 */ 3094void 3095pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3096{ 3097 pt_entry_t *pte; 3098 3099 vm_page_lock_queues(); 3100 PMAP_LOCK(pmap); 3101 pte = pmap_pte(pmap, va); 3102 3103 if (wired && !pmap_pte_w(pte)) { 3104 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3105 pmap->pm_stats.wired_count++; 3106 } else if (!wired && pmap_pte_w(pte)) { 3107 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3108 pmap->pm_stats.wired_count--; 3109 } 3110 3111 /* 3112 * Wiring is not a hardware characteristic so there is no need to 3113 * invalidate TLB. 3114 */ 3115 pmap_pte_release(pte); 3116 PMAP_UNLOCK(pmap); 3117 vm_page_unlock_queues(); 3118} 3119 3120 3121 3122/* 3123 * Copy the range specified by src_addr/len 3124 * from the source map to the range dst_addr/len 3125 * in the destination map. 3126 * 3127 * This routine is only advisory and need not do anything. 3128 */ 3129 3130void 3131pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3132 vm_offset_t src_addr) 3133{ 3134 vm_page_t free; 3135 vm_offset_t addr; 3136 vm_offset_t end_addr = src_addr + len; 3137 vm_offset_t pdnxt; 3138 3139 if (dst_addr != src_addr) 3140 return; 3141 3142 if (!pmap_is_current(src_pmap)) { 3143 CTR2(KTR_PMAP, 3144 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3145 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3146 3147 return; 3148 } 3149 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3150 dst_pmap, src_pmap, dst_addr, len, src_addr); 3151 3152#ifdef HAMFISTED_LOCKING 3153 mtx_lock(&createdelete_lock); 3154#endif 3155 3156 vm_page_lock_queues(); 3157 if (dst_pmap < src_pmap) { 3158 PMAP_LOCK(dst_pmap); 3159 PMAP_LOCK(src_pmap); 3160 } else { 3161 PMAP_LOCK(src_pmap); 3162 PMAP_LOCK(dst_pmap); 3163 } 3164 sched_pin(); 3165 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3166 pt_entry_t *src_pte, *dst_pte; 3167 vm_page_t dstmpte, srcmpte; 3168 pd_entry_t srcptepaddr; 3169 u_int ptepindex; 3170 3171 KASSERT(addr < UPT_MIN_ADDRESS, 3172 ("pmap_copy: invalid to pmap_copy page tables")); 3173 3174 pdnxt = (addr + NBPDR) & ~PDRMASK; 3175 if (pdnxt < addr) 3176 pdnxt = end_addr; 3177 ptepindex = addr >> PDRSHIFT; 3178 3179 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3180 if (srcptepaddr == 0) 3181 continue; 3182 3183 if (srcptepaddr & PG_PS) { 3184 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3185 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3186 dst_pmap->pm_stats.resident_count += 3187 NBPDR / PAGE_SIZE; 3188 } 3189 continue; 3190 } 3191 3192 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3193 KASSERT(srcmpte->wire_count > 0, 3194 ("pmap_copy: source page table page is unused")); 3195 3196 if (pdnxt > end_addr) 3197 pdnxt = end_addr; 3198 3199 src_pte = vtopte(addr); 3200 while (addr < pdnxt) { 3201 pt_entry_t ptetemp; 3202 ptetemp = *src_pte; 3203 /* 3204 * we only virtual copy managed pages 3205 */ 3206 if ((ptetemp & PG_MANAGED) != 0) { 3207 dstmpte = pmap_allocpte(dst_pmap, addr, 3208 M_NOWAIT); 3209 if (dstmpte == NULL) 3210 goto out; 3211 dst_pte = pmap_pte_quick(dst_pmap, addr); 3212 if (*dst_pte == 0 && 3213 pmap_try_insert_pv_entry(dst_pmap, addr, 3214 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3215 /* 3216 * Clear the wired, modified, and 3217 * accessed (referenced) bits 3218 * during the copy. 3219 */ 3220 KASSERT(ptetemp != 0, ("src_pte not set")); 3221 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3222 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3223 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3224 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3225 dst_pmap->pm_stats.resident_count++; 3226 } else { 3227 free = NULL; 3228 if (pmap_unwire_pte_hold(dst_pmap, 3229 dstmpte, &free)) { 3230 pmap_invalidate_page(dst_pmap, 3231 addr); 3232 pmap_free_zero_pages(free); 3233 } 3234 goto out; 3235 } 3236 if (dstmpte->wire_count >= srcmpte->wire_count) 3237 break; 3238 } 3239 addr += PAGE_SIZE; 3240 src_pte++; 3241 } 3242 } 3243out: 3244 PT_UPDATES_FLUSH(); 3245 sched_unpin(); 3246 vm_page_unlock_queues(); 3247 PMAP_UNLOCK(src_pmap); 3248 PMAP_UNLOCK(dst_pmap); 3249 3250#ifdef HAMFISTED_LOCKING 3251 mtx_unlock(&createdelete_lock); 3252#endif 3253} 3254 3255static __inline void 3256pagezero(void *page) 3257{ 3258#if defined(I686_CPU) 3259 if (cpu_class == CPUCLASS_686) { 3260#if defined(CPU_ENABLE_SSE) 3261 if (cpu_feature & CPUID_SSE2) 3262 sse2_pagezero(page); 3263 else 3264#endif 3265 i686_pagezero(page); 3266 } else 3267#endif 3268 bzero(page, PAGE_SIZE); 3269} 3270 3271/* 3272 * pmap_zero_page zeros the specified hardware page by mapping 3273 * the page into KVM and using bzero to clear its contents. 3274 */ 3275void 3276pmap_zero_page(vm_page_t m) 3277{ 3278 struct sysmaps *sysmaps; 3279 3280 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3281 mtx_lock(&sysmaps->lock); 3282 if (*sysmaps->CMAP2) 3283 panic("pmap_zero_page: CMAP2 busy"); 3284 sched_pin(); 3285 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3286 pagezero(sysmaps->CADDR2); 3287 PT_SET_MA(sysmaps->CADDR2, 0); 3288 sched_unpin(); 3289 mtx_unlock(&sysmaps->lock); 3290} 3291 3292/* 3293 * pmap_zero_page_area zeros the specified hardware page by mapping 3294 * the page into KVM and using bzero to clear its contents. 3295 * 3296 * off and size may not cover an area beyond a single hardware page. 3297 */ 3298void 3299pmap_zero_page_area(vm_page_t m, int off, int size) 3300{ 3301 struct sysmaps *sysmaps; 3302 3303 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3304 mtx_lock(&sysmaps->lock); 3305 if (*sysmaps->CMAP2) 3306 panic("pmap_zero_page_area: CMAP2 busy"); 3307 sched_pin(); 3308 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3309 3310 if (off == 0 && size == PAGE_SIZE) 3311 pagezero(sysmaps->CADDR2); 3312 else 3313 bzero((char *)sysmaps->CADDR2 + off, size); 3314 PT_SET_MA(sysmaps->CADDR2, 0); 3315 sched_unpin(); 3316 mtx_unlock(&sysmaps->lock); 3317} 3318 3319/* 3320 * pmap_zero_page_idle zeros the specified hardware page by mapping 3321 * the page into KVM and using bzero to clear its contents. This 3322 * is intended to be called from the vm_pagezero process only and 3323 * outside of Giant. 3324 */ 3325void 3326pmap_zero_page_idle(vm_page_t m) 3327{ 3328 3329 if (*CMAP3) 3330 panic("pmap_zero_page_idle: CMAP3 busy"); 3331 sched_pin(); 3332 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3333 pagezero(CADDR3); 3334 PT_SET_MA(CADDR3, 0); 3335 sched_unpin(); 3336} 3337 3338/* 3339 * pmap_copy_page copies the specified (machine independent) 3340 * page by mapping the page into virtual memory and using 3341 * bcopy to copy the page, one machine dependent page at a 3342 * time. 3343 */ 3344void 3345pmap_copy_page(vm_page_t src, vm_page_t dst) 3346{ 3347 struct sysmaps *sysmaps; 3348 3349 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3350 mtx_lock(&sysmaps->lock); 3351 if (*sysmaps->CMAP1) 3352 panic("pmap_copy_page: CMAP1 busy"); 3353 if (*sysmaps->CMAP2) 3354 panic("pmap_copy_page: CMAP2 busy"); 3355 sched_pin(); 3356 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3357 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3358 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3359 PT_SET_MA(sysmaps->CADDR1, 0); 3360 PT_SET_MA(sysmaps->CADDR2, 0); 3361 sched_unpin(); 3362 mtx_unlock(&sysmaps->lock); 3363} 3364 3365/* 3366 * Returns true if the pmap's pv is one of the first 3367 * 16 pvs linked to from this page. This count may 3368 * be changed upwards or downwards in the future; it 3369 * is only necessary that true be returned for a small 3370 * subset of pmaps for proper page aging. 3371 */ 3372boolean_t 3373pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3374{ 3375 pv_entry_t pv; 3376 int loops = 0; 3377 boolean_t rv; 3378 3379 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3380 ("pmap_page_exists_quick: page %p is not managed", m)); 3381 rv = FALSE; 3382 vm_page_lock_queues(); 3383 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3384 if (PV_PMAP(pv) == pmap) { 3385 rv = TRUE; 3386 break; 3387 } 3388 loops++; 3389 if (loops >= 16) 3390 break; 3391 } 3392 vm_page_unlock_queues(); 3393 return (rv); 3394} 3395 3396/* 3397 * pmap_page_wired_mappings: 3398 * 3399 * Return the number of managed mappings to the given physical page 3400 * that are wired. 3401 */ 3402int 3403pmap_page_wired_mappings(vm_page_t m) 3404{ 3405 pv_entry_t pv; 3406 pt_entry_t *pte; 3407 pmap_t pmap; 3408 int count; 3409 3410 count = 0; 3411 if ((m->oflags & VPO_UNMANAGED) != 0) 3412 return (count); 3413 vm_page_lock_queues(); 3414 sched_pin(); 3415 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3416 pmap = PV_PMAP(pv); 3417 PMAP_LOCK(pmap); 3418 pte = pmap_pte_quick(pmap, pv->pv_va); 3419 if ((*pte & PG_W) != 0) 3420 count++; 3421 PMAP_UNLOCK(pmap); 3422 } 3423 sched_unpin(); 3424 vm_page_unlock_queues(); 3425 return (count); 3426} 3427 3428/* 3429 * Returns TRUE if the given page is mapped. Otherwise, returns FALSE. 3430 */ 3431boolean_t 3432pmap_page_is_mapped(vm_page_t m) 3433{ 3434 3435 if ((m->oflags & VPO_UNMANAGED) != 0) 3436 return (FALSE); 3437 return (!TAILQ_EMPTY(&m->md.pv_list)); 3438} 3439 3440/* 3441 * Remove all pages from specified address space 3442 * this aids process exit speeds. Also, this code 3443 * is special cased for current process only, but 3444 * can have the more generic (and slightly slower) 3445 * mode enabled. This is much faster than pmap_remove 3446 * in the case of running down an entire address space. 3447 */ 3448void 3449pmap_remove_pages(pmap_t pmap) 3450{ 3451 pt_entry_t *pte, tpte; 3452 vm_page_t m, free = NULL; 3453 pv_entry_t pv; 3454 struct pv_chunk *pc, *npc; 3455 int field, idx; 3456 int32_t bit; 3457 uint32_t inuse, bitmask; 3458 int allfree; 3459 3460 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3461 3462 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3463 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3464 return; 3465 } 3466 vm_page_lock_queues(); 3467 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3468 PMAP_LOCK(pmap); 3469 sched_pin(); 3470 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3471 allfree = 1; 3472 for (field = 0; field < _NPCM; field++) { 3473 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 3474 while (inuse != 0) { 3475 bit = bsfl(inuse); 3476 bitmask = 1UL << bit; 3477 idx = field * 32 + bit; 3478 pv = &pc->pc_pventry[idx]; 3479 inuse &= ~bitmask; 3480 3481 pte = vtopte(pv->pv_va); 3482 tpte = *pte ? xpmap_mtop(*pte) : 0; 3483 3484 if (tpte == 0) { 3485 printf( 3486 "TPTE at %p IS ZERO @ VA %08x\n", 3487 pte, pv->pv_va); 3488 panic("bad pte"); 3489 } 3490 3491/* 3492 * We cannot remove wired pages from a process' mapping at this time 3493 */ 3494 if (tpte & PG_W) { 3495 allfree = 0; 3496 continue; 3497 } 3498 3499 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3500 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3501 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3502 m, (uintmax_t)m->phys_addr, 3503 (uintmax_t)tpte)); 3504 3505 KASSERT(m < &vm_page_array[vm_page_array_size], 3506 ("pmap_remove_pages: bad tpte %#jx", 3507 (uintmax_t)tpte)); 3508 3509 3510 PT_CLEAR_VA(pte, FALSE); 3511 3512 /* 3513 * Update the vm_page_t clean/reference bits. 3514 */ 3515 if (tpte & PG_M) 3516 vm_page_dirty(m); 3517 3518 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3519 if (TAILQ_EMPTY(&m->md.pv_list)) 3520 vm_page_aflag_clear(m, PGA_WRITEABLE); 3521 3522 pmap_unuse_pt(pmap, pv->pv_va, &free); 3523 3524 /* Mark free */ 3525 PV_STAT(pv_entry_frees++); 3526 PV_STAT(pv_entry_spare++); 3527 pv_entry_count--; 3528 pc->pc_map[field] |= bitmask; 3529 pmap->pm_stats.resident_count--; 3530 } 3531 } 3532 PT_UPDATES_FLUSH(); 3533 if (allfree) { 3534 PV_STAT(pv_entry_spare -= _NPCPV); 3535 PV_STAT(pc_chunk_count--); 3536 PV_STAT(pc_chunk_frees++); 3537 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3538 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 3539 pmap_qremove((vm_offset_t)pc, 1); 3540 vm_page_unwire(m, 0); 3541 vm_page_free(m); 3542 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 3543 } 3544 } 3545 PT_UPDATES_FLUSH(); 3546 if (*PMAP1) 3547 PT_SET_MA(PADDR1, 0); 3548 3549 sched_unpin(); 3550 pmap_invalidate_all(pmap); 3551 vm_page_unlock_queues(); 3552 PMAP_UNLOCK(pmap); 3553 pmap_free_zero_pages(free); 3554} 3555 3556/* 3557 * pmap_is_modified: 3558 * 3559 * Return whether or not the specified physical page was modified 3560 * in any physical maps. 3561 */ 3562boolean_t 3563pmap_is_modified(vm_page_t m) 3564{ 3565 pv_entry_t pv; 3566 pt_entry_t *pte; 3567 pmap_t pmap; 3568 boolean_t rv; 3569 3570 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3571 ("pmap_is_modified: page %p is not managed", m)); 3572 rv = FALSE; 3573 3574 /* 3575 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 3576 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3577 * is clear, no PTEs can have PG_M set. 3578 */ 3579 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3580 if ((m->oflags & VPO_BUSY) == 0 && 3581 (m->aflags & PGA_WRITEABLE) == 0) 3582 return (rv); 3583 vm_page_lock_queues(); 3584 sched_pin(); 3585 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3586 pmap = PV_PMAP(pv); 3587 PMAP_LOCK(pmap); 3588 pte = pmap_pte_quick(pmap, pv->pv_va); 3589 rv = (*pte & PG_M) != 0; 3590 PMAP_UNLOCK(pmap); 3591 if (rv) 3592 break; 3593 } 3594 if (*PMAP1) 3595 PT_SET_MA(PADDR1, 0); 3596 sched_unpin(); 3597 vm_page_unlock_queues(); 3598 return (rv); 3599} 3600 3601/* 3602 * pmap_is_prefaultable: 3603 * 3604 * Return whether or not the specified virtual address is elgible 3605 * for prefault. 3606 */ 3607static boolean_t 3608pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3609{ 3610 pt_entry_t *pte; 3611 boolean_t rv = FALSE; 3612 3613 return (rv); 3614 3615 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3616 pte = vtopte(addr); 3617 rv = (*pte == 0); 3618 } 3619 return (rv); 3620} 3621 3622boolean_t 3623pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3624{ 3625 boolean_t rv; 3626 3627 PMAP_LOCK(pmap); 3628 rv = pmap_is_prefaultable_locked(pmap, addr); 3629 PMAP_UNLOCK(pmap); 3630 return (rv); 3631} 3632 3633boolean_t 3634pmap_is_referenced(vm_page_t m) 3635{ 3636 pv_entry_t pv; 3637 pt_entry_t *pte; 3638 pmap_t pmap; 3639 boolean_t rv; 3640 3641 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3642 ("pmap_is_referenced: page %p is not managed", m)); 3643 rv = FALSE; 3644 vm_page_lock_queues(); 3645 sched_pin(); 3646 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3647 pmap = PV_PMAP(pv); 3648 PMAP_LOCK(pmap); 3649 pte = pmap_pte_quick(pmap, pv->pv_va); 3650 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3651 PMAP_UNLOCK(pmap); 3652 if (rv) 3653 break; 3654 } 3655 if (*PMAP1) 3656 PT_SET_MA(PADDR1, 0); 3657 sched_unpin(); 3658 vm_page_unlock_queues(); 3659 return (rv); 3660} 3661 3662void 3663pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3664{ 3665 int i, npages = round_page(len) >> PAGE_SHIFT; 3666 for (i = 0; i < npages; i++) { 3667 pt_entry_t *pte; 3668 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3669 vm_page_lock_queues(); 3670 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3671 vm_page_unlock_queues(); 3672 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3673 pmap_pte_release(pte); 3674 } 3675} 3676 3677void 3678pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3679{ 3680 int i, npages = round_page(len) >> PAGE_SHIFT; 3681 for (i = 0; i < npages; i++) { 3682 pt_entry_t *pte; 3683 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3684 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3685 vm_page_lock_queues(); 3686 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3687 vm_page_unlock_queues(); 3688 pmap_pte_release(pte); 3689 } 3690} 3691 3692/* 3693 * Clear the write and modified bits in each of the given page's mappings. 3694 */ 3695void 3696pmap_remove_write(vm_page_t m) 3697{ 3698 pv_entry_t pv; 3699 pmap_t pmap; 3700 pt_entry_t oldpte, *pte; 3701 3702 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3703 ("pmap_remove_write: page %p is not managed", m)); 3704 3705 /* 3706 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 3707 * another thread while the object is locked. Thus, if PGA_WRITEABLE 3708 * is clear, no page table entries need updating. 3709 */ 3710 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3711 if ((m->oflags & VPO_BUSY) == 0 && 3712 (m->aflags & PGA_WRITEABLE) == 0) 3713 return; 3714 vm_page_lock_queues(); 3715 sched_pin(); 3716 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3717 pmap = PV_PMAP(pv); 3718 PMAP_LOCK(pmap); 3719 pte = pmap_pte_quick(pmap, pv->pv_va); 3720retry: 3721 oldpte = *pte; 3722 if ((oldpte & PG_RW) != 0) { 3723 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3724 3725 /* 3726 * Regardless of whether a pte is 32 or 64 bits 3727 * in size, PG_RW and PG_M are among the least 3728 * significant 32 bits. 3729 */ 3730 PT_SET_VA_MA(pte, newpte, TRUE); 3731 if (*pte != newpte) 3732 goto retry; 3733 3734 if ((oldpte & PG_M) != 0) 3735 vm_page_dirty(m); 3736 pmap_invalidate_page(pmap, pv->pv_va); 3737 } 3738 PMAP_UNLOCK(pmap); 3739 } 3740 vm_page_aflag_clear(m, PGA_WRITEABLE); 3741 PT_UPDATES_FLUSH(); 3742 if (*PMAP1) 3743 PT_SET_MA(PADDR1, 0); 3744 sched_unpin(); 3745 vm_page_unlock_queues(); 3746} 3747 3748/* 3749 * pmap_ts_referenced: 3750 * 3751 * Return a count of reference bits for a page, clearing those bits. 3752 * It is not necessary for every reference bit to be cleared, but it 3753 * is necessary that 0 only be returned when there are truly no 3754 * reference bits set. 3755 * 3756 * XXX: The exact number of bits to check and clear is a matter that 3757 * should be tested and standardized at some point in the future for 3758 * optimal aging of shared pages. 3759 */ 3760int 3761pmap_ts_referenced(vm_page_t m) 3762{ 3763 pv_entry_t pv, pvf, pvn; 3764 pmap_t pmap; 3765 pt_entry_t *pte; 3766 int rtval = 0; 3767 3768 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3769 ("pmap_ts_referenced: page %p is not managed", m)); 3770 vm_page_lock_queues(); 3771 sched_pin(); 3772 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3773 pvf = pv; 3774 do { 3775 pvn = TAILQ_NEXT(pv, pv_list); 3776 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3777 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3778 pmap = PV_PMAP(pv); 3779 PMAP_LOCK(pmap); 3780 pte = pmap_pte_quick(pmap, pv->pv_va); 3781 if ((*pte & PG_A) != 0) { 3782 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3783 pmap_invalidate_page(pmap, pv->pv_va); 3784 rtval++; 3785 if (rtval > 4) 3786 pvn = NULL; 3787 } 3788 PMAP_UNLOCK(pmap); 3789 } while ((pv = pvn) != NULL && pv != pvf); 3790 } 3791 PT_UPDATES_FLUSH(); 3792 if (*PMAP1) 3793 PT_SET_MA(PADDR1, 0); 3794 sched_unpin(); 3795 vm_page_unlock_queues(); 3796 return (rtval); 3797} 3798 3799/* 3800 * Clear the modify bits on the specified physical page. 3801 */ 3802void 3803pmap_clear_modify(vm_page_t m) 3804{ 3805 pv_entry_t pv; 3806 pmap_t pmap; 3807 pt_entry_t *pte; 3808 3809 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3810 ("pmap_clear_modify: page %p is not managed", m)); 3811 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3812 KASSERT((m->oflags & VPO_BUSY) == 0, 3813 ("pmap_clear_modify: page %p is busy", m)); 3814 3815 /* 3816 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 3817 * If the object containing the page is locked and the page is not 3818 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 3819 */ 3820 if ((m->aflags & PGA_WRITEABLE) == 0) 3821 return; 3822 vm_page_lock_queues(); 3823 sched_pin(); 3824 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3825 pmap = PV_PMAP(pv); 3826 PMAP_LOCK(pmap); 3827 pte = pmap_pte_quick(pmap, pv->pv_va); 3828 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3829 /* 3830 * Regardless of whether a pte is 32 or 64 bits 3831 * in size, PG_M is among the least significant 3832 * 32 bits. 3833 */ 3834 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3835 pmap_invalidate_page(pmap, pv->pv_va); 3836 } 3837 PMAP_UNLOCK(pmap); 3838 } 3839 sched_unpin(); 3840 vm_page_unlock_queues(); 3841} 3842 3843/* 3844 * pmap_clear_reference: 3845 * 3846 * Clear the reference bit on the specified physical page. 3847 */ 3848void 3849pmap_clear_reference(vm_page_t m) 3850{ 3851 pv_entry_t pv; 3852 pmap_t pmap; 3853 pt_entry_t *pte; 3854 3855 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3856 ("pmap_clear_reference: page %p is not managed", m)); 3857 vm_page_lock_queues(); 3858 sched_pin(); 3859 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3860 pmap = PV_PMAP(pv); 3861 PMAP_LOCK(pmap); 3862 pte = pmap_pte_quick(pmap, pv->pv_va); 3863 if ((*pte & PG_A) != 0) { 3864 /* 3865 * Regardless of whether a pte is 32 or 64 bits 3866 * in size, PG_A is among the least significant 3867 * 32 bits. 3868 */ 3869 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3870 pmap_invalidate_page(pmap, pv->pv_va); 3871 } 3872 PMAP_UNLOCK(pmap); 3873 } 3874 sched_unpin(); 3875 vm_page_unlock_queues(); 3876} 3877 3878/* 3879 * Miscellaneous support routines follow 3880 */ 3881 3882/* 3883 * Map a set of physical memory pages into the kernel virtual 3884 * address space. Return a pointer to where it is mapped. This 3885 * routine is intended to be used for mapping device memory, 3886 * NOT real memory. 3887 */ 3888void * 3889pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 3890{ 3891 vm_offset_t va, offset; 3892 vm_size_t tmpsize; 3893 3894 offset = pa & PAGE_MASK; 3895 size = roundup(offset + size, PAGE_SIZE); 3896 pa = pa & PG_FRAME; 3897 3898 if (pa < KERNLOAD && pa + size <= KERNLOAD) 3899 va = KERNBASE + pa; 3900 else 3901 va = kmem_alloc_nofault(kernel_map, size); 3902 if (!va) 3903 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3904 3905 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 3906 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 3907 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 3908 pmap_invalidate_cache_range(va, va + size); 3909 return ((void *)(va + offset)); 3910} 3911 3912void * 3913pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3914{ 3915 3916 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 3917} 3918 3919void * 3920pmap_mapbios(vm_paddr_t pa, vm_size_t size) 3921{ 3922 3923 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 3924} 3925 3926void 3927pmap_unmapdev(vm_offset_t va, vm_size_t size) 3928{ 3929 vm_offset_t base, offset, tmpva; 3930 3931 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 3932 return; 3933 base = trunc_page(va); 3934 offset = va & PAGE_MASK; 3935 size = roundup(offset + size, PAGE_SIZE); 3936 critical_enter(); 3937 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 3938 pmap_kremove(tmpva); 3939 pmap_invalidate_range(kernel_pmap, va, tmpva); 3940 critical_exit(); 3941 kmem_free(kernel_map, base, size); 3942} 3943 3944/* 3945 * Sets the memory attribute for the specified page. 3946 */ 3947void 3948pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 3949{ 3950 3951 m->md.pat_mode = ma; 3952 if ((m->flags & PG_FICTITIOUS) != 0) 3953 return; 3954 3955 /* 3956 * If "m" is a normal page, flush it from the cache. 3957 * See pmap_invalidate_cache_range(). 3958 * 3959 * First, try to find an existing mapping of the page by sf 3960 * buffer. sf_buf_invalidate_cache() modifies mapping and 3961 * flushes the cache. 3962 */ 3963 if (sf_buf_invalidate_cache(m)) 3964 return; 3965 3966 /* 3967 * If page is not mapped by sf buffer, but CPU does not 3968 * support self snoop, map the page transient and do 3969 * invalidation. In the worst case, whole cache is flushed by 3970 * pmap_invalidate_cache_range(). 3971 */ 3972 if ((cpu_feature & CPUID_SS) == 0) 3973 pmap_flush_page(m); 3974} 3975 3976static void 3977pmap_flush_page(vm_page_t m) 3978{ 3979 struct sysmaps *sysmaps; 3980 vm_offset_t sva, eva; 3981 3982 if ((cpu_feature & CPUID_CLFSH) != 0) { 3983 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3984 mtx_lock(&sysmaps->lock); 3985 if (*sysmaps->CMAP2) 3986 panic("pmap_flush_page: CMAP2 busy"); 3987 sched_pin(); 3988 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 3989 VM_PAGE_TO_MACH(m) | PG_A | PG_M | 3990 pmap_cache_bits(m->md.pat_mode, 0)); 3991 invlcaddr(sysmaps->CADDR2); 3992 sva = (vm_offset_t)sysmaps->CADDR2; 3993 eva = sva + PAGE_SIZE; 3994 3995 /* 3996 * Use mfence despite the ordering implied by 3997 * mtx_{un,}lock() because clflush is not guaranteed 3998 * to be ordered by any other instruction. 3999 */ 4000 mfence(); 4001 for (; sva < eva; sva += cpu_clflush_line_size) 4002 clflush(sva); 4003 mfence(); 4004 PT_SET_MA(sysmaps->CADDR2, 0); 4005 sched_unpin(); 4006 mtx_unlock(&sysmaps->lock); 4007 } else 4008 pmap_invalidate_cache(); 4009} 4010 4011/* 4012 * Changes the specified virtual address range's memory type to that given by 4013 * the parameter "mode". The specified virtual address range must be 4014 * completely contained within either the kernel map. 4015 * 4016 * Returns zero if the change completed successfully, and either EINVAL or 4017 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4018 * of the virtual address range was not mapped, and ENOMEM is returned if 4019 * there was insufficient memory available to complete the change. 4020 */ 4021int 4022pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4023{ 4024 vm_offset_t base, offset, tmpva; 4025 pt_entry_t *pte; 4026 u_int opte, npte; 4027 pd_entry_t *pde; 4028 boolean_t changed; 4029 4030 base = trunc_page(va); 4031 offset = va & PAGE_MASK; 4032 size = roundup(offset + size, PAGE_SIZE); 4033 4034 /* Only supported on kernel virtual addresses. */ 4035 if (base <= VM_MAXUSER_ADDRESS) 4036 return (EINVAL); 4037 4038 /* 4MB pages and pages that aren't mapped aren't supported. */ 4039 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4040 pde = pmap_pde(kernel_pmap, tmpva); 4041 if (*pde & PG_PS) 4042 return (EINVAL); 4043 if ((*pde & PG_V) == 0) 4044 return (EINVAL); 4045 pte = vtopte(va); 4046 if ((*pte & PG_V) == 0) 4047 return (EINVAL); 4048 } 4049 4050 changed = FALSE; 4051 4052 /* 4053 * Ok, all the pages exist and are 4k, so run through them updating 4054 * their cache mode. 4055 */ 4056 for (tmpva = base; size > 0; ) { 4057 pte = vtopte(tmpva); 4058 4059 /* 4060 * The cache mode bits are all in the low 32-bits of the 4061 * PTE, so we can just spin on updating the low 32-bits. 4062 */ 4063 do { 4064 opte = *(u_int *)pte; 4065 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4066 npte |= pmap_cache_bits(mode, 0); 4067 PT_SET_VA_MA(pte, npte, TRUE); 4068 } while (npte != opte && (*pte != npte)); 4069 if (npte != opte) 4070 changed = TRUE; 4071 tmpva += PAGE_SIZE; 4072 size -= PAGE_SIZE; 4073 } 4074 4075 /* 4076 * Flush CPU caches to make sure any data isn't cached that 4077 * shouldn't be, etc. 4078 */ 4079 if (changed) { 4080 pmap_invalidate_range(kernel_pmap, base, tmpva); 4081 pmap_invalidate_cache_range(base, tmpva); 4082 } 4083 return (0); 4084} 4085 4086/* 4087 * perform the pmap work for mincore 4088 */ 4089int 4090pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4091{ 4092 pt_entry_t *ptep, pte; 4093 vm_paddr_t pa; 4094 int val; 4095 4096 PMAP_LOCK(pmap); 4097retry: 4098 ptep = pmap_pte(pmap, addr); 4099 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4100 pmap_pte_release(ptep); 4101 val = 0; 4102 if ((pte & PG_V) != 0) { 4103 val |= MINCORE_INCORE; 4104 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4105 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4106 if ((pte & PG_A) != 0) 4107 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4108 } 4109 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4110 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4111 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4112 pa = pte & PG_FRAME; 4113 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4114 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4115 goto retry; 4116 } else 4117 PA_UNLOCK_COND(*locked_pa); 4118 PMAP_UNLOCK(pmap); 4119 return (val); 4120} 4121 4122void 4123pmap_activate(struct thread *td) 4124{ 4125 pmap_t pmap, oldpmap; 4126 u_int cpuid; 4127 u_int32_t cr3; 4128 4129 critical_enter(); 4130 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4131 oldpmap = PCPU_GET(curpmap); 4132 cpuid = PCPU_GET(cpuid); 4133#if defined(SMP) 4134 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 4135 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 4136#else 4137 CPU_CLR(cpuid, &oldpmap->pm_active); 4138 CPU_SET(cpuid, &pmap->pm_active); 4139#endif 4140#ifdef PAE 4141 cr3 = vtophys(pmap->pm_pdpt); 4142#else 4143 cr3 = vtophys(pmap->pm_pdir); 4144#endif 4145 /* 4146 * pmap_activate is for the current thread on the current cpu 4147 */ 4148 td->td_pcb->pcb_cr3 = cr3; 4149 PT_UPDATES_FLUSH(); 4150 load_cr3(cr3); 4151 PCPU_SET(curpmap, pmap); 4152 critical_exit(); 4153} 4154 4155void 4156pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4157{ 4158} 4159 4160/* 4161 * Increase the starting virtual address of the given mapping if a 4162 * different alignment might result in more superpage mappings. 4163 */ 4164void 4165pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4166 vm_offset_t *addr, vm_size_t size) 4167{ 4168 vm_offset_t superpage_offset; 4169 4170 if (size < NBPDR) 4171 return; 4172 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4173 offset += ptoa(object->pg_color); 4174 superpage_offset = offset & PDRMASK; 4175 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4176 (*addr & PDRMASK) == superpage_offset) 4177 return; 4178 if ((*addr & PDRMASK) < superpage_offset) 4179 *addr = (*addr & ~PDRMASK) + superpage_offset; 4180 else 4181 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4182} 4183 4184void 4185pmap_suspend() 4186{ 4187 pmap_t pmap; 4188 int i, pdir, offset; 4189 vm_paddr_t pdirma; 4190 mmu_update_t mu[4]; 4191 4192 /* 4193 * We need to remove the recursive mapping structure from all 4194 * our pmaps so that Xen doesn't get confused when it restores 4195 * the page tables. The recursive map lives at page directory 4196 * index PTDPTDI. We assume that the suspend code has stopped 4197 * the other vcpus (if any). 4198 */ 4199 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4200 for (i = 0; i < 4; i++) { 4201 /* 4202 * Figure out which page directory (L2) page 4203 * contains this bit of the recursive map and 4204 * the offset within that page of the map 4205 * entry 4206 */ 4207 pdir = (PTDPTDI + i) / NPDEPG; 4208 offset = (PTDPTDI + i) % NPDEPG; 4209 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4210 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4211 mu[i].val = 0; 4212 } 4213 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4214 } 4215} 4216 4217void 4218pmap_resume() 4219{ 4220 pmap_t pmap; 4221 int i, pdir, offset; 4222 vm_paddr_t pdirma; 4223 mmu_update_t mu[4]; 4224 4225 /* 4226 * Restore the recursive map that we removed on suspend. 4227 */ 4228 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4229 for (i = 0; i < 4; i++) { 4230 /* 4231 * Figure out which page directory (L2) page 4232 * contains this bit of the recursive map and 4233 * the offset within that page of the map 4234 * entry 4235 */ 4236 pdir = (PTDPTDI + i) / NPDEPG; 4237 offset = (PTDPTDI + i) % NPDEPG; 4238 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4239 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4240 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4241 } 4242 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4243 } 4244} 4245 4246#if defined(PMAP_DEBUG) 4247pmap_pid_dump(int pid) 4248{ 4249 pmap_t pmap; 4250 struct proc *p; 4251 int npte = 0; 4252 int index; 4253 4254 sx_slock(&allproc_lock); 4255 FOREACH_PROC_IN_SYSTEM(p) { 4256 if (p->p_pid != pid) 4257 continue; 4258 4259 if (p->p_vmspace) { 4260 int i,j; 4261 index = 0; 4262 pmap = vmspace_pmap(p->p_vmspace); 4263 for (i = 0; i < NPDEPTD; i++) { 4264 pd_entry_t *pde; 4265 pt_entry_t *pte; 4266 vm_offset_t base = i << PDRSHIFT; 4267 4268 pde = &pmap->pm_pdir[i]; 4269 if (pde && pmap_pde_v(pde)) { 4270 for (j = 0; j < NPTEPG; j++) { 4271 vm_offset_t va = base + (j << PAGE_SHIFT); 4272 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4273 if (index) { 4274 index = 0; 4275 printf("\n"); 4276 } 4277 sx_sunlock(&allproc_lock); 4278 return (npte); 4279 } 4280 pte = pmap_pte(pmap, va); 4281 if (pte && pmap_pte_v(pte)) { 4282 pt_entry_t pa; 4283 vm_page_t m; 4284 pa = PT_GET(pte); 4285 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4286 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4287 va, pa, m->hold_count, m->wire_count, m->flags); 4288 npte++; 4289 index++; 4290 if (index >= 2) { 4291 index = 0; 4292 printf("\n"); 4293 } else { 4294 printf(" "); 4295 } 4296 } 4297 } 4298 } 4299 } 4300 } 4301 } 4302 sx_sunlock(&allproc_lock); 4303 return (npte); 4304} 4305#endif 4306 4307#if defined(DEBUG) 4308 4309static void pads(pmap_t pm); 4310void pmap_pvdump(vm_paddr_t pa); 4311 4312/* print address space of pmap*/ 4313static void 4314pads(pmap_t pm) 4315{ 4316 int i, j; 4317 vm_paddr_t va; 4318 pt_entry_t *ptep; 4319 4320 if (pm == kernel_pmap) 4321 return; 4322 for (i = 0; i < NPDEPTD; i++) 4323 if (pm->pm_pdir[i]) 4324 for (j = 0; j < NPTEPG; j++) { 4325 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4326 if (pm == kernel_pmap && va < KERNBASE) 4327 continue; 4328 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4329 continue; 4330 ptep = pmap_pte(pm, va); 4331 if (pmap_pte_v(ptep)) 4332 printf("%x:%x ", va, *ptep); 4333 }; 4334 4335} 4336 4337void 4338pmap_pvdump(vm_paddr_t pa) 4339{ 4340 pv_entry_t pv; 4341 pmap_t pmap; 4342 vm_page_t m; 4343 4344 printf("pa %x", pa); 4345 m = PHYS_TO_VM_PAGE(pa); 4346 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4347 pmap = PV_PMAP(pv); 4348 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4349 pads(pmap); 4350 } 4351 printf(" "); 4352} 4353#endif 4354