pmap.c revision 226843
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 226843 2011-10-27 16:39:17Z alc $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_smp.h" 109#include "opt_xbox.h" 110 111#include <sys/param.h> 112#include <sys/systm.h> 113#include <sys/kernel.h> 114#include <sys/ktr.h> 115#include <sys/lock.h> 116#include <sys/malloc.h> 117#include <sys/mman.h> 118#include <sys/msgbuf.h> 119#include <sys/mutex.h> 120#include <sys/proc.h> 121#include <sys/sf_buf.h> 122#include <sys/sx.h> 123#include <sys/vmmeter.h> 124#include <sys/sched.h> 125#include <sys/sysctl.h> 126#ifdef SMP 127#include <sys/smp.h> 128#endif 129 130#include <vm/vm.h> 131#include <vm/vm_param.h> 132#include <vm/vm_kern.h> 133#include <vm/vm_page.h> 134#include <vm/vm_map.h> 135#include <vm/vm_object.h> 136#include <vm/vm_extern.h> 137#include <vm/vm_pageout.h> 138#include <vm/vm_pager.h> 139#include <vm/uma.h> 140 141#include <machine/cpu.h> 142#include <machine/cputypes.h> 143#include <machine/md_var.h> 144#include <machine/pcb.h> 145#include <machine/specialreg.h> 146#ifdef SMP 147#include <machine/smp.h> 148#endif 149 150#ifdef XBOX 151#include <machine/xbox.h> 152#endif 153 154#include <xen/interface/xen.h> 155#include <xen/hypervisor.h> 156#include <machine/xen/hypercall.h> 157#include <machine/xen/xenvar.h> 158#include <machine/xen/xenfunc.h> 159 160#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 161#define CPU_ENABLE_SSE 162#endif 163 164#ifndef PMAP_SHPGPERPROC 165#define PMAP_SHPGPERPROC 200 166#endif 167 168#define DIAGNOSTIC 169 170#if !defined(DIAGNOSTIC) 171#ifdef __GNUC_GNU_INLINE__ 172#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 173#else 174#define PMAP_INLINE extern inline 175#endif 176#else 177#define PMAP_INLINE 178#endif 179 180#define PV_STATS 181#ifdef PV_STATS 182#define PV_STAT(x) do { x ; } while (0) 183#else 184#define PV_STAT(x) do { } while (0) 185#endif 186 187#define pa_index(pa) ((pa) >> PDRSHIFT) 188#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 189 190/* 191 * Get PDEs and PTEs for user/kernel address space 192 */ 193#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 194#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 195 196#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 197#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 198#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 199#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 200#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 201 202#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 203 204#define HAMFISTED_LOCKING 205#ifdef HAMFISTED_LOCKING 206static struct mtx createdelete_lock; 207#endif 208 209struct pmap kernel_pmap_store; 210LIST_HEAD(pmaplist, pmap); 211static struct pmaplist allpmaps; 212static struct mtx allpmaps_lock; 213 214vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 215vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 216int pgeflag = 0; /* PG_G or-in */ 217int pseflag = 0; /* PG_PS or-in */ 218 219int nkpt; 220vm_offset_t kernel_vm_end; 221extern u_int32_t KERNend; 222 223#ifdef PAE 224pt_entry_t pg_nx; 225#endif 226 227static int pat_works; /* Is page attribute table sane? */ 228 229/* 230 * Data for the pv entry allocation mechanism 231 */ 232static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 233static struct md_page *pv_table; 234static int shpgperproc = PMAP_SHPGPERPROC; 235 236struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 237int pv_maxchunks; /* How many chunks we have KVA for */ 238vm_offset_t pv_vafree; /* freelist stored in the PTE */ 239 240/* 241 * All those kernel PT submaps that BSD is so fond of 242 */ 243struct sysmaps { 244 struct mtx lock; 245 pt_entry_t *CMAP1; 246 pt_entry_t *CMAP2; 247 caddr_t CADDR1; 248 caddr_t CADDR2; 249}; 250static struct sysmaps sysmaps_pcpu[MAXCPU]; 251static pt_entry_t *CMAP3; 252caddr_t ptvmmap = 0; 253static caddr_t CADDR3; 254struct msgbuf *msgbufp = 0; 255 256/* 257 * Crashdump maps. 258 */ 259static caddr_t crashdumpmap; 260 261static pt_entry_t *PMAP1 = 0, *PMAP2; 262static pt_entry_t *PADDR1 = 0, *PADDR2; 263#ifdef SMP 264static int PMAP1cpu; 265static int PMAP1changedcpu; 266SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 267 &PMAP1changedcpu, 0, 268 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 269#endif 270static int PMAP1changed; 271SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 272 &PMAP1changed, 0, 273 "Number of times pmap_pte_quick changed PMAP1"); 274static int PMAP1unchanged; 275SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 276 &PMAP1unchanged, 0, 277 "Number of times pmap_pte_quick didn't change PMAP1"); 278static struct mtx PMAP2mutex; 279 280SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 281static int pg_ps_enabled; 282SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 283 "Are large page mappings enabled?"); 284 285SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 286 "Max number of PV entries"); 287SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 288 "Page share factor per proc"); 289SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 290 "2/4MB page mapping counters"); 291 292static u_long pmap_pde_mappings; 293SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 294 &pmap_pde_mappings, 0, "2/4MB page mappings"); 295 296static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 297static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 298static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 299static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 300 vm_offset_t va); 301 302static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 303 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 304static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 305 vm_page_t *free); 306static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 307 vm_page_t *free); 308static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 309 vm_offset_t va); 310static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 311 vm_page_t m); 312 313static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 314 315static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 316static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 317static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 318static void pmap_pte_release(pt_entry_t *pte); 319static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 320static vm_offset_t pmap_kmem_choose(vm_offset_t addr); 321static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 322static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 323 324static __inline void pagezero(void *page); 325 326CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 327CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 328 329/* 330 * If you get an error here, then you set KVA_PAGES wrong! See the 331 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 332 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 333 */ 334CTASSERT(KERNBASE % (1 << 24) == 0); 335 336 337 338void 339pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 340{ 341 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 342 343 switch (type) { 344 case SH_PD_SET_VA: 345#if 0 346 xen_queue_pt_update(shadow_pdir_ma, 347 xpmap_ptom(val & ~(PG_RW))); 348#endif 349 xen_queue_pt_update(pdir_ma, 350 xpmap_ptom(val)); 351 break; 352 case SH_PD_SET_VA_MA: 353#if 0 354 xen_queue_pt_update(shadow_pdir_ma, 355 val & ~(PG_RW)); 356#endif 357 xen_queue_pt_update(pdir_ma, val); 358 break; 359 case SH_PD_SET_VA_CLEAR: 360#if 0 361 xen_queue_pt_update(shadow_pdir_ma, 0); 362#endif 363 xen_queue_pt_update(pdir_ma, 0); 364 break; 365 } 366} 367 368/* 369 * Move the kernel virtual free pointer to the next 370 * 4MB. This is used to help improve performance 371 * by using a large (4MB) page for much of the kernel 372 * (.text, .data, .bss) 373 */ 374static vm_offset_t 375pmap_kmem_choose(vm_offset_t addr) 376{ 377 vm_offset_t newaddr = addr; 378 379#ifndef DISABLE_PSE 380 if (cpu_feature & CPUID_PSE) 381 newaddr = (addr + PDRMASK) & ~PDRMASK; 382#endif 383 return newaddr; 384} 385 386/* 387 * Bootstrap the system enough to run with virtual memory. 388 * 389 * On the i386 this is called after mapping has already been enabled 390 * and just syncs the pmap module with what has already been done. 391 * [We can't call it easily with mapping off since the kernel is not 392 * mapped with PA == VA, hence we would have to relocate every address 393 * from the linked base (virtual) address "KERNBASE" to the actual 394 * (physical) address starting relative to 0] 395 */ 396void 397pmap_bootstrap(vm_paddr_t firstaddr) 398{ 399 vm_offset_t va; 400 pt_entry_t *pte, *unused; 401 struct sysmaps *sysmaps; 402 int i; 403 404 /* 405 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 406 * large. It should instead be correctly calculated in locore.s and 407 * not based on 'first' (which is a physical address, not a virtual 408 * address, for the start of unused physical memory). The kernel 409 * page tables are NOT double mapped and thus should not be included 410 * in this calculation. 411 */ 412 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 413 virtual_avail = pmap_kmem_choose(virtual_avail); 414 415 virtual_end = VM_MAX_KERNEL_ADDRESS; 416 417 /* 418 * Initialize the kernel pmap (which is statically allocated). 419 */ 420 PMAP_LOCK_INIT(kernel_pmap); 421 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 422#ifdef PAE 423 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 424#endif 425 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 426 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 427 LIST_INIT(&allpmaps); 428 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 429 mtx_lock_spin(&allpmaps_lock); 430 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 431 mtx_unlock_spin(&allpmaps_lock); 432 if (nkpt == 0) 433 nkpt = NKPT; 434 435 /* 436 * Reserve some special page table entries/VA space for temporary 437 * mapping of pages. 438 */ 439#define SYSMAP(c, p, v, n) \ 440 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 441 442 va = virtual_avail; 443 pte = vtopte(va); 444 445 /* 446 * CMAP1/CMAP2 are used for zeroing and copying pages. 447 * CMAP3 is used for the idle process page zeroing. 448 */ 449 for (i = 0; i < MAXCPU; i++) { 450 sysmaps = &sysmaps_pcpu[i]; 451 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 452 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 453 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 454 PT_SET_MA(sysmaps->CADDR1, 0); 455 PT_SET_MA(sysmaps->CADDR2, 0); 456 } 457 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 458 PT_SET_MA(CADDR3, 0); 459 460 /* 461 * Crashdump maps. 462 */ 463 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 464 465 /* 466 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 467 */ 468 SYSMAP(caddr_t, unused, ptvmmap, 1) 469 470 /* 471 * msgbufp is used to map the system message buffer. 472 */ 473 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 474 475 /* 476 * ptemap is used for pmap_pte_quick 477 */ 478 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1); 479 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1); 480 481 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 482 483 virtual_avail = va; 484 485 /* 486 * Leave in place an identity mapping (virt == phys) for the low 1 MB 487 * physical memory region that is used by the ACPI wakeup code. This 488 * mapping must not have PG_G set. 489 */ 490#ifndef XEN 491 /* 492 * leave here deliberately to show that this is not supported 493 */ 494#ifdef XBOX 495 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 496 * an early stadium, we cannot yet neatly map video memory ... :-( 497 * Better fixes are very welcome! */ 498 if (!arch_i386_is_xbox) 499#endif 500 for (i = 1; i < NKPT; i++) 501 PTD[i] = 0; 502 503 /* Initialize the PAT MSR if present. */ 504 pmap_init_pat(); 505 506 /* Turn on PG_G on kernel page(s) */ 507 pmap_set_pg(); 508#endif 509 510#ifdef HAMFISTED_LOCKING 511 mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF); 512#endif 513} 514 515/* 516 * Setup the PAT MSR. 517 */ 518void 519pmap_init_pat(void) 520{ 521 uint64_t pat_msr; 522 523 /* Bail if this CPU doesn't implement PAT. */ 524 if (!(cpu_feature & CPUID_PAT)) 525 return; 526 527 if (cpu_vendor_id != CPU_VENDOR_INTEL || 528 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 529 /* 530 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 531 * Program 4 and 5 as WP and WC. 532 * Leave 6 and 7 as UC and UC-. 533 */ 534 pat_msr = rdmsr(MSR_PAT); 535 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 536 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 537 PAT_VALUE(5, PAT_WRITE_COMBINING); 538 pat_works = 1; 539 } else { 540 /* 541 * Due to some Intel errata, we can only safely use the lower 4 542 * PAT entries. Thus, just replace PAT Index 2 with WC instead 543 * of UC-. 544 * 545 * Intel Pentium III Processor Specification Update 546 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 547 * or Mode C Paging) 548 * 549 * Intel Pentium IV Processor Specification Update 550 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 551 */ 552 pat_msr = rdmsr(MSR_PAT); 553 pat_msr &= ~PAT_MASK(2); 554 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 555 pat_works = 0; 556 } 557 wrmsr(MSR_PAT, pat_msr); 558} 559 560/* 561 * Initialize a vm_page's machine-dependent fields. 562 */ 563void 564pmap_page_init(vm_page_t m) 565{ 566 567 TAILQ_INIT(&m->md.pv_list); 568 m->md.pat_mode = PAT_WRITE_BACK; 569} 570 571/* 572 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 573 * Requirements: 574 * - Must deal with pages in order to ensure that none of the PG_* bits 575 * are ever set, PG_V in particular. 576 * - Assumes we can write to ptes without pte_store() atomic ops, even 577 * on PAE systems. This should be ok. 578 * - Assumes nothing will ever test these addresses for 0 to indicate 579 * no mapping instead of correctly checking PG_V. 580 * - Assumes a vm_offset_t will fit in a pte (true for i386). 581 * Because PG_V is never set, there can be no mappings to invalidate. 582 */ 583static int ptelist_count = 0; 584static vm_offset_t 585pmap_ptelist_alloc(vm_offset_t *head) 586{ 587 vm_offset_t va; 588 vm_offset_t *phead = (vm_offset_t *)*head; 589 590 if (ptelist_count == 0) { 591 printf("out of memory!!!!!!\n"); 592 return (0); /* Out of memory */ 593 } 594 ptelist_count--; 595 va = phead[ptelist_count]; 596 return (va); 597} 598 599static void 600pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 601{ 602 vm_offset_t *phead = (vm_offset_t *)*head; 603 604 phead[ptelist_count++] = va; 605} 606 607static void 608pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 609{ 610 int i, nstackpages; 611 vm_offset_t va; 612 vm_page_t m; 613 614 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 615 for (i = 0; i < nstackpages; i++) { 616 va = (vm_offset_t)base + i * PAGE_SIZE; 617 m = vm_page_alloc(NULL, i, 618 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 619 VM_ALLOC_ZERO); 620 pmap_qenter(va, &m, 1); 621 } 622 623 *head = (vm_offset_t)base; 624 for (i = npages - 1; i >= nstackpages; i--) { 625 va = (vm_offset_t)base + i * PAGE_SIZE; 626 pmap_ptelist_free(head, va); 627 } 628} 629 630 631/* 632 * Initialize the pmap module. 633 * Called by vm_init, to initialize any structures that the pmap 634 * system needs to map virtual memory. 635 */ 636void 637pmap_init(void) 638{ 639 vm_page_t mpte; 640 vm_size_t s; 641 int i, pv_npg; 642 643 /* 644 * Initialize the vm page array entries for the kernel pmap's 645 * page table pages. 646 */ 647 for (i = 0; i < nkpt; i++) { 648 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(PTD[i + KPTDI] & PG_FRAME)); 649 KASSERT(mpte >= vm_page_array && 650 mpte < &vm_page_array[vm_page_array_size], 651 ("pmap_init: page table page is out of range")); 652 mpte->pindex = i + KPTDI; 653 mpte->phys_addr = xpmap_mtop(PTD[i + KPTDI] & PG_FRAME); 654 } 655 656 /* 657 * Initialize the address space (zone) for the pv entries. Set a 658 * high water mark so that the system can recover from excessive 659 * numbers of pv entries. 660 */ 661 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 662 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 663 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 664 pv_entry_max = roundup(pv_entry_max, _NPCPV); 665 pv_entry_high_water = 9 * (pv_entry_max / 10); 666 667 /* 668 * Are large page mappings enabled? 669 */ 670 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 671 672 /* 673 * Calculate the size of the pv head table for superpages. 674 */ 675 for (i = 0; phys_avail[i + 1]; i += 2); 676 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 677 678 /* 679 * Allocate memory for the pv head table for superpages. 680 */ 681 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 682 s = round_page(s); 683 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 684 for (i = 0; i < pv_npg; i++) 685 TAILQ_INIT(&pv_table[i].pv_list); 686 687 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 688 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 689 PAGE_SIZE * pv_maxchunks); 690 if (pv_chunkbase == NULL) 691 panic("pmap_init: not enough kvm for pv chunks"); 692 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 693} 694 695 696/*************************************************** 697 * Low level helper routines..... 698 ***************************************************/ 699 700/* 701 * Determine the appropriate bits to set in a PTE or PDE for a specified 702 * caching mode. 703 */ 704int 705pmap_cache_bits(int mode, boolean_t is_pde) 706{ 707 int pat_flag, pat_index, cache_bits; 708 709 /* The PAT bit is different for PTE's and PDE's. */ 710 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 711 712 /* If we don't support PAT, map extended modes to older ones. */ 713 if (!(cpu_feature & CPUID_PAT)) { 714 switch (mode) { 715 case PAT_UNCACHEABLE: 716 case PAT_WRITE_THROUGH: 717 case PAT_WRITE_BACK: 718 break; 719 case PAT_UNCACHED: 720 case PAT_WRITE_COMBINING: 721 case PAT_WRITE_PROTECTED: 722 mode = PAT_UNCACHEABLE; 723 break; 724 } 725 } 726 727 /* Map the caching mode to a PAT index. */ 728 if (pat_works) { 729 switch (mode) { 730 case PAT_UNCACHEABLE: 731 pat_index = 3; 732 break; 733 case PAT_WRITE_THROUGH: 734 pat_index = 1; 735 break; 736 case PAT_WRITE_BACK: 737 pat_index = 0; 738 break; 739 case PAT_UNCACHED: 740 pat_index = 2; 741 break; 742 case PAT_WRITE_COMBINING: 743 pat_index = 5; 744 break; 745 case PAT_WRITE_PROTECTED: 746 pat_index = 4; 747 break; 748 default: 749 panic("Unknown caching mode %d\n", mode); 750 } 751 } else { 752 switch (mode) { 753 case PAT_UNCACHED: 754 case PAT_UNCACHEABLE: 755 case PAT_WRITE_PROTECTED: 756 pat_index = 3; 757 break; 758 case PAT_WRITE_THROUGH: 759 pat_index = 1; 760 break; 761 case PAT_WRITE_BACK: 762 pat_index = 0; 763 break; 764 case PAT_WRITE_COMBINING: 765 pat_index = 2; 766 break; 767 default: 768 panic("Unknown caching mode %d\n", mode); 769 } 770 } 771 772 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 773 cache_bits = 0; 774 if (pat_index & 0x4) 775 cache_bits |= pat_flag; 776 if (pat_index & 0x2) 777 cache_bits |= PG_NC_PCD; 778 if (pat_index & 0x1) 779 cache_bits |= PG_NC_PWT; 780 return (cache_bits); 781} 782#ifdef SMP 783/* 784 * For SMP, these functions have to use the IPI mechanism for coherence. 785 * 786 * N.B.: Before calling any of the following TLB invalidation functions, 787 * the calling processor must ensure that all stores updating a non- 788 * kernel page table are globally performed. Otherwise, another 789 * processor could cache an old, pre-update entry without being 790 * invalidated. This can happen one of two ways: (1) The pmap becomes 791 * active on another processor after its pm_active field is checked by 792 * one of the following functions but before a store updating the page 793 * table is globally performed. (2) The pmap becomes active on another 794 * processor before its pm_active field is checked but due to 795 * speculative loads one of the following functions stills reads the 796 * pmap as inactive on the other processor. 797 * 798 * The kernel page table is exempt because its pm_active field is 799 * immutable. The kernel page table is always active on every 800 * processor. 801 */ 802void 803pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 804{ 805 cpuset_t other_cpus; 806 u_int cpuid; 807 808 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 809 pmap, va); 810 811 sched_pin(); 812 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 813 invlpg(va); 814 smp_invlpg(va); 815 } else { 816 cpuid = PCPU_GET(cpuid); 817 other_cpus = all_cpus; 818 CPU_CLR(cpuid, &other_cpus); 819 if (CPU_ISSET(cpuid, &pmap->pm_active)) 820 invlpg(va); 821 CPU_AND(&other_cpus, &pmap->pm_active); 822 if (!CPU_EMPTY(&other_cpus)) 823 smp_masked_invlpg(other_cpus, va); 824 } 825 sched_unpin(); 826 PT_UPDATES_FLUSH(); 827} 828 829void 830pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 831{ 832 cpuset_t other_cpus; 833 vm_offset_t addr; 834 u_int cpuid; 835 836 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 837 pmap, sva, eva); 838 839 sched_pin(); 840 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 841 for (addr = sva; addr < eva; addr += PAGE_SIZE) 842 invlpg(addr); 843 smp_invlpg_range(sva, eva); 844 } else { 845 cpuid = PCPU_GET(cpuid); 846 other_cpus = all_cpus; 847 CPU_CLR(cpuid, &other_cpus); 848 if (CPU_ISSET(cpuid, &pmap->pm_active)) 849 for (addr = sva; addr < eva; addr += PAGE_SIZE) 850 invlpg(addr); 851 CPU_AND(&other_cpus, &pmap->pm_active); 852 if (!CPU_EMPTY(&other_cpus)) 853 smp_masked_invlpg_range(other_cpus, sva, eva); 854 } 855 sched_unpin(); 856 PT_UPDATES_FLUSH(); 857} 858 859void 860pmap_invalidate_all(pmap_t pmap) 861{ 862 cpuset_t other_cpus; 863 u_int cpuid; 864 865 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 866 867 sched_pin(); 868 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 869 invltlb(); 870 smp_invltlb(); 871 } else { 872 cpuid = PCPU_GET(cpuid); 873 other_cpus = all_cpus; 874 CPU_CLR(cpuid, &other_cpus); 875 if (CPU_ISSET(cpuid, &pmap->pm_active)) 876 invltlb(); 877 CPU_AND(&other_cpus, &pmap->pm_active); 878 if (!CPU_EMPTY(&other_cpus)) 879 smp_masked_invltlb(other_cpus); 880 } 881 sched_unpin(); 882} 883 884void 885pmap_invalidate_cache(void) 886{ 887 888 sched_pin(); 889 wbinvd(); 890 smp_cache_flush(); 891 sched_unpin(); 892} 893#else /* !SMP */ 894/* 895 * Normal, non-SMP, 486+ invalidation functions. 896 * We inline these within pmap.c for speed. 897 */ 898PMAP_INLINE void 899pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 900{ 901 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 902 pmap, va); 903 904 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 905 invlpg(va); 906 PT_UPDATES_FLUSH(); 907} 908 909PMAP_INLINE void 910pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 911{ 912 vm_offset_t addr; 913 914 if (eva - sva > PAGE_SIZE) 915 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 916 pmap, sva, eva); 917 918 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 919 for (addr = sva; addr < eva; addr += PAGE_SIZE) 920 invlpg(addr); 921 PT_UPDATES_FLUSH(); 922} 923 924PMAP_INLINE void 925pmap_invalidate_all(pmap_t pmap) 926{ 927 928 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 929 930 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 931 invltlb(); 932} 933 934PMAP_INLINE void 935pmap_invalidate_cache(void) 936{ 937 938 wbinvd(); 939} 940#endif /* !SMP */ 941 942void 943pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 944{ 945 946 KASSERT((sva & PAGE_MASK) == 0, 947 ("pmap_invalidate_cache_range: sva not page-aligned")); 948 KASSERT((eva & PAGE_MASK) == 0, 949 ("pmap_invalidate_cache_range: eva not page-aligned")); 950 951 if (cpu_feature & CPUID_SS) 952 ; /* If "Self Snoop" is supported, do nothing. */ 953 else if (cpu_feature & CPUID_CLFSH) { 954 955 /* 956 * Otherwise, do per-cache line flush. Use the mfence 957 * instruction to insure that previous stores are 958 * included in the write-back. The processor 959 * propagates flush to other processors in the cache 960 * coherence domain. 961 */ 962 mfence(); 963 for (; sva < eva; sva += cpu_clflush_line_size) 964 clflush(sva); 965 mfence(); 966 } else { 967 968 /* 969 * No targeted cache flush methods are supported by CPU, 970 * globally invalidate cache as a last resort. 971 */ 972 pmap_invalidate_cache(); 973 } 974} 975 976/* 977 * Are we current address space or kernel? N.B. We return FALSE when 978 * a pmap's page table is in use because a kernel thread is borrowing 979 * it. The borrowed page table can change spontaneously, making any 980 * dependence on its continued use subject to a race condition. 981 */ 982static __inline int 983pmap_is_current(pmap_t pmap) 984{ 985 986 return (pmap == kernel_pmap || 987 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 988 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 989} 990 991/* 992 * If the given pmap is not the current or kernel pmap, the returned pte must 993 * be released by passing it to pmap_pte_release(). 994 */ 995pt_entry_t * 996pmap_pte(pmap_t pmap, vm_offset_t va) 997{ 998 pd_entry_t newpf; 999 pd_entry_t *pde; 1000 1001 pde = pmap_pde(pmap, va); 1002 if (*pde & PG_PS) 1003 return (pde); 1004 if (*pde != 0) { 1005 /* are we current address space or kernel? */ 1006 if (pmap_is_current(pmap)) 1007 return (vtopte(va)); 1008 mtx_lock(&PMAP2mutex); 1009 newpf = *pde & PG_FRAME; 1010 if ((*PMAP2 & PG_FRAME) != newpf) { 1011 vm_page_lock_queues(); 1012 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 1013 vm_page_unlock_queues(); 1014 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 1015 pmap, va, (*PMAP2 & 0xffffffff)); 1016 } 1017 1018 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1019 } 1020 return (0); 1021} 1022 1023/* 1024 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1025 * being NULL. 1026 */ 1027static __inline void 1028pmap_pte_release(pt_entry_t *pte) 1029{ 1030 1031 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 1032 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 1033 *PMAP2); 1034 vm_page_lock_queues(); 1035 PT_SET_VA(PMAP2, 0, TRUE); 1036 vm_page_unlock_queues(); 1037 mtx_unlock(&PMAP2mutex); 1038 } 1039} 1040 1041static __inline void 1042invlcaddr(void *caddr) 1043{ 1044 1045 invlpg((u_int)caddr); 1046 PT_UPDATES_FLUSH(); 1047} 1048 1049/* 1050 * Super fast pmap_pte routine best used when scanning 1051 * the pv lists. This eliminates many coarse-grained 1052 * invltlb calls. Note that many of the pv list 1053 * scans are across different pmaps. It is very wasteful 1054 * to do an entire invltlb for checking a single mapping. 1055 * 1056 * If the given pmap is not the current pmap, vm_page_queue_mtx 1057 * must be held and curthread pinned to a CPU. 1058 */ 1059static pt_entry_t * 1060pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1061{ 1062 pd_entry_t newpf; 1063 pd_entry_t *pde; 1064 1065 pde = pmap_pde(pmap, va); 1066 if (*pde & PG_PS) 1067 return (pde); 1068 if (*pde != 0) { 1069 /* are we current address space or kernel? */ 1070 if (pmap_is_current(pmap)) 1071 return (vtopte(va)); 1072 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1073 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1074 newpf = *pde & PG_FRAME; 1075 if ((*PMAP1 & PG_FRAME) != newpf) { 1076 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1077 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1078 pmap, va, (u_long)*PMAP1); 1079 1080#ifdef SMP 1081 PMAP1cpu = PCPU_GET(cpuid); 1082#endif 1083 PMAP1changed++; 1084 } else 1085#ifdef SMP 1086 if (PMAP1cpu != PCPU_GET(cpuid)) { 1087 PMAP1cpu = PCPU_GET(cpuid); 1088 invlcaddr(PADDR1); 1089 PMAP1changedcpu++; 1090 } else 1091#endif 1092 PMAP1unchanged++; 1093 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1094 } 1095 return (0); 1096} 1097 1098/* 1099 * Routine: pmap_extract 1100 * Function: 1101 * Extract the physical page address associated 1102 * with the given map/virtual_address pair. 1103 */ 1104vm_paddr_t 1105pmap_extract(pmap_t pmap, vm_offset_t va) 1106{ 1107 vm_paddr_t rtval; 1108 pt_entry_t *pte; 1109 pd_entry_t pde; 1110 pt_entry_t pteval; 1111 1112 rtval = 0; 1113 PMAP_LOCK(pmap); 1114 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1115 if (pde != 0) { 1116 if ((pde & PG_PS) != 0) { 1117 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1118 PMAP_UNLOCK(pmap); 1119 return rtval; 1120 } 1121 pte = pmap_pte(pmap, va); 1122 pteval = *pte ? xpmap_mtop(*pte) : 0; 1123 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1124 pmap_pte_release(pte); 1125 } 1126 PMAP_UNLOCK(pmap); 1127 return (rtval); 1128} 1129 1130/* 1131 * Routine: pmap_extract_ma 1132 * Function: 1133 * Like pmap_extract, but returns machine address 1134 */ 1135vm_paddr_t 1136pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1137{ 1138 vm_paddr_t rtval; 1139 pt_entry_t *pte; 1140 pd_entry_t pde; 1141 1142 rtval = 0; 1143 PMAP_LOCK(pmap); 1144 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1145 if (pde != 0) { 1146 if ((pde & PG_PS) != 0) { 1147 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1148 PMAP_UNLOCK(pmap); 1149 return rtval; 1150 } 1151 pte = pmap_pte(pmap, va); 1152 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1153 pmap_pte_release(pte); 1154 } 1155 PMAP_UNLOCK(pmap); 1156 return (rtval); 1157} 1158 1159/* 1160 * Routine: pmap_extract_and_hold 1161 * Function: 1162 * Atomically extract and hold the physical page 1163 * with the given pmap and virtual address pair 1164 * if that mapping permits the given protection. 1165 */ 1166vm_page_t 1167pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1168{ 1169 pd_entry_t pde; 1170 pt_entry_t pte; 1171 vm_page_t m; 1172 vm_paddr_t pa; 1173 1174 pa = 0; 1175 m = NULL; 1176 PMAP_LOCK(pmap); 1177retry: 1178 pde = PT_GET(pmap_pde(pmap, va)); 1179 if (pde != 0) { 1180 if (pde & PG_PS) { 1181 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1182 if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) | 1183 (va & PDRMASK), &pa)) 1184 goto retry; 1185 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1186 (va & PDRMASK)); 1187 vm_page_hold(m); 1188 } 1189 } else { 1190 sched_pin(); 1191 pte = PT_GET(pmap_pte_quick(pmap, va)); 1192 if (*PMAP1) 1193 PT_SET_MA(PADDR1, 0); 1194 if ((pte & PG_V) && 1195 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1196 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa)) 1197 goto retry; 1198 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1199 vm_page_hold(m); 1200 } 1201 sched_unpin(); 1202 } 1203 } 1204 PA_UNLOCK_COND(pa); 1205 PMAP_UNLOCK(pmap); 1206 return (m); 1207} 1208 1209/*************************************************** 1210 * Low level mapping routines..... 1211 ***************************************************/ 1212 1213/* 1214 * Add a wired page to the kva. 1215 * Note: not SMP coherent. 1216 */ 1217void 1218pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1219{ 1220 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1221} 1222 1223void 1224pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1225{ 1226 pt_entry_t *pte; 1227 1228 pte = vtopte(va); 1229 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1230} 1231 1232 1233static __inline void 1234pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1235{ 1236 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1237} 1238 1239/* 1240 * Remove a page from the kernel pagetables. 1241 * Note: not SMP coherent. 1242 */ 1243PMAP_INLINE void 1244pmap_kremove(vm_offset_t va) 1245{ 1246 pt_entry_t *pte; 1247 1248 pte = vtopte(va); 1249 PT_CLEAR_VA(pte, FALSE); 1250} 1251 1252/* 1253 * Used to map a range of physical addresses into kernel 1254 * virtual address space. 1255 * 1256 * The value passed in '*virt' is a suggested virtual address for 1257 * the mapping. Architectures which can support a direct-mapped 1258 * physical to virtual region can return the appropriate address 1259 * within that region, leaving '*virt' unchanged. Other 1260 * architectures should map the pages starting at '*virt' and 1261 * update '*virt' with the first usable address after the mapped 1262 * region. 1263 */ 1264vm_offset_t 1265pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1266{ 1267 vm_offset_t va, sva; 1268 1269 va = sva = *virt; 1270 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1271 va, start, end, prot); 1272 while (start < end) { 1273 pmap_kenter(va, start); 1274 va += PAGE_SIZE; 1275 start += PAGE_SIZE; 1276 } 1277 pmap_invalidate_range(kernel_pmap, sva, va); 1278 *virt = va; 1279 return (sva); 1280} 1281 1282 1283/* 1284 * Add a list of wired pages to the kva 1285 * this routine is only used for temporary 1286 * kernel mappings that do not need to have 1287 * page modification or references recorded. 1288 * Note that old mappings are simply written 1289 * over. The page *must* be wired. 1290 * Note: SMP coherent. Uses a ranged shootdown IPI. 1291 */ 1292void 1293pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1294{ 1295 pt_entry_t *endpte, *pte; 1296 vm_paddr_t pa; 1297 vm_offset_t va = sva; 1298 int mclcount = 0; 1299 multicall_entry_t mcl[16]; 1300 multicall_entry_t *mclp = mcl; 1301 int error; 1302 1303 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1304 pte = vtopte(sva); 1305 endpte = pte + count; 1306 while (pte < endpte) { 1307 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1308 1309 mclp->op = __HYPERVISOR_update_va_mapping; 1310 mclp->args[0] = va; 1311 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1312 mclp->args[2] = (uint32_t)(pa >> 32); 1313 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1314 1315 va += PAGE_SIZE; 1316 pte++; 1317 ma++; 1318 mclp++; 1319 mclcount++; 1320 if (mclcount == 16) { 1321 error = HYPERVISOR_multicall(mcl, mclcount); 1322 mclp = mcl; 1323 mclcount = 0; 1324 KASSERT(error == 0, ("bad multicall %d", error)); 1325 } 1326 } 1327 if (mclcount) { 1328 error = HYPERVISOR_multicall(mcl, mclcount); 1329 KASSERT(error == 0, ("bad multicall %d", error)); 1330 } 1331 1332#ifdef INVARIANTS 1333 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1334 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1335#endif 1336} 1337 1338 1339/* 1340 * This routine tears out page mappings from the 1341 * kernel -- it is meant only for temporary mappings. 1342 * Note: SMP coherent. Uses a ranged shootdown IPI. 1343 */ 1344void 1345pmap_qremove(vm_offset_t sva, int count) 1346{ 1347 vm_offset_t va; 1348 1349 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1350 va = sva; 1351 vm_page_lock_queues(); 1352 critical_enter(); 1353 while (count-- > 0) { 1354 pmap_kremove(va); 1355 va += PAGE_SIZE; 1356 } 1357 PT_UPDATES_FLUSH(); 1358 pmap_invalidate_range(kernel_pmap, sva, va); 1359 critical_exit(); 1360 vm_page_unlock_queues(); 1361} 1362 1363/*************************************************** 1364 * Page table page management routines..... 1365 ***************************************************/ 1366static __inline void 1367pmap_free_zero_pages(vm_page_t free) 1368{ 1369 vm_page_t m; 1370 1371 while (free != NULL) { 1372 m = free; 1373 free = m->right; 1374 vm_page_free_zero(m); 1375 } 1376} 1377 1378/* 1379 * This routine unholds page table pages, and if the hold count 1380 * drops to zero, then it decrements the wire count. 1381 */ 1382static __inline int 1383pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1384{ 1385 1386 --m->wire_count; 1387 if (m->wire_count == 0) 1388 return _pmap_unwire_pte_hold(pmap, m, free); 1389 else 1390 return 0; 1391} 1392 1393static int 1394_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1395{ 1396 vm_offset_t pteva; 1397 1398 PT_UPDATES_FLUSH(); 1399 /* 1400 * unmap the page table page 1401 */ 1402 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1403 /* 1404 * page *might* contain residual mapping :-/ 1405 */ 1406 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1407 pmap_zero_page(m); 1408 --pmap->pm_stats.resident_count; 1409 1410 /* 1411 * This is a release store so that the ordinary store unmapping 1412 * the page table page is globally performed before TLB shoot- 1413 * down is begun. 1414 */ 1415 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1416 1417 /* 1418 * Do an invltlb to make the invalidated mapping 1419 * take effect immediately. 1420 */ 1421 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1422 pmap_invalidate_page(pmap, pteva); 1423 1424 /* 1425 * Put page on a list so that it is released after 1426 * *ALL* TLB shootdown is done 1427 */ 1428 m->right = *free; 1429 *free = m; 1430 1431 return 1; 1432} 1433 1434/* 1435 * After removing a page table entry, this routine is used to 1436 * conditionally free the page, and manage the hold/wire counts. 1437 */ 1438static int 1439pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1440{ 1441 pd_entry_t ptepde; 1442 vm_page_t mpte; 1443 1444 if (va >= VM_MAXUSER_ADDRESS) 1445 return 0; 1446 ptepde = PT_GET(pmap_pde(pmap, va)); 1447 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1448 return pmap_unwire_pte_hold(pmap, mpte, free); 1449} 1450 1451void 1452pmap_pinit0(pmap_t pmap) 1453{ 1454 1455 PMAP_LOCK_INIT(pmap); 1456 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1457#ifdef PAE 1458 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1459#endif 1460 CPU_ZERO(&pmap->pm_active); 1461 PCPU_SET(curpmap, pmap); 1462 TAILQ_INIT(&pmap->pm_pvchunk); 1463 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1464 mtx_lock_spin(&allpmaps_lock); 1465 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1466 mtx_unlock_spin(&allpmaps_lock); 1467} 1468 1469/* 1470 * Initialize a preallocated and zeroed pmap structure, 1471 * such as one in a vmspace structure. 1472 */ 1473int 1474pmap_pinit(pmap_t pmap) 1475{ 1476 vm_page_t m, ptdpg[NPGPTD + 1]; 1477 int npgptd = NPGPTD + 1; 1478 int i; 1479 1480#ifdef HAMFISTED_LOCKING 1481 mtx_lock(&createdelete_lock); 1482#endif 1483 1484 PMAP_LOCK_INIT(pmap); 1485 1486 /* 1487 * No need to allocate page table space yet but we do need a valid 1488 * page directory table. 1489 */ 1490 if (pmap->pm_pdir == NULL) { 1491 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1492 NBPTD); 1493 if (pmap->pm_pdir == NULL) { 1494 PMAP_LOCK_DESTROY(pmap); 1495#ifdef HAMFISTED_LOCKING 1496 mtx_unlock(&createdelete_lock); 1497#endif 1498 return (0); 1499 } 1500#ifdef PAE 1501 pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1502#endif 1503 } 1504 1505 /* 1506 * allocate the page directory page(s) 1507 */ 1508 for (i = 0; i < npgptd;) { 1509 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1510 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1511 if (m == NULL) 1512 VM_WAIT; 1513 else { 1514 ptdpg[i++] = m; 1515 } 1516 } 1517 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1518 for (i = 0; i < NPGPTD; i++) { 1519 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1520 pagezero(&pmap->pm_pdir[i*NPTEPG]); 1521 } 1522 1523 mtx_lock_spin(&allpmaps_lock); 1524 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1525 mtx_unlock_spin(&allpmaps_lock); 1526 /* Wire in kernel global address entries. */ 1527 1528 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1529#ifdef PAE 1530 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1531 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1532 bzero(pmap->pm_pdpt, PAGE_SIZE); 1533 for (i = 0; i < NPGPTD; i++) { 1534 vm_paddr_t ma; 1535 1536 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1537 pmap->pm_pdpt[i] = ma | PG_V; 1538 1539 } 1540#endif 1541 for (i = 0; i < NPGPTD; i++) { 1542 pt_entry_t *pd; 1543 vm_paddr_t ma; 1544 1545 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1546 pd = pmap->pm_pdir + (i * NPDEPG); 1547 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1548#if 0 1549 xen_pgd_pin(ma); 1550#endif 1551 } 1552 1553#ifdef PAE 1554 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1555#endif 1556 vm_page_lock_queues(); 1557 xen_flush_queue(); 1558 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1559 for (i = 0; i < NPGPTD; i++) { 1560 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1561 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1562 } 1563 xen_flush_queue(); 1564 vm_page_unlock_queues(); 1565 CPU_ZERO(&pmap->pm_active); 1566 TAILQ_INIT(&pmap->pm_pvchunk); 1567 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1568 1569#ifdef HAMFISTED_LOCKING 1570 mtx_unlock(&createdelete_lock); 1571#endif 1572 return (1); 1573} 1574 1575/* 1576 * this routine is called if the page table page is not 1577 * mapped correctly. 1578 */ 1579static vm_page_t 1580_pmap_allocpte(pmap_t pmap, unsigned int ptepindex, int flags) 1581{ 1582 vm_paddr_t ptema; 1583 vm_page_t m; 1584 1585 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1586 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1587 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1588 1589 /* 1590 * Allocate a page table page. 1591 */ 1592 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1593 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1594 if (flags & M_WAITOK) { 1595 PMAP_UNLOCK(pmap); 1596 vm_page_unlock_queues(); 1597 VM_WAIT; 1598 vm_page_lock_queues(); 1599 PMAP_LOCK(pmap); 1600 } 1601 1602 /* 1603 * Indicate the need to retry. While waiting, the page table 1604 * page may have been allocated. 1605 */ 1606 return (NULL); 1607 } 1608 if ((m->flags & PG_ZERO) == 0) 1609 pmap_zero_page(m); 1610 1611 /* 1612 * Map the pagetable page into the process address space, if 1613 * it isn't already there. 1614 */ 1615 pmap->pm_stats.resident_count++; 1616 1617 ptema = VM_PAGE_TO_MACH(m); 1618 xen_pt_pin(ptema); 1619 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1620 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1621 1622 KASSERT(pmap->pm_pdir[ptepindex], 1623 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1624 return (m); 1625} 1626 1627static vm_page_t 1628pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1629{ 1630 unsigned ptepindex; 1631 pd_entry_t ptema; 1632 vm_page_t m; 1633 1634 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1635 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1636 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1637 1638 /* 1639 * Calculate pagetable page index 1640 */ 1641 ptepindex = va >> PDRSHIFT; 1642retry: 1643 /* 1644 * Get the page directory entry 1645 */ 1646 ptema = pmap->pm_pdir[ptepindex]; 1647 1648 /* 1649 * This supports switching from a 4MB page to a 1650 * normal 4K page. 1651 */ 1652 if (ptema & PG_PS) { 1653 /* 1654 * XXX 1655 */ 1656 pmap->pm_pdir[ptepindex] = 0; 1657 ptema = 0; 1658 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1659 pmap_invalidate_all(kernel_pmap); 1660 } 1661 1662 /* 1663 * If the page table page is mapped, we just increment the 1664 * hold count, and activate it. 1665 */ 1666 if (ptema & PG_V) { 1667 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1668 m->wire_count++; 1669 } else { 1670 /* 1671 * Here if the pte page isn't mapped, or if it has 1672 * been deallocated. 1673 */ 1674 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1675 pmap, va, flags); 1676 m = _pmap_allocpte(pmap, ptepindex, flags); 1677 if (m == NULL && (flags & M_WAITOK)) 1678 goto retry; 1679 1680 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1681 } 1682 return (m); 1683} 1684 1685 1686/*************************************************** 1687* Pmap allocation/deallocation routines. 1688 ***************************************************/ 1689 1690#ifdef SMP 1691/* 1692 * Deal with a SMP shootdown of other users of the pmap that we are 1693 * trying to dispose of. This can be a bit hairy. 1694 */ 1695static cpuset_t *lazymask; 1696static u_int lazyptd; 1697static volatile u_int lazywait; 1698 1699void pmap_lazyfix_action(void); 1700 1701void 1702pmap_lazyfix_action(void) 1703{ 1704 1705#ifdef COUNT_IPIS 1706 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1707#endif 1708 if (rcr3() == lazyptd) 1709 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1710 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1711 atomic_store_rel_int(&lazywait, 1); 1712} 1713 1714static void 1715pmap_lazyfix_self(u_int cpuid) 1716{ 1717 1718 if (rcr3() == lazyptd) 1719 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1720 CPU_CLR_ATOMIC(cpuid, lazymask); 1721} 1722 1723 1724static void 1725pmap_lazyfix(pmap_t pmap) 1726{ 1727 cpuset_t mymask, mask; 1728 u_int cpuid, spins; 1729 int lsb; 1730 1731 mask = pmap->pm_active; 1732 while (!CPU_EMPTY(&mask)) { 1733 spins = 50000000; 1734 1735 /* Find least significant set bit. */ 1736 lsb = cpusetobj_ffs(&mask); 1737 MPASS(lsb != 0); 1738 lsb--; 1739 CPU_SETOF(lsb, &mask); 1740 mtx_lock_spin(&smp_ipi_mtx); 1741#ifdef PAE 1742 lazyptd = vtophys(pmap->pm_pdpt); 1743#else 1744 lazyptd = vtophys(pmap->pm_pdir); 1745#endif 1746 cpuid = PCPU_GET(cpuid); 1747 1748 /* Use a cpuset just for having an easy check. */ 1749 CPU_SETOF(cpuid, &mymask); 1750 if (!CPU_CMP(&mask, &mymask)) { 1751 lazymask = &pmap->pm_active; 1752 pmap_lazyfix_self(cpuid); 1753 } else { 1754 atomic_store_rel_int((u_int *)&lazymask, 1755 (u_int)&pmap->pm_active); 1756 atomic_store_rel_int(&lazywait, 0); 1757 ipi_selected(mask, IPI_LAZYPMAP); 1758 while (lazywait == 0) { 1759 ia32_pause(); 1760 if (--spins == 0) 1761 break; 1762 } 1763 } 1764 mtx_unlock_spin(&smp_ipi_mtx); 1765 if (spins == 0) 1766 printf("pmap_lazyfix: spun for 50000000\n"); 1767 mask = pmap->pm_active; 1768 } 1769} 1770 1771#else /* SMP */ 1772 1773/* 1774 * Cleaning up on uniprocessor is easy. For various reasons, we're 1775 * unlikely to have to even execute this code, including the fact 1776 * that the cleanup is deferred until the parent does a wait(2), which 1777 * means that another userland process has run. 1778 */ 1779static void 1780pmap_lazyfix(pmap_t pmap) 1781{ 1782 u_int cr3; 1783 1784 cr3 = vtophys(pmap->pm_pdir); 1785 if (cr3 == rcr3()) { 1786 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1787 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 1788 } 1789} 1790#endif /* SMP */ 1791 1792/* 1793 * Release any resources held by the given physical map. 1794 * Called when a pmap initialized by pmap_pinit is being released. 1795 * Should only be called if the map contains no valid mappings. 1796 */ 1797void 1798pmap_release(pmap_t pmap) 1799{ 1800 vm_page_t m, ptdpg[2*NPGPTD+1]; 1801 vm_paddr_t ma; 1802 int i; 1803#ifdef PAE 1804 int npgptd = NPGPTD + 1; 1805#else 1806 int npgptd = NPGPTD; 1807#endif 1808 KASSERT(pmap->pm_stats.resident_count == 0, 1809 ("pmap_release: pmap resident count %ld != 0", 1810 pmap->pm_stats.resident_count)); 1811 PT_UPDATES_FLUSH(); 1812 1813#ifdef HAMFISTED_LOCKING 1814 mtx_lock(&createdelete_lock); 1815#endif 1816 1817 pmap_lazyfix(pmap); 1818 mtx_lock_spin(&allpmaps_lock); 1819 LIST_REMOVE(pmap, pm_list); 1820 mtx_unlock_spin(&allpmaps_lock); 1821 1822 for (i = 0; i < NPGPTD; i++) 1823 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1824 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1825#ifdef PAE 1826 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1827#endif 1828 1829 for (i = 0; i < npgptd; i++) { 1830 m = ptdpg[i]; 1831 ma = VM_PAGE_TO_MACH(m); 1832 /* unpinning L1 and L2 treated the same */ 1833#if 0 1834 xen_pgd_unpin(ma); 1835#else 1836 if (i == NPGPTD) 1837 xen_pgd_unpin(ma); 1838#endif 1839#ifdef PAE 1840 if (i < NPGPTD) 1841 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1842 ("pmap_release: got wrong ptd page")); 1843#endif 1844 m->wire_count--; 1845 atomic_subtract_int(&cnt.v_wire_count, 1); 1846 vm_page_free(m); 1847 } 1848#ifdef PAE 1849 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1850#endif 1851 PMAP_LOCK_DESTROY(pmap); 1852 1853#ifdef HAMFISTED_LOCKING 1854 mtx_unlock(&createdelete_lock); 1855#endif 1856} 1857 1858static int 1859kvm_size(SYSCTL_HANDLER_ARGS) 1860{ 1861 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1862 1863 return sysctl_handle_long(oidp, &ksize, 0, req); 1864} 1865SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1866 0, 0, kvm_size, "IU", "Size of KVM"); 1867 1868static int 1869kvm_free(SYSCTL_HANDLER_ARGS) 1870{ 1871 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1872 1873 return sysctl_handle_long(oidp, &kfree, 0, req); 1874} 1875SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1876 0, 0, kvm_free, "IU", "Amount of KVM free"); 1877 1878/* 1879 * grow the number of kernel page table entries, if needed 1880 */ 1881void 1882pmap_growkernel(vm_offset_t addr) 1883{ 1884 struct pmap *pmap; 1885 vm_paddr_t ptppaddr; 1886 vm_page_t nkpg; 1887 pd_entry_t newpdir; 1888 1889 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1890 if (kernel_vm_end == 0) { 1891 kernel_vm_end = KERNBASE; 1892 nkpt = 0; 1893 while (pdir_pde(PTD, kernel_vm_end)) { 1894 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1895 nkpt++; 1896 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1897 kernel_vm_end = kernel_map->max_offset; 1898 break; 1899 } 1900 } 1901 } 1902 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1903 if (addr - 1 >= kernel_map->max_offset) 1904 addr = kernel_map->max_offset; 1905 while (kernel_vm_end < addr) { 1906 if (pdir_pde(PTD, kernel_vm_end)) { 1907 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1908 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1909 kernel_vm_end = kernel_map->max_offset; 1910 break; 1911 } 1912 continue; 1913 } 1914 1915 /* 1916 * This index is bogus, but out of the way 1917 */ 1918 nkpg = vm_page_alloc(NULL, nkpt, 1919 VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED); 1920 if (!nkpg) 1921 panic("pmap_growkernel: no memory to grow kernel"); 1922 1923 nkpt++; 1924 1925 pmap_zero_page(nkpg); 1926 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1927 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1928 vm_page_lock_queues(); 1929 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1930 mtx_lock_spin(&allpmaps_lock); 1931 LIST_FOREACH(pmap, &allpmaps, pm_list) 1932 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1933 1934 mtx_unlock_spin(&allpmaps_lock); 1935 vm_page_unlock_queues(); 1936 1937 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1938 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1939 kernel_vm_end = kernel_map->max_offset; 1940 break; 1941 } 1942 } 1943} 1944 1945 1946/*************************************************** 1947 * page management routines. 1948 ***************************************************/ 1949 1950CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1951CTASSERT(_NPCM == 11); 1952 1953static __inline struct pv_chunk * 1954pv_to_chunk(pv_entry_t pv) 1955{ 1956 1957 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1958} 1959 1960#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1961 1962#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1963#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1964 1965static uint32_t pc_freemask[11] = { 1966 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1967 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1968 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1969 PC_FREE0_9, PC_FREE10 1970}; 1971 1972SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1973 "Current number of pv entries"); 1974 1975#ifdef PV_STATS 1976static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1977 1978SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1979 "Current number of pv entry chunks"); 1980SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1981 "Current number of pv entry chunks allocated"); 1982SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1983 "Current number of pv entry chunks frees"); 1984SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1985 "Number of times tried to get a chunk page but failed."); 1986 1987static long pv_entry_frees, pv_entry_allocs; 1988static int pv_entry_spare; 1989 1990SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1991 "Current number of pv entry frees"); 1992SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1993 "Current number of pv entry allocs"); 1994SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1995 "Current number of spare pv entries"); 1996 1997static int pmap_collect_inactive, pmap_collect_active; 1998 1999SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 2000 "Current number times pmap_collect called on inactive queue"); 2001SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 2002 "Current number times pmap_collect called on active queue"); 2003#endif 2004 2005/* 2006 * We are in a serious low memory condition. Resort to 2007 * drastic measures to free some pages so we can allocate 2008 * another pv entry chunk. This is normally called to 2009 * unmap inactive pages, and if necessary, active pages. 2010 */ 2011static void 2012pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 2013{ 2014 pmap_t pmap; 2015 pt_entry_t *pte, tpte; 2016 pv_entry_t next_pv, pv; 2017 vm_offset_t va; 2018 vm_page_t m, free; 2019 2020 sched_pin(); 2021 TAILQ_FOREACH(m, &vpq->pl, pageq) { 2022 if ((m->flags & PG_MARKER) != 0 || m->hold_count || m->busy) 2023 continue; 2024 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 2025 va = pv->pv_va; 2026 pmap = PV_PMAP(pv); 2027 /* Avoid deadlock and lock recursion. */ 2028 if (pmap > locked_pmap) 2029 PMAP_LOCK(pmap); 2030 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 2031 continue; 2032 pmap->pm_stats.resident_count--; 2033 pte = pmap_pte_quick(pmap, va); 2034 tpte = pte_load_clear(pte); 2035 KASSERT((tpte & PG_W) == 0, 2036 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2037 if (tpte & PG_A) 2038 vm_page_aflag_set(m, PGA_REFERENCED); 2039 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2040 vm_page_dirty(m); 2041 free = NULL; 2042 pmap_unuse_pt(pmap, va, &free); 2043 pmap_invalidate_page(pmap, va); 2044 pmap_free_zero_pages(free); 2045 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2046 free_pv_entry(pmap, pv); 2047 if (pmap != locked_pmap) 2048 PMAP_UNLOCK(pmap); 2049 } 2050 if (TAILQ_EMPTY(&m->md.pv_list)) 2051 vm_page_aflag_clear(m, PGA_WRITEABLE); 2052 } 2053 sched_unpin(); 2054} 2055 2056 2057/* 2058 * free the pv_entry back to the free list 2059 */ 2060static void 2061free_pv_entry(pmap_t pmap, pv_entry_t pv) 2062{ 2063 vm_page_t m; 2064 struct pv_chunk *pc; 2065 int idx, field, bit; 2066 2067 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2068 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2069 PV_STAT(pv_entry_frees++); 2070 PV_STAT(pv_entry_spare++); 2071 pv_entry_count--; 2072 pc = pv_to_chunk(pv); 2073 idx = pv - &pc->pc_pventry[0]; 2074 field = idx / 32; 2075 bit = idx % 32; 2076 pc->pc_map[field] |= 1ul << bit; 2077 /* move to head of list */ 2078 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2079 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2080 for (idx = 0; idx < _NPCM; idx++) 2081 if (pc->pc_map[idx] != pc_freemask[idx]) 2082 return; 2083 PV_STAT(pv_entry_spare -= _NPCPV); 2084 PV_STAT(pc_chunk_count--); 2085 PV_STAT(pc_chunk_frees++); 2086 /* entire chunk is free, return it */ 2087 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2088 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2089 pmap_qremove((vm_offset_t)pc, 1); 2090 vm_page_unwire(m, 0); 2091 vm_page_free(m); 2092 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2093} 2094 2095/* 2096 * get a new pv_entry, allocating a block from the system 2097 * when needed. 2098 */ 2099static pv_entry_t 2100get_pv_entry(pmap_t pmap, int try) 2101{ 2102 static const struct timeval printinterval = { 60, 0 }; 2103 static struct timeval lastprint; 2104 struct vpgqueues *pq; 2105 int bit, field; 2106 pv_entry_t pv; 2107 struct pv_chunk *pc; 2108 vm_page_t m; 2109 2110 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2111 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2112 PV_STAT(pv_entry_allocs++); 2113 pv_entry_count++; 2114 if (pv_entry_count > pv_entry_high_water) 2115 if (ratecheck(&lastprint, &printinterval)) 2116 printf("Approaching the limit on PV entries, consider " 2117 "increasing either the vm.pmap.shpgperproc or the " 2118 "vm.pmap.pv_entry_max tunable.\n"); 2119 pq = NULL; 2120retry: 2121 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2122 if (pc != NULL) { 2123 for (field = 0; field < _NPCM; field++) { 2124 if (pc->pc_map[field]) { 2125 bit = bsfl(pc->pc_map[field]); 2126 break; 2127 } 2128 } 2129 if (field < _NPCM) { 2130 pv = &pc->pc_pventry[field * 32 + bit]; 2131 pc->pc_map[field] &= ~(1ul << bit); 2132 /* If this was the last item, move it to tail */ 2133 for (field = 0; field < _NPCM; field++) 2134 if (pc->pc_map[field] != 0) { 2135 PV_STAT(pv_entry_spare--); 2136 return (pv); /* not full, return */ 2137 } 2138 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2139 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2140 PV_STAT(pv_entry_spare--); 2141 return (pv); 2142 } 2143 } 2144 /* 2145 * Access to the ptelist "pv_vafree" is synchronized by the page 2146 * queues lock. If "pv_vafree" is currently non-empty, it will 2147 * remain non-empty until pmap_ptelist_alloc() completes. 2148 */ 2149 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, (pq == 2150 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2151 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2152 if (try) { 2153 pv_entry_count--; 2154 PV_STAT(pc_chunk_tryfail++); 2155 return (NULL); 2156 } 2157 /* 2158 * Reclaim pv entries: At first, destroy mappings to 2159 * inactive pages. After that, if a pv chunk entry 2160 * is still needed, destroy mappings to active pages. 2161 */ 2162 if (pq == NULL) { 2163 PV_STAT(pmap_collect_inactive++); 2164 pq = &vm_page_queues[PQ_INACTIVE]; 2165 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2166 PV_STAT(pmap_collect_active++); 2167 pq = &vm_page_queues[PQ_ACTIVE]; 2168 } else 2169 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2170 pmap_collect(pmap, pq); 2171 goto retry; 2172 } 2173 PV_STAT(pc_chunk_count++); 2174 PV_STAT(pc_chunk_allocs++); 2175 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2176 pmap_qenter((vm_offset_t)pc, &m, 1); 2177 if ((m->flags & PG_ZERO) == 0) 2178 pagezero(pc); 2179 pc->pc_pmap = pmap; 2180 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2181 for (field = 1; field < _NPCM; field++) 2182 pc->pc_map[field] = pc_freemask[field]; 2183 pv = &pc->pc_pventry[0]; 2184 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2185 PV_STAT(pv_entry_spare += _NPCPV - 1); 2186 return (pv); 2187} 2188 2189static __inline pv_entry_t 2190pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2191{ 2192 pv_entry_t pv; 2193 2194 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2195 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2196 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2197 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2198 break; 2199 } 2200 } 2201 return (pv); 2202} 2203 2204static void 2205pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2206{ 2207 pv_entry_t pv; 2208 2209 pv = pmap_pvh_remove(pvh, pmap, va); 2210 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2211 free_pv_entry(pmap, pv); 2212} 2213 2214static void 2215pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2216{ 2217 2218 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2219 pmap_pvh_free(&m->md, pmap, va); 2220 if (TAILQ_EMPTY(&m->md.pv_list)) 2221 vm_page_aflag_clear(m, PGA_WRITEABLE); 2222} 2223 2224/* 2225 * Conditionally create a pv entry. 2226 */ 2227static boolean_t 2228pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2229{ 2230 pv_entry_t pv; 2231 2232 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2233 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2234 if (pv_entry_count < pv_entry_high_water && 2235 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2236 pv->pv_va = va; 2237 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2238 return (TRUE); 2239 } else 2240 return (FALSE); 2241} 2242 2243/* 2244 * pmap_remove_pte: do the things to unmap a page in a process 2245 */ 2246static int 2247pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2248{ 2249 pt_entry_t oldpte; 2250 vm_page_t m; 2251 2252 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2253 pmap, (u_long)*ptq, va); 2254 2255 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2256 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2257 oldpte = *ptq; 2258 PT_SET_VA_MA(ptq, 0, TRUE); 2259 if (oldpte & PG_W) 2260 pmap->pm_stats.wired_count -= 1; 2261 /* 2262 * Machines that don't support invlpg, also don't support 2263 * PG_G. 2264 */ 2265 if (oldpte & PG_G) 2266 pmap_invalidate_page(kernel_pmap, va); 2267 pmap->pm_stats.resident_count -= 1; 2268 if (oldpte & PG_MANAGED) { 2269 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2270 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2271 vm_page_dirty(m); 2272 if (oldpte & PG_A) 2273 vm_page_aflag_set(m, PGA_REFERENCED); 2274 pmap_remove_entry(pmap, m, va); 2275 } 2276 return (pmap_unuse_pt(pmap, va, free)); 2277} 2278 2279/* 2280 * Remove a single page from a process address space 2281 */ 2282static void 2283pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2284{ 2285 pt_entry_t *pte; 2286 2287 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2288 pmap, va); 2289 2290 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2291 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2292 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2293 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2294 return; 2295 pmap_remove_pte(pmap, pte, va, free); 2296 pmap_invalidate_page(pmap, va); 2297 if (*PMAP1) 2298 PT_SET_MA(PADDR1, 0); 2299 2300} 2301 2302/* 2303 * Remove the given range of addresses from the specified map. 2304 * 2305 * It is assumed that the start and end are properly 2306 * rounded to the page size. 2307 */ 2308void 2309pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2310{ 2311 vm_offset_t pdnxt; 2312 pd_entry_t ptpaddr; 2313 pt_entry_t *pte; 2314 vm_page_t free = NULL; 2315 int anyvalid; 2316 2317 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2318 pmap, sva, eva); 2319 2320 /* 2321 * Perform an unsynchronized read. This is, however, safe. 2322 */ 2323 if (pmap->pm_stats.resident_count == 0) 2324 return; 2325 2326 anyvalid = 0; 2327 2328 vm_page_lock_queues(); 2329 sched_pin(); 2330 PMAP_LOCK(pmap); 2331 2332 /* 2333 * special handling of removing one page. a very 2334 * common operation and easy to short circuit some 2335 * code. 2336 */ 2337 if ((sva + PAGE_SIZE == eva) && 2338 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2339 pmap_remove_page(pmap, sva, &free); 2340 goto out; 2341 } 2342 2343 for (; sva < eva; sva = pdnxt) { 2344 unsigned pdirindex; 2345 2346 /* 2347 * Calculate index for next page table. 2348 */ 2349 pdnxt = (sva + NBPDR) & ~PDRMASK; 2350 if (pmap->pm_stats.resident_count == 0) 2351 break; 2352 2353 pdirindex = sva >> PDRSHIFT; 2354 ptpaddr = pmap->pm_pdir[pdirindex]; 2355 2356 /* 2357 * Weed out invalid mappings. Note: we assume that the page 2358 * directory table is always allocated, and in kernel virtual. 2359 */ 2360 if (ptpaddr == 0) 2361 continue; 2362 2363 /* 2364 * Check for large page. 2365 */ 2366 if ((ptpaddr & PG_PS) != 0) { 2367 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2368 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2369 anyvalid = 1; 2370 continue; 2371 } 2372 2373 /* 2374 * Limit our scan to either the end of the va represented 2375 * by the current page table page, or to the end of the 2376 * range being removed. 2377 */ 2378 if (pdnxt > eva) 2379 pdnxt = eva; 2380 2381 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2382 sva += PAGE_SIZE) { 2383 if ((*pte & PG_V) == 0) 2384 continue; 2385 2386 /* 2387 * The TLB entry for a PG_G mapping is invalidated 2388 * by pmap_remove_pte(). 2389 */ 2390 if ((*pte & PG_G) == 0) 2391 anyvalid = 1; 2392 if (pmap_remove_pte(pmap, pte, sva, &free)) 2393 break; 2394 } 2395 } 2396 PT_UPDATES_FLUSH(); 2397 if (*PMAP1) 2398 PT_SET_VA_MA(PMAP1, 0, TRUE); 2399out: 2400 if (anyvalid) 2401 pmap_invalidate_all(pmap); 2402 sched_unpin(); 2403 vm_page_unlock_queues(); 2404 PMAP_UNLOCK(pmap); 2405 pmap_free_zero_pages(free); 2406} 2407 2408/* 2409 * Routine: pmap_remove_all 2410 * Function: 2411 * Removes this physical page from 2412 * all physical maps in which it resides. 2413 * Reflects back modify bits to the pager. 2414 * 2415 * Notes: 2416 * Original versions of this routine were very 2417 * inefficient because they iteratively called 2418 * pmap_remove (slow...) 2419 */ 2420 2421void 2422pmap_remove_all(vm_page_t m) 2423{ 2424 pv_entry_t pv; 2425 pmap_t pmap; 2426 pt_entry_t *pte, tpte; 2427 vm_page_t free; 2428 2429 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2430 ("pmap_remove_all: page %p is not managed", m)); 2431 free = NULL; 2432 vm_page_lock_queues(); 2433 sched_pin(); 2434 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2435 pmap = PV_PMAP(pv); 2436 PMAP_LOCK(pmap); 2437 pmap->pm_stats.resident_count--; 2438 pte = pmap_pte_quick(pmap, pv->pv_va); 2439 2440 tpte = *pte; 2441 PT_SET_VA_MA(pte, 0, TRUE); 2442 if (tpte & PG_W) 2443 pmap->pm_stats.wired_count--; 2444 if (tpte & PG_A) 2445 vm_page_aflag_set(m, PGA_REFERENCED); 2446 2447 /* 2448 * Update the vm_page_t clean and reference bits. 2449 */ 2450 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2451 vm_page_dirty(m); 2452 pmap_unuse_pt(pmap, pv->pv_va, &free); 2453 pmap_invalidate_page(pmap, pv->pv_va); 2454 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2455 free_pv_entry(pmap, pv); 2456 PMAP_UNLOCK(pmap); 2457 } 2458 vm_page_aflag_clear(m, PGA_WRITEABLE); 2459 PT_UPDATES_FLUSH(); 2460 if (*PMAP1) 2461 PT_SET_MA(PADDR1, 0); 2462 sched_unpin(); 2463 vm_page_unlock_queues(); 2464 pmap_free_zero_pages(free); 2465} 2466 2467/* 2468 * Set the physical protection on the 2469 * specified range of this map as requested. 2470 */ 2471void 2472pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2473{ 2474 vm_offset_t pdnxt; 2475 pd_entry_t ptpaddr; 2476 pt_entry_t *pte; 2477 int anychanged; 2478 2479 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2480 pmap, sva, eva, prot); 2481 2482 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2483 pmap_remove(pmap, sva, eva); 2484 return; 2485 } 2486 2487#ifdef PAE 2488 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2489 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2490 return; 2491#else 2492 if (prot & VM_PROT_WRITE) 2493 return; 2494#endif 2495 2496 anychanged = 0; 2497 2498 vm_page_lock_queues(); 2499 sched_pin(); 2500 PMAP_LOCK(pmap); 2501 for (; sva < eva; sva = pdnxt) { 2502 pt_entry_t obits, pbits; 2503 unsigned pdirindex; 2504 2505 pdnxt = (sva + NBPDR) & ~PDRMASK; 2506 2507 pdirindex = sva >> PDRSHIFT; 2508 ptpaddr = pmap->pm_pdir[pdirindex]; 2509 2510 /* 2511 * Weed out invalid mappings. Note: we assume that the page 2512 * directory table is always allocated, and in kernel virtual. 2513 */ 2514 if (ptpaddr == 0) 2515 continue; 2516 2517 /* 2518 * Check for large page. 2519 */ 2520 if ((ptpaddr & PG_PS) != 0) { 2521 if ((prot & VM_PROT_WRITE) == 0) 2522 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2523#ifdef PAE 2524 if ((prot & VM_PROT_EXECUTE) == 0) 2525 pmap->pm_pdir[pdirindex] |= pg_nx; 2526#endif 2527 anychanged = 1; 2528 continue; 2529 } 2530 2531 if (pdnxt > eva) 2532 pdnxt = eva; 2533 2534 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2535 sva += PAGE_SIZE) { 2536 vm_page_t m; 2537 2538retry: 2539 /* 2540 * Regardless of whether a pte is 32 or 64 bits in 2541 * size, PG_RW, PG_A, and PG_M are among the least 2542 * significant 32 bits. 2543 */ 2544 obits = pbits = *pte; 2545 if ((pbits & PG_V) == 0) 2546 continue; 2547 2548 if ((prot & VM_PROT_WRITE) == 0) { 2549 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2550 (PG_MANAGED | PG_M | PG_RW)) { 2551 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2552 PG_FRAME); 2553 vm_page_dirty(m); 2554 } 2555 pbits &= ~(PG_RW | PG_M); 2556 } 2557#ifdef PAE 2558 if ((prot & VM_PROT_EXECUTE) == 0) 2559 pbits |= pg_nx; 2560#endif 2561 2562 if (pbits != obits) { 2563 obits = *pte; 2564 PT_SET_VA_MA(pte, pbits, TRUE); 2565 if (*pte != pbits) 2566 goto retry; 2567 if (obits & PG_G) 2568 pmap_invalidate_page(pmap, sva); 2569 else 2570 anychanged = 1; 2571 } 2572 } 2573 } 2574 PT_UPDATES_FLUSH(); 2575 if (*PMAP1) 2576 PT_SET_VA_MA(PMAP1, 0, TRUE); 2577 if (anychanged) 2578 pmap_invalidate_all(pmap); 2579 sched_unpin(); 2580 vm_page_unlock_queues(); 2581 PMAP_UNLOCK(pmap); 2582} 2583 2584/* 2585 * Insert the given physical page (p) at 2586 * the specified virtual address (v) in the 2587 * target physical map with the protection requested. 2588 * 2589 * If specified, the page will be wired down, meaning 2590 * that the related pte can not be reclaimed. 2591 * 2592 * NB: This is the only routine which MAY NOT lazy-evaluate 2593 * or lose information. That is, this routine must actually 2594 * insert this page into the given map NOW. 2595 */ 2596void 2597pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2598 vm_prot_t prot, boolean_t wired) 2599{ 2600 pd_entry_t *pde; 2601 pt_entry_t *pte; 2602 pt_entry_t newpte, origpte; 2603 pv_entry_t pv; 2604 vm_paddr_t opa, pa; 2605 vm_page_t mpte, om; 2606 boolean_t invlva; 2607 2608 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2609 pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2610 va = trunc_page(va); 2611 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2612 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2613 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2614 va)); 2615 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0, 2616 ("pmap_enter: page %p is not busy", m)); 2617 2618 mpte = NULL; 2619 2620 vm_page_lock_queues(); 2621 PMAP_LOCK(pmap); 2622 sched_pin(); 2623 2624 /* 2625 * In the case that a page table page is not 2626 * resident, we are creating it here. 2627 */ 2628 if (va < VM_MAXUSER_ADDRESS) { 2629 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2630 } 2631 2632 pde = pmap_pde(pmap, va); 2633 if ((*pde & PG_PS) != 0) 2634 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2635 pte = pmap_pte_quick(pmap, va); 2636 2637 /* 2638 * Page Directory table entry not valid, we need a new PT page 2639 */ 2640 if (pte == NULL) { 2641 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2642 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2643 } 2644 2645 pa = VM_PAGE_TO_PHYS(m); 2646 om = NULL; 2647 opa = origpte = 0; 2648 2649#if 0 2650 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2651 pte, *pte)); 2652#endif 2653 origpte = *pte; 2654 if (origpte) 2655 origpte = xpmap_mtop(origpte); 2656 opa = origpte & PG_FRAME; 2657 2658 /* 2659 * Mapping has not changed, must be protection or wiring change. 2660 */ 2661 if (origpte && (opa == pa)) { 2662 /* 2663 * Wiring change, just update stats. We don't worry about 2664 * wiring PT pages as they remain resident as long as there 2665 * are valid mappings in them. Hence, if a user page is wired, 2666 * the PT page will be also. 2667 */ 2668 if (wired && ((origpte & PG_W) == 0)) 2669 pmap->pm_stats.wired_count++; 2670 else if (!wired && (origpte & PG_W)) 2671 pmap->pm_stats.wired_count--; 2672 2673 /* 2674 * Remove extra pte reference 2675 */ 2676 if (mpte) 2677 mpte->wire_count--; 2678 2679 if (origpte & PG_MANAGED) { 2680 om = m; 2681 pa |= PG_MANAGED; 2682 } 2683 goto validate; 2684 } 2685 2686 pv = NULL; 2687 2688 /* 2689 * Mapping has changed, invalidate old range and fall through to 2690 * handle validating new mapping. 2691 */ 2692 if (opa) { 2693 if (origpte & PG_W) 2694 pmap->pm_stats.wired_count--; 2695 if (origpte & PG_MANAGED) { 2696 om = PHYS_TO_VM_PAGE(opa); 2697 pv = pmap_pvh_remove(&om->md, pmap, va); 2698 } else if (va < VM_MAXUSER_ADDRESS) 2699 printf("va=0x%x is unmanaged :-( \n", va); 2700 2701 if (mpte != NULL) { 2702 mpte->wire_count--; 2703 KASSERT(mpte->wire_count > 0, 2704 ("pmap_enter: missing reference to page table page," 2705 " va: 0x%x", va)); 2706 } 2707 } else 2708 pmap->pm_stats.resident_count++; 2709 2710 /* 2711 * Enter on the PV list if part of our managed memory. 2712 */ 2713 if ((m->oflags & VPO_UNMANAGED) == 0) { 2714 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2715 ("pmap_enter: managed mapping within the clean submap")); 2716 if (pv == NULL) 2717 pv = get_pv_entry(pmap, FALSE); 2718 pv->pv_va = va; 2719 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2720 pa |= PG_MANAGED; 2721 } else if (pv != NULL) 2722 free_pv_entry(pmap, pv); 2723 2724 /* 2725 * Increment counters 2726 */ 2727 if (wired) 2728 pmap->pm_stats.wired_count++; 2729 2730validate: 2731 /* 2732 * Now validate mapping with desired protection/wiring. 2733 */ 2734 newpte = (pt_entry_t)(pa | PG_V); 2735 if ((prot & VM_PROT_WRITE) != 0) { 2736 newpte |= PG_RW; 2737 if ((newpte & PG_MANAGED) != 0) 2738 vm_page_aflag_set(m, PGA_WRITEABLE); 2739 } 2740#ifdef PAE 2741 if ((prot & VM_PROT_EXECUTE) == 0) 2742 newpte |= pg_nx; 2743#endif 2744 if (wired) 2745 newpte |= PG_W; 2746 if (va < VM_MAXUSER_ADDRESS) 2747 newpte |= PG_U; 2748 if (pmap == kernel_pmap) 2749 newpte |= pgeflag; 2750 2751 critical_enter(); 2752 /* 2753 * if the mapping or permission bits are different, we need 2754 * to update the pte. 2755 */ 2756 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2757 if (origpte) { 2758 invlva = FALSE; 2759 origpte = *pte; 2760 PT_SET_VA(pte, newpte | PG_A, FALSE); 2761 if (origpte & PG_A) { 2762 if (origpte & PG_MANAGED) 2763 vm_page_aflag_set(om, PGA_REFERENCED); 2764 if (opa != VM_PAGE_TO_PHYS(m)) 2765 invlva = TRUE; 2766#ifdef PAE 2767 if ((origpte & PG_NX) == 0 && 2768 (newpte & PG_NX) != 0) 2769 invlva = TRUE; 2770#endif 2771 } 2772 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2773 if ((origpte & PG_MANAGED) != 0) 2774 vm_page_dirty(om); 2775 if ((prot & VM_PROT_WRITE) == 0) 2776 invlva = TRUE; 2777 } 2778 if ((origpte & PG_MANAGED) != 0 && 2779 TAILQ_EMPTY(&om->md.pv_list)) 2780 vm_page_aflag_clear(om, PGA_WRITEABLE); 2781 if (invlva) 2782 pmap_invalidate_page(pmap, va); 2783 } else{ 2784 PT_SET_VA(pte, newpte | PG_A, FALSE); 2785 } 2786 2787 } 2788 PT_UPDATES_FLUSH(); 2789 critical_exit(); 2790 if (*PMAP1) 2791 PT_SET_VA_MA(PMAP1, 0, TRUE); 2792 sched_unpin(); 2793 vm_page_unlock_queues(); 2794 PMAP_UNLOCK(pmap); 2795} 2796 2797/* 2798 * Maps a sequence of resident pages belonging to the same object. 2799 * The sequence begins with the given page m_start. This page is 2800 * mapped at the given virtual address start. Each subsequent page is 2801 * mapped at a virtual address that is offset from start by the same 2802 * amount as the page is offset from m_start within the object. The 2803 * last page in the sequence is the page with the largest offset from 2804 * m_start that can be mapped at a virtual address less than the given 2805 * virtual address end. Not every virtual page between start and end 2806 * is mapped; only those for which a resident page exists with the 2807 * corresponding offset from m_start are mapped. 2808 */ 2809void 2810pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2811 vm_page_t m_start, vm_prot_t prot) 2812{ 2813 vm_page_t m, mpte; 2814 vm_pindex_t diff, psize; 2815 multicall_entry_t mcl[16]; 2816 multicall_entry_t *mclp = mcl; 2817 int error, count = 0; 2818 2819 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2820 psize = atop(end - start); 2821 2822 mpte = NULL; 2823 m = m_start; 2824 vm_page_lock_queues(); 2825 PMAP_LOCK(pmap); 2826 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2827 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2828 prot, mpte); 2829 m = TAILQ_NEXT(m, listq); 2830 if (count == 16) { 2831 error = HYPERVISOR_multicall(mcl, count); 2832 KASSERT(error == 0, ("bad multicall %d", error)); 2833 mclp = mcl; 2834 count = 0; 2835 } 2836 } 2837 if (count) { 2838 error = HYPERVISOR_multicall(mcl, count); 2839 KASSERT(error == 0, ("bad multicall %d", error)); 2840 } 2841 vm_page_unlock_queues(); 2842 PMAP_UNLOCK(pmap); 2843} 2844 2845/* 2846 * this code makes some *MAJOR* assumptions: 2847 * 1. Current pmap & pmap exists. 2848 * 2. Not wired. 2849 * 3. Read access. 2850 * 4. No page table pages. 2851 * but is *MUCH* faster than pmap_enter... 2852 */ 2853 2854void 2855pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2856{ 2857 multicall_entry_t mcl, *mclp; 2858 int count = 0; 2859 mclp = &mcl; 2860 2861 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2862 pmap, va, m, prot); 2863 2864 vm_page_lock_queues(); 2865 PMAP_LOCK(pmap); 2866 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2867 if (count) 2868 HYPERVISOR_multicall(&mcl, count); 2869 vm_page_unlock_queues(); 2870 PMAP_UNLOCK(pmap); 2871} 2872 2873#ifdef notyet 2874void 2875pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2876{ 2877 int i, error, index = 0; 2878 multicall_entry_t mcl[16]; 2879 multicall_entry_t *mclp = mcl; 2880 2881 PMAP_LOCK(pmap); 2882 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2883 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2884 continue; 2885 2886 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2887 if (index == 16) { 2888 error = HYPERVISOR_multicall(mcl, index); 2889 mclp = mcl; 2890 index = 0; 2891 KASSERT(error == 0, ("bad multicall %d", error)); 2892 } 2893 } 2894 if (index) { 2895 error = HYPERVISOR_multicall(mcl, index); 2896 KASSERT(error == 0, ("bad multicall %d", error)); 2897 } 2898 2899 PMAP_UNLOCK(pmap); 2900} 2901#endif 2902 2903static vm_page_t 2904pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2905 vm_prot_t prot, vm_page_t mpte) 2906{ 2907 pt_entry_t *pte; 2908 vm_paddr_t pa; 2909 vm_page_t free; 2910 multicall_entry_t *mcl = *mclpp; 2911 2912 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2913 (m->oflags & VPO_UNMANAGED) != 0, 2914 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2915 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2916 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2917 2918 /* 2919 * In the case that a page table page is not 2920 * resident, we are creating it here. 2921 */ 2922 if (va < VM_MAXUSER_ADDRESS) { 2923 unsigned ptepindex; 2924 pd_entry_t ptema; 2925 2926 /* 2927 * Calculate pagetable page index 2928 */ 2929 ptepindex = va >> PDRSHIFT; 2930 if (mpte && (mpte->pindex == ptepindex)) { 2931 mpte->wire_count++; 2932 } else { 2933 /* 2934 * Get the page directory entry 2935 */ 2936 ptema = pmap->pm_pdir[ptepindex]; 2937 2938 /* 2939 * If the page table page is mapped, we just increment 2940 * the hold count, and activate it. 2941 */ 2942 if (ptema & PG_V) { 2943 if (ptema & PG_PS) 2944 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2945 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2946 mpte->wire_count++; 2947 } else { 2948 mpte = _pmap_allocpte(pmap, ptepindex, 2949 M_NOWAIT); 2950 if (mpte == NULL) 2951 return (mpte); 2952 } 2953 } 2954 } else { 2955 mpte = NULL; 2956 } 2957 2958 /* 2959 * This call to vtopte makes the assumption that we are 2960 * entering the page into the current pmap. In order to support 2961 * quick entry into any pmap, one would likely use pmap_pte_quick. 2962 * But that isn't as quick as vtopte. 2963 */ 2964 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 2965 pte = vtopte(va); 2966 if (*pte & PG_V) { 2967 if (mpte != NULL) { 2968 mpte->wire_count--; 2969 mpte = NULL; 2970 } 2971 return (mpte); 2972 } 2973 2974 /* 2975 * Enter on the PV list if part of our managed memory. 2976 */ 2977 if ((m->oflags & VPO_UNMANAGED) == 0 && 2978 !pmap_try_insert_pv_entry(pmap, va, m)) { 2979 if (mpte != NULL) { 2980 free = NULL; 2981 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 2982 pmap_invalidate_page(pmap, va); 2983 pmap_free_zero_pages(free); 2984 } 2985 2986 mpte = NULL; 2987 } 2988 return (mpte); 2989 } 2990 2991 /* 2992 * Increment counters 2993 */ 2994 pmap->pm_stats.resident_count++; 2995 2996 pa = VM_PAGE_TO_PHYS(m); 2997#ifdef PAE 2998 if ((prot & VM_PROT_EXECUTE) == 0) 2999 pa |= pg_nx; 3000#endif 3001 3002#if 0 3003 /* 3004 * Now validate mapping with RO protection 3005 */ 3006 if ((m->oflags & VPO_UNMANAGED) != 0) 3007 pte_store(pte, pa | PG_V | PG_U); 3008 else 3009 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3010#else 3011 /* 3012 * Now validate mapping with RO protection 3013 */ 3014 if ((m->oflags & VPO_UNMANAGED) != 0) 3015 pa = xpmap_ptom(pa | PG_V | PG_U); 3016 else 3017 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3018 3019 mcl->op = __HYPERVISOR_update_va_mapping; 3020 mcl->args[0] = va; 3021 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3022 mcl->args[2] = (uint32_t)(pa >> 32); 3023 mcl->args[3] = 0; 3024 *mclpp = mcl + 1; 3025 *count = *count + 1; 3026#endif 3027 return mpte; 3028} 3029 3030/* 3031 * Make a temporary mapping for a physical address. This is only intended 3032 * to be used for panic dumps. 3033 */ 3034void * 3035pmap_kenter_temporary(vm_paddr_t pa, int i) 3036{ 3037 vm_offset_t va; 3038 vm_paddr_t ma = xpmap_ptom(pa); 3039 3040 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3041 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3042 invlpg(va); 3043 return ((void *)crashdumpmap); 3044} 3045 3046/* 3047 * This code maps large physical mmap regions into the 3048 * processor address space. Note that some shortcuts 3049 * are taken, but the code works. 3050 */ 3051void 3052pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 3053 vm_object_t object, vm_pindex_t pindex, 3054 vm_size_t size) 3055{ 3056 pd_entry_t *pde; 3057 vm_paddr_t pa, ptepa; 3058 vm_page_t p; 3059 int pat_mode; 3060 3061 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3062 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3063 ("pmap_object_init_pt: non-device object")); 3064 if (pseflag && 3065 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3066 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3067 return; 3068 p = vm_page_lookup(object, pindex); 3069 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3070 ("pmap_object_init_pt: invalid page %p", p)); 3071 pat_mode = p->md.pat_mode; 3072 /* 3073 * Abort the mapping if the first page is not physically 3074 * aligned to a 2/4MB page boundary. 3075 */ 3076 ptepa = VM_PAGE_TO_PHYS(p); 3077 if (ptepa & (NBPDR - 1)) 3078 return; 3079 /* 3080 * Skip the first page. Abort the mapping if the rest of 3081 * the pages are not physically contiguous or have differing 3082 * memory attributes. 3083 */ 3084 p = TAILQ_NEXT(p, listq); 3085 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3086 pa += PAGE_SIZE) { 3087 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3088 ("pmap_object_init_pt: invalid page %p", p)); 3089 if (pa != VM_PAGE_TO_PHYS(p) || 3090 pat_mode != p->md.pat_mode) 3091 return; 3092 p = TAILQ_NEXT(p, listq); 3093 } 3094 /* Map using 2/4MB pages. */ 3095 PMAP_LOCK(pmap); 3096 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3097 size; pa += NBPDR) { 3098 pde = pmap_pde(pmap, addr); 3099 if (*pde == 0) { 3100 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3101 PG_U | PG_RW | PG_V); 3102 pmap->pm_stats.resident_count += NBPDR / 3103 PAGE_SIZE; 3104 pmap_pde_mappings++; 3105 } 3106 /* Else continue on if the PDE is already valid. */ 3107 addr += NBPDR; 3108 } 3109 PMAP_UNLOCK(pmap); 3110 } 3111} 3112 3113/* 3114 * Routine: pmap_change_wiring 3115 * Function: Change the wiring attribute for a map/virtual-address 3116 * pair. 3117 * In/out conditions: 3118 * The mapping must already exist in the pmap. 3119 */ 3120void 3121pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3122{ 3123 pt_entry_t *pte; 3124 3125 vm_page_lock_queues(); 3126 PMAP_LOCK(pmap); 3127 pte = pmap_pte(pmap, va); 3128 3129 if (wired && !pmap_pte_w(pte)) { 3130 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3131 pmap->pm_stats.wired_count++; 3132 } else if (!wired && pmap_pte_w(pte)) { 3133 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3134 pmap->pm_stats.wired_count--; 3135 } 3136 3137 /* 3138 * Wiring is not a hardware characteristic so there is no need to 3139 * invalidate TLB. 3140 */ 3141 pmap_pte_release(pte); 3142 PMAP_UNLOCK(pmap); 3143 vm_page_unlock_queues(); 3144} 3145 3146 3147 3148/* 3149 * Copy the range specified by src_addr/len 3150 * from the source map to the range dst_addr/len 3151 * in the destination map. 3152 * 3153 * This routine is only advisory and need not do anything. 3154 */ 3155 3156void 3157pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3158 vm_offset_t src_addr) 3159{ 3160 vm_page_t free; 3161 vm_offset_t addr; 3162 vm_offset_t end_addr = src_addr + len; 3163 vm_offset_t pdnxt; 3164 3165 if (dst_addr != src_addr) 3166 return; 3167 3168 if (!pmap_is_current(src_pmap)) { 3169 CTR2(KTR_PMAP, 3170 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3171 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3172 3173 return; 3174 } 3175 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3176 dst_pmap, src_pmap, dst_addr, len, src_addr); 3177 3178#ifdef HAMFISTED_LOCKING 3179 mtx_lock(&createdelete_lock); 3180#endif 3181 3182 vm_page_lock_queues(); 3183 if (dst_pmap < src_pmap) { 3184 PMAP_LOCK(dst_pmap); 3185 PMAP_LOCK(src_pmap); 3186 } else { 3187 PMAP_LOCK(src_pmap); 3188 PMAP_LOCK(dst_pmap); 3189 } 3190 sched_pin(); 3191 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3192 pt_entry_t *src_pte, *dst_pte; 3193 vm_page_t dstmpte, srcmpte; 3194 pd_entry_t srcptepaddr; 3195 unsigned ptepindex; 3196 3197 KASSERT(addr < UPT_MIN_ADDRESS, 3198 ("pmap_copy: invalid to pmap_copy page tables")); 3199 3200 pdnxt = (addr + NBPDR) & ~PDRMASK; 3201 ptepindex = addr >> PDRSHIFT; 3202 3203 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3204 if (srcptepaddr == 0) 3205 continue; 3206 3207 if (srcptepaddr & PG_PS) { 3208 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3209 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3210 dst_pmap->pm_stats.resident_count += 3211 NBPDR / PAGE_SIZE; 3212 } 3213 continue; 3214 } 3215 3216 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3217 KASSERT(srcmpte->wire_count > 0, 3218 ("pmap_copy: source page table page is unused")); 3219 3220 if (pdnxt > end_addr) 3221 pdnxt = end_addr; 3222 3223 src_pte = vtopte(addr); 3224 while (addr < pdnxt) { 3225 pt_entry_t ptetemp; 3226 ptetemp = *src_pte; 3227 /* 3228 * we only virtual copy managed pages 3229 */ 3230 if ((ptetemp & PG_MANAGED) != 0) { 3231 dstmpte = pmap_allocpte(dst_pmap, addr, 3232 M_NOWAIT); 3233 if (dstmpte == NULL) 3234 break; 3235 dst_pte = pmap_pte_quick(dst_pmap, addr); 3236 if (*dst_pte == 0 && 3237 pmap_try_insert_pv_entry(dst_pmap, addr, 3238 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3239 /* 3240 * Clear the wired, modified, and 3241 * accessed (referenced) bits 3242 * during the copy. 3243 */ 3244 KASSERT(ptetemp != 0, ("src_pte not set")); 3245 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3246 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3247 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3248 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3249 dst_pmap->pm_stats.resident_count++; 3250 } else { 3251 free = NULL; 3252 if (pmap_unwire_pte_hold(dst_pmap, 3253 dstmpte, &free)) { 3254 pmap_invalidate_page(dst_pmap, 3255 addr); 3256 pmap_free_zero_pages(free); 3257 } 3258 } 3259 if (dstmpte->wire_count >= srcmpte->wire_count) 3260 break; 3261 } 3262 addr += PAGE_SIZE; 3263 src_pte++; 3264 } 3265 } 3266 PT_UPDATES_FLUSH(); 3267 sched_unpin(); 3268 vm_page_unlock_queues(); 3269 PMAP_UNLOCK(src_pmap); 3270 PMAP_UNLOCK(dst_pmap); 3271 3272#ifdef HAMFISTED_LOCKING 3273 mtx_unlock(&createdelete_lock); 3274#endif 3275} 3276 3277static __inline void 3278pagezero(void *page) 3279{ 3280#if defined(I686_CPU) 3281 if (cpu_class == CPUCLASS_686) { 3282#if defined(CPU_ENABLE_SSE) 3283 if (cpu_feature & CPUID_SSE2) 3284 sse2_pagezero(page); 3285 else 3286#endif 3287 i686_pagezero(page); 3288 } else 3289#endif 3290 bzero(page, PAGE_SIZE); 3291} 3292 3293/* 3294 * pmap_zero_page zeros the specified hardware page by mapping 3295 * the page into KVM and using bzero to clear its contents. 3296 */ 3297void 3298pmap_zero_page(vm_page_t m) 3299{ 3300 struct sysmaps *sysmaps; 3301 3302 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3303 mtx_lock(&sysmaps->lock); 3304 if (*sysmaps->CMAP2) 3305 panic("pmap_zero_page: CMAP2 busy"); 3306 sched_pin(); 3307 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3308 pagezero(sysmaps->CADDR2); 3309 PT_SET_MA(sysmaps->CADDR2, 0); 3310 sched_unpin(); 3311 mtx_unlock(&sysmaps->lock); 3312} 3313 3314/* 3315 * pmap_zero_page_area zeros the specified hardware page by mapping 3316 * the page into KVM and using bzero to clear its contents. 3317 * 3318 * off and size may not cover an area beyond a single hardware page. 3319 */ 3320void 3321pmap_zero_page_area(vm_page_t m, int off, int size) 3322{ 3323 struct sysmaps *sysmaps; 3324 3325 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3326 mtx_lock(&sysmaps->lock); 3327 if (*sysmaps->CMAP2) 3328 panic("pmap_zero_page: CMAP2 busy"); 3329 sched_pin(); 3330 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3331 3332 if (off == 0 && size == PAGE_SIZE) 3333 pagezero(sysmaps->CADDR2); 3334 else 3335 bzero((char *)sysmaps->CADDR2 + off, size); 3336 PT_SET_MA(sysmaps->CADDR2, 0); 3337 sched_unpin(); 3338 mtx_unlock(&sysmaps->lock); 3339} 3340 3341/* 3342 * pmap_zero_page_idle zeros the specified hardware page by mapping 3343 * the page into KVM and using bzero to clear its contents. This 3344 * is intended to be called from the vm_pagezero process only and 3345 * outside of Giant. 3346 */ 3347void 3348pmap_zero_page_idle(vm_page_t m) 3349{ 3350 3351 if (*CMAP3) 3352 panic("pmap_zero_page: CMAP3 busy"); 3353 sched_pin(); 3354 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3355 pagezero(CADDR3); 3356 PT_SET_MA(CADDR3, 0); 3357 sched_unpin(); 3358} 3359 3360/* 3361 * pmap_copy_page copies the specified (machine independent) 3362 * page by mapping the page into virtual memory and using 3363 * bcopy to copy the page, one machine dependent page at a 3364 * time. 3365 */ 3366void 3367pmap_copy_page(vm_page_t src, vm_page_t dst) 3368{ 3369 struct sysmaps *sysmaps; 3370 3371 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3372 mtx_lock(&sysmaps->lock); 3373 if (*sysmaps->CMAP1) 3374 panic("pmap_copy_page: CMAP1 busy"); 3375 if (*sysmaps->CMAP2) 3376 panic("pmap_copy_page: CMAP2 busy"); 3377 sched_pin(); 3378 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3379 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3380 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3381 PT_SET_MA(sysmaps->CADDR1, 0); 3382 PT_SET_MA(sysmaps->CADDR2, 0); 3383 sched_unpin(); 3384 mtx_unlock(&sysmaps->lock); 3385} 3386 3387/* 3388 * Returns true if the pmap's pv is one of the first 3389 * 16 pvs linked to from this page. This count may 3390 * be changed upwards or downwards in the future; it 3391 * is only necessary that true be returned for a small 3392 * subset of pmaps for proper page aging. 3393 */ 3394boolean_t 3395pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3396{ 3397 pv_entry_t pv; 3398 int loops = 0; 3399 boolean_t rv; 3400 3401 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3402 ("pmap_page_exists_quick: page %p is not managed", m)); 3403 rv = FALSE; 3404 vm_page_lock_queues(); 3405 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3406 if (PV_PMAP(pv) == pmap) { 3407 rv = TRUE; 3408 break; 3409 } 3410 loops++; 3411 if (loops >= 16) 3412 break; 3413 } 3414 vm_page_unlock_queues(); 3415 return (rv); 3416} 3417 3418/* 3419 * pmap_page_wired_mappings: 3420 * 3421 * Return the number of managed mappings to the given physical page 3422 * that are wired. 3423 */ 3424int 3425pmap_page_wired_mappings(vm_page_t m) 3426{ 3427 pv_entry_t pv; 3428 pt_entry_t *pte; 3429 pmap_t pmap; 3430 int count; 3431 3432 count = 0; 3433 if ((m->oflags & VPO_UNMANAGED) != 0) 3434 return (count); 3435 vm_page_lock_queues(); 3436 sched_pin(); 3437 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3438 pmap = PV_PMAP(pv); 3439 PMAP_LOCK(pmap); 3440 pte = pmap_pte_quick(pmap, pv->pv_va); 3441 if ((*pte & PG_W) != 0) 3442 count++; 3443 PMAP_UNLOCK(pmap); 3444 } 3445 sched_unpin(); 3446 vm_page_unlock_queues(); 3447 return (count); 3448} 3449 3450/* 3451 * Returns TRUE if the given page is mapped individually or as part of 3452 * a 4mpage. Otherwise, returns FALSE. 3453 */ 3454boolean_t 3455pmap_page_is_mapped(vm_page_t m) 3456{ 3457 boolean_t rv; 3458 3459 if ((m->oflags & VPO_UNMANAGED) != 0) 3460 return (FALSE); 3461 vm_page_lock_queues(); 3462 rv = !TAILQ_EMPTY(&m->md.pv_list) || 3463 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list); 3464 vm_page_unlock_queues(); 3465 return (rv); 3466} 3467 3468/* 3469 * Remove all pages from specified address space 3470 * this aids process exit speeds. Also, this code 3471 * is special cased for current process only, but 3472 * can have the more generic (and slightly slower) 3473 * mode enabled. This is much faster than pmap_remove 3474 * in the case of running down an entire address space. 3475 */ 3476void 3477pmap_remove_pages(pmap_t pmap) 3478{ 3479 pt_entry_t *pte, tpte; 3480 vm_page_t m, free = NULL; 3481 pv_entry_t pv; 3482 struct pv_chunk *pc, *npc; 3483 int field, idx; 3484 int32_t bit; 3485 uint32_t inuse, bitmask; 3486 int allfree; 3487 3488 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3489 3490 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3491 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3492 return; 3493 } 3494 vm_page_lock_queues(); 3495 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3496 PMAP_LOCK(pmap); 3497 sched_pin(); 3498 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3499 allfree = 1; 3500 for (field = 0; field < _NPCM; field++) { 3501 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 3502 while (inuse != 0) { 3503 bit = bsfl(inuse); 3504 bitmask = 1UL << bit; 3505 idx = field * 32 + bit; 3506 pv = &pc->pc_pventry[idx]; 3507 inuse &= ~bitmask; 3508 3509 pte = vtopte(pv->pv_va); 3510 tpte = *pte ? xpmap_mtop(*pte) : 0; 3511 3512 if (tpte == 0) { 3513 printf( 3514 "TPTE at %p IS ZERO @ VA %08x\n", 3515 pte, pv->pv_va); 3516 panic("bad pte"); 3517 } 3518 3519/* 3520 * We cannot remove wired pages from a process' mapping at this time 3521 */ 3522 if (tpte & PG_W) { 3523 allfree = 0; 3524 continue; 3525 } 3526 3527 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3528 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3529 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3530 m, (uintmax_t)m->phys_addr, 3531 (uintmax_t)tpte)); 3532 3533 KASSERT(m < &vm_page_array[vm_page_array_size], 3534 ("pmap_remove_pages: bad tpte %#jx", 3535 (uintmax_t)tpte)); 3536 3537 3538 PT_CLEAR_VA(pte, FALSE); 3539 3540 /* 3541 * Update the vm_page_t clean/reference bits. 3542 */ 3543 if (tpte & PG_M) 3544 vm_page_dirty(m); 3545 3546 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3547 if (TAILQ_EMPTY(&m->md.pv_list)) 3548 vm_page_aflag_clear(m, PGA_WRITEABLE); 3549 3550 pmap_unuse_pt(pmap, pv->pv_va, &free); 3551 3552 /* Mark free */ 3553 PV_STAT(pv_entry_frees++); 3554 PV_STAT(pv_entry_spare++); 3555 pv_entry_count--; 3556 pc->pc_map[field] |= bitmask; 3557 pmap->pm_stats.resident_count--; 3558 } 3559 } 3560 PT_UPDATES_FLUSH(); 3561 if (allfree) { 3562 PV_STAT(pv_entry_spare -= _NPCPV); 3563 PV_STAT(pc_chunk_count--); 3564 PV_STAT(pc_chunk_frees++); 3565 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3566 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 3567 pmap_qremove((vm_offset_t)pc, 1); 3568 vm_page_unwire(m, 0); 3569 vm_page_free(m); 3570 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 3571 } 3572 } 3573 PT_UPDATES_FLUSH(); 3574 if (*PMAP1) 3575 PT_SET_MA(PADDR1, 0); 3576 3577 sched_unpin(); 3578 pmap_invalidate_all(pmap); 3579 vm_page_unlock_queues(); 3580 PMAP_UNLOCK(pmap); 3581 pmap_free_zero_pages(free); 3582} 3583 3584/* 3585 * pmap_is_modified: 3586 * 3587 * Return whether or not the specified physical page was modified 3588 * in any physical maps. 3589 */ 3590boolean_t 3591pmap_is_modified(vm_page_t m) 3592{ 3593 pv_entry_t pv; 3594 pt_entry_t *pte; 3595 pmap_t pmap; 3596 boolean_t rv; 3597 3598 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3599 ("pmap_is_modified: page %p is not managed", m)); 3600 rv = FALSE; 3601 3602 /* 3603 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 3604 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3605 * is clear, no PTEs can have PG_M set. 3606 */ 3607 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3608 if ((m->oflags & VPO_BUSY) == 0 && 3609 (m->aflags & PGA_WRITEABLE) == 0) 3610 return (rv); 3611 vm_page_lock_queues(); 3612 sched_pin(); 3613 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3614 pmap = PV_PMAP(pv); 3615 PMAP_LOCK(pmap); 3616 pte = pmap_pte_quick(pmap, pv->pv_va); 3617 rv = (*pte & PG_M) != 0; 3618 PMAP_UNLOCK(pmap); 3619 if (rv) 3620 break; 3621 } 3622 if (*PMAP1) 3623 PT_SET_MA(PADDR1, 0); 3624 sched_unpin(); 3625 vm_page_unlock_queues(); 3626 return (rv); 3627} 3628 3629/* 3630 * pmap_is_prefaultable: 3631 * 3632 * Return whether or not the specified virtual address is elgible 3633 * for prefault. 3634 */ 3635static boolean_t 3636pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3637{ 3638 pt_entry_t *pte; 3639 boolean_t rv = FALSE; 3640 3641 return (rv); 3642 3643 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3644 pte = vtopte(addr); 3645 rv = (*pte == 0); 3646 } 3647 return (rv); 3648} 3649 3650boolean_t 3651pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3652{ 3653 boolean_t rv; 3654 3655 PMAP_LOCK(pmap); 3656 rv = pmap_is_prefaultable_locked(pmap, addr); 3657 PMAP_UNLOCK(pmap); 3658 return (rv); 3659} 3660 3661boolean_t 3662pmap_is_referenced(vm_page_t m) 3663{ 3664 pv_entry_t pv; 3665 pt_entry_t *pte; 3666 pmap_t pmap; 3667 boolean_t rv; 3668 3669 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3670 ("pmap_is_referenced: page %p is not managed", m)); 3671 rv = FALSE; 3672 vm_page_lock_queues(); 3673 sched_pin(); 3674 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3675 pmap = PV_PMAP(pv); 3676 PMAP_LOCK(pmap); 3677 pte = pmap_pte_quick(pmap, pv->pv_va); 3678 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3679 PMAP_UNLOCK(pmap); 3680 if (rv) 3681 break; 3682 } 3683 if (*PMAP1) 3684 PT_SET_MA(PADDR1, 0); 3685 sched_unpin(); 3686 vm_page_unlock_queues(); 3687 return (rv); 3688} 3689 3690void 3691pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3692{ 3693 int i, npages = round_page(len) >> PAGE_SHIFT; 3694 for (i = 0; i < npages; i++) { 3695 pt_entry_t *pte; 3696 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3697 vm_page_lock_queues(); 3698 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3699 vm_page_unlock_queues(); 3700 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3701 pmap_pte_release(pte); 3702 } 3703} 3704 3705void 3706pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3707{ 3708 int i, npages = round_page(len) >> PAGE_SHIFT; 3709 for (i = 0; i < npages; i++) { 3710 pt_entry_t *pte; 3711 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3712 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3713 vm_page_lock_queues(); 3714 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3715 vm_page_unlock_queues(); 3716 pmap_pte_release(pte); 3717 } 3718} 3719 3720/* 3721 * Clear the write and modified bits in each of the given page's mappings. 3722 */ 3723void 3724pmap_remove_write(vm_page_t m) 3725{ 3726 pv_entry_t pv; 3727 pmap_t pmap; 3728 pt_entry_t oldpte, *pte; 3729 3730 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3731 ("pmap_remove_write: page %p is not managed", m)); 3732 3733 /* 3734 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 3735 * another thread while the object is locked. Thus, if PGA_WRITEABLE 3736 * is clear, no page table entries need updating. 3737 */ 3738 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3739 if ((m->oflags & VPO_BUSY) == 0 && 3740 (m->aflags & PGA_WRITEABLE) == 0) 3741 return; 3742 vm_page_lock_queues(); 3743 sched_pin(); 3744 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3745 pmap = PV_PMAP(pv); 3746 PMAP_LOCK(pmap); 3747 pte = pmap_pte_quick(pmap, pv->pv_va); 3748retry: 3749 oldpte = *pte; 3750 if ((oldpte & PG_RW) != 0) { 3751 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3752 3753 /* 3754 * Regardless of whether a pte is 32 or 64 bits 3755 * in size, PG_RW and PG_M are among the least 3756 * significant 32 bits. 3757 */ 3758 PT_SET_VA_MA(pte, newpte, TRUE); 3759 if (*pte != newpte) 3760 goto retry; 3761 3762 if ((oldpte & PG_M) != 0) 3763 vm_page_dirty(m); 3764 pmap_invalidate_page(pmap, pv->pv_va); 3765 } 3766 PMAP_UNLOCK(pmap); 3767 } 3768 vm_page_aflag_clear(m, PGA_WRITEABLE); 3769 PT_UPDATES_FLUSH(); 3770 if (*PMAP1) 3771 PT_SET_MA(PADDR1, 0); 3772 sched_unpin(); 3773 vm_page_unlock_queues(); 3774} 3775 3776/* 3777 * pmap_ts_referenced: 3778 * 3779 * Return a count of reference bits for a page, clearing those bits. 3780 * It is not necessary for every reference bit to be cleared, but it 3781 * is necessary that 0 only be returned when there are truly no 3782 * reference bits set. 3783 * 3784 * XXX: The exact number of bits to check and clear is a matter that 3785 * should be tested and standardized at some point in the future for 3786 * optimal aging of shared pages. 3787 */ 3788int 3789pmap_ts_referenced(vm_page_t m) 3790{ 3791 pv_entry_t pv, pvf, pvn; 3792 pmap_t pmap; 3793 pt_entry_t *pte; 3794 int rtval = 0; 3795 3796 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3797 ("pmap_ts_referenced: page %p is not managed", m)); 3798 vm_page_lock_queues(); 3799 sched_pin(); 3800 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3801 pvf = pv; 3802 do { 3803 pvn = TAILQ_NEXT(pv, pv_list); 3804 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3805 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3806 pmap = PV_PMAP(pv); 3807 PMAP_LOCK(pmap); 3808 pte = pmap_pte_quick(pmap, pv->pv_va); 3809 if ((*pte & PG_A) != 0) { 3810 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3811 pmap_invalidate_page(pmap, pv->pv_va); 3812 rtval++; 3813 if (rtval > 4) 3814 pvn = NULL; 3815 } 3816 PMAP_UNLOCK(pmap); 3817 } while ((pv = pvn) != NULL && pv != pvf); 3818 } 3819 PT_UPDATES_FLUSH(); 3820 if (*PMAP1) 3821 PT_SET_MA(PADDR1, 0); 3822 3823 sched_unpin(); 3824 vm_page_unlock_queues(); 3825 return (rtval); 3826} 3827 3828/* 3829 * Clear the modify bits on the specified physical page. 3830 */ 3831void 3832pmap_clear_modify(vm_page_t m) 3833{ 3834 pv_entry_t pv; 3835 pmap_t pmap; 3836 pt_entry_t *pte; 3837 3838 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3839 ("pmap_clear_modify: page %p is not managed", m)); 3840 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3841 KASSERT((m->oflags & VPO_BUSY) == 0, 3842 ("pmap_clear_modify: page %p is busy", m)); 3843 3844 /* 3845 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 3846 * If the object containing the page is locked and the page is not 3847 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 3848 */ 3849 if ((m->aflags & PGA_WRITEABLE) == 0) 3850 return; 3851 vm_page_lock_queues(); 3852 sched_pin(); 3853 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3854 pmap = PV_PMAP(pv); 3855 PMAP_LOCK(pmap); 3856 pte = pmap_pte_quick(pmap, pv->pv_va); 3857 if ((*pte & PG_M) != 0) { 3858 /* 3859 * Regardless of whether a pte is 32 or 64 bits 3860 * in size, PG_M is among the least significant 3861 * 32 bits. 3862 */ 3863 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3864 pmap_invalidate_page(pmap, pv->pv_va); 3865 } 3866 PMAP_UNLOCK(pmap); 3867 } 3868 sched_unpin(); 3869 vm_page_unlock_queues(); 3870} 3871 3872/* 3873 * pmap_clear_reference: 3874 * 3875 * Clear the reference bit on the specified physical page. 3876 */ 3877void 3878pmap_clear_reference(vm_page_t m) 3879{ 3880 pv_entry_t pv; 3881 pmap_t pmap; 3882 pt_entry_t *pte; 3883 3884 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3885 ("pmap_clear_reference: page %p is not managed", m)); 3886 vm_page_lock_queues(); 3887 sched_pin(); 3888 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3889 pmap = PV_PMAP(pv); 3890 PMAP_LOCK(pmap); 3891 pte = pmap_pte_quick(pmap, pv->pv_va); 3892 if ((*pte & PG_A) != 0) { 3893 /* 3894 * Regardless of whether a pte is 32 or 64 bits 3895 * in size, PG_A is among the least significant 3896 * 32 bits. 3897 */ 3898 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3899 pmap_invalidate_page(pmap, pv->pv_va); 3900 } 3901 PMAP_UNLOCK(pmap); 3902 } 3903 sched_unpin(); 3904 vm_page_unlock_queues(); 3905} 3906 3907/* 3908 * Miscellaneous support routines follow 3909 */ 3910 3911/* 3912 * Map a set of physical memory pages into the kernel virtual 3913 * address space. Return a pointer to where it is mapped. This 3914 * routine is intended to be used for mapping device memory, 3915 * NOT real memory. 3916 */ 3917void * 3918pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 3919{ 3920 vm_offset_t va, offset; 3921 vm_size_t tmpsize; 3922 3923 offset = pa & PAGE_MASK; 3924 size = roundup(offset + size, PAGE_SIZE); 3925 pa = pa & PG_FRAME; 3926 3927 if (pa < KERNLOAD && pa + size <= KERNLOAD) 3928 va = KERNBASE + pa; 3929 else 3930 va = kmem_alloc_nofault(kernel_map, size); 3931 if (!va) 3932 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3933 3934 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 3935 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 3936 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 3937 pmap_invalidate_cache_range(va, va + size); 3938 return ((void *)(va + offset)); 3939} 3940 3941void * 3942pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3943{ 3944 3945 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 3946} 3947 3948void * 3949pmap_mapbios(vm_paddr_t pa, vm_size_t size) 3950{ 3951 3952 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 3953} 3954 3955void 3956pmap_unmapdev(vm_offset_t va, vm_size_t size) 3957{ 3958 vm_offset_t base, offset, tmpva; 3959 3960 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 3961 return; 3962 base = trunc_page(va); 3963 offset = va & PAGE_MASK; 3964 size = roundup(offset + size, PAGE_SIZE); 3965 critical_enter(); 3966 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 3967 pmap_kremove(tmpva); 3968 pmap_invalidate_range(kernel_pmap, va, tmpva); 3969 critical_exit(); 3970 kmem_free(kernel_map, base, size); 3971} 3972 3973/* 3974 * Sets the memory attribute for the specified page. 3975 */ 3976void 3977pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 3978{ 3979 struct sysmaps *sysmaps; 3980 vm_offset_t sva, eva; 3981 3982 m->md.pat_mode = ma; 3983 if ((m->flags & PG_FICTITIOUS) != 0) 3984 return; 3985 3986 /* 3987 * If "m" is a normal page, flush it from the cache. 3988 * See pmap_invalidate_cache_range(). 3989 * 3990 * First, try to find an existing mapping of the page by sf 3991 * buffer. sf_buf_invalidate_cache() modifies mapping and 3992 * flushes the cache. 3993 */ 3994 if (sf_buf_invalidate_cache(m)) 3995 return; 3996 3997 /* 3998 * If page is not mapped by sf buffer, but CPU does not 3999 * support self snoop, map the page transient and do 4000 * invalidation. In the worst case, whole cache is flushed by 4001 * pmap_invalidate_cache_range(). 4002 */ 4003 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 4004 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4005 mtx_lock(&sysmaps->lock); 4006 if (*sysmaps->CMAP2) 4007 panic("pmap_page_set_memattr: CMAP2 busy"); 4008 sched_pin(); 4009 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 4010 VM_PAGE_TO_MACH(m) | PG_A | PG_M | 4011 pmap_cache_bits(m->md.pat_mode, 0)); 4012 invlcaddr(sysmaps->CADDR2); 4013 sva = (vm_offset_t)sysmaps->CADDR2; 4014 eva = sva + PAGE_SIZE; 4015 } else 4016 sva = eva = 0; /* gcc */ 4017 pmap_invalidate_cache_range(sva, eva); 4018 if (sva != 0) { 4019 PT_SET_MA(sysmaps->CADDR2, 0); 4020 sched_unpin(); 4021 mtx_unlock(&sysmaps->lock); 4022 } 4023} 4024 4025int 4026pmap_change_attr(va, size, mode) 4027 vm_offset_t va; 4028 vm_size_t size; 4029 int mode; 4030{ 4031 vm_offset_t base, offset, tmpva; 4032 pt_entry_t *pte; 4033 u_int opte, npte; 4034 pd_entry_t *pde; 4035 boolean_t changed; 4036 4037 base = trunc_page(va); 4038 offset = va & PAGE_MASK; 4039 size = roundup(offset + size, PAGE_SIZE); 4040 4041 /* Only supported on kernel virtual addresses. */ 4042 if (base <= VM_MAXUSER_ADDRESS) 4043 return (EINVAL); 4044 4045 /* 4MB pages and pages that aren't mapped aren't supported. */ 4046 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4047 pde = pmap_pde(kernel_pmap, tmpva); 4048 if (*pde & PG_PS) 4049 return (EINVAL); 4050 if ((*pde & PG_V) == 0) 4051 return (EINVAL); 4052 pte = vtopte(va); 4053 if ((*pte & PG_V) == 0) 4054 return (EINVAL); 4055 } 4056 4057 changed = FALSE; 4058 4059 /* 4060 * Ok, all the pages exist and are 4k, so run through them updating 4061 * their cache mode. 4062 */ 4063 for (tmpva = base; size > 0; ) { 4064 pte = vtopte(tmpva); 4065 4066 /* 4067 * The cache mode bits are all in the low 32-bits of the 4068 * PTE, so we can just spin on updating the low 32-bits. 4069 */ 4070 do { 4071 opte = *(u_int *)pte; 4072 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4073 npte |= pmap_cache_bits(mode, 0); 4074 PT_SET_VA_MA(pte, npte, TRUE); 4075 } while (npte != opte && (*pte != npte)); 4076 if (npte != opte) 4077 changed = TRUE; 4078 tmpva += PAGE_SIZE; 4079 size -= PAGE_SIZE; 4080 } 4081 4082 /* 4083 * Flush CPU caches to make sure any data isn't cached that shouldn't 4084 * be, etc. 4085 */ 4086 if (changed) { 4087 pmap_invalidate_range(kernel_pmap, base, tmpva); 4088 pmap_invalidate_cache_range(base, tmpva); 4089 } 4090 return (0); 4091} 4092 4093/* 4094 * perform the pmap work for mincore 4095 */ 4096int 4097pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4098{ 4099 pt_entry_t *ptep, pte; 4100 vm_paddr_t pa; 4101 int val; 4102 4103 PMAP_LOCK(pmap); 4104retry: 4105 ptep = pmap_pte(pmap, addr); 4106 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4107 pmap_pte_release(ptep); 4108 val = 0; 4109 if ((pte & PG_V) != 0) { 4110 val |= MINCORE_INCORE; 4111 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4112 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4113 if ((pte & PG_A) != 0) 4114 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4115 } 4116 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4117 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4118 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4119 pa = pte & PG_FRAME; 4120 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4121 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4122 goto retry; 4123 } else 4124 PA_UNLOCK_COND(*locked_pa); 4125 PMAP_UNLOCK(pmap); 4126 return (val); 4127} 4128 4129void 4130pmap_activate(struct thread *td) 4131{ 4132 pmap_t pmap, oldpmap; 4133 u_int cpuid; 4134 u_int32_t cr3; 4135 4136 critical_enter(); 4137 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4138 oldpmap = PCPU_GET(curpmap); 4139 cpuid = PCPU_GET(cpuid); 4140#if defined(SMP) 4141 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 4142 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 4143#else 4144 CPU_CLR(cpuid, &oldpmap->pm_active); 4145 CPU_SET(cpuid, &pmap->pm_active); 4146#endif 4147#ifdef PAE 4148 cr3 = vtophys(pmap->pm_pdpt); 4149#else 4150 cr3 = vtophys(pmap->pm_pdir); 4151#endif 4152 /* 4153 * pmap_activate is for the current thread on the current cpu 4154 */ 4155 td->td_pcb->pcb_cr3 = cr3; 4156 PT_UPDATES_FLUSH(); 4157 load_cr3(cr3); 4158 PCPU_SET(curpmap, pmap); 4159 critical_exit(); 4160} 4161 4162void 4163pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4164{ 4165} 4166 4167/* 4168 * Increase the starting virtual address of the given mapping if a 4169 * different alignment might result in more superpage mappings. 4170 */ 4171void 4172pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4173 vm_offset_t *addr, vm_size_t size) 4174{ 4175 vm_offset_t superpage_offset; 4176 4177 if (size < NBPDR) 4178 return; 4179 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4180 offset += ptoa(object->pg_color); 4181 superpage_offset = offset & PDRMASK; 4182 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4183 (*addr & PDRMASK) == superpage_offset) 4184 return; 4185 if ((*addr & PDRMASK) < superpage_offset) 4186 *addr = (*addr & ~PDRMASK) + superpage_offset; 4187 else 4188 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4189} 4190 4191void 4192pmap_suspend() 4193{ 4194 pmap_t pmap; 4195 int i, pdir, offset; 4196 vm_paddr_t pdirma; 4197 mmu_update_t mu[4]; 4198 4199 /* 4200 * We need to remove the recursive mapping structure from all 4201 * our pmaps so that Xen doesn't get confused when it restores 4202 * the page tables. The recursive map lives at page directory 4203 * index PTDPTDI. We assume that the suspend code has stopped 4204 * the other vcpus (if any). 4205 */ 4206 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4207 for (i = 0; i < 4; i++) { 4208 /* 4209 * Figure out which page directory (L2) page 4210 * contains this bit of the recursive map and 4211 * the offset within that page of the map 4212 * entry 4213 */ 4214 pdir = (PTDPTDI + i) / NPDEPG; 4215 offset = (PTDPTDI + i) % NPDEPG; 4216 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4217 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4218 mu[i].val = 0; 4219 } 4220 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4221 } 4222} 4223 4224void 4225pmap_resume() 4226{ 4227 pmap_t pmap; 4228 int i, pdir, offset; 4229 vm_paddr_t pdirma; 4230 mmu_update_t mu[4]; 4231 4232 /* 4233 * Restore the recursive map that we removed on suspend. 4234 */ 4235 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4236 for (i = 0; i < 4; i++) { 4237 /* 4238 * Figure out which page directory (L2) page 4239 * contains this bit of the recursive map and 4240 * the offset within that page of the map 4241 * entry 4242 */ 4243 pdir = (PTDPTDI + i) / NPDEPG; 4244 offset = (PTDPTDI + i) % NPDEPG; 4245 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4246 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4247 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4248 } 4249 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4250 } 4251} 4252 4253#if defined(PMAP_DEBUG) 4254pmap_pid_dump(int pid) 4255{ 4256 pmap_t pmap; 4257 struct proc *p; 4258 int npte = 0; 4259 int index; 4260 4261 sx_slock(&allproc_lock); 4262 FOREACH_PROC_IN_SYSTEM(p) { 4263 if (p->p_pid != pid) 4264 continue; 4265 4266 if (p->p_vmspace) { 4267 int i,j; 4268 index = 0; 4269 pmap = vmspace_pmap(p->p_vmspace); 4270 for (i = 0; i < NPDEPTD; i++) { 4271 pd_entry_t *pde; 4272 pt_entry_t *pte; 4273 vm_offset_t base = i << PDRSHIFT; 4274 4275 pde = &pmap->pm_pdir[i]; 4276 if (pde && pmap_pde_v(pde)) { 4277 for (j = 0; j < NPTEPG; j++) { 4278 vm_offset_t va = base + (j << PAGE_SHIFT); 4279 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4280 if (index) { 4281 index = 0; 4282 printf("\n"); 4283 } 4284 sx_sunlock(&allproc_lock); 4285 return npte; 4286 } 4287 pte = pmap_pte(pmap, va); 4288 if (pte && pmap_pte_v(pte)) { 4289 pt_entry_t pa; 4290 vm_page_t m; 4291 pa = PT_GET(pte); 4292 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4293 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4294 va, pa, m->hold_count, m->wire_count, m->flags); 4295 npte++; 4296 index++; 4297 if (index >= 2) { 4298 index = 0; 4299 printf("\n"); 4300 } else { 4301 printf(" "); 4302 } 4303 } 4304 } 4305 } 4306 } 4307 } 4308 } 4309 sx_sunlock(&allproc_lock); 4310 return npte; 4311} 4312#endif 4313 4314#if defined(DEBUG) 4315 4316static void pads(pmap_t pm); 4317void pmap_pvdump(vm_paddr_t pa); 4318 4319/* print address space of pmap*/ 4320static void 4321pads(pmap_t pm) 4322{ 4323 int i, j; 4324 vm_paddr_t va; 4325 pt_entry_t *ptep; 4326 4327 if (pm == kernel_pmap) 4328 return; 4329 for (i = 0; i < NPDEPTD; i++) 4330 if (pm->pm_pdir[i]) 4331 for (j = 0; j < NPTEPG; j++) { 4332 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4333 if (pm == kernel_pmap && va < KERNBASE) 4334 continue; 4335 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4336 continue; 4337 ptep = pmap_pte(pm, va); 4338 if (pmap_pte_v(ptep)) 4339 printf("%x:%x ", va, *ptep); 4340 }; 4341 4342} 4343 4344void 4345pmap_pvdump(vm_paddr_t pa) 4346{ 4347 pv_entry_t pv; 4348 pmap_t pmap; 4349 vm_page_t m; 4350 4351 printf("pa %x", pa); 4352 m = PHYS_TO_VM_PAGE(pa); 4353 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4354 pmap = PV_PMAP(pv); 4355 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4356 pads(pmap); 4357 } 4358 printf(" "); 4359} 4360#endif 4361