pmap.c revision 223758
1194140Simp/*- 2194140Simp * Copyright (c) 1991 Regents of the University of California. 3194140Simp * All rights reserved. 4194140Simp * Copyright (c) 1994 John S. Dyson 5194140Simp * All rights reserved. 6194140Simp * Copyright (c) 1994 David Greenman 7194140Simp * All rights reserved. 8194140Simp * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9194140Simp * All rights reserved. 10194140Simp * 11194140Simp * This code is derived from software contributed to Berkeley by 12194140Simp * the Systems Programming Group of the University of Utah Computer 13194140Simp * Science Department and William Jolitz of UUNET Technologies Inc. 14194140Simp * 15194140Simp * Redistribution and use in source and binary forms, with or without 16194140Simp * modification, are permitted provided that the following conditions 17194140Simp * are met: 18194140Simp * 1. Redistributions of source code must retain the above copyright 19194140Simp * notice, this list of conditions and the following disclaimer. 20194140Simp * 2. Redistributions in binary form must reproduce the above copyright 21194140Simp * notice, this list of conditions and the following disclaimer in the 22194140Simp * documentation and/or other materials provided with the distribution. 23194140Simp * 3. All advertising materials mentioning features or use of this software 24194140Simp * must display the following acknowledgement: 25194140Simp * This product includes software developed by the University of 26194140Simp * California, Berkeley and its contributors. 27194140Simp * 4. Neither the name of the University nor the names of its contributors 28194140Simp * may be used to endorse or promote products derived from this software 29194140Simp * without specific prior written permission. 30194140Simp * 31194140Simp * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32196262Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33196262Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34194140Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35196262Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36196262Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37196262Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38196262Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39196262Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40196262Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41196262Simp * SUCH DAMAGE. 42196262Simp * 43196262Simp * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44196262Simp */ 45196262Simp/*- 46196262Simp * Copyright (c) 2003 Networks Associates Technology, Inc. 47196262Simp * All rights reserved. 48196262Simp * 49196262Simp * This software was developed for the FreeBSD Project by Jake Burkholder, 50210311Sjmallett * Safeport Network Services, and Network Associates Laboratories, the 51210311Sjmallett * Security Research Division of Network Associates, Inc. under 52196262Simp * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53196262Simp * CHATS research program. 54196262Simp * 55196262Simp * Redistribution and use in source and binary forms, with or without 56196262Simp * modification, are permitted provided that the following conditions 57196262Simp * are met: 58196262Simp * 1. Redistributions of source code must retain the above copyright 59196262Simp * notice, this list of conditions and the following disclaimer. 60196262Simp * 2. Redistributions in binary form must reproduce the above copyright 61196262Simp * notice, this list of conditions and the following disclaimer in the 62196262Simp * documentation and/or other materials provided with the distribution. 63194140Simp * 64194140Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65202063Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66196262Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67196262Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68196262Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69196262Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70194140Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71196262Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72196262Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73196262Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74194140Simp * SUCH DAMAGE. 75210311Sjmallett */ 76210311Sjmallett 77210311Sjmallett#include <sys/cdefs.h> 78210311Sjmallett__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 223758 2011-07-04 12:04:52Z attilio $"); 79210311Sjmallett 80194140Simp/* 81196262Simp * Manages physical address maps. 82194140Simp * 83196262Simp * In addition to hardware address maps, this 84194140Simp * module is called upon to provide software-use-only 85194140Simp * maps which may or may not be stored in the same 86210311Sjmallett * form as hardware maps. These pseudo-maps are 87210311Sjmallett * used to store intermediate results from copy 88210311Sjmallett * operations to and from address spaces. 89210311Sjmallett * 90210311Sjmallett * Since the information managed by this module is 91210311Sjmallett * also stored by the logical address mapping module, 92210311Sjmallett * this module may throw away valid virtual-to-physical 93196262Simp * mappings at almost any time. However, invalidations 94196262Simp * of virtual-to-physical mappings must be done as 95217518Simp * requested. 96217518Simp * 97194140Simp * In order to cope with hardware architectures which 98210311Sjmallett * make virtual-to-physical map invalidates expensive, 99210311Sjmallett * this module may delay invalidate or reduced protection 100210311Sjmallett * operations until such time as they are actually 101210311Sjmallett * necessary. This module is given full information as 102216069Sjmallett * to which processors are currently using which maps, 103210311Sjmallett * and to when physical maps must be made correct. 104216069Sjmallett */ 105210311Sjmallett 106210311Sjmallett#include "opt_cpu.h" 107210311Sjmallett#include "opt_pmap.h" 108210311Sjmallett#include "opt_smp.h" 109210311Sjmallett#include "opt_xbox.h" 110210311Sjmallett 111210311Sjmallett#include <sys/param.h> 112210311Sjmallett#include <sys/systm.h> 113210311Sjmallett#include <sys/kernel.h> 114216069Sjmallett#include <sys/ktr.h> 115210311Sjmallett#include <sys/lock.h> 116210311Sjmallett#include <sys/malloc.h> 117210311Sjmallett#include <sys/mman.h> 118201530Simp#include <sys/msgbuf.h> 119201530Simp#include <sys/mutex.h> 120201530Simp#include <sys/proc.h> 121210311Sjmallett#include <sys/sf_buf.h> 122210311Sjmallett#include <sys/sx.h> 123210311Sjmallett#include <sys/vmmeter.h> 124200344Simp#include <sys/sched.h> 125200344Simp#include <sys/sysctl.h> 126210311Sjmallett#ifdef SMP 127210311Sjmallett#include <sys/smp.h> 128210311Sjmallett#endif 129210311Sjmallett 130210311Sjmallett#include <vm/vm.h> 131210311Sjmallett#include <vm/vm_param.h> 132210311Sjmallett#include <vm/vm_kern.h> 133210311Sjmallett#include <vm/vm_page.h> 134210311Sjmallett#include <vm/vm_map.h> 135198669Srrs#include <vm/vm_object.h> 136198669Srrs#include <vm/vm_extern.h> 137198669Srrs#include <vm/vm_pageout.h> 138198669Srrs#include <vm/vm_pager.h> 139198669Srrs#include <vm/uma.h> 140196262Simp 141194140Simp#include <machine/cpu.h> 142194140Simp#include <machine/cputypes.h> 143194140Simp#include <machine/md_var.h> 144196314Simp#include <machine/pcb.h> 145196314Simp#include <machine/specialreg.h> 146194140Simp#ifdef SMP 147210311Sjmallett#include <machine/smp.h> 148194140Simp#endif 149194140Simp 150201530Simp#ifdef XBOX 151201530Simp#include <machine/xbox.h> 152194140Simp#endif 153201530Simp 154194140Simp#include <xen/interface/xen.h> 155210311Sjmallett#include <xen/hypervisor.h> 156201530Simp#include <machine/xen/hypercall.h> 157194140Simp#include <machine/xen/xenvar.h> 158201530Simp#include <machine/xen/xenfunc.h> 159201530Simp 160201530Simp#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 161194140Simp#define CPU_ENABLE_SSE 162194140Simp#endif 163201530Simp 164201530Simp#ifndef PMAP_SHPGPERPROC 165194140Simp#define PMAP_SHPGPERPROC 200 166201530Simp#endif 167194140Simp 168210311Sjmallett#define DIAGNOSTIC 169201530Simp 170201530Simp#if !defined(DIAGNOSTIC) 171194140Simp#ifdef __GNUC_GNU_INLINE__ 172194140Simp#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 173201530Simp#else 174201530Simp#define PMAP_INLINE extern inline 175194140Simp#endif 176201530Simp#else 177201530Simp#define PMAP_INLINE 178194140Simp#endif 179210311Sjmallett 180201530Simp#define PV_STATS 181194140Simp#ifdef PV_STATS 182201530Simp#define PV_STAT(x) do { x ; } while (0) 183201530Simp#else 184201530Simp#define PV_STAT(x) do { } while (0) 185201530Simp#endif 186201530Simp 187201530Simp#define pa_index(pa) ((pa) >> PDRSHIFT) 188201530Simp#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 189201530Simp 190201530Simp/* 191194140Simp * Get PDEs and PTEs for user/kernel address space 192194140Simp */ 193201530Simp#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 194201530Simp#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 195194140Simp 196201530Simp#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 197201530Simp#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 198194140Simp#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 199210311Sjmallett#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 200201530Simp#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 201194140Simp 202201530Simp#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 203201530Simp 204201530Simp#define HAMFISTED_LOCKING 205201530Simp#ifdef HAMFISTED_LOCKING 206201530Simpstatic struct mtx createdelete_lock; 207210311Sjmallett#endif 208201530Simp 209194140Simpstruct pmap kernel_pmap_store; 210194140SimpLIST_HEAD(pmaplist, pmap); 211194140Simpstatic struct pmaplist allpmaps; 212194140Simpstatic struct mtx allpmaps_lock; 213201530Simp 214201530Simpvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 215194140Simpvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 216210311Sjmallettint pgeflag = 0; /* PG_G or-in */ 217201530Simpint pseflag = 0; /* PG_PS or-in */ 218201530Simp 219201530Simpint nkpt; 220201530Simpvm_offset_t kernel_vm_end; 221194140Simpextern u_int32_t KERNend; 222194140Simp 223201530Simp#ifdef PAE 224201530Simppt_entry_t pg_nx; 225194140Simp#endif 226201530Simp 227194140Simpstatic int pat_works; /* Is page attribute table sane? */ 228201530Simp 229201530Simp/* 230194140Simp * Data for the pv entry allocation mechanism 231194140Simp */ 232194140Simpstatic int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 233194140Simpstatic struct md_page *pv_table; 234194140Simpstatic int shpgperproc = PMAP_SHPGPERPROC; 235194140Simp 236194140Simpstruct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 237194140Simpint pv_maxchunks; /* How many chunks we have KVA for */ 238201530Simpvm_offset_t pv_vafree; /* freelist stored in the PTE */ 239201530Simp 240194140Simp/* 241194140Simp * All those kernel PT submaps that BSD is so fond of 242194140Simp */ 243194140Simpstruct sysmaps { 244194140Simp struct mtx lock; 245194140Simp pt_entry_t *CMAP1; 246194140Simp pt_entry_t *CMAP2; 247194140Simp caddr_t CADDR1; 248201530Simp caddr_t CADDR2; 249201530Simp}; 250194140Simpstatic struct sysmaps sysmaps_pcpu[MAXCPU]; 251210311Sjmallettstatic pt_entry_t *CMAP3; 252210311Sjmallettcaddr_t ptvmmap = 0; 253210311Sjmallettstatic caddr_t CADDR3; 254210311Sjmallettstruct msgbuf *msgbufp = 0; 255210311Sjmallett 256194140Simp/* 257210311Sjmallett * Crashdump maps. 258210311Sjmallett */ 259210311Sjmallettstatic caddr_t crashdumpmap; 260210311Sjmallett 261210311Sjmallettstatic pt_entry_t *PMAP1 = 0, *PMAP2; 262210311Sjmallettstatic pt_entry_t *PADDR1 = 0, *PADDR2; 263194140Simp#ifdef SMP 264194140Simpstatic int PMAP1cpu; 265210311Sjmallettstatic int PMAP1changedcpu; 266210311SjmallettSYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 267194140Simp &PMAP1changedcpu, 0, 268210311Sjmallett "Number of times pmap_pte_quick changed CPU with same PMAP1"); 269210311Sjmallett#endif 270216318Sgonzostatic int PMAP1changed; 271194140SimpSYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 272210311Sjmallett &PMAP1changed, 0, 273194140Simp "Number of times pmap_pte_quick changed PMAP1"); 274210311Sjmallettstatic int PMAP1unchanged; 275210311SjmallettSYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 276210311Sjmallett &PMAP1unchanged, 0, 277210311Sjmallett "Number of times pmap_pte_quick didn't change PMAP1"); 278194140Simpstatic struct mtx PMAP2mutex; 279216318Sgonzo 280216320SgonzoSYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 281216318Sgonzostatic int pg_ps_enabled; 282210311SjmallettSYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 283210311Sjmallett "Are large page mappings enabled?"); 284201530Simp 285194140SimpSYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 286210311Sjmallett "Max number of PV entries"); 287210311SjmallettSYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 288210311Sjmallett "Page share factor per proc"); 289210311SjmallettSYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 290210311Sjmallett "2/4MB page mapping counters"); 291210311Sjmallett 292216773Sjmallettstatic u_long pmap_pde_mappings; 293216773SjmallettSYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 294216773Sjmallett &pmap_pde_mappings, 0, "2/4MB page mappings"); 295216773Sjmallett 296216773Sjmallettstatic void free_pv_entry(pmap_t pmap, pv_entry_t pv); 297216773Sjmallettstatic pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 298216773Sjmallettstatic void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 299216773Sjmallettstatic pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 300210311Sjmallett vm_offset_t va); 301210311Sjmallett 302210311Sjmallettstatic vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 303210311Sjmallett vm_page_t m, vm_prot_t prot, vm_page_t mpte); 304194140Simpstatic int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 305212842Sjmallett vm_page_t *free); 306212842Sjmallettstatic void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 307212842Sjmallett vm_page_t *free); 308212842Sjmallettstatic void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 309212842Sjmallett vm_offset_t va); 310212842Sjmallettstatic boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 311212842Sjmallett vm_page_t m); 312212842Sjmallett 313212842Sjmallettstatic vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 314212842Sjmallett 315212842Sjmallettstatic vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 316212842Sjmallettstatic int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 317210311Sjmallettstatic pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 318194140Simpstatic void pmap_pte_release(pt_entry_t *pte); 319210311Sjmallettstatic int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 320210311Sjmallettstatic vm_offset_t pmap_kmem_choose(vm_offset_t addr); 321210311Sjmallettstatic boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 322210311Sjmallettstatic void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 323194140Simp 324210311Sjmallettstatic __inline void pagezero(void *page); 325210311Sjmallett 326194140SimpCTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 327210311SjmallettCTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 328201530Simp 329194140Simp/* 330216320Sgonzo * If you get an error here, then you set KVA_PAGES wrong! See the 331216318Sgonzo * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 332216318Sgonzo * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 333202831Simp */ 334202831SimpCTASSERT(KERNBASE % (1 << 24) == 0); 335202831Simp 336196262Simp 337201530Simp 338201530Simpvoid 339196262Simppd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 340210311Sjmallett{ 341196262Simp vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 342194140Simp 343210311Sjmallett switch (type) { 344210311Sjmallett case SH_PD_SET_VA: 345210311Sjmallett#if 0 346210311Sjmallett xen_queue_pt_update(shadow_pdir_ma, 347210311Sjmallett xpmap_ptom(val & ~(PG_RW))); 348210311Sjmallett#endif 349210311Sjmallett xen_queue_pt_update(pdir_ma, 350210311Sjmallett xpmap_ptom(val)); 351210311Sjmallett break; 352210311Sjmallett case SH_PD_SET_VA_MA: 353210311Sjmallett#if 0 354201845Simp xen_queue_pt_update(shadow_pdir_ma, 355201881Simp val & ~(PG_RW)); 356202831Simp#endif 357202831Simp xen_queue_pt_update(pdir_ma, val); 358201845Simp break; 359202831Simp case SH_PD_SET_VA_CLEAR: 360200344Simp#if 0 361210311Sjmallett xen_queue_pt_update(shadow_pdir_ma, 0); 362210311Sjmallett#endif 363210311Sjmallett xen_queue_pt_update(pdir_ma, 0); 364210311Sjmallett break; 365210311Sjmallett } 366210311Sjmallett} 367196262Simp 368194140Simp/* 369202831Simp * Move the kernel virtual free pointer to the next 370202831Simp * 4MB. This is used to help improve performance 371202831Simp * by using a large (4MB) page for much of the kernel 372202831Simp * (.text, .data, .bss) 373202831Simp */ 374202831Simpstatic vm_offset_t 375202831Simppmap_kmem_choose(vm_offset_t addr) 376196262Simp{ 377202831Simp vm_offset_t newaddr = addr; 378196262Simp 379196262Simp#ifndef DISABLE_PSE 380196262Simp if (cpu_feature & CPUID_PSE) 381202831Simp newaddr = (addr + PDRMASK) & ~PDRMASK; 382202831Simp#endif 383196262Simp return newaddr; 384196262Simp} 385202850Simp 386202850Simp/* 387202850Simp * Bootstrap the system enough to run with virtual memory. 388196262Simp * 389217518Simp * On the i386 this is called after mapping has already been enabled 390217518Simp * and just syncs the pmap module with what has already been done. 391217518Simp * [We can't call it easily with mapping off since the kernel is not 392210311Sjmallett * mapped with PA == VA, hence we would have to relocate every address 393206721Sjmallett * from the linked base (virtual) address "KERNBASE" to the actual 394217518Simp * (physical) address starting relative to 0] 395206721Sjmallett */ 396206721Sjmallettvoid 397206721Sjmallettpmap_bootstrap(vm_paddr_t firstaddr) 398210311Sjmallett{ 399206721Sjmallett vm_offset_t va; 400210311Sjmallett pt_entry_t *pte, *unused; 401206721Sjmallett struct sysmaps *sysmaps; 402210311Sjmallett int i; 403210311Sjmallett 404210311Sjmallett /* 405210311Sjmallett * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 406210311Sjmallett * large. It should instead be correctly calculated in locore.s and 407210311Sjmallett * not based on 'first' (which is a physical address, not a virtual 408210311Sjmallett * address, for the start of unused physical memory). The kernel 409196262Simp * page tables are NOT double mapped and thus should not be included 410196262Simp * in this calculation. 411210311Sjmallett */ 412210311Sjmallett virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 413210311Sjmallett virtual_avail = pmap_kmem_choose(virtual_avail); 414210311Sjmallett 415210311Sjmallett virtual_end = VM_MAX_KERNEL_ADDRESS; 416210311Sjmallett 417210311Sjmallett /* 418210311Sjmallett * Initialize the kernel pmap (which is statically allocated). 419210311Sjmallett */ 420210311Sjmallett PMAP_LOCK_INIT(kernel_pmap); 421210311Sjmallett kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 422210311Sjmallett#ifdef PAE 423210311Sjmallett kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 424210311Sjmallett#endif 425210311Sjmallett CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 426215990Sjmallett TAILQ_INIT(&kernel_pmap->pm_pvchunk); 427215990Sjmallett LIST_INIT(&allpmaps); 428215990Sjmallett mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 429215990Sjmallett mtx_lock_spin(&allpmaps_lock); 430215990Sjmallett LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 431215990Sjmallett mtx_unlock_spin(&allpmaps_lock); 432215990Sjmallett if (nkpt == 0) 433215990Sjmallett nkpt = NKPT; 434215990Sjmallett 435215990Sjmallett /* 436215990Sjmallett * Reserve some special page table entries/VA space for temporary 437215990Sjmallett * mapping of pages. 438215990Sjmallett */ 439215990Sjmallett#define SYSMAP(c, p, v, n) \ 440215990Sjmallett v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 441215990Sjmallett 442215990Sjmallett va = virtual_avail; 443215990Sjmallett pte = vtopte(va); 444215990Sjmallett 445215990Sjmallett /* 446215990Sjmallett * CMAP1/CMAP2 are used for zeroing and copying pages. 447215990Sjmallett * CMAP3 is used for the idle process page zeroing. 448215990Sjmallett */ 449215990Sjmallett for (i = 0; i < MAXCPU; i++) { 450215990Sjmallett sysmaps = &sysmaps_pcpu[i]; 451215990Sjmallett mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 452215990Sjmallett SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 453215990Sjmallett SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 454215990Sjmallett PT_SET_MA(sysmaps->CADDR1, 0); 455215990Sjmallett PT_SET_MA(sysmaps->CADDR2, 0); 456215990Sjmallett } 457215990Sjmallett SYSMAP(caddr_t, CMAP3, CADDR3, 1) 458215990Sjmallett PT_SET_MA(CADDR3, 0); 459215990Sjmallett 460215990Sjmallett /* 461215990Sjmallett * Crashdump maps. 462215990Sjmallett */ 463215990Sjmallett SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 464215990Sjmallett 465215990Sjmallett /* 466215990Sjmallett * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 467215990Sjmallett */ 468215990Sjmallett SYSMAP(caddr_t, unused, ptvmmap, 1) 469202831Simp 470194140Simp /* 471194140Simp * msgbufp is used to map the system message buffer. 472194140Simp */ 473194140Simp SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 474194140Simp 475194140Simp /* 476194140Simp * ptemap is used for pmap_pte_quick 477194140Simp */ 478194140Simp SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1); 479194140Simp SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1); 480194140Simp 481194140Simp mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 482194140Simp 483194140Simp virtual_avail = va; 484194140Simp 485194140Simp /* 486194140Simp * Leave in place an identity mapping (virt == phys) for the low 1 MB 487194140Simp * physical memory region that is used by the ACPI wakeup code. This 488194140Simp * mapping must not have PG_G set. 489194140Simp */ 490194140Simp#ifndef XEN 491194140Simp /* 492194140Simp * leave here deliberately to show that this is not supported 493194140Simp */ 494194140Simp#ifdef XBOX 495194140Simp /* FIXME: This is gross, but needed for the XBOX. Since we are in such 496194140Simp * an early stadium, we cannot yet neatly map video memory ... :-( 497194140Simp * Better fixes are very welcome! */ 498194140Simp if (!arch_i386_is_xbox) 499200344Simp#endif 500200344Simp for (i = 1; i < NKPT; i++) 501200344Simp PTD[i] = 0; 502194140Simp 503200344Simp /* Initialize the PAT MSR if present. */ 504200344Simp pmap_init_pat(); 505200344Simp 506200344Simp /* Turn on PG_G on kernel page(s) */ 507200344Simp pmap_set_pg(); 508200344Simp#endif 509194140Simp 510200344Simp#ifdef HAMFISTED_LOCKING 511200344Simp mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF); 512200344Simp#endif 513200344Simp} 514200344Simp 515200344Simp/* 516200344Simp * Setup the PAT MSR. 517200344Simp */ 518200344Simpvoid 519200344Simppmap_init_pat(void) 520200344Simp{ 521200344Simp uint64_t pat_msr; 522200344Simp 523200344Simp /* Bail if this CPU doesn't implement PAT. */ 524200344Simp if (!(cpu_feature & CPUID_PAT)) 525200344Simp return; 526200344Simp 527200344Simp if (cpu_vendor_id != CPU_VENDOR_INTEL || 528200344Simp (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 529200344Simp /* 530200344Simp * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 531200344Simp * Program 4 and 5 as WP and WC. 532200344Simp * Leave 6 and 7 as UC and UC-. 533194140Simp */ 534194140Simp pat_msr = rdmsr(MSR_PAT); 535210311Sjmallett pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 536194140Simp pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 537194140Simp PAT_VALUE(5, PAT_WRITE_COMBINING); 538194140Simp pat_works = 1; 539200344Simp } else { 540210311Sjmallett /* 541194140Simp * Due to some Intel errata, we can only safely use the lower 4 542210311Sjmallett * PAT entries. Thus, just replace PAT Index 2 with WC instead 543210311Sjmallett * of UC-. 544204777Sjmallett * 545204777Sjmallett * Intel Pentium III Processor Specification Update 546210311Sjmallett * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 547204777Sjmallett * or Mode C Paging) 548194140Simp * 549194140Simp * Intel Pentium IV Processor Specification Update 550200344Simp * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 551210311Sjmallett */ 552194140Simp pat_msr = rdmsr(MSR_PAT); 553200344Simp pat_msr &= ~PAT_MASK(2); 554200344Simp pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 555210311Sjmallett pat_works = 0; 556210311Sjmallett } 557210311Sjmallett wrmsr(MSR_PAT, pat_msr); 558210311Sjmallett} 559200344Simp 560210311Sjmallett/* 561210311Sjmallett * Initialize a vm_page's machine-dependent fields. 562210311Sjmallett */ 563210311Sjmallettvoid 564210311Sjmallettpmap_page_init(vm_page_t m) 565210311Sjmallett{ 566194140Simp 567215990Sjmallett TAILQ_INIT(&m->md.pv_list); 568210311Sjmallett m->md.pat_mode = PAT_WRITE_BACK; 569210311Sjmallett} 570210311Sjmallett 571210311Sjmallett/* 572228088Sgonzo * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 573228088Sgonzo * Requirements: 574228853Sgonzo * - Must deal with pages in order to ensure that none of the PG_* bits 575228853Sgonzo * are ever set, PG_V in particular. 576228872Sgonzo * - Assumes we can write to ptes without pte_store() atomic ops, even 577228872Sgonzo * on PAE systems. This should be ok. 578232402Sjmallett * - Assumes nothing will ever test these addresses for 0 to indicate 579194140Simp * no mapping instead of correctly checking PG_V. 580194140Simp * - Assumes a vm_offset_t will fit in a pte (true for i386). 581200344Simp * Because PG_V is never set, there can be no mappings to invalidate. 582200344Simp */ 583194140Simpstatic int ptelist_count = 0; 584210311Sjmallettstatic vm_offset_t 585210311Sjmallettpmap_ptelist_alloc(vm_offset_t *head) 586210311Sjmallett{ 587194140Simp vm_offset_t va; 588210311Sjmallett vm_offset_t *phead = (vm_offset_t *)*head; 589210311Sjmallett 590210311Sjmallett if (ptelist_count == 0) { 591210311Sjmallett printf("out of memory!!!!!!\n"); 592210311Sjmallett return (0); /* Out of memory */ 593210311Sjmallett } 594210311Sjmallett ptelist_count--; 595215990Sjmallett va = phead[ptelist_count]; 596210311Sjmallett return (va); 597215990Sjmallett} 598210311Sjmallett 599194140Simpstatic void 600210311Sjmallettpmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 601210311Sjmallett{ 602210311Sjmallett vm_offset_t *phead = (vm_offset_t *)*head; 603210311Sjmallett 604210311Sjmallett phead[ptelist_count++] = va; 605194140Simp} 606210311Sjmallett 607210311Sjmallettstatic void 608210311Sjmallettpmap_ptelist_init(vm_offset_t *head, void *base, int npages) 609194140Simp{ 610202831Simp int i, nstackpages; 611210311Sjmallett vm_offset_t va; 612210311Sjmallett vm_page_t m; 613210311Sjmallett 614210311Sjmallett nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 615210311Sjmallett for (i = 0; i < nstackpages; i++) { 616210311Sjmallett va = (vm_offset_t)base + i * PAGE_SIZE; 617210311Sjmallett m = vm_page_alloc(NULL, i, 618210311Sjmallett VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 619210311Sjmallett VM_ALLOC_ZERO); 620217518Simp pmap_qenter(va, &m, 1); 621217518Simp } 622210311Sjmallett 623210311Sjmallett *head = (vm_offset_t)base; 624217518Simp for (i = npages - 1; i >= nstackpages; i--) { 625217518Simp va = (vm_offset_t)base + i * PAGE_SIZE; 626217518Simp pmap_ptelist_free(head, va); 627217518Simp } 628210311Sjmallett} 629217518Simp 630210311Sjmallett 631217518Simp/* 632210311Sjmallett * Initialize the pmap module. 633217518Simp * Called by vm_init, to initialize any structures that the pmap 634217518Simp * system needs to map virtual memory. 635194140Simp */ 636202831Simpvoid 637pmap_init(void) 638{ 639 vm_page_t mpte; 640 vm_size_t s; 641 int i, pv_npg; 642 643 /* 644 * Initialize the vm page array entries for the kernel pmap's 645 * page table pages. 646 */ 647 for (i = 0; i < nkpt; i++) { 648 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(PTD[i + KPTDI] & PG_FRAME)); 649 KASSERT(mpte >= vm_page_array && 650 mpte < &vm_page_array[vm_page_array_size], 651 ("pmap_init: page table page is out of range")); 652 mpte->pindex = i + KPTDI; 653 mpte->phys_addr = xpmap_mtop(PTD[i + KPTDI] & PG_FRAME); 654 } 655 656 /* 657 * Initialize the address space (zone) for the pv entries. Set a 658 * high water mark so that the system can recover from excessive 659 * numbers of pv entries. 660 */ 661 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 662 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 663 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 664 pv_entry_max = roundup(pv_entry_max, _NPCPV); 665 pv_entry_high_water = 9 * (pv_entry_max / 10); 666 667 /* 668 * Are large page mappings enabled? 669 */ 670 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 671 672 /* 673 * Calculate the size of the pv head table for superpages. 674 */ 675 for (i = 0; phys_avail[i + 1]; i += 2); 676 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 677 678 /* 679 * Allocate memory for the pv head table for superpages. 680 */ 681 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 682 s = round_page(s); 683 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 684 for (i = 0; i < pv_npg; i++) 685 TAILQ_INIT(&pv_table[i].pv_list); 686 687 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 688 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 689 PAGE_SIZE * pv_maxchunks); 690 if (pv_chunkbase == NULL) 691 panic("pmap_init: not enough kvm for pv chunks"); 692 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 693} 694 695 696/*************************************************** 697 * Low level helper routines..... 698 ***************************************************/ 699 700/* 701 * Determine the appropriate bits to set in a PTE or PDE for a specified 702 * caching mode. 703 */ 704int 705pmap_cache_bits(int mode, boolean_t is_pde) 706{ 707 int pat_flag, pat_index, cache_bits; 708 709 /* The PAT bit is different for PTE's and PDE's. */ 710 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 711 712 /* If we don't support PAT, map extended modes to older ones. */ 713 if (!(cpu_feature & CPUID_PAT)) { 714 switch (mode) { 715 case PAT_UNCACHEABLE: 716 case PAT_WRITE_THROUGH: 717 case PAT_WRITE_BACK: 718 break; 719 case PAT_UNCACHED: 720 case PAT_WRITE_COMBINING: 721 case PAT_WRITE_PROTECTED: 722 mode = PAT_UNCACHEABLE; 723 break; 724 } 725 } 726 727 /* Map the caching mode to a PAT index. */ 728 if (pat_works) { 729 switch (mode) { 730 case PAT_UNCACHEABLE: 731 pat_index = 3; 732 break; 733 case PAT_WRITE_THROUGH: 734 pat_index = 1; 735 break; 736 case PAT_WRITE_BACK: 737 pat_index = 0; 738 break; 739 case PAT_UNCACHED: 740 pat_index = 2; 741 break; 742 case PAT_WRITE_COMBINING: 743 pat_index = 5; 744 break; 745 case PAT_WRITE_PROTECTED: 746 pat_index = 4; 747 break; 748 default: 749 panic("Unknown caching mode %d\n", mode); 750 } 751 } else { 752 switch (mode) { 753 case PAT_UNCACHED: 754 case PAT_UNCACHEABLE: 755 case PAT_WRITE_PROTECTED: 756 pat_index = 3; 757 break; 758 case PAT_WRITE_THROUGH: 759 pat_index = 1; 760 break; 761 case PAT_WRITE_BACK: 762 pat_index = 0; 763 break; 764 case PAT_WRITE_COMBINING: 765 pat_index = 2; 766 break; 767 default: 768 panic("Unknown caching mode %d\n", mode); 769 } 770 } 771 772 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 773 cache_bits = 0; 774 if (pat_index & 0x4) 775 cache_bits |= pat_flag; 776 if (pat_index & 0x2) 777 cache_bits |= PG_NC_PCD; 778 if (pat_index & 0x1) 779 cache_bits |= PG_NC_PWT; 780 return (cache_bits); 781} 782#ifdef SMP 783/* 784 * For SMP, these functions have to use the IPI mechanism for coherence. 785 * 786 * N.B.: Before calling any of the following TLB invalidation functions, 787 * the calling processor must ensure that all stores updating a non- 788 * kernel page table are globally performed. Otherwise, another 789 * processor could cache an old, pre-update entry without being 790 * invalidated. This can happen one of two ways: (1) The pmap becomes 791 * active on another processor after its pm_active field is checked by 792 * one of the following functions but before a store updating the page 793 * table is globally performed. (2) The pmap becomes active on another 794 * processor before its pm_active field is checked but due to 795 * speculative loads one of the following functions stills reads the 796 * pmap as inactive on the other processor. 797 * 798 * The kernel page table is exempt because its pm_active field is 799 * immutable. The kernel page table is always active on every 800 * processor. 801 */ 802void 803pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 804{ 805 cpuset_t other_cpus; 806 u_int cpuid; 807 808 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 809 pmap, va); 810 811 sched_pin(); 812 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 813 invlpg(va); 814 smp_invlpg(va); 815 } else { 816 cpuid = PCPU_GET(cpuid); 817 other_cpus = all_cpus; 818 CPU_CLR(cpuid, &other_cpus); 819 if (CPU_ISSET(cpuid, &pmap->pm_active)) 820 invlpg(va); 821 CPU_AND(&other_cpus, &pmap->pm_active); 822 if (!CPU_EMPTY(&other_cpus)) 823 smp_masked_invlpg(other_cpus, va); 824 } 825 sched_unpin(); 826 PT_UPDATES_FLUSH(); 827} 828 829void 830pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 831{ 832 cpuset_t other_cpus; 833 vm_offset_t addr; 834 u_int cpuid; 835 836 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 837 pmap, sva, eva); 838 839 sched_pin(); 840 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 841 for (addr = sva; addr < eva; addr += PAGE_SIZE) 842 invlpg(addr); 843 smp_invlpg_range(sva, eva); 844 } else { 845 cpuid = PCPU_GET(cpuid); 846 other_cpus = all_cpus; 847 CPU_CLR(cpuid, &other_cpus); 848 if (CPU_ISSET(cpuid, &pmap->pm_active)) 849 for (addr = sva; addr < eva; addr += PAGE_SIZE) 850 invlpg(addr); 851 CPU_AND(&other_cpus, &pmap->pm_active); 852 if (!CPU_EMPTY(&other_cpus)) 853 smp_masked_invlpg_range(other_cpus, sva, eva); 854 } 855 sched_unpin(); 856 PT_UPDATES_FLUSH(); 857} 858 859void 860pmap_invalidate_all(pmap_t pmap) 861{ 862 cpuset_t other_cpus; 863 u_int cpuid; 864 865 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 866 867 sched_pin(); 868 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 869 invltlb(); 870 smp_invltlb(); 871 } else { 872 cpuid = PCPU_GET(cpuid); 873 other_cpus = all_cpus; 874 CPU_CLR(cpuid, &other_cpus); 875 if (CPU_ISSET(cpuid, &pmap->pm_active)) 876 invltlb(); 877 CPU_AND(&other_cpus, &pmap->pm_active); 878 if (!CPU_EMPTY(&other_cpus)) 879 smp_masked_invltlb(other_cpus); 880 } 881 sched_unpin(); 882} 883 884void 885pmap_invalidate_cache(void) 886{ 887 888 sched_pin(); 889 wbinvd(); 890 smp_cache_flush(); 891 sched_unpin(); 892} 893#else /* !SMP */ 894/* 895 * Normal, non-SMP, 486+ invalidation functions. 896 * We inline these within pmap.c for speed. 897 */ 898PMAP_INLINE void 899pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 900{ 901 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 902 pmap, va); 903 904 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 905 invlpg(va); 906 PT_UPDATES_FLUSH(); 907} 908 909PMAP_INLINE void 910pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 911{ 912 vm_offset_t addr; 913 914 if (eva - sva > PAGE_SIZE) 915 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 916 pmap, sva, eva); 917 918 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 919 for (addr = sva; addr < eva; addr += PAGE_SIZE) 920 invlpg(addr); 921 PT_UPDATES_FLUSH(); 922} 923 924PMAP_INLINE void 925pmap_invalidate_all(pmap_t pmap) 926{ 927 928 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 929 930 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 931 invltlb(); 932} 933 934PMAP_INLINE void 935pmap_invalidate_cache(void) 936{ 937 938 wbinvd(); 939} 940#endif /* !SMP */ 941 942void 943pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 944{ 945 946 KASSERT((sva & PAGE_MASK) == 0, 947 ("pmap_invalidate_cache_range: sva not page-aligned")); 948 KASSERT((eva & PAGE_MASK) == 0, 949 ("pmap_invalidate_cache_range: eva not page-aligned")); 950 951 if (cpu_feature & CPUID_SS) 952 ; /* If "Self Snoop" is supported, do nothing. */ 953 else if (cpu_feature & CPUID_CLFSH) { 954 955 /* 956 * Otherwise, do per-cache line flush. Use the mfence 957 * instruction to insure that previous stores are 958 * included in the write-back. The processor 959 * propagates flush to other processors in the cache 960 * coherence domain. 961 */ 962 mfence(); 963 for (; sva < eva; sva += cpu_clflush_line_size) 964 clflush(sva); 965 mfence(); 966 } else { 967 968 /* 969 * No targeted cache flush methods are supported by CPU, 970 * globally invalidate cache as a last resort. 971 */ 972 pmap_invalidate_cache(); 973 } 974} 975 976/* 977 * Are we current address space or kernel? N.B. We return FALSE when 978 * a pmap's page table is in use because a kernel thread is borrowing 979 * it. The borrowed page table can change spontaneously, making any 980 * dependence on its continued use subject to a race condition. 981 */ 982static __inline int 983pmap_is_current(pmap_t pmap) 984{ 985 986 return (pmap == kernel_pmap || 987 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 988 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 989} 990 991/* 992 * If the given pmap is not the current or kernel pmap, the returned pte must 993 * be released by passing it to pmap_pte_release(). 994 */ 995pt_entry_t * 996pmap_pte(pmap_t pmap, vm_offset_t va) 997{ 998 pd_entry_t newpf; 999 pd_entry_t *pde; 1000 1001 pde = pmap_pde(pmap, va); 1002 if (*pde & PG_PS) 1003 return (pde); 1004 if (*pde != 0) { 1005 /* are we current address space or kernel? */ 1006 if (pmap_is_current(pmap)) 1007 return (vtopte(va)); 1008 mtx_lock(&PMAP2mutex); 1009 newpf = *pde & PG_FRAME; 1010 if ((*PMAP2 & PG_FRAME) != newpf) { 1011 vm_page_lock_queues(); 1012 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 1013 vm_page_unlock_queues(); 1014 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 1015 pmap, va, (*PMAP2 & 0xffffffff)); 1016 } 1017 1018 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1019 } 1020 return (0); 1021} 1022 1023/* 1024 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1025 * being NULL. 1026 */ 1027static __inline void 1028pmap_pte_release(pt_entry_t *pte) 1029{ 1030 1031 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 1032 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 1033 *PMAP2); 1034 vm_page_lock_queues(); 1035 PT_SET_VA(PMAP2, 0, TRUE); 1036 vm_page_unlock_queues(); 1037 mtx_unlock(&PMAP2mutex); 1038 } 1039} 1040 1041static __inline void 1042invlcaddr(void *caddr) 1043{ 1044 1045 invlpg((u_int)caddr); 1046 PT_UPDATES_FLUSH(); 1047} 1048 1049/* 1050 * Super fast pmap_pte routine best used when scanning 1051 * the pv lists. This eliminates many coarse-grained 1052 * invltlb calls. Note that many of the pv list 1053 * scans are across different pmaps. It is very wasteful 1054 * to do an entire invltlb for checking a single mapping. 1055 * 1056 * If the given pmap is not the current pmap, vm_page_queue_mtx 1057 * must be held and curthread pinned to a CPU. 1058 */ 1059static pt_entry_t * 1060pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1061{ 1062 pd_entry_t newpf; 1063 pd_entry_t *pde; 1064 1065 pde = pmap_pde(pmap, va); 1066 if (*pde & PG_PS) 1067 return (pde); 1068 if (*pde != 0) { 1069 /* are we current address space or kernel? */ 1070 if (pmap_is_current(pmap)) 1071 return (vtopte(va)); 1072 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1073 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1074 newpf = *pde & PG_FRAME; 1075 if ((*PMAP1 & PG_FRAME) != newpf) { 1076 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1077 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1078 pmap, va, (u_long)*PMAP1); 1079 1080#ifdef SMP 1081 PMAP1cpu = PCPU_GET(cpuid); 1082#endif 1083 PMAP1changed++; 1084 } else 1085#ifdef SMP 1086 if (PMAP1cpu != PCPU_GET(cpuid)) { 1087 PMAP1cpu = PCPU_GET(cpuid); 1088 invlcaddr(PADDR1); 1089 PMAP1changedcpu++; 1090 } else 1091#endif 1092 PMAP1unchanged++; 1093 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1094 } 1095 return (0); 1096} 1097 1098/* 1099 * Routine: pmap_extract 1100 * Function: 1101 * Extract the physical page address associated 1102 * with the given map/virtual_address pair. 1103 */ 1104vm_paddr_t 1105pmap_extract(pmap_t pmap, vm_offset_t va) 1106{ 1107 vm_paddr_t rtval; 1108 pt_entry_t *pte; 1109 pd_entry_t pde; 1110 pt_entry_t pteval; 1111 1112 rtval = 0; 1113 PMAP_LOCK(pmap); 1114 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1115 if (pde != 0) { 1116 if ((pde & PG_PS) != 0) { 1117 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1118 PMAP_UNLOCK(pmap); 1119 return rtval; 1120 } 1121 pte = pmap_pte(pmap, va); 1122 pteval = *pte ? xpmap_mtop(*pte) : 0; 1123 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1124 pmap_pte_release(pte); 1125 } 1126 PMAP_UNLOCK(pmap); 1127 return (rtval); 1128} 1129 1130/* 1131 * Routine: pmap_extract_ma 1132 * Function: 1133 * Like pmap_extract, but returns machine address 1134 */ 1135vm_paddr_t 1136pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1137{ 1138 vm_paddr_t rtval; 1139 pt_entry_t *pte; 1140 pd_entry_t pde; 1141 1142 rtval = 0; 1143 PMAP_LOCK(pmap); 1144 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1145 if (pde != 0) { 1146 if ((pde & PG_PS) != 0) { 1147 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1148 PMAP_UNLOCK(pmap); 1149 return rtval; 1150 } 1151 pte = pmap_pte(pmap, va); 1152 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1153 pmap_pte_release(pte); 1154 } 1155 PMAP_UNLOCK(pmap); 1156 return (rtval); 1157} 1158 1159/* 1160 * Routine: pmap_extract_and_hold 1161 * Function: 1162 * Atomically extract and hold the physical page 1163 * with the given pmap and virtual address pair 1164 * if that mapping permits the given protection. 1165 */ 1166vm_page_t 1167pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1168{ 1169 pd_entry_t pde; 1170 pt_entry_t pte; 1171 vm_page_t m; 1172 vm_paddr_t pa; 1173 1174 pa = 0; 1175 m = NULL; 1176 PMAP_LOCK(pmap); 1177retry: 1178 pde = PT_GET(pmap_pde(pmap, va)); 1179 if (pde != 0) { 1180 if (pde & PG_PS) { 1181 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1182 if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) | 1183 (va & PDRMASK), &pa)) 1184 goto retry; 1185 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1186 (va & PDRMASK)); 1187 vm_page_hold(m); 1188 } 1189 } else { 1190 sched_pin(); 1191 pte = PT_GET(pmap_pte_quick(pmap, va)); 1192 if (*PMAP1) 1193 PT_SET_MA(PADDR1, 0); 1194 if ((pte & PG_V) && 1195 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1196 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa)) 1197 goto retry; 1198 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1199 vm_page_hold(m); 1200 } 1201 sched_unpin(); 1202 } 1203 } 1204 PA_UNLOCK_COND(pa); 1205 PMAP_UNLOCK(pmap); 1206 return (m); 1207} 1208 1209/*************************************************** 1210 * Low level mapping routines..... 1211 ***************************************************/ 1212 1213/* 1214 * Add a wired page to the kva. 1215 * Note: not SMP coherent. 1216 */ 1217void 1218pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1219{ 1220 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1221} 1222 1223void 1224pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1225{ 1226 pt_entry_t *pte; 1227 1228 pte = vtopte(va); 1229 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1230} 1231 1232 1233static __inline void 1234pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1235{ 1236 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1237} 1238 1239/* 1240 * Remove a page from the kernel pagetables. 1241 * Note: not SMP coherent. 1242 */ 1243PMAP_INLINE void 1244pmap_kremove(vm_offset_t va) 1245{ 1246 pt_entry_t *pte; 1247 1248 pte = vtopte(va); 1249 PT_CLEAR_VA(pte, FALSE); 1250} 1251 1252/* 1253 * Used to map a range of physical addresses into kernel 1254 * virtual address space. 1255 * 1256 * The value passed in '*virt' is a suggested virtual address for 1257 * the mapping. Architectures which can support a direct-mapped 1258 * physical to virtual region can return the appropriate address 1259 * within that region, leaving '*virt' unchanged. Other 1260 * architectures should map the pages starting at '*virt' and 1261 * update '*virt' with the first usable address after the mapped 1262 * region. 1263 */ 1264vm_offset_t 1265pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1266{ 1267 vm_offset_t va, sva; 1268 1269 va = sva = *virt; 1270 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1271 va, start, end, prot); 1272 while (start < end) { 1273 pmap_kenter(va, start); 1274 va += PAGE_SIZE; 1275 start += PAGE_SIZE; 1276 } 1277 pmap_invalidate_range(kernel_pmap, sva, va); 1278 *virt = va; 1279 return (sva); 1280} 1281 1282 1283/* 1284 * Add a list of wired pages to the kva 1285 * this routine is only used for temporary 1286 * kernel mappings that do not need to have 1287 * page modification or references recorded. 1288 * Note that old mappings are simply written 1289 * over. The page *must* be wired. 1290 * Note: SMP coherent. Uses a ranged shootdown IPI. 1291 */ 1292void 1293pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1294{ 1295 pt_entry_t *endpte, *pte; 1296 vm_paddr_t pa; 1297 vm_offset_t va = sva; 1298 int mclcount = 0; 1299 multicall_entry_t mcl[16]; 1300 multicall_entry_t *mclp = mcl; 1301 int error; 1302 1303 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1304 pte = vtopte(sva); 1305 endpte = pte + count; 1306 while (pte < endpte) { 1307 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1308 1309 mclp->op = __HYPERVISOR_update_va_mapping; 1310 mclp->args[0] = va; 1311 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1312 mclp->args[2] = (uint32_t)(pa >> 32); 1313 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1314 1315 va += PAGE_SIZE; 1316 pte++; 1317 ma++; 1318 mclp++; 1319 mclcount++; 1320 if (mclcount == 16) { 1321 error = HYPERVISOR_multicall(mcl, mclcount); 1322 mclp = mcl; 1323 mclcount = 0; 1324 KASSERT(error == 0, ("bad multicall %d", error)); 1325 } 1326 } 1327 if (mclcount) { 1328 error = HYPERVISOR_multicall(mcl, mclcount); 1329 KASSERT(error == 0, ("bad multicall %d", error)); 1330 } 1331 1332#ifdef INVARIANTS 1333 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1334 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1335#endif 1336} 1337 1338 1339/* 1340 * This routine tears out page mappings from the 1341 * kernel -- it is meant only for temporary mappings. 1342 * Note: SMP coherent. Uses a ranged shootdown IPI. 1343 */ 1344void 1345pmap_qremove(vm_offset_t sva, int count) 1346{ 1347 vm_offset_t va; 1348 1349 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1350 va = sva; 1351 vm_page_lock_queues(); 1352 critical_enter(); 1353 while (count-- > 0) { 1354 pmap_kremove(va); 1355 va += PAGE_SIZE; 1356 } 1357 PT_UPDATES_FLUSH(); 1358 pmap_invalidate_range(kernel_pmap, sva, va); 1359 critical_exit(); 1360 vm_page_unlock_queues(); 1361} 1362 1363/*************************************************** 1364 * Page table page management routines..... 1365 ***************************************************/ 1366static __inline void 1367pmap_free_zero_pages(vm_page_t free) 1368{ 1369 vm_page_t m; 1370 1371 while (free != NULL) { 1372 m = free; 1373 free = m->right; 1374 vm_page_free_zero(m); 1375 } 1376} 1377 1378/* 1379 * This routine unholds page table pages, and if the hold count 1380 * drops to zero, then it decrements the wire count. 1381 */ 1382static __inline int 1383pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1384{ 1385 1386 --m->wire_count; 1387 if (m->wire_count == 0) 1388 return _pmap_unwire_pte_hold(pmap, m, free); 1389 else 1390 return 0; 1391} 1392 1393static int 1394_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1395{ 1396 vm_offset_t pteva; 1397 1398 PT_UPDATES_FLUSH(); 1399 /* 1400 * unmap the page table page 1401 */ 1402 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1403 /* 1404 * page *might* contain residual mapping :-/ 1405 */ 1406 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1407 pmap_zero_page(m); 1408 --pmap->pm_stats.resident_count; 1409 1410 /* 1411 * This is a release store so that the ordinary store unmapping 1412 * the page table page is globally performed before TLB shoot- 1413 * down is begun. 1414 */ 1415 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1416 1417 /* 1418 * Do an invltlb to make the invalidated mapping 1419 * take effect immediately. 1420 */ 1421 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1422 pmap_invalidate_page(pmap, pteva); 1423 1424 /* 1425 * Put page on a list so that it is released after 1426 * *ALL* TLB shootdown is done 1427 */ 1428 m->right = *free; 1429 *free = m; 1430 1431 return 1; 1432} 1433 1434/* 1435 * After removing a page table entry, this routine is used to 1436 * conditionally free the page, and manage the hold/wire counts. 1437 */ 1438static int 1439pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1440{ 1441 pd_entry_t ptepde; 1442 vm_page_t mpte; 1443 1444 if (va >= VM_MAXUSER_ADDRESS) 1445 return 0; 1446 ptepde = PT_GET(pmap_pde(pmap, va)); 1447 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1448 return pmap_unwire_pte_hold(pmap, mpte, free); 1449} 1450 1451void 1452pmap_pinit0(pmap_t pmap) 1453{ 1454 1455 PMAP_LOCK_INIT(pmap); 1456 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1457#ifdef PAE 1458 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1459#endif 1460 CPU_ZERO(&pmap->pm_active); 1461 PCPU_SET(curpmap, pmap); 1462 TAILQ_INIT(&pmap->pm_pvchunk); 1463 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1464 mtx_lock_spin(&allpmaps_lock); 1465 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1466 mtx_unlock_spin(&allpmaps_lock); 1467} 1468 1469/* 1470 * Initialize a preallocated and zeroed pmap structure, 1471 * such as one in a vmspace structure. 1472 */ 1473int 1474pmap_pinit(pmap_t pmap) 1475{ 1476 vm_page_t m, ptdpg[NPGPTD + 1]; 1477 int npgptd = NPGPTD + 1; 1478 static int color; 1479 int i; 1480 1481#ifdef HAMFISTED_LOCKING 1482 mtx_lock(&createdelete_lock); 1483#endif 1484 1485 PMAP_LOCK_INIT(pmap); 1486 1487 /* 1488 * No need to allocate page table space yet but we do need a valid 1489 * page directory table. 1490 */ 1491 if (pmap->pm_pdir == NULL) { 1492 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1493 NBPTD); 1494 if (pmap->pm_pdir == NULL) { 1495 PMAP_LOCK_DESTROY(pmap); 1496#ifdef HAMFISTED_LOCKING 1497 mtx_unlock(&createdelete_lock); 1498#endif 1499 return (0); 1500 } 1501#ifdef PAE 1502 pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1503#endif 1504 } 1505 1506 /* 1507 * allocate the page directory page(s) 1508 */ 1509 for (i = 0; i < npgptd;) { 1510 m = vm_page_alloc(NULL, color++, 1511 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1512 VM_ALLOC_ZERO); 1513 if (m == NULL) 1514 VM_WAIT; 1515 else { 1516 ptdpg[i++] = m; 1517 } 1518 } 1519 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1520 for (i = 0; i < NPGPTD; i++) { 1521 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1522 pagezero(&pmap->pm_pdir[i*NPTEPG]); 1523 } 1524 1525 mtx_lock_spin(&allpmaps_lock); 1526 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1527 mtx_unlock_spin(&allpmaps_lock); 1528 /* Wire in kernel global address entries. */ 1529 1530 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1531#ifdef PAE 1532 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1533 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1534 bzero(pmap->pm_pdpt, PAGE_SIZE); 1535 for (i = 0; i < NPGPTD; i++) { 1536 vm_paddr_t ma; 1537 1538 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1539 pmap->pm_pdpt[i] = ma | PG_V; 1540 1541 } 1542#endif 1543 for (i = 0; i < NPGPTD; i++) { 1544 pt_entry_t *pd; 1545 vm_paddr_t ma; 1546 1547 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1548 pd = pmap->pm_pdir + (i * NPDEPG); 1549 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1550#if 0 1551 xen_pgd_pin(ma); 1552#endif 1553 } 1554 1555#ifdef PAE 1556 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1557#endif 1558 vm_page_lock_queues(); 1559 xen_flush_queue(); 1560 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1561 for (i = 0; i < NPGPTD; i++) { 1562 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1563 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1564 } 1565 xen_flush_queue(); 1566 vm_page_unlock_queues(); 1567 CPU_ZERO(&pmap->pm_active); 1568 TAILQ_INIT(&pmap->pm_pvchunk); 1569 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1570 1571#ifdef HAMFISTED_LOCKING 1572 mtx_unlock(&createdelete_lock); 1573#endif 1574 return (1); 1575} 1576 1577/* 1578 * this routine is called if the page table page is not 1579 * mapped correctly. 1580 */ 1581static vm_page_t 1582_pmap_allocpte(pmap_t pmap, unsigned int ptepindex, int flags) 1583{ 1584 vm_paddr_t ptema; 1585 vm_page_t m; 1586 1587 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1588 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1589 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1590 1591 /* 1592 * Allocate a page table page. 1593 */ 1594 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1595 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1596 if (flags & M_WAITOK) { 1597 PMAP_UNLOCK(pmap); 1598 vm_page_unlock_queues(); 1599 VM_WAIT; 1600 vm_page_lock_queues(); 1601 PMAP_LOCK(pmap); 1602 } 1603 1604 /* 1605 * Indicate the need to retry. While waiting, the page table 1606 * page may have been allocated. 1607 */ 1608 return (NULL); 1609 } 1610 if ((m->flags & PG_ZERO) == 0) 1611 pmap_zero_page(m); 1612 1613 /* 1614 * Map the pagetable page into the process address space, if 1615 * it isn't already there. 1616 */ 1617 pmap->pm_stats.resident_count++; 1618 1619 ptema = VM_PAGE_TO_MACH(m); 1620 xen_pt_pin(ptema); 1621 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1622 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1623 1624 KASSERT(pmap->pm_pdir[ptepindex], 1625 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1626 return (m); 1627} 1628 1629static vm_page_t 1630pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1631{ 1632 unsigned ptepindex; 1633 pd_entry_t ptema; 1634 vm_page_t m; 1635 1636 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1637 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1638 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1639 1640 /* 1641 * Calculate pagetable page index 1642 */ 1643 ptepindex = va >> PDRSHIFT; 1644retry: 1645 /* 1646 * Get the page directory entry 1647 */ 1648 ptema = pmap->pm_pdir[ptepindex]; 1649 1650 /* 1651 * This supports switching from a 4MB page to a 1652 * normal 4K page. 1653 */ 1654 if (ptema & PG_PS) { 1655 /* 1656 * XXX 1657 */ 1658 pmap->pm_pdir[ptepindex] = 0; 1659 ptema = 0; 1660 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1661 pmap_invalidate_all(kernel_pmap); 1662 } 1663 1664 /* 1665 * If the page table page is mapped, we just increment the 1666 * hold count, and activate it. 1667 */ 1668 if (ptema & PG_V) { 1669 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1670 m->wire_count++; 1671 } else { 1672 /* 1673 * Here if the pte page isn't mapped, or if it has 1674 * been deallocated. 1675 */ 1676 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1677 pmap, va, flags); 1678 m = _pmap_allocpte(pmap, ptepindex, flags); 1679 if (m == NULL && (flags & M_WAITOK)) 1680 goto retry; 1681 1682 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1683 } 1684 return (m); 1685} 1686 1687 1688/*************************************************** 1689* Pmap allocation/deallocation routines. 1690 ***************************************************/ 1691 1692#ifdef SMP 1693/* 1694 * Deal with a SMP shootdown of other users of the pmap that we are 1695 * trying to dispose of. This can be a bit hairy. 1696 */ 1697static cpuset_t *lazymask; 1698static u_int lazyptd; 1699static volatile u_int lazywait; 1700 1701void pmap_lazyfix_action(void); 1702 1703void 1704pmap_lazyfix_action(void) 1705{ 1706 1707#ifdef COUNT_IPIS 1708 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1709#endif 1710 if (rcr3() == lazyptd) 1711 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1712 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1713 atomic_store_rel_int(&lazywait, 1); 1714} 1715 1716static void 1717pmap_lazyfix_self(u_int cpuid) 1718{ 1719 1720 if (rcr3() == lazyptd) 1721 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1722 CPU_CLR_ATOMIC(cpuid, lazymask); 1723} 1724 1725 1726static void 1727pmap_lazyfix(pmap_t pmap) 1728{ 1729 cpuset_t mymask, mask; 1730 u_int cpuid, spins; 1731 int lsb; 1732 1733 mask = pmap->pm_active; 1734 while (!CPU_EMPTY(&mask)) { 1735 spins = 50000000; 1736 1737 /* Find least significant set bit. */ 1738 lsb = cpusetobj_ffs(&mask); 1739 MPASS(lsb != 0); 1740 lsb--; 1741 CPU_SETOF(lsb, &mask); 1742 mtx_lock_spin(&smp_ipi_mtx); 1743#ifdef PAE 1744 lazyptd = vtophys(pmap->pm_pdpt); 1745#else 1746 lazyptd = vtophys(pmap->pm_pdir); 1747#endif 1748 cpuid = PCPU_GET(cpuid); 1749 1750 /* Use a cpuset just for having an easy check. */ 1751 CPU_SETOF(cpuid, &mymask); 1752 if (!CPU_CMP(&mask, &mymask)) { 1753 lazymask = &pmap->pm_active; 1754 pmap_lazyfix_self(cpuid); 1755 } else { 1756 atomic_store_rel_int((u_int *)&lazymask, 1757 (u_int)&pmap->pm_active); 1758 atomic_store_rel_int(&lazywait, 0); 1759 ipi_selected(mask, IPI_LAZYPMAP); 1760 while (lazywait == 0) { 1761 ia32_pause(); 1762 if (--spins == 0) 1763 break; 1764 } 1765 } 1766 mtx_unlock_spin(&smp_ipi_mtx); 1767 if (spins == 0) 1768 printf("pmap_lazyfix: spun for 50000000\n"); 1769 mask = pmap->pm_active; 1770 } 1771} 1772 1773#else /* SMP */ 1774 1775/* 1776 * Cleaning up on uniprocessor is easy. For various reasons, we're 1777 * unlikely to have to even execute this code, including the fact 1778 * that the cleanup is deferred until the parent does a wait(2), which 1779 * means that another userland process has run. 1780 */ 1781static void 1782pmap_lazyfix(pmap_t pmap) 1783{ 1784 u_int cr3; 1785 1786 cr3 = vtophys(pmap->pm_pdir); 1787 if (cr3 == rcr3()) { 1788 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1789 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 1790 } 1791} 1792#endif /* SMP */ 1793 1794/* 1795 * Release any resources held by the given physical map. 1796 * Called when a pmap initialized by pmap_pinit is being released. 1797 * Should only be called if the map contains no valid mappings. 1798 */ 1799void 1800pmap_release(pmap_t pmap) 1801{ 1802 vm_page_t m, ptdpg[2*NPGPTD+1]; 1803 vm_paddr_t ma; 1804 int i; 1805#ifdef PAE 1806 int npgptd = NPGPTD + 1; 1807#else 1808 int npgptd = NPGPTD; 1809#endif 1810 KASSERT(pmap->pm_stats.resident_count == 0, 1811 ("pmap_release: pmap resident count %ld != 0", 1812 pmap->pm_stats.resident_count)); 1813 PT_UPDATES_FLUSH(); 1814 1815#ifdef HAMFISTED_LOCKING 1816 mtx_lock(&createdelete_lock); 1817#endif 1818 1819 pmap_lazyfix(pmap); 1820 mtx_lock_spin(&allpmaps_lock); 1821 LIST_REMOVE(pmap, pm_list); 1822 mtx_unlock_spin(&allpmaps_lock); 1823 1824 for (i = 0; i < NPGPTD; i++) 1825 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1826 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1827#ifdef PAE 1828 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1829#endif 1830 1831 for (i = 0; i < npgptd; i++) { 1832 m = ptdpg[i]; 1833 ma = VM_PAGE_TO_MACH(m); 1834 /* unpinning L1 and L2 treated the same */ 1835#if 0 1836 xen_pgd_unpin(ma); 1837#else 1838 if (i == NPGPTD) 1839 xen_pgd_unpin(ma); 1840#endif 1841#ifdef PAE 1842 if (i < NPGPTD) 1843 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1844 ("pmap_release: got wrong ptd page")); 1845#endif 1846 m->wire_count--; 1847 atomic_subtract_int(&cnt.v_wire_count, 1); 1848 vm_page_free(m); 1849 } 1850#ifdef PAE 1851 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1852#endif 1853 PMAP_LOCK_DESTROY(pmap); 1854 1855#ifdef HAMFISTED_LOCKING 1856 mtx_unlock(&createdelete_lock); 1857#endif 1858} 1859 1860static int 1861kvm_size(SYSCTL_HANDLER_ARGS) 1862{ 1863 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1864 1865 return sysctl_handle_long(oidp, &ksize, 0, req); 1866} 1867SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1868 0, 0, kvm_size, "IU", "Size of KVM"); 1869 1870static int 1871kvm_free(SYSCTL_HANDLER_ARGS) 1872{ 1873 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1874 1875 return sysctl_handle_long(oidp, &kfree, 0, req); 1876} 1877SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1878 0, 0, kvm_free, "IU", "Amount of KVM free"); 1879 1880/* 1881 * grow the number of kernel page table entries, if needed 1882 */ 1883void 1884pmap_growkernel(vm_offset_t addr) 1885{ 1886 struct pmap *pmap; 1887 vm_paddr_t ptppaddr; 1888 vm_page_t nkpg; 1889 pd_entry_t newpdir; 1890 1891 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1892 if (kernel_vm_end == 0) { 1893 kernel_vm_end = KERNBASE; 1894 nkpt = 0; 1895 while (pdir_pde(PTD, kernel_vm_end)) { 1896 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1897 nkpt++; 1898 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1899 kernel_vm_end = kernel_map->max_offset; 1900 break; 1901 } 1902 } 1903 } 1904 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1905 if (addr - 1 >= kernel_map->max_offset) 1906 addr = kernel_map->max_offset; 1907 while (kernel_vm_end < addr) { 1908 if (pdir_pde(PTD, kernel_vm_end)) { 1909 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1910 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1911 kernel_vm_end = kernel_map->max_offset; 1912 break; 1913 } 1914 continue; 1915 } 1916 1917 /* 1918 * This index is bogus, but out of the way 1919 */ 1920 nkpg = vm_page_alloc(NULL, nkpt, 1921 VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED); 1922 if (!nkpg) 1923 panic("pmap_growkernel: no memory to grow kernel"); 1924 1925 nkpt++; 1926 1927 pmap_zero_page(nkpg); 1928 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1929 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1930 vm_page_lock_queues(); 1931 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1932 mtx_lock_spin(&allpmaps_lock); 1933 LIST_FOREACH(pmap, &allpmaps, pm_list) 1934 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1935 1936 mtx_unlock_spin(&allpmaps_lock); 1937 vm_page_unlock_queues(); 1938 1939 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1940 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1941 kernel_vm_end = kernel_map->max_offset; 1942 break; 1943 } 1944 } 1945} 1946 1947 1948/*************************************************** 1949 * page management routines. 1950 ***************************************************/ 1951 1952CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1953CTASSERT(_NPCM == 11); 1954 1955static __inline struct pv_chunk * 1956pv_to_chunk(pv_entry_t pv) 1957{ 1958 1959 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1960} 1961 1962#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1963 1964#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1965#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1966 1967static uint32_t pc_freemask[11] = { 1968 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1969 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1970 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1971 PC_FREE0_9, PC_FREE10 1972}; 1973 1974SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1975 "Current number of pv entries"); 1976 1977#ifdef PV_STATS 1978static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1979 1980SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1981 "Current number of pv entry chunks"); 1982SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1983 "Current number of pv entry chunks allocated"); 1984SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1985 "Current number of pv entry chunks frees"); 1986SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1987 "Number of times tried to get a chunk page but failed."); 1988 1989static long pv_entry_frees, pv_entry_allocs; 1990static int pv_entry_spare; 1991 1992SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1993 "Current number of pv entry frees"); 1994SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1995 "Current number of pv entry allocs"); 1996SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1997 "Current number of spare pv entries"); 1998 1999static int pmap_collect_inactive, pmap_collect_active; 2000 2001SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 2002 "Current number times pmap_collect called on inactive queue"); 2003SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 2004 "Current number times pmap_collect called on active queue"); 2005#endif 2006 2007/* 2008 * We are in a serious low memory condition. Resort to 2009 * drastic measures to free some pages so we can allocate 2010 * another pv entry chunk. This is normally called to 2011 * unmap inactive pages, and if necessary, active pages. 2012 */ 2013static void 2014pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 2015{ 2016 pmap_t pmap; 2017 pt_entry_t *pte, tpte; 2018 pv_entry_t next_pv, pv; 2019 vm_offset_t va; 2020 vm_page_t m, free; 2021 2022 sched_pin(); 2023 TAILQ_FOREACH(m, &vpq->pl, pageq) { 2024 if ((m->flags & PG_MARKER) != 0 || m->hold_count || m->busy) 2025 continue; 2026 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 2027 va = pv->pv_va; 2028 pmap = PV_PMAP(pv); 2029 /* Avoid deadlock and lock recursion. */ 2030 if (pmap > locked_pmap) 2031 PMAP_LOCK(pmap); 2032 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 2033 continue; 2034 pmap->pm_stats.resident_count--; 2035 pte = pmap_pte_quick(pmap, va); 2036 tpte = pte_load_clear(pte); 2037 KASSERT((tpte & PG_W) == 0, 2038 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2039 if (tpte & PG_A) 2040 vm_page_flag_set(m, PG_REFERENCED); 2041 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2042 vm_page_dirty(m); 2043 free = NULL; 2044 pmap_unuse_pt(pmap, va, &free); 2045 pmap_invalidate_page(pmap, va); 2046 pmap_free_zero_pages(free); 2047 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2048 free_pv_entry(pmap, pv); 2049 if (pmap != locked_pmap) 2050 PMAP_UNLOCK(pmap); 2051 } 2052 if (TAILQ_EMPTY(&m->md.pv_list)) 2053 vm_page_flag_clear(m, PG_WRITEABLE); 2054 } 2055 sched_unpin(); 2056} 2057 2058 2059/* 2060 * free the pv_entry back to the free list 2061 */ 2062static void 2063free_pv_entry(pmap_t pmap, pv_entry_t pv) 2064{ 2065 vm_page_t m; 2066 struct pv_chunk *pc; 2067 int idx, field, bit; 2068 2069 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2070 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2071 PV_STAT(pv_entry_frees++); 2072 PV_STAT(pv_entry_spare++); 2073 pv_entry_count--; 2074 pc = pv_to_chunk(pv); 2075 idx = pv - &pc->pc_pventry[0]; 2076 field = idx / 32; 2077 bit = idx % 32; 2078 pc->pc_map[field] |= 1ul << bit; 2079 /* move to head of list */ 2080 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2081 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2082 for (idx = 0; idx < _NPCM; idx++) 2083 if (pc->pc_map[idx] != pc_freemask[idx]) 2084 return; 2085 PV_STAT(pv_entry_spare -= _NPCPV); 2086 PV_STAT(pc_chunk_count--); 2087 PV_STAT(pc_chunk_frees++); 2088 /* entire chunk is free, return it */ 2089 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2090 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2091 pmap_qremove((vm_offset_t)pc, 1); 2092 vm_page_unwire(m, 0); 2093 vm_page_free(m); 2094 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2095} 2096 2097/* 2098 * get a new pv_entry, allocating a block from the system 2099 * when needed. 2100 */ 2101static pv_entry_t 2102get_pv_entry(pmap_t pmap, int try) 2103{ 2104 static const struct timeval printinterval = { 60, 0 }; 2105 static struct timeval lastprint; 2106 static vm_pindex_t colour; 2107 struct vpgqueues *pq; 2108 int bit, field; 2109 pv_entry_t pv; 2110 struct pv_chunk *pc; 2111 vm_page_t m; 2112 2113 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2114 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2115 PV_STAT(pv_entry_allocs++); 2116 pv_entry_count++; 2117 if (pv_entry_count > pv_entry_high_water) 2118 if (ratecheck(&lastprint, &printinterval)) 2119 printf("Approaching the limit on PV entries, consider " 2120 "increasing either the vm.pmap.shpgperproc or the " 2121 "vm.pmap.pv_entry_max tunable.\n"); 2122 pq = NULL; 2123retry: 2124 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2125 if (pc != NULL) { 2126 for (field = 0; field < _NPCM; field++) { 2127 if (pc->pc_map[field]) { 2128 bit = bsfl(pc->pc_map[field]); 2129 break; 2130 } 2131 } 2132 if (field < _NPCM) { 2133 pv = &pc->pc_pventry[field * 32 + bit]; 2134 pc->pc_map[field] &= ~(1ul << bit); 2135 /* If this was the last item, move it to tail */ 2136 for (field = 0; field < _NPCM; field++) 2137 if (pc->pc_map[field] != 0) { 2138 PV_STAT(pv_entry_spare--); 2139 return (pv); /* not full, return */ 2140 } 2141 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2142 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2143 PV_STAT(pv_entry_spare--); 2144 return (pv); 2145 } 2146 } 2147 /* 2148 * Access to the ptelist "pv_vafree" is synchronized by the page 2149 * queues lock. If "pv_vafree" is currently non-empty, it will 2150 * remain non-empty until pmap_ptelist_alloc() completes. 2151 */ 2152 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2153 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2154 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2155 if (try) { 2156 pv_entry_count--; 2157 PV_STAT(pc_chunk_tryfail++); 2158 return (NULL); 2159 } 2160 /* 2161 * Reclaim pv entries: At first, destroy mappings to 2162 * inactive pages. After that, if a pv chunk entry 2163 * is still needed, destroy mappings to active pages. 2164 */ 2165 if (pq == NULL) { 2166 PV_STAT(pmap_collect_inactive++); 2167 pq = &vm_page_queues[PQ_INACTIVE]; 2168 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2169 PV_STAT(pmap_collect_active++); 2170 pq = &vm_page_queues[PQ_ACTIVE]; 2171 } else 2172 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2173 pmap_collect(pmap, pq); 2174 goto retry; 2175 } 2176 PV_STAT(pc_chunk_count++); 2177 PV_STAT(pc_chunk_allocs++); 2178 colour++; 2179 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2180 pmap_qenter((vm_offset_t)pc, &m, 1); 2181 if ((m->flags & PG_ZERO) == 0) 2182 pagezero(pc); 2183 pc->pc_pmap = pmap; 2184 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2185 for (field = 1; field < _NPCM; field++) 2186 pc->pc_map[field] = pc_freemask[field]; 2187 pv = &pc->pc_pventry[0]; 2188 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2189 PV_STAT(pv_entry_spare += _NPCPV - 1); 2190 return (pv); 2191} 2192 2193static __inline pv_entry_t 2194pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2195{ 2196 pv_entry_t pv; 2197 2198 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2199 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2200 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2201 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2202 break; 2203 } 2204 } 2205 return (pv); 2206} 2207 2208static void 2209pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2210{ 2211 pv_entry_t pv; 2212 2213 pv = pmap_pvh_remove(pvh, pmap, va); 2214 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2215 free_pv_entry(pmap, pv); 2216} 2217 2218static void 2219pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2220{ 2221 2222 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2223 pmap_pvh_free(&m->md, pmap, va); 2224 if (TAILQ_EMPTY(&m->md.pv_list)) 2225 vm_page_flag_clear(m, PG_WRITEABLE); 2226} 2227 2228/* 2229 * Conditionally create a pv entry. 2230 */ 2231static boolean_t 2232pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2233{ 2234 pv_entry_t pv; 2235 2236 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2237 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2238 if (pv_entry_count < pv_entry_high_water && 2239 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2240 pv->pv_va = va; 2241 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2242 return (TRUE); 2243 } else 2244 return (FALSE); 2245} 2246 2247/* 2248 * pmap_remove_pte: do the things to unmap a page in a process 2249 */ 2250static int 2251pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2252{ 2253 pt_entry_t oldpte; 2254 vm_page_t m; 2255 2256 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2257 pmap, (u_long)*ptq, va); 2258 2259 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2260 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2261 oldpte = *ptq; 2262 PT_SET_VA_MA(ptq, 0, TRUE); 2263 if (oldpte & PG_W) 2264 pmap->pm_stats.wired_count -= 1; 2265 /* 2266 * Machines that don't support invlpg, also don't support 2267 * PG_G. 2268 */ 2269 if (oldpte & PG_G) 2270 pmap_invalidate_page(kernel_pmap, va); 2271 pmap->pm_stats.resident_count -= 1; 2272 if (oldpte & PG_MANAGED) { 2273 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2274 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2275 vm_page_dirty(m); 2276 if (oldpte & PG_A) 2277 vm_page_flag_set(m, PG_REFERENCED); 2278 pmap_remove_entry(pmap, m, va); 2279 } 2280 return (pmap_unuse_pt(pmap, va, free)); 2281} 2282 2283/* 2284 * Remove a single page from a process address space 2285 */ 2286static void 2287pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2288{ 2289 pt_entry_t *pte; 2290 2291 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2292 pmap, va); 2293 2294 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2295 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2296 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2297 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2298 return; 2299 pmap_remove_pte(pmap, pte, va, free); 2300 pmap_invalidate_page(pmap, va); 2301 if (*PMAP1) 2302 PT_SET_MA(PADDR1, 0); 2303 2304} 2305 2306/* 2307 * Remove the given range of addresses from the specified map. 2308 * 2309 * It is assumed that the start and end are properly 2310 * rounded to the page size. 2311 */ 2312void 2313pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2314{ 2315 vm_offset_t pdnxt; 2316 pd_entry_t ptpaddr; 2317 pt_entry_t *pte; 2318 vm_page_t free = NULL; 2319 int anyvalid; 2320 2321 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2322 pmap, sva, eva); 2323 2324 /* 2325 * Perform an unsynchronized read. This is, however, safe. 2326 */ 2327 if (pmap->pm_stats.resident_count == 0) 2328 return; 2329 2330 anyvalid = 0; 2331 2332 vm_page_lock_queues(); 2333 sched_pin(); 2334 PMAP_LOCK(pmap); 2335 2336 /* 2337 * special handling of removing one page. a very 2338 * common operation and easy to short circuit some 2339 * code. 2340 */ 2341 if ((sva + PAGE_SIZE == eva) && 2342 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2343 pmap_remove_page(pmap, sva, &free); 2344 goto out; 2345 } 2346 2347 for (; sva < eva; sva = pdnxt) { 2348 unsigned pdirindex; 2349 2350 /* 2351 * Calculate index for next page table. 2352 */ 2353 pdnxt = (sva + NBPDR) & ~PDRMASK; 2354 if (pmap->pm_stats.resident_count == 0) 2355 break; 2356 2357 pdirindex = sva >> PDRSHIFT; 2358 ptpaddr = pmap->pm_pdir[pdirindex]; 2359 2360 /* 2361 * Weed out invalid mappings. Note: we assume that the page 2362 * directory table is always allocated, and in kernel virtual. 2363 */ 2364 if (ptpaddr == 0) 2365 continue; 2366 2367 /* 2368 * Check for large page. 2369 */ 2370 if ((ptpaddr & PG_PS) != 0) { 2371 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2372 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2373 anyvalid = 1; 2374 continue; 2375 } 2376 2377 /* 2378 * Limit our scan to either the end of the va represented 2379 * by the current page table page, or to the end of the 2380 * range being removed. 2381 */ 2382 if (pdnxt > eva) 2383 pdnxt = eva; 2384 2385 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2386 sva += PAGE_SIZE) { 2387 if ((*pte & PG_V) == 0) 2388 continue; 2389 2390 /* 2391 * The TLB entry for a PG_G mapping is invalidated 2392 * by pmap_remove_pte(). 2393 */ 2394 if ((*pte & PG_G) == 0) 2395 anyvalid = 1; 2396 if (pmap_remove_pte(pmap, pte, sva, &free)) 2397 break; 2398 } 2399 } 2400 PT_UPDATES_FLUSH(); 2401 if (*PMAP1) 2402 PT_SET_VA_MA(PMAP1, 0, TRUE); 2403out: 2404 if (anyvalid) 2405 pmap_invalidate_all(pmap); 2406 sched_unpin(); 2407 vm_page_unlock_queues(); 2408 PMAP_UNLOCK(pmap); 2409 pmap_free_zero_pages(free); 2410} 2411 2412/* 2413 * Routine: pmap_remove_all 2414 * Function: 2415 * Removes this physical page from 2416 * all physical maps in which it resides. 2417 * Reflects back modify bits to the pager. 2418 * 2419 * Notes: 2420 * Original versions of this routine were very 2421 * inefficient because they iteratively called 2422 * pmap_remove (slow...) 2423 */ 2424 2425void 2426pmap_remove_all(vm_page_t m) 2427{ 2428 pv_entry_t pv; 2429 pmap_t pmap; 2430 pt_entry_t *pte, tpte; 2431 vm_page_t free; 2432 2433 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2434 ("pmap_remove_all: page %p is not managed", m)); 2435 free = NULL; 2436 vm_page_lock_queues(); 2437 sched_pin(); 2438 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2439 pmap = PV_PMAP(pv); 2440 PMAP_LOCK(pmap); 2441 pmap->pm_stats.resident_count--; 2442 pte = pmap_pte_quick(pmap, pv->pv_va); 2443 2444 tpte = *pte; 2445 PT_SET_VA_MA(pte, 0, TRUE); 2446 if (tpte & PG_W) 2447 pmap->pm_stats.wired_count--; 2448 if (tpte & PG_A) 2449 vm_page_flag_set(m, PG_REFERENCED); 2450 2451 /* 2452 * Update the vm_page_t clean and reference bits. 2453 */ 2454 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2455 vm_page_dirty(m); 2456 pmap_unuse_pt(pmap, pv->pv_va, &free); 2457 pmap_invalidate_page(pmap, pv->pv_va); 2458 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2459 free_pv_entry(pmap, pv); 2460 PMAP_UNLOCK(pmap); 2461 } 2462 vm_page_flag_clear(m, PG_WRITEABLE); 2463 PT_UPDATES_FLUSH(); 2464 if (*PMAP1) 2465 PT_SET_MA(PADDR1, 0); 2466 sched_unpin(); 2467 vm_page_unlock_queues(); 2468 pmap_free_zero_pages(free); 2469} 2470 2471/* 2472 * Set the physical protection on the 2473 * specified range of this map as requested. 2474 */ 2475void 2476pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2477{ 2478 vm_offset_t pdnxt; 2479 pd_entry_t ptpaddr; 2480 pt_entry_t *pte; 2481 int anychanged; 2482 2483 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2484 pmap, sva, eva, prot); 2485 2486 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2487 pmap_remove(pmap, sva, eva); 2488 return; 2489 } 2490 2491#ifdef PAE 2492 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2493 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2494 return; 2495#else 2496 if (prot & VM_PROT_WRITE) 2497 return; 2498#endif 2499 2500 anychanged = 0; 2501 2502 vm_page_lock_queues(); 2503 sched_pin(); 2504 PMAP_LOCK(pmap); 2505 for (; sva < eva; sva = pdnxt) { 2506 pt_entry_t obits, pbits; 2507 unsigned pdirindex; 2508 2509 pdnxt = (sva + NBPDR) & ~PDRMASK; 2510 2511 pdirindex = sva >> PDRSHIFT; 2512 ptpaddr = pmap->pm_pdir[pdirindex]; 2513 2514 /* 2515 * Weed out invalid mappings. Note: we assume that the page 2516 * directory table is always allocated, and in kernel virtual. 2517 */ 2518 if (ptpaddr == 0) 2519 continue; 2520 2521 /* 2522 * Check for large page. 2523 */ 2524 if ((ptpaddr & PG_PS) != 0) { 2525 if ((prot & VM_PROT_WRITE) == 0) 2526 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2527#ifdef PAE 2528 if ((prot & VM_PROT_EXECUTE) == 0) 2529 pmap->pm_pdir[pdirindex] |= pg_nx; 2530#endif 2531 anychanged = 1; 2532 continue; 2533 } 2534 2535 if (pdnxt > eva) 2536 pdnxt = eva; 2537 2538 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2539 sva += PAGE_SIZE) { 2540 vm_page_t m; 2541 2542retry: 2543 /* 2544 * Regardless of whether a pte is 32 or 64 bits in 2545 * size, PG_RW, PG_A, and PG_M are among the least 2546 * significant 32 bits. 2547 */ 2548 obits = pbits = *pte; 2549 if ((pbits & PG_V) == 0) 2550 continue; 2551 2552 if ((prot & VM_PROT_WRITE) == 0) { 2553 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2554 (PG_MANAGED | PG_M | PG_RW)) { 2555 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2556 PG_FRAME); 2557 vm_page_dirty(m); 2558 } 2559 pbits &= ~(PG_RW | PG_M); 2560 } 2561#ifdef PAE 2562 if ((prot & VM_PROT_EXECUTE) == 0) 2563 pbits |= pg_nx; 2564#endif 2565 2566 if (pbits != obits) { 2567 obits = *pte; 2568 PT_SET_VA_MA(pte, pbits, TRUE); 2569 if (*pte != pbits) 2570 goto retry; 2571 if (obits & PG_G) 2572 pmap_invalidate_page(pmap, sva); 2573 else 2574 anychanged = 1; 2575 } 2576 } 2577 } 2578 PT_UPDATES_FLUSH(); 2579 if (*PMAP1) 2580 PT_SET_VA_MA(PMAP1, 0, TRUE); 2581 if (anychanged) 2582 pmap_invalidate_all(pmap); 2583 sched_unpin(); 2584 vm_page_unlock_queues(); 2585 PMAP_UNLOCK(pmap); 2586} 2587 2588/* 2589 * Insert the given physical page (p) at 2590 * the specified virtual address (v) in the 2591 * target physical map with the protection requested. 2592 * 2593 * If specified, the page will be wired down, meaning 2594 * that the related pte can not be reclaimed. 2595 * 2596 * NB: This is the only routine which MAY NOT lazy-evaluate 2597 * or lose information. That is, this routine must actually 2598 * insert this page into the given map NOW. 2599 */ 2600void 2601pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2602 vm_prot_t prot, boolean_t wired) 2603{ 2604 pd_entry_t *pde; 2605 pt_entry_t *pte; 2606 pt_entry_t newpte, origpte; 2607 pv_entry_t pv; 2608 vm_paddr_t opa, pa; 2609 vm_page_t mpte, om; 2610 boolean_t invlva; 2611 2612 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2613 pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2614 va = trunc_page(va); 2615 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2616 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2617 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2618 va)); 2619 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 2620 (m->oflags & VPO_BUSY) != 0, 2621 ("pmap_enter: page %p is not busy", m)); 2622 2623 mpte = NULL; 2624 2625 vm_page_lock_queues(); 2626 PMAP_LOCK(pmap); 2627 sched_pin(); 2628 2629 /* 2630 * In the case that a page table page is not 2631 * resident, we are creating it here. 2632 */ 2633 if (va < VM_MAXUSER_ADDRESS) { 2634 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2635 } 2636 2637 pde = pmap_pde(pmap, va); 2638 if ((*pde & PG_PS) != 0) 2639 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2640 pte = pmap_pte_quick(pmap, va); 2641 2642 /* 2643 * Page Directory table entry not valid, we need a new PT page 2644 */ 2645 if (pte == NULL) { 2646 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2647 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2648 } 2649 2650 pa = VM_PAGE_TO_PHYS(m); 2651 om = NULL; 2652 opa = origpte = 0; 2653 2654#if 0 2655 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2656 pte, *pte)); 2657#endif 2658 origpte = *pte; 2659 if (origpte) 2660 origpte = xpmap_mtop(origpte); 2661 opa = origpte & PG_FRAME; 2662 2663 /* 2664 * Mapping has not changed, must be protection or wiring change. 2665 */ 2666 if (origpte && (opa == pa)) { 2667 /* 2668 * Wiring change, just update stats. We don't worry about 2669 * wiring PT pages as they remain resident as long as there 2670 * are valid mappings in them. Hence, if a user page is wired, 2671 * the PT page will be also. 2672 */ 2673 if (wired && ((origpte & PG_W) == 0)) 2674 pmap->pm_stats.wired_count++; 2675 else if (!wired && (origpte & PG_W)) 2676 pmap->pm_stats.wired_count--; 2677 2678 /* 2679 * Remove extra pte reference 2680 */ 2681 if (mpte) 2682 mpte->wire_count--; 2683 2684 if (origpte & PG_MANAGED) { 2685 om = m; 2686 pa |= PG_MANAGED; 2687 } 2688 goto validate; 2689 } 2690 2691 pv = NULL; 2692 2693 /* 2694 * Mapping has changed, invalidate old range and fall through to 2695 * handle validating new mapping. 2696 */ 2697 if (opa) { 2698 if (origpte & PG_W) 2699 pmap->pm_stats.wired_count--; 2700 if (origpte & PG_MANAGED) { 2701 om = PHYS_TO_VM_PAGE(opa); 2702 pv = pmap_pvh_remove(&om->md, pmap, va); 2703 } else if (va < VM_MAXUSER_ADDRESS) 2704 printf("va=0x%x is unmanaged :-( \n", va); 2705 2706 if (mpte != NULL) { 2707 mpte->wire_count--; 2708 KASSERT(mpte->wire_count > 0, 2709 ("pmap_enter: missing reference to page table page," 2710 " va: 0x%x", va)); 2711 } 2712 } else 2713 pmap->pm_stats.resident_count++; 2714 2715 /* 2716 * Enter on the PV list if part of our managed memory. 2717 */ 2718 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 2719 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2720 ("pmap_enter: managed mapping within the clean submap")); 2721 if (pv == NULL) 2722 pv = get_pv_entry(pmap, FALSE); 2723 pv->pv_va = va; 2724 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2725 pa |= PG_MANAGED; 2726 } else if (pv != NULL) 2727 free_pv_entry(pmap, pv); 2728 2729 /* 2730 * Increment counters 2731 */ 2732 if (wired) 2733 pmap->pm_stats.wired_count++; 2734 2735validate: 2736 /* 2737 * Now validate mapping with desired protection/wiring. 2738 */ 2739 newpte = (pt_entry_t)(pa | PG_V); 2740 if ((prot & VM_PROT_WRITE) != 0) { 2741 newpte |= PG_RW; 2742 if ((newpte & PG_MANAGED) != 0) 2743 vm_page_flag_set(m, PG_WRITEABLE); 2744 } 2745#ifdef PAE 2746 if ((prot & VM_PROT_EXECUTE) == 0) 2747 newpte |= pg_nx; 2748#endif 2749 if (wired) 2750 newpte |= PG_W; 2751 if (va < VM_MAXUSER_ADDRESS) 2752 newpte |= PG_U; 2753 if (pmap == kernel_pmap) 2754 newpte |= pgeflag; 2755 2756 critical_enter(); 2757 /* 2758 * if the mapping or permission bits are different, we need 2759 * to update the pte. 2760 */ 2761 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2762 if (origpte) { 2763 invlva = FALSE; 2764 origpte = *pte; 2765 PT_SET_VA(pte, newpte | PG_A, FALSE); 2766 if (origpte & PG_A) { 2767 if (origpte & PG_MANAGED) 2768 vm_page_flag_set(om, PG_REFERENCED); 2769 if (opa != VM_PAGE_TO_PHYS(m)) 2770 invlva = TRUE; 2771#ifdef PAE 2772 if ((origpte & PG_NX) == 0 && 2773 (newpte & PG_NX) != 0) 2774 invlva = TRUE; 2775#endif 2776 } 2777 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2778 if ((origpte & PG_MANAGED) != 0) 2779 vm_page_dirty(om); 2780 if ((prot & VM_PROT_WRITE) == 0) 2781 invlva = TRUE; 2782 } 2783 if ((origpte & PG_MANAGED) != 0 && 2784 TAILQ_EMPTY(&om->md.pv_list)) 2785 vm_page_flag_clear(om, PG_WRITEABLE); 2786 if (invlva) 2787 pmap_invalidate_page(pmap, va); 2788 } else{ 2789 PT_SET_VA(pte, newpte | PG_A, FALSE); 2790 } 2791 2792 } 2793 PT_UPDATES_FLUSH(); 2794 critical_exit(); 2795 if (*PMAP1) 2796 PT_SET_VA_MA(PMAP1, 0, TRUE); 2797 sched_unpin(); 2798 vm_page_unlock_queues(); 2799 PMAP_UNLOCK(pmap); 2800} 2801 2802/* 2803 * Maps a sequence of resident pages belonging to the same object. 2804 * The sequence begins with the given page m_start. This page is 2805 * mapped at the given virtual address start. Each subsequent page is 2806 * mapped at a virtual address that is offset from start by the same 2807 * amount as the page is offset from m_start within the object. The 2808 * last page in the sequence is the page with the largest offset from 2809 * m_start that can be mapped at a virtual address less than the given 2810 * virtual address end. Not every virtual page between start and end 2811 * is mapped; only those for which a resident page exists with the 2812 * corresponding offset from m_start are mapped. 2813 */ 2814void 2815pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2816 vm_page_t m_start, vm_prot_t prot) 2817{ 2818 vm_page_t m, mpte; 2819 vm_pindex_t diff, psize; 2820 multicall_entry_t mcl[16]; 2821 multicall_entry_t *mclp = mcl; 2822 int error, count = 0; 2823 2824 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2825 psize = atop(end - start); 2826 2827 mpte = NULL; 2828 m = m_start; 2829 vm_page_lock_queues(); 2830 PMAP_LOCK(pmap); 2831 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2832 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2833 prot, mpte); 2834 m = TAILQ_NEXT(m, listq); 2835 if (count == 16) { 2836 error = HYPERVISOR_multicall(mcl, count); 2837 KASSERT(error == 0, ("bad multicall %d", error)); 2838 mclp = mcl; 2839 count = 0; 2840 } 2841 } 2842 if (count) { 2843 error = HYPERVISOR_multicall(mcl, count); 2844 KASSERT(error == 0, ("bad multicall %d", error)); 2845 } 2846 vm_page_unlock_queues(); 2847 PMAP_UNLOCK(pmap); 2848} 2849 2850/* 2851 * this code makes some *MAJOR* assumptions: 2852 * 1. Current pmap & pmap exists. 2853 * 2. Not wired. 2854 * 3. Read access. 2855 * 4. No page table pages. 2856 * but is *MUCH* faster than pmap_enter... 2857 */ 2858 2859void 2860pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2861{ 2862 multicall_entry_t mcl, *mclp; 2863 int count = 0; 2864 mclp = &mcl; 2865 2866 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2867 pmap, va, m, prot); 2868 2869 vm_page_lock_queues(); 2870 PMAP_LOCK(pmap); 2871 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2872 if (count) 2873 HYPERVISOR_multicall(&mcl, count); 2874 vm_page_unlock_queues(); 2875 PMAP_UNLOCK(pmap); 2876} 2877 2878#ifdef notyet 2879void 2880pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2881{ 2882 int i, error, index = 0; 2883 multicall_entry_t mcl[16]; 2884 multicall_entry_t *mclp = mcl; 2885 2886 PMAP_LOCK(pmap); 2887 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2888 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2889 continue; 2890 2891 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2892 if (index == 16) { 2893 error = HYPERVISOR_multicall(mcl, index); 2894 mclp = mcl; 2895 index = 0; 2896 KASSERT(error == 0, ("bad multicall %d", error)); 2897 } 2898 } 2899 if (index) { 2900 error = HYPERVISOR_multicall(mcl, index); 2901 KASSERT(error == 0, ("bad multicall %d", error)); 2902 } 2903 2904 PMAP_UNLOCK(pmap); 2905} 2906#endif 2907 2908static vm_page_t 2909pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2910 vm_prot_t prot, vm_page_t mpte) 2911{ 2912 pt_entry_t *pte; 2913 vm_paddr_t pa; 2914 vm_page_t free; 2915 multicall_entry_t *mcl = *mclpp; 2916 2917 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2918 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 2919 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2920 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2921 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2922 2923 /* 2924 * In the case that a page table page is not 2925 * resident, we are creating it here. 2926 */ 2927 if (va < VM_MAXUSER_ADDRESS) { 2928 unsigned ptepindex; 2929 pd_entry_t ptema; 2930 2931 /* 2932 * Calculate pagetable page index 2933 */ 2934 ptepindex = va >> PDRSHIFT; 2935 if (mpte && (mpte->pindex == ptepindex)) { 2936 mpte->wire_count++; 2937 } else { 2938 /* 2939 * Get the page directory entry 2940 */ 2941 ptema = pmap->pm_pdir[ptepindex]; 2942 2943 /* 2944 * If the page table page is mapped, we just increment 2945 * the hold count, and activate it. 2946 */ 2947 if (ptema & PG_V) { 2948 if (ptema & PG_PS) 2949 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2950 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2951 mpte->wire_count++; 2952 } else { 2953 mpte = _pmap_allocpte(pmap, ptepindex, 2954 M_NOWAIT); 2955 if (mpte == NULL) 2956 return (mpte); 2957 } 2958 } 2959 } else { 2960 mpte = NULL; 2961 } 2962 2963 /* 2964 * This call to vtopte makes the assumption that we are 2965 * entering the page into the current pmap. In order to support 2966 * quick entry into any pmap, one would likely use pmap_pte_quick. 2967 * But that isn't as quick as vtopte. 2968 */ 2969 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 2970 pte = vtopte(va); 2971 if (*pte & PG_V) { 2972 if (mpte != NULL) { 2973 mpte->wire_count--; 2974 mpte = NULL; 2975 } 2976 return (mpte); 2977 } 2978 2979 /* 2980 * Enter on the PV list if part of our managed memory. 2981 */ 2982 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 2983 !pmap_try_insert_pv_entry(pmap, va, m)) { 2984 if (mpte != NULL) { 2985 free = NULL; 2986 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 2987 pmap_invalidate_page(pmap, va); 2988 pmap_free_zero_pages(free); 2989 } 2990 2991 mpte = NULL; 2992 } 2993 return (mpte); 2994 } 2995 2996 /* 2997 * Increment counters 2998 */ 2999 pmap->pm_stats.resident_count++; 3000 3001 pa = VM_PAGE_TO_PHYS(m); 3002#ifdef PAE 3003 if ((prot & VM_PROT_EXECUTE) == 0) 3004 pa |= pg_nx; 3005#endif 3006 3007#if 0 3008 /* 3009 * Now validate mapping with RO protection 3010 */ 3011 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3012 pte_store(pte, pa | PG_V | PG_U); 3013 else 3014 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3015#else 3016 /* 3017 * Now validate mapping with RO protection 3018 */ 3019 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3020 pa = xpmap_ptom(pa | PG_V | PG_U); 3021 else 3022 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3023 3024 mcl->op = __HYPERVISOR_update_va_mapping; 3025 mcl->args[0] = va; 3026 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3027 mcl->args[2] = (uint32_t)(pa >> 32); 3028 mcl->args[3] = 0; 3029 *mclpp = mcl + 1; 3030 *count = *count + 1; 3031#endif 3032 return mpte; 3033} 3034 3035/* 3036 * Make a temporary mapping for a physical address. This is only intended 3037 * to be used for panic dumps. 3038 */ 3039void * 3040pmap_kenter_temporary(vm_paddr_t pa, int i) 3041{ 3042 vm_offset_t va; 3043 vm_paddr_t ma = xpmap_ptom(pa); 3044 3045 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3046 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3047 invlpg(va); 3048 return ((void *)crashdumpmap); 3049} 3050 3051/* 3052 * This code maps large physical mmap regions into the 3053 * processor address space. Note that some shortcuts 3054 * are taken, but the code works. 3055 */ 3056void 3057pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 3058 vm_object_t object, vm_pindex_t pindex, 3059 vm_size_t size) 3060{ 3061 pd_entry_t *pde; 3062 vm_paddr_t pa, ptepa; 3063 vm_page_t p; 3064 int pat_mode; 3065 3066 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3067 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3068 ("pmap_object_init_pt: non-device object")); 3069 if (pseflag && 3070 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3071 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3072 return; 3073 p = vm_page_lookup(object, pindex); 3074 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3075 ("pmap_object_init_pt: invalid page %p", p)); 3076 pat_mode = p->md.pat_mode; 3077 /* 3078 * Abort the mapping if the first page is not physically 3079 * aligned to a 2/4MB page boundary. 3080 */ 3081 ptepa = VM_PAGE_TO_PHYS(p); 3082 if (ptepa & (NBPDR - 1)) 3083 return; 3084 /* 3085 * Skip the first page. Abort the mapping if the rest of 3086 * the pages are not physically contiguous or have differing 3087 * memory attributes. 3088 */ 3089 p = TAILQ_NEXT(p, listq); 3090 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3091 pa += PAGE_SIZE) { 3092 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3093 ("pmap_object_init_pt: invalid page %p", p)); 3094 if (pa != VM_PAGE_TO_PHYS(p) || 3095 pat_mode != p->md.pat_mode) 3096 return; 3097 p = TAILQ_NEXT(p, listq); 3098 } 3099 /* Map using 2/4MB pages. */ 3100 PMAP_LOCK(pmap); 3101 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3102 size; pa += NBPDR) { 3103 pde = pmap_pde(pmap, addr); 3104 if (*pde == 0) { 3105 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3106 PG_U | PG_RW | PG_V); 3107 pmap->pm_stats.resident_count += NBPDR / 3108 PAGE_SIZE; 3109 pmap_pde_mappings++; 3110 } 3111 /* Else continue on if the PDE is already valid. */ 3112 addr += NBPDR; 3113 } 3114 PMAP_UNLOCK(pmap); 3115 } 3116} 3117 3118/* 3119 * Routine: pmap_change_wiring 3120 * Function: Change the wiring attribute for a map/virtual-address 3121 * pair. 3122 * In/out conditions: 3123 * The mapping must already exist in the pmap. 3124 */ 3125void 3126pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3127{ 3128 pt_entry_t *pte; 3129 3130 vm_page_lock_queues(); 3131 PMAP_LOCK(pmap); 3132 pte = pmap_pte(pmap, va); 3133 3134 if (wired && !pmap_pte_w(pte)) { 3135 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3136 pmap->pm_stats.wired_count++; 3137 } else if (!wired && pmap_pte_w(pte)) { 3138 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3139 pmap->pm_stats.wired_count--; 3140 } 3141 3142 /* 3143 * Wiring is not a hardware characteristic so there is no need to 3144 * invalidate TLB. 3145 */ 3146 pmap_pte_release(pte); 3147 PMAP_UNLOCK(pmap); 3148 vm_page_unlock_queues(); 3149} 3150 3151 3152 3153/* 3154 * Copy the range specified by src_addr/len 3155 * from the source map to the range dst_addr/len 3156 * in the destination map. 3157 * 3158 * This routine is only advisory and need not do anything. 3159 */ 3160 3161void 3162pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3163 vm_offset_t src_addr) 3164{ 3165 vm_page_t free; 3166 vm_offset_t addr; 3167 vm_offset_t end_addr = src_addr + len; 3168 vm_offset_t pdnxt; 3169 3170 if (dst_addr != src_addr) 3171 return; 3172 3173 if (!pmap_is_current(src_pmap)) { 3174 CTR2(KTR_PMAP, 3175 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3176 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3177 3178 return; 3179 } 3180 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3181 dst_pmap, src_pmap, dst_addr, len, src_addr); 3182 3183#ifdef HAMFISTED_LOCKING 3184 mtx_lock(&createdelete_lock); 3185#endif 3186 3187 vm_page_lock_queues(); 3188 if (dst_pmap < src_pmap) { 3189 PMAP_LOCK(dst_pmap); 3190 PMAP_LOCK(src_pmap); 3191 } else { 3192 PMAP_LOCK(src_pmap); 3193 PMAP_LOCK(dst_pmap); 3194 } 3195 sched_pin(); 3196 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3197 pt_entry_t *src_pte, *dst_pte; 3198 vm_page_t dstmpte, srcmpte; 3199 pd_entry_t srcptepaddr; 3200 unsigned ptepindex; 3201 3202 KASSERT(addr < UPT_MIN_ADDRESS, 3203 ("pmap_copy: invalid to pmap_copy page tables")); 3204 3205 pdnxt = (addr + NBPDR) & ~PDRMASK; 3206 ptepindex = addr >> PDRSHIFT; 3207 3208 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3209 if (srcptepaddr == 0) 3210 continue; 3211 3212 if (srcptepaddr & PG_PS) { 3213 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3214 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3215 dst_pmap->pm_stats.resident_count += 3216 NBPDR / PAGE_SIZE; 3217 } 3218 continue; 3219 } 3220 3221 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3222 KASSERT(srcmpte->wire_count > 0, 3223 ("pmap_copy: source page table page is unused")); 3224 3225 if (pdnxt > end_addr) 3226 pdnxt = end_addr; 3227 3228 src_pte = vtopte(addr); 3229 while (addr < pdnxt) { 3230 pt_entry_t ptetemp; 3231 ptetemp = *src_pte; 3232 /* 3233 * we only virtual copy managed pages 3234 */ 3235 if ((ptetemp & PG_MANAGED) != 0) { 3236 dstmpte = pmap_allocpte(dst_pmap, addr, 3237 M_NOWAIT); 3238 if (dstmpte == NULL) 3239 break; 3240 dst_pte = pmap_pte_quick(dst_pmap, addr); 3241 if (*dst_pte == 0 && 3242 pmap_try_insert_pv_entry(dst_pmap, addr, 3243 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3244 /* 3245 * Clear the wired, modified, and 3246 * accessed (referenced) bits 3247 * during the copy. 3248 */ 3249 KASSERT(ptetemp != 0, ("src_pte not set")); 3250 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3251 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3252 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3253 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3254 dst_pmap->pm_stats.resident_count++; 3255 } else { 3256 free = NULL; 3257 if (pmap_unwire_pte_hold(dst_pmap, 3258 dstmpte, &free)) { 3259 pmap_invalidate_page(dst_pmap, 3260 addr); 3261 pmap_free_zero_pages(free); 3262 } 3263 } 3264 if (dstmpte->wire_count >= srcmpte->wire_count) 3265 break; 3266 } 3267 addr += PAGE_SIZE; 3268 src_pte++; 3269 } 3270 } 3271 PT_UPDATES_FLUSH(); 3272 sched_unpin(); 3273 vm_page_unlock_queues(); 3274 PMAP_UNLOCK(src_pmap); 3275 PMAP_UNLOCK(dst_pmap); 3276 3277#ifdef HAMFISTED_LOCKING 3278 mtx_unlock(&createdelete_lock); 3279#endif 3280} 3281 3282static __inline void 3283pagezero(void *page) 3284{ 3285#if defined(I686_CPU) 3286 if (cpu_class == CPUCLASS_686) { 3287#if defined(CPU_ENABLE_SSE) 3288 if (cpu_feature & CPUID_SSE2) 3289 sse2_pagezero(page); 3290 else 3291#endif 3292 i686_pagezero(page); 3293 } else 3294#endif 3295 bzero(page, PAGE_SIZE); 3296} 3297 3298/* 3299 * pmap_zero_page zeros the specified hardware page by mapping 3300 * the page into KVM and using bzero to clear its contents. 3301 */ 3302void 3303pmap_zero_page(vm_page_t m) 3304{ 3305 struct sysmaps *sysmaps; 3306 3307 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3308 mtx_lock(&sysmaps->lock); 3309 if (*sysmaps->CMAP2) 3310 panic("pmap_zero_page: CMAP2 busy"); 3311 sched_pin(); 3312 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3313 pagezero(sysmaps->CADDR2); 3314 PT_SET_MA(sysmaps->CADDR2, 0); 3315 sched_unpin(); 3316 mtx_unlock(&sysmaps->lock); 3317} 3318 3319/* 3320 * pmap_zero_page_area zeros the specified hardware page by mapping 3321 * the page into KVM and using bzero to clear its contents. 3322 * 3323 * off and size may not cover an area beyond a single hardware page. 3324 */ 3325void 3326pmap_zero_page_area(vm_page_t m, int off, int size) 3327{ 3328 struct sysmaps *sysmaps; 3329 3330 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3331 mtx_lock(&sysmaps->lock); 3332 if (*sysmaps->CMAP2) 3333 panic("pmap_zero_page: CMAP2 busy"); 3334 sched_pin(); 3335 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3336 3337 if (off == 0 && size == PAGE_SIZE) 3338 pagezero(sysmaps->CADDR2); 3339 else 3340 bzero((char *)sysmaps->CADDR2 + off, size); 3341 PT_SET_MA(sysmaps->CADDR2, 0); 3342 sched_unpin(); 3343 mtx_unlock(&sysmaps->lock); 3344} 3345 3346/* 3347 * pmap_zero_page_idle zeros the specified hardware page by mapping 3348 * the page into KVM and using bzero to clear its contents. This 3349 * is intended to be called from the vm_pagezero process only and 3350 * outside of Giant. 3351 */ 3352void 3353pmap_zero_page_idle(vm_page_t m) 3354{ 3355 3356 if (*CMAP3) 3357 panic("pmap_zero_page: CMAP3 busy"); 3358 sched_pin(); 3359 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3360 pagezero(CADDR3); 3361 PT_SET_MA(CADDR3, 0); 3362 sched_unpin(); 3363} 3364 3365/* 3366 * pmap_copy_page copies the specified (machine independent) 3367 * page by mapping the page into virtual memory and using 3368 * bcopy to copy the page, one machine dependent page at a 3369 * time. 3370 */ 3371void 3372pmap_copy_page(vm_page_t src, vm_page_t dst) 3373{ 3374 struct sysmaps *sysmaps; 3375 3376 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3377 mtx_lock(&sysmaps->lock); 3378 if (*sysmaps->CMAP1) 3379 panic("pmap_copy_page: CMAP1 busy"); 3380 if (*sysmaps->CMAP2) 3381 panic("pmap_copy_page: CMAP2 busy"); 3382 sched_pin(); 3383 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3384 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3385 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3386 PT_SET_MA(sysmaps->CADDR1, 0); 3387 PT_SET_MA(sysmaps->CADDR2, 0); 3388 sched_unpin(); 3389 mtx_unlock(&sysmaps->lock); 3390} 3391 3392/* 3393 * Returns true if the pmap's pv is one of the first 3394 * 16 pvs linked to from this page. This count may 3395 * be changed upwards or downwards in the future; it 3396 * is only necessary that true be returned for a small 3397 * subset of pmaps for proper page aging. 3398 */ 3399boolean_t 3400pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3401{ 3402 pv_entry_t pv; 3403 int loops = 0; 3404 boolean_t rv; 3405 3406 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3407 ("pmap_page_exists_quick: page %p is not managed", m)); 3408 rv = FALSE; 3409 vm_page_lock_queues(); 3410 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3411 if (PV_PMAP(pv) == pmap) { 3412 rv = TRUE; 3413 break; 3414 } 3415 loops++; 3416 if (loops >= 16) 3417 break; 3418 } 3419 vm_page_unlock_queues(); 3420 return (rv); 3421} 3422 3423/* 3424 * pmap_page_wired_mappings: 3425 * 3426 * Return the number of managed mappings to the given physical page 3427 * that are wired. 3428 */ 3429int 3430pmap_page_wired_mappings(vm_page_t m) 3431{ 3432 pv_entry_t pv; 3433 pt_entry_t *pte; 3434 pmap_t pmap; 3435 int count; 3436 3437 count = 0; 3438 if ((m->flags & PG_FICTITIOUS) != 0) 3439 return (count); 3440 vm_page_lock_queues(); 3441 sched_pin(); 3442 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3443 pmap = PV_PMAP(pv); 3444 PMAP_LOCK(pmap); 3445 pte = pmap_pte_quick(pmap, pv->pv_va); 3446 if ((*pte & PG_W) != 0) 3447 count++; 3448 PMAP_UNLOCK(pmap); 3449 } 3450 sched_unpin(); 3451 vm_page_unlock_queues(); 3452 return (count); 3453} 3454 3455/* 3456 * Returns TRUE if the given page is mapped individually or as part of 3457 * a 4mpage. Otherwise, returns FALSE. 3458 */ 3459boolean_t 3460pmap_page_is_mapped(vm_page_t m) 3461{ 3462 boolean_t rv; 3463 3464 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 3465 return (FALSE); 3466 vm_page_lock_queues(); 3467 rv = !TAILQ_EMPTY(&m->md.pv_list) || 3468 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list); 3469 vm_page_unlock_queues(); 3470 return (rv); 3471} 3472 3473/* 3474 * Remove all pages from specified address space 3475 * this aids process exit speeds. Also, this code 3476 * is special cased for current process only, but 3477 * can have the more generic (and slightly slower) 3478 * mode enabled. This is much faster than pmap_remove 3479 * in the case of running down an entire address space. 3480 */ 3481void 3482pmap_remove_pages(pmap_t pmap) 3483{ 3484 pt_entry_t *pte, tpte; 3485 vm_page_t m, free = NULL; 3486 pv_entry_t pv; 3487 struct pv_chunk *pc, *npc; 3488 int field, idx; 3489 int32_t bit; 3490 uint32_t inuse, bitmask; 3491 int allfree; 3492 3493 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3494 3495 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3496 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3497 return; 3498 } 3499 vm_page_lock_queues(); 3500 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3501 PMAP_LOCK(pmap); 3502 sched_pin(); 3503 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3504 allfree = 1; 3505 for (field = 0; field < _NPCM; field++) { 3506 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 3507 while (inuse != 0) { 3508 bit = bsfl(inuse); 3509 bitmask = 1UL << bit; 3510 idx = field * 32 + bit; 3511 pv = &pc->pc_pventry[idx]; 3512 inuse &= ~bitmask; 3513 3514 pte = vtopte(pv->pv_va); 3515 tpte = *pte ? xpmap_mtop(*pte) : 0; 3516 3517 if (tpte == 0) { 3518 printf( 3519 "TPTE at %p IS ZERO @ VA %08x\n", 3520 pte, pv->pv_va); 3521 panic("bad pte"); 3522 } 3523 3524/* 3525 * We cannot remove wired pages from a process' mapping at this time 3526 */ 3527 if (tpte & PG_W) { 3528 allfree = 0; 3529 continue; 3530 } 3531 3532 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3533 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3534 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3535 m, (uintmax_t)m->phys_addr, 3536 (uintmax_t)tpte)); 3537 3538 KASSERT(m < &vm_page_array[vm_page_array_size], 3539 ("pmap_remove_pages: bad tpte %#jx", 3540 (uintmax_t)tpte)); 3541 3542 3543 PT_CLEAR_VA(pte, FALSE); 3544 3545 /* 3546 * Update the vm_page_t clean/reference bits. 3547 */ 3548 if (tpte & PG_M) 3549 vm_page_dirty(m); 3550 3551 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3552 if (TAILQ_EMPTY(&m->md.pv_list)) 3553 vm_page_flag_clear(m, PG_WRITEABLE); 3554 3555 pmap_unuse_pt(pmap, pv->pv_va, &free); 3556 3557 /* Mark free */ 3558 PV_STAT(pv_entry_frees++); 3559 PV_STAT(pv_entry_spare++); 3560 pv_entry_count--; 3561 pc->pc_map[field] |= bitmask; 3562 pmap->pm_stats.resident_count--; 3563 } 3564 } 3565 PT_UPDATES_FLUSH(); 3566 if (allfree) { 3567 PV_STAT(pv_entry_spare -= _NPCPV); 3568 PV_STAT(pc_chunk_count--); 3569 PV_STAT(pc_chunk_frees++); 3570 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3571 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 3572 pmap_qremove((vm_offset_t)pc, 1); 3573 vm_page_unwire(m, 0); 3574 vm_page_free(m); 3575 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 3576 } 3577 } 3578 PT_UPDATES_FLUSH(); 3579 if (*PMAP1) 3580 PT_SET_MA(PADDR1, 0); 3581 3582 sched_unpin(); 3583 pmap_invalidate_all(pmap); 3584 vm_page_unlock_queues(); 3585 PMAP_UNLOCK(pmap); 3586 pmap_free_zero_pages(free); 3587} 3588 3589/* 3590 * pmap_is_modified: 3591 * 3592 * Return whether or not the specified physical page was modified 3593 * in any physical maps. 3594 */ 3595boolean_t 3596pmap_is_modified(vm_page_t m) 3597{ 3598 pv_entry_t pv; 3599 pt_entry_t *pte; 3600 pmap_t pmap; 3601 boolean_t rv; 3602 3603 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3604 ("pmap_is_modified: page %p is not managed", m)); 3605 rv = FALSE; 3606 3607 /* 3608 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 3609 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 3610 * is clear, no PTEs can have PG_M set. 3611 */ 3612 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3613 if ((m->oflags & VPO_BUSY) == 0 && 3614 (m->flags & PG_WRITEABLE) == 0) 3615 return (rv); 3616 vm_page_lock_queues(); 3617 sched_pin(); 3618 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3619 pmap = PV_PMAP(pv); 3620 PMAP_LOCK(pmap); 3621 pte = pmap_pte_quick(pmap, pv->pv_va); 3622 rv = (*pte & PG_M) != 0; 3623 PMAP_UNLOCK(pmap); 3624 if (rv) 3625 break; 3626 } 3627 if (*PMAP1) 3628 PT_SET_MA(PADDR1, 0); 3629 sched_unpin(); 3630 vm_page_unlock_queues(); 3631 return (rv); 3632} 3633 3634/* 3635 * pmap_is_prefaultable: 3636 * 3637 * Return whether or not the specified virtual address is elgible 3638 * for prefault. 3639 */ 3640static boolean_t 3641pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3642{ 3643 pt_entry_t *pte; 3644 boolean_t rv = FALSE; 3645 3646 return (rv); 3647 3648 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3649 pte = vtopte(addr); 3650 rv = (*pte == 0); 3651 } 3652 return (rv); 3653} 3654 3655boolean_t 3656pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3657{ 3658 boolean_t rv; 3659 3660 PMAP_LOCK(pmap); 3661 rv = pmap_is_prefaultable_locked(pmap, addr); 3662 PMAP_UNLOCK(pmap); 3663 return (rv); 3664} 3665 3666boolean_t 3667pmap_is_referenced(vm_page_t m) 3668{ 3669 pv_entry_t pv; 3670 pt_entry_t *pte; 3671 pmap_t pmap; 3672 boolean_t rv; 3673 3674 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3675 ("pmap_is_referenced: page %p is not managed", m)); 3676 rv = FALSE; 3677 vm_page_lock_queues(); 3678 sched_pin(); 3679 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3680 pmap = PV_PMAP(pv); 3681 PMAP_LOCK(pmap); 3682 pte = pmap_pte_quick(pmap, pv->pv_va); 3683 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3684 PMAP_UNLOCK(pmap); 3685 if (rv) 3686 break; 3687 } 3688 if (*PMAP1) 3689 PT_SET_MA(PADDR1, 0); 3690 sched_unpin(); 3691 vm_page_unlock_queues(); 3692 return (rv); 3693} 3694 3695void 3696pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3697{ 3698 int i, npages = round_page(len) >> PAGE_SHIFT; 3699 for (i = 0; i < npages; i++) { 3700 pt_entry_t *pte; 3701 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3702 vm_page_lock_queues(); 3703 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3704 vm_page_unlock_queues(); 3705 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3706 pmap_pte_release(pte); 3707 } 3708} 3709 3710void 3711pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3712{ 3713 int i, npages = round_page(len) >> PAGE_SHIFT; 3714 for (i = 0; i < npages; i++) { 3715 pt_entry_t *pte; 3716 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3717 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3718 vm_page_lock_queues(); 3719 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3720 vm_page_unlock_queues(); 3721 pmap_pte_release(pte); 3722 } 3723} 3724 3725/* 3726 * Clear the write and modified bits in each of the given page's mappings. 3727 */ 3728void 3729pmap_remove_write(vm_page_t m) 3730{ 3731 pv_entry_t pv; 3732 pmap_t pmap; 3733 pt_entry_t oldpte, *pte; 3734 3735 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3736 ("pmap_remove_write: page %p is not managed", m)); 3737 3738 /* 3739 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 3740 * another thread while the object is locked. Thus, if PG_WRITEABLE 3741 * is clear, no page table entries need updating. 3742 */ 3743 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3744 if ((m->oflags & VPO_BUSY) == 0 && 3745 (m->flags & PG_WRITEABLE) == 0) 3746 return; 3747 vm_page_lock_queues(); 3748 sched_pin(); 3749 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3750 pmap = PV_PMAP(pv); 3751 PMAP_LOCK(pmap); 3752 pte = pmap_pte_quick(pmap, pv->pv_va); 3753retry: 3754 oldpte = *pte; 3755 if ((oldpte & PG_RW) != 0) { 3756 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3757 3758 /* 3759 * Regardless of whether a pte is 32 or 64 bits 3760 * in size, PG_RW and PG_M are among the least 3761 * significant 32 bits. 3762 */ 3763 PT_SET_VA_MA(pte, newpte, TRUE); 3764 if (*pte != newpte) 3765 goto retry; 3766 3767 if ((oldpte & PG_M) != 0) 3768 vm_page_dirty(m); 3769 pmap_invalidate_page(pmap, pv->pv_va); 3770 } 3771 PMAP_UNLOCK(pmap); 3772 } 3773 vm_page_flag_clear(m, PG_WRITEABLE); 3774 PT_UPDATES_FLUSH(); 3775 if (*PMAP1) 3776 PT_SET_MA(PADDR1, 0); 3777 sched_unpin(); 3778 vm_page_unlock_queues(); 3779} 3780 3781/* 3782 * pmap_ts_referenced: 3783 * 3784 * Return a count of reference bits for a page, clearing those bits. 3785 * It is not necessary for every reference bit to be cleared, but it 3786 * is necessary that 0 only be returned when there are truly no 3787 * reference bits set. 3788 * 3789 * XXX: The exact number of bits to check and clear is a matter that 3790 * should be tested and standardized at some point in the future for 3791 * optimal aging of shared pages. 3792 */ 3793int 3794pmap_ts_referenced(vm_page_t m) 3795{ 3796 pv_entry_t pv, pvf, pvn; 3797 pmap_t pmap; 3798 pt_entry_t *pte; 3799 int rtval = 0; 3800 3801 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3802 ("pmap_ts_referenced: page %p is not managed", m)); 3803 vm_page_lock_queues(); 3804 sched_pin(); 3805 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3806 pvf = pv; 3807 do { 3808 pvn = TAILQ_NEXT(pv, pv_list); 3809 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3810 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3811 pmap = PV_PMAP(pv); 3812 PMAP_LOCK(pmap); 3813 pte = pmap_pte_quick(pmap, pv->pv_va); 3814 if ((*pte & PG_A) != 0) { 3815 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3816 pmap_invalidate_page(pmap, pv->pv_va); 3817 rtval++; 3818 if (rtval > 4) 3819 pvn = NULL; 3820 } 3821 PMAP_UNLOCK(pmap); 3822 } while ((pv = pvn) != NULL && pv != pvf); 3823 } 3824 PT_UPDATES_FLUSH(); 3825 if (*PMAP1) 3826 PT_SET_MA(PADDR1, 0); 3827 3828 sched_unpin(); 3829 vm_page_unlock_queues(); 3830 return (rtval); 3831} 3832 3833/* 3834 * Clear the modify bits on the specified physical page. 3835 */ 3836void 3837pmap_clear_modify(vm_page_t m) 3838{ 3839 pv_entry_t pv; 3840 pmap_t pmap; 3841 pt_entry_t *pte; 3842 3843 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3844 ("pmap_clear_modify: page %p is not managed", m)); 3845 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3846 KASSERT((m->oflags & VPO_BUSY) == 0, 3847 ("pmap_clear_modify: page %p is busy", m)); 3848 3849 /* 3850 * If the page is not PG_WRITEABLE, then no PTEs can have PG_M set. 3851 * If the object containing the page is locked and the page is not 3852 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 3853 */ 3854 if ((m->flags & PG_WRITEABLE) == 0) 3855 return; 3856 vm_page_lock_queues(); 3857 sched_pin(); 3858 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3859 pmap = PV_PMAP(pv); 3860 PMAP_LOCK(pmap); 3861 pte = pmap_pte_quick(pmap, pv->pv_va); 3862 if ((*pte & PG_M) != 0) { 3863 /* 3864 * Regardless of whether a pte is 32 or 64 bits 3865 * in size, PG_M is among the least significant 3866 * 32 bits. 3867 */ 3868 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3869 pmap_invalidate_page(pmap, pv->pv_va); 3870 } 3871 PMAP_UNLOCK(pmap); 3872 } 3873 sched_unpin(); 3874 vm_page_unlock_queues(); 3875} 3876 3877/* 3878 * pmap_clear_reference: 3879 * 3880 * Clear the reference bit on the specified physical page. 3881 */ 3882void 3883pmap_clear_reference(vm_page_t m) 3884{ 3885 pv_entry_t pv; 3886 pmap_t pmap; 3887 pt_entry_t *pte; 3888 3889 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3890 ("pmap_clear_reference: page %p is not managed", m)); 3891 vm_page_lock_queues(); 3892 sched_pin(); 3893 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3894 pmap = PV_PMAP(pv); 3895 PMAP_LOCK(pmap); 3896 pte = pmap_pte_quick(pmap, pv->pv_va); 3897 if ((*pte & PG_A) != 0) { 3898 /* 3899 * Regardless of whether a pte is 32 or 64 bits 3900 * in size, PG_A is among the least significant 3901 * 32 bits. 3902 */ 3903 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3904 pmap_invalidate_page(pmap, pv->pv_va); 3905 } 3906 PMAP_UNLOCK(pmap); 3907 } 3908 sched_unpin(); 3909 vm_page_unlock_queues(); 3910} 3911 3912/* 3913 * Miscellaneous support routines follow 3914 */ 3915 3916/* 3917 * Map a set of physical memory pages into the kernel virtual 3918 * address space. Return a pointer to where it is mapped. This 3919 * routine is intended to be used for mapping device memory, 3920 * NOT real memory. 3921 */ 3922void * 3923pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 3924{ 3925 vm_offset_t va, offset; 3926 vm_size_t tmpsize; 3927 3928 offset = pa & PAGE_MASK; 3929 size = roundup(offset + size, PAGE_SIZE); 3930 pa = pa & PG_FRAME; 3931 3932 if (pa < KERNLOAD && pa + size <= KERNLOAD) 3933 va = KERNBASE + pa; 3934 else 3935 va = kmem_alloc_nofault(kernel_map, size); 3936 if (!va) 3937 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3938 3939 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 3940 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 3941 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 3942 pmap_invalidate_cache_range(va, va + size); 3943 return ((void *)(va + offset)); 3944} 3945 3946void * 3947pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3948{ 3949 3950 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 3951} 3952 3953void * 3954pmap_mapbios(vm_paddr_t pa, vm_size_t size) 3955{ 3956 3957 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 3958} 3959 3960void 3961pmap_unmapdev(vm_offset_t va, vm_size_t size) 3962{ 3963 vm_offset_t base, offset, tmpva; 3964 3965 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 3966 return; 3967 base = trunc_page(va); 3968 offset = va & PAGE_MASK; 3969 size = roundup(offset + size, PAGE_SIZE); 3970 critical_enter(); 3971 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 3972 pmap_kremove(tmpva); 3973 pmap_invalidate_range(kernel_pmap, va, tmpva); 3974 critical_exit(); 3975 kmem_free(kernel_map, base, size); 3976} 3977 3978/* 3979 * Sets the memory attribute for the specified page. 3980 */ 3981void 3982pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 3983{ 3984 struct sysmaps *sysmaps; 3985 vm_offset_t sva, eva; 3986 3987 m->md.pat_mode = ma; 3988 if ((m->flags & PG_FICTITIOUS) != 0) 3989 return; 3990 3991 /* 3992 * If "m" is a normal page, flush it from the cache. 3993 * See pmap_invalidate_cache_range(). 3994 * 3995 * First, try to find an existing mapping of the page by sf 3996 * buffer. sf_buf_invalidate_cache() modifies mapping and 3997 * flushes the cache. 3998 */ 3999 if (sf_buf_invalidate_cache(m)) 4000 return; 4001 4002 /* 4003 * If page is not mapped by sf buffer, but CPU does not 4004 * support self snoop, map the page transient and do 4005 * invalidation. In the worst case, whole cache is flushed by 4006 * pmap_invalidate_cache_range(). 4007 */ 4008 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 4009 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4010 mtx_lock(&sysmaps->lock); 4011 if (*sysmaps->CMAP2) 4012 panic("pmap_page_set_memattr: CMAP2 busy"); 4013 sched_pin(); 4014 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 4015 VM_PAGE_TO_MACH(m) | PG_A | PG_M | 4016 pmap_cache_bits(m->md.pat_mode, 0)); 4017 invlcaddr(sysmaps->CADDR2); 4018 sva = (vm_offset_t)sysmaps->CADDR2; 4019 eva = sva + PAGE_SIZE; 4020 } else 4021 sva = eva = 0; /* gcc */ 4022 pmap_invalidate_cache_range(sva, eva); 4023 if (sva != 0) { 4024 PT_SET_MA(sysmaps->CADDR2, 0); 4025 sched_unpin(); 4026 mtx_unlock(&sysmaps->lock); 4027 } 4028} 4029 4030int 4031pmap_change_attr(va, size, mode) 4032 vm_offset_t va; 4033 vm_size_t size; 4034 int mode; 4035{ 4036 vm_offset_t base, offset, tmpva; 4037 pt_entry_t *pte; 4038 u_int opte, npte; 4039 pd_entry_t *pde; 4040 boolean_t changed; 4041 4042 base = trunc_page(va); 4043 offset = va & PAGE_MASK; 4044 size = roundup(offset + size, PAGE_SIZE); 4045 4046 /* Only supported on kernel virtual addresses. */ 4047 if (base <= VM_MAXUSER_ADDRESS) 4048 return (EINVAL); 4049 4050 /* 4MB pages and pages that aren't mapped aren't supported. */ 4051 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4052 pde = pmap_pde(kernel_pmap, tmpva); 4053 if (*pde & PG_PS) 4054 return (EINVAL); 4055 if ((*pde & PG_V) == 0) 4056 return (EINVAL); 4057 pte = vtopte(va); 4058 if ((*pte & PG_V) == 0) 4059 return (EINVAL); 4060 } 4061 4062 changed = FALSE; 4063 4064 /* 4065 * Ok, all the pages exist and are 4k, so run through them updating 4066 * their cache mode. 4067 */ 4068 for (tmpva = base; size > 0; ) { 4069 pte = vtopte(tmpva); 4070 4071 /* 4072 * The cache mode bits are all in the low 32-bits of the 4073 * PTE, so we can just spin on updating the low 32-bits. 4074 */ 4075 do { 4076 opte = *(u_int *)pte; 4077 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4078 npte |= pmap_cache_bits(mode, 0); 4079 PT_SET_VA_MA(pte, npte, TRUE); 4080 } while (npte != opte && (*pte != npte)); 4081 if (npte != opte) 4082 changed = TRUE; 4083 tmpva += PAGE_SIZE; 4084 size -= PAGE_SIZE; 4085 } 4086 4087 /* 4088 * Flush CPU caches to make sure any data isn't cached that shouldn't 4089 * be, etc. 4090 */ 4091 if (changed) { 4092 pmap_invalidate_range(kernel_pmap, base, tmpva); 4093 pmap_invalidate_cache_range(base, tmpva); 4094 } 4095 return (0); 4096} 4097 4098/* 4099 * perform the pmap work for mincore 4100 */ 4101int 4102pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4103{ 4104 pt_entry_t *ptep, pte; 4105 vm_paddr_t pa; 4106 int val; 4107 4108 PMAP_LOCK(pmap); 4109retry: 4110 ptep = pmap_pte(pmap, addr); 4111 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4112 pmap_pte_release(ptep); 4113 val = 0; 4114 if ((pte & PG_V) != 0) { 4115 val |= MINCORE_INCORE; 4116 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4117 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4118 if ((pte & PG_A) != 0) 4119 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4120 } 4121 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4122 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4123 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4124 pa = pte & PG_FRAME; 4125 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4126 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4127 goto retry; 4128 } else 4129 PA_UNLOCK_COND(*locked_pa); 4130 PMAP_UNLOCK(pmap); 4131 return (val); 4132} 4133 4134void 4135pmap_activate(struct thread *td) 4136{ 4137 pmap_t pmap, oldpmap; 4138 u_int cpuid; 4139 u_int32_t cr3; 4140 4141 critical_enter(); 4142 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4143 oldpmap = PCPU_GET(curpmap); 4144 cpuid = PCPU_GET(cpuid); 4145#if defined(SMP) 4146 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 4147 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 4148#else 4149 CPU_CLR(cpuid, &oldpmap->pm_active); 4150 CPU_SET(cpuid, &pmap->pm_active); 4151#endif 4152#ifdef PAE 4153 cr3 = vtophys(pmap->pm_pdpt); 4154#else 4155 cr3 = vtophys(pmap->pm_pdir); 4156#endif 4157 /* 4158 * pmap_activate is for the current thread on the current cpu 4159 */ 4160 td->td_pcb->pcb_cr3 = cr3; 4161 PT_UPDATES_FLUSH(); 4162 load_cr3(cr3); 4163 PCPU_SET(curpmap, pmap); 4164 critical_exit(); 4165} 4166 4167void 4168pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4169{ 4170} 4171 4172/* 4173 * Increase the starting virtual address of the given mapping if a 4174 * different alignment might result in more superpage mappings. 4175 */ 4176void 4177pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4178 vm_offset_t *addr, vm_size_t size) 4179{ 4180 vm_offset_t superpage_offset; 4181 4182 if (size < NBPDR) 4183 return; 4184 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4185 offset += ptoa(object->pg_color); 4186 superpage_offset = offset & PDRMASK; 4187 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4188 (*addr & PDRMASK) == superpage_offset) 4189 return; 4190 if ((*addr & PDRMASK) < superpage_offset) 4191 *addr = (*addr & ~PDRMASK) + superpage_offset; 4192 else 4193 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4194} 4195 4196void 4197pmap_suspend() 4198{ 4199 pmap_t pmap; 4200 int i, pdir, offset; 4201 vm_paddr_t pdirma; 4202 mmu_update_t mu[4]; 4203 4204 /* 4205 * We need to remove the recursive mapping structure from all 4206 * our pmaps so that Xen doesn't get confused when it restores 4207 * the page tables. The recursive map lives at page directory 4208 * index PTDPTDI. We assume that the suspend code has stopped 4209 * the other vcpus (if any). 4210 */ 4211 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4212 for (i = 0; i < 4; i++) { 4213 /* 4214 * Figure out which page directory (L2) page 4215 * contains this bit of the recursive map and 4216 * the offset within that page of the map 4217 * entry 4218 */ 4219 pdir = (PTDPTDI + i) / NPDEPG; 4220 offset = (PTDPTDI + i) % NPDEPG; 4221 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4222 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4223 mu[i].val = 0; 4224 } 4225 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4226 } 4227} 4228 4229void 4230pmap_resume() 4231{ 4232 pmap_t pmap; 4233 int i, pdir, offset; 4234 vm_paddr_t pdirma; 4235 mmu_update_t mu[4]; 4236 4237 /* 4238 * Restore the recursive map that we removed on suspend. 4239 */ 4240 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4241 for (i = 0; i < 4; i++) { 4242 /* 4243 * Figure out which page directory (L2) page 4244 * contains this bit of the recursive map and 4245 * the offset within that page of the map 4246 * entry 4247 */ 4248 pdir = (PTDPTDI + i) / NPDEPG; 4249 offset = (PTDPTDI + i) % NPDEPG; 4250 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4251 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4252 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4253 } 4254 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4255 } 4256} 4257 4258#if defined(PMAP_DEBUG) 4259pmap_pid_dump(int pid) 4260{ 4261 pmap_t pmap; 4262 struct proc *p; 4263 int npte = 0; 4264 int index; 4265 4266 sx_slock(&allproc_lock); 4267 FOREACH_PROC_IN_SYSTEM(p) { 4268 if (p->p_pid != pid) 4269 continue; 4270 4271 if (p->p_vmspace) { 4272 int i,j; 4273 index = 0; 4274 pmap = vmspace_pmap(p->p_vmspace); 4275 for (i = 0; i < NPDEPTD; i++) { 4276 pd_entry_t *pde; 4277 pt_entry_t *pte; 4278 vm_offset_t base = i << PDRSHIFT; 4279 4280 pde = &pmap->pm_pdir[i]; 4281 if (pde && pmap_pde_v(pde)) { 4282 for (j = 0; j < NPTEPG; j++) { 4283 vm_offset_t va = base + (j << PAGE_SHIFT); 4284 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4285 if (index) { 4286 index = 0; 4287 printf("\n"); 4288 } 4289 sx_sunlock(&allproc_lock); 4290 return npte; 4291 } 4292 pte = pmap_pte(pmap, va); 4293 if (pte && pmap_pte_v(pte)) { 4294 pt_entry_t pa; 4295 vm_page_t m; 4296 pa = PT_GET(pte); 4297 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4298 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4299 va, pa, m->hold_count, m->wire_count, m->flags); 4300 npte++; 4301 index++; 4302 if (index >= 2) { 4303 index = 0; 4304 printf("\n"); 4305 } else { 4306 printf(" "); 4307 } 4308 } 4309 } 4310 } 4311 } 4312 } 4313 } 4314 sx_sunlock(&allproc_lock); 4315 return npte; 4316} 4317#endif 4318 4319#if defined(DEBUG) 4320 4321static void pads(pmap_t pm); 4322void pmap_pvdump(vm_paddr_t pa); 4323 4324/* print address space of pmap*/ 4325static void 4326pads(pmap_t pm) 4327{ 4328 int i, j; 4329 vm_paddr_t va; 4330 pt_entry_t *ptep; 4331 4332 if (pm == kernel_pmap) 4333 return; 4334 for (i = 0; i < NPDEPTD; i++) 4335 if (pm->pm_pdir[i]) 4336 for (j = 0; j < NPTEPG; j++) { 4337 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4338 if (pm == kernel_pmap && va < KERNBASE) 4339 continue; 4340 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4341 continue; 4342 ptep = pmap_pte(pm, va); 4343 if (pmap_pte_v(ptep)) 4344 printf("%x:%x ", va, *ptep); 4345 }; 4346 4347} 4348 4349void 4350pmap_pvdump(vm_paddr_t pa) 4351{ 4352 pv_entry_t pv; 4353 pmap_t pmap; 4354 vm_page_t m; 4355 4356 printf("pa %x", pa); 4357 m = PHYS_TO_VM_PAGE(pa); 4358 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4359 pmap = PV_PMAP(pv); 4360 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4361 pads(pmap); 4362 } 4363 printf(" "); 4364} 4365#endif 4366