pmap.c revision 222813
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 222813 2011-06-07 08:46:13Z attilio $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_smp.h" 109#include "opt_xbox.h" 110 111#include <sys/param.h> 112#include <sys/systm.h> 113#include <sys/kernel.h> 114#include <sys/ktr.h> 115#include <sys/lock.h> 116#include <sys/malloc.h> 117#include <sys/mman.h> 118#include <sys/msgbuf.h> 119#include <sys/mutex.h> 120#include <sys/proc.h> 121#include <sys/sf_buf.h> 122#include <sys/sx.h> 123#include <sys/vmmeter.h> 124#include <sys/sched.h> 125#include <sys/sysctl.h> 126#ifdef SMP 127#include <sys/smp.h> 128#endif 129 130#include <vm/vm.h> 131#include <vm/vm_param.h> 132#include <vm/vm_kern.h> 133#include <vm/vm_page.h> 134#include <vm/vm_map.h> 135#include <vm/vm_object.h> 136#include <vm/vm_extern.h> 137#include <vm/vm_pageout.h> 138#include <vm/vm_pager.h> 139#include <vm/uma.h> 140 141#include <machine/cpu.h> 142#include <machine/cputypes.h> 143#include <machine/md_var.h> 144#include <machine/pcb.h> 145#include <machine/specialreg.h> 146#ifdef SMP 147#include <machine/smp.h> 148#endif 149 150#ifdef XBOX 151#include <machine/xbox.h> 152#endif 153 154#include <xen/interface/xen.h> 155#include <xen/hypervisor.h> 156#include <machine/xen/hypercall.h> 157#include <machine/xen/xenvar.h> 158#include <machine/xen/xenfunc.h> 159 160#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 161#define CPU_ENABLE_SSE 162#endif 163 164#ifndef PMAP_SHPGPERPROC 165#define PMAP_SHPGPERPROC 200 166#endif 167 168#define DIAGNOSTIC 169 170#if !defined(DIAGNOSTIC) 171#ifdef __GNUC_GNU_INLINE__ 172#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 173#else 174#define PMAP_INLINE extern inline 175#endif 176#else 177#define PMAP_INLINE 178#endif 179 180#define PV_STATS 181#ifdef PV_STATS 182#define PV_STAT(x) do { x ; } while (0) 183#else 184#define PV_STAT(x) do { } while (0) 185#endif 186 187#define pa_index(pa) ((pa) >> PDRSHIFT) 188#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 189 190/* 191 * Get PDEs and PTEs for user/kernel address space 192 */ 193#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 194#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 195 196#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 197#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 198#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 199#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 200#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 201 202#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 203 204#define HAMFISTED_LOCKING 205#ifdef HAMFISTED_LOCKING 206static struct mtx createdelete_lock; 207#endif 208 209struct pmap kernel_pmap_store; 210LIST_HEAD(pmaplist, pmap); 211static struct pmaplist allpmaps; 212static struct mtx allpmaps_lock; 213 214vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 215vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 216int pgeflag = 0; /* PG_G or-in */ 217int pseflag = 0; /* PG_PS or-in */ 218 219int nkpt; 220vm_offset_t kernel_vm_end; 221extern u_int32_t KERNend; 222 223#ifdef PAE 224pt_entry_t pg_nx; 225#endif 226 227static int pat_works; /* Is page attribute table sane? */ 228 229/* 230 * Data for the pv entry allocation mechanism 231 */ 232static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 233static struct md_page *pv_table; 234static int shpgperproc = PMAP_SHPGPERPROC; 235 236struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 237int pv_maxchunks; /* How many chunks we have KVA for */ 238vm_offset_t pv_vafree; /* freelist stored in the PTE */ 239 240/* 241 * All those kernel PT submaps that BSD is so fond of 242 */ 243struct sysmaps { 244 struct mtx lock; 245 pt_entry_t *CMAP1; 246 pt_entry_t *CMAP2; 247 caddr_t CADDR1; 248 caddr_t CADDR2; 249}; 250static struct sysmaps sysmaps_pcpu[MAXCPU]; 251static pt_entry_t *CMAP3; 252caddr_t ptvmmap = 0; 253static caddr_t CADDR3; 254struct msgbuf *msgbufp = 0; 255 256/* 257 * Crashdump maps. 258 */ 259static caddr_t crashdumpmap; 260 261static pt_entry_t *PMAP1 = 0, *PMAP2; 262static pt_entry_t *PADDR1 = 0, *PADDR2; 263#ifdef SMP 264static int PMAP1cpu; 265static int PMAP1changedcpu; 266SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 267 &PMAP1changedcpu, 0, 268 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 269#endif 270static int PMAP1changed; 271SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 272 &PMAP1changed, 0, 273 "Number of times pmap_pte_quick changed PMAP1"); 274static int PMAP1unchanged; 275SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 276 &PMAP1unchanged, 0, 277 "Number of times pmap_pte_quick didn't change PMAP1"); 278static struct mtx PMAP2mutex; 279 280SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 281static int pg_ps_enabled; 282SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 283 "Are large page mappings enabled?"); 284 285SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 286 "Max number of PV entries"); 287SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 288 "Page share factor per proc"); 289SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 290 "2/4MB page mapping counters"); 291 292static u_long pmap_pde_mappings; 293SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 294 &pmap_pde_mappings, 0, "2/4MB page mappings"); 295 296static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 297static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 298static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 299static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 300 vm_offset_t va); 301 302static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 303 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 304static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 305 vm_page_t *free); 306static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 307 vm_page_t *free); 308static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 309 vm_offset_t va); 310static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 311 vm_page_t m); 312 313static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 314 315static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 316static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 317static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 318static void pmap_pte_release(pt_entry_t *pte); 319static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 320static vm_offset_t pmap_kmem_choose(vm_offset_t addr); 321static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 322static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 323 324static __inline void pagezero(void *page); 325 326CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 327CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 328 329/* 330 * If you get an error here, then you set KVA_PAGES wrong! See the 331 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 332 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 333 */ 334CTASSERT(KERNBASE % (1 << 24) == 0); 335 336 337 338void 339pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 340{ 341 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 342 343 switch (type) { 344 case SH_PD_SET_VA: 345#if 0 346 xen_queue_pt_update(shadow_pdir_ma, 347 xpmap_ptom(val & ~(PG_RW))); 348#endif 349 xen_queue_pt_update(pdir_ma, 350 xpmap_ptom(val)); 351 break; 352 case SH_PD_SET_VA_MA: 353#if 0 354 xen_queue_pt_update(shadow_pdir_ma, 355 val & ~(PG_RW)); 356#endif 357 xen_queue_pt_update(pdir_ma, val); 358 break; 359 case SH_PD_SET_VA_CLEAR: 360#if 0 361 xen_queue_pt_update(shadow_pdir_ma, 0); 362#endif 363 xen_queue_pt_update(pdir_ma, 0); 364 break; 365 } 366} 367 368/* 369 * Move the kernel virtual free pointer to the next 370 * 4MB. This is used to help improve performance 371 * by using a large (4MB) page for much of the kernel 372 * (.text, .data, .bss) 373 */ 374static vm_offset_t 375pmap_kmem_choose(vm_offset_t addr) 376{ 377 vm_offset_t newaddr = addr; 378 379#ifndef DISABLE_PSE 380 if (cpu_feature & CPUID_PSE) 381 newaddr = (addr + PDRMASK) & ~PDRMASK; 382#endif 383 return newaddr; 384} 385 386/* 387 * Bootstrap the system enough to run with virtual memory. 388 * 389 * On the i386 this is called after mapping has already been enabled 390 * and just syncs the pmap module with what has already been done. 391 * [We can't call it easily with mapping off since the kernel is not 392 * mapped with PA == VA, hence we would have to relocate every address 393 * from the linked base (virtual) address "KERNBASE" to the actual 394 * (physical) address starting relative to 0] 395 */ 396void 397pmap_bootstrap(vm_paddr_t firstaddr) 398{ 399 vm_offset_t va; 400 pt_entry_t *pte, *unused; 401 struct sysmaps *sysmaps; 402 int i; 403 404 /* 405 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 406 * large. It should instead be correctly calculated in locore.s and 407 * not based on 'first' (which is a physical address, not a virtual 408 * address, for the start of unused physical memory). The kernel 409 * page tables are NOT double mapped and thus should not be included 410 * in this calculation. 411 */ 412 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 413 virtual_avail = pmap_kmem_choose(virtual_avail); 414 415 virtual_end = VM_MAX_KERNEL_ADDRESS; 416 417 /* 418 * Initialize the kernel pmap (which is statically allocated). 419 */ 420 PMAP_LOCK_INIT(kernel_pmap); 421 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 422#ifdef PAE 423 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 424#endif 425 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 426 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 427 LIST_INIT(&allpmaps); 428 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 429 mtx_lock_spin(&allpmaps_lock); 430 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 431 mtx_unlock_spin(&allpmaps_lock); 432 if (nkpt == 0) 433 nkpt = NKPT; 434 435 /* 436 * Reserve some special page table entries/VA space for temporary 437 * mapping of pages. 438 */ 439#define SYSMAP(c, p, v, n) \ 440 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 441 442 va = virtual_avail; 443 pte = vtopte(va); 444 445 /* 446 * CMAP1/CMAP2 are used for zeroing and copying pages. 447 * CMAP3 is used for the idle process page zeroing. 448 */ 449 for (i = 0; i < MAXCPU; i++) { 450 sysmaps = &sysmaps_pcpu[i]; 451 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 452 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 453 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 454 PT_SET_MA(sysmaps->CADDR1, 0); 455 PT_SET_MA(sysmaps->CADDR2, 0); 456 } 457 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 458 PT_SET_MA(CADDR3, 0); 459 460 /* 461 * Crashdump maps. 462 */ 463 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 464 465 /* 466 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 467 */ 468 SYSMAP(caddr_t, unused, ptvmmap, 1) 469 470 /* 471 * msgbufp is used to map the system message buffer. 472 */ 473 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 474 475 /* 476 * ptemap is used for pmap_pte_quick 477 */ 478 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1); 479 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1); 480 481 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 482 483 virtual_avail = va; 484 485 /* 486 * Leave in place an identity mapping (virt == phys) for the low 1 MB 487 * physical memory region that is used by the ACPI wakeup code. This 488 * mapping must not have PG_G set. 489 */ 490#ifndef XEN 491 /* 492 * leave here deliberately to show that this is not supported 493 */ 494#ifdef XBOX 495 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 496 * an early stadium, we cannot yet neatly map video memory ... :-( 497 * Better fixes are very welcome! */ 498 if (!arch_i386_is_xbox) 499#endif 500 for (i = 1; i < NKPT; i++) 501 PTD[i] = 0; 502 503 /* Initialize the PAT MSR if present. */ 504 pmap_init_pat(); 505 506 /* Turn on PG_G on kernel page(s) */ 507 pmap_set_pg(); 508#endif 509 510#ifdef HAMFISTED_LOCKING 511 mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF); 512#endif 513} 514 515/* 516 * Setup the PAT MSR. 517 */ 518void 519pmap_init_pat(void) 520{ 521 uint64_t pat_msr; 522 523 /* Bail if this CPU doesn't implement PAT. */ 524 if (!(cpu_feature & CPUID_PAT)) 525 return; 526 527 if (cpu_vendor_id != CPU_VENDOR_INTEL || 528 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 529 /* 530 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 531 * Program 4 and 5 as WP and WC. 532 * Leave 6 and 7 as UC and UC-. 533 */ 534 pat_msr = rdmsr(MSR_PAT); 535 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 536 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 537 PAT_VALUE(5, PAT_WRITE_COMBINING); 538 pat_works = 1; 539 } else { 540 /* 541 * Due to some Intel errata, we can only safely use the lower 4 542 * PAT entries. Thus, just replace PAT Index 2 with WC instead 543 * of UC-. 544 * 545 * Intel Pentium III Processor Specification Update 546 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 547 * or Mode C Paging) 548 * 549 * Intel Pentium IV Processor Specification Update 550 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 551 */ 552 pat_msr = rdmsr(MSR_PAT); 553 pat_msr &= ~PAT_MASK(2); 554 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 555 pat_works = 0; 556 } 557 wrmsr(MSR_PAT, pat_msr); 558} 559 560/* 561 * Initialize a vm_page's machine-dependent fields. 562 */ 563void 564pmap_page_init(vm_page_t m) 565{ 566 567 TAILQ_INIT(&m->md.pv_list); 568 m->md.pat_mode = PAT_WRITE_BACK; 569} 570 571/* 572 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 573 * Requirements: 574 * - Must deal with pages in order to ensure that none of the PG_* bits 575 * are ever set, PG_V in particular. 576 * - Assumes we can write to ptes without pte_store() atomic ops, even 577 * on PAE systems. This should be ok. 578 * - Assumes nothing will ever test these addresses for 0 to indicate 579 * no mapping instead of correctly checking PG_V. 580 * - Assumes a vm_offset_t will fit in a pte (true for i386). 581 * Because PG_V is never set, there can be no mappings to invalidate. 582 */ 583static int ptelist_count = 0; 584static vm_offset_t 585pmap_ptelist_alloc(vm_offset_t *head) 586{ 587 vm_offset_t va; 588 vm_offset_t *phead = (vm_offset_t *)*head; 589 590 if (ptelist_count == 0) { 591 printf("out of memory!!!!!!\n"); 592 return (0); /* Out of memory */ 593 } 594 ptelist_count--; 595 va = phead[ptelist_count]; 596 return (va); 597} 598 599static void 600pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 601{ 602 vm_offset_t *phead = (vm_offset_t *)*head; 603 604 phead[ptelist_count++] = va; 605} 606 607static void 608pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 609{ 610 int i, nstackpages; 611 vm_offset_t va; 612 vm_page_t m; 613 614 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 615 for (i = 0; i < nstackpages; i++) { 616 va = (vm_offset_t)base + i * PAGE_SIZE; 617 m = vm_page_alloc(NULL, i, 618 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 619 VM_ALLOC_ZERO); 620 pmap_qenter(va, &m, 1); 621 } 622 623 *head = (vm_offset_t)base; 624 for (i = npages - 1; i >= nstackpages; i--) { 625 va = (vm_offset_t)base + i * PAGE_SIZE; 626 pmap_ptelist_free(head, va); 627 } 628} 629 630 631/* 632 * Initialize the pmap module. 633 * Called by vm_init, to initialize any structures that the pmap 634 * system needs to map virtual memory. 635 */ 636void 637pmap_init(void) 638{ 639 vm_page_t mpte; 640 vm_size_t s; 641 int i, pv_npg; 642 643 /* 644 * Initialize the vm page array entries for the kernel pmap's 645 * page table pages. 646 */ 647 for (i = 0; i < nkpt; i++) { 648 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(PTD[i + KPTDI] & PG_FRAME)); 649 KASSERT(mpte >= vm_page_array && 650 mpte < &vm_page_array[vm_page_array_size], 651 ("pmap_init: page table page is out of range")); 652 mpte->pindex = i + KPTDI; 653 mpte->phys_addr = xpmap_mtop(PTD[i + KPTDI] & PG_FRAME); 654 } 655 656 /* 657 * Initialize the address space (zone) for the pv entries. Set a 658 * high water mark so that the system can recover from excessive 659 * numbers of pv entries. 660 */ 661 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 662 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 663 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 664 pv_entry_max = roundup(pv_entry_max, _NPCPV); 665 pv_entry_high_water = 9 * (pv_entry_max / 10); 666 667 /* 668 * Are large page mappings enabled? 669 */ 670 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 671 672 /* 673 * Calculate the size of the pv head table for superpages. 674 */ 675 for (i = 0; phys_avail[i + 1]; i += 2); 676 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 677 678 /* 679 * Allocate memory for the pv head table for superpages. 680 */ 681 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 682 s = round_page(s); 683 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 684 for (i = 0; i < pv_npg; i++) 685 TAILQ_INIT(&pv_table[i].pv_list); 686 687 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 688 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 689 PAGE_SIZE * pv_maxchunks); 690 if (pv_chunkbase == NULL) 691 panic("pmap_init: not enough kvm for pv chunks"); 692 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 693} 694 695 696/*************************************************** 697 * Low level helper routines..... 698 ***************************************************/ 699 700/* 701 * Determine the appropriate bits to set in a PTE or PDE for a specified 702 * caching mode. 703 */ 704int 705pmap_cache_bits(int mode, boolean_t is_pde) 706{ 707 int pat_flag, pat_index, cache_bits; 708 709 /* The PAT bit is different for PTE's and PDE's. */ 710 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 711 712 /* If we don't support PAT, map extended modes to older ones. */ 713 if (!(cpu_feature & CPUID_PAT)) { 714 switch (mode) { 715 case PAT_UNCACHEABLE: 716 case PAT_WRITE_THROUGH: 717 case PAT_WRITE_BACK: 718 break; 719 case PAT_UNCACHED: 720 case PAT_WRITE_COMBINING: 721 case PAT_WRITE_PROTECTED: 722 mode = PAT_UNCACHEABLE; 723 break; 724 } 725 } 726 727 /* Map the caching mode to a PAT index. */ 728 if (pat_works) { 729 switch (mode) { 730 case PAT_UNCACHEABLE: 731 pat_index = 3; 732 break; 733 case PAT_WRITE_THROUGH: 734 pat_index = 1; 735 break; 736 case PAT_WRITE_BACK: 737 pat_index = 0; 738 break; 739 case PAT_UNCACHED: 740 pat_index = 2; 741 break; 742 case PAT_WRITE_COMBINING: 743 pat_index = 5; 744 break; 745 case PAT_WRITE_PROTECTED: 746 pat_index = 4; 747 break; 748 default: 749 panic("Unknown caching mode %d\n", mode); 750 } 751 } else { 752 switch (mode) { 753 case PAT_UNCACHED: 754 case PAT_UNCACHEABLE: 755 case PAT_WRITE_PROTECTED: 756 pat_index = 3; 757 break; 758 case PAT_WRITE_THROUGH: 759 pat_index = 1; 760 break; 761 case PAT_WRITE_BACK: 762 pat_index = 0; 763 break; 764 case PAT_WRITE_COMBINING: 765 pat_index = 2; 766 break; 767 default: 768 panic("Unknown caching mode %d\n", mode); 769 } 770 } 771 772 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 773 cache_bits = 0; 774 if (pat_index & 0x4) 775 cache_bits |= pat_flag; 776 if (pat_index & 0x2) 777 cache_bits |= PG_NC_PCD; 778 if (pat_index & 0x1) 779 cache_bits |= PG_NC_PWT; 780 return (cache_bits); 781} 782#ifdef SMP 783/* 784 * For SMP, these functions have to use the IPI mechanism for coherence. 785 * 786 * N.B.: Before calling any of the following TLB invalidation functions, 787 * the calling processor must ensure that all stores updating a non- 788 * kernel page table are globally performed. Otherwise, another 789 * processor could cache an old, pre-update entry without being 790 * invalidated. This can happen one of two ways: (1) The pmap becomes 791 * active on another processor after its pm_active field is checked by 792 * one of the following functions but before a store updating the page 793 * table is globally performed. (2) The pmap becomes active on another 794 * processor before its pm_active field is checked but due to 795 * speculative loads one of the following functions stills reads the 796 * pmap as inactive on the other processor. 797 * 798 * The kernel page table is exempt because its pm_active field is 799 * immutable. The kernel page table is always active on every 800 * processor. 801 */ 802void 803pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 804{ 805 cpuset_t cpumask, other_cpus; 806 807 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 808 pmap, va); 809 810 sched_pin(); 811 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 812 invlpg(va); 813 smp_invlpg(va); 814 } else { 815 cpumask = PCPU_GET(cpumask); 816 other_cpus = PCPU_GET(other_cpus); 817 if (CPU_OVERLAP(&pmap->pm_active, &cpumask)) 818 invlpg(va); 819 CPU_AND(&other_cpus, &pmap->pm_active); 820 if (!CPU_EMPTY(&other_cpus)) 821 smp_masked_invlpg(other_cpus, va); 822 } 823 sched_unpin(); 824 PT_UPDATES_FLUSH(); 825} 826 827void 828pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 829{ 830 cpuset_t cpumask, other_cpus; 831 vm_offset_t addr; 832 833 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 834 pmap, sva, eva); 835 836 sched_pin(); 837 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 838 for (addr = sva; addr < eva; addr += PAGE_SIZE) 839 invlpg(addr); 840 smp_invlpg_range(sva, eva); 841 } else { 842 cpumask = PCPU_GET(cpumask); 843 other_cpus = PCPU_GET(other_cpus); 844 if (CPU_OVERLAP(&pmap->pm_active, &cpumask)) 845 for (addr = sva; addr < eva; addr += PAGE_SIZE) 846 invlpg(addr); 847 CPU_AND(&other_cpus, &pmap->pm_active); 848 if (!CPU_EMPTY(&other_cpus)) 849 smp_masked_invlpg_range(other_cpus, sva, eva); 850 } 851 sched_unpin(); 852 PT_UPDATES_FLUSH(); 853} 854 855void 856pmap_invalidate_all(pmap_t pmap) 857{ 858 cpuset_t cpumask, other_cpus; 859 860 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 861 862 sched_pin(); 863 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 864 invltlb(); 865 smp_invltlb(); 866 } else { 867 cpumask = PCPU_GET(cpumask); 868 other_cpus = PCPU_GET(other_cpus); 869 if (CPU_OVERLAP(&pmap->pm_active, &cpumask)) 870 invltlb(); 871 CPU_AND(&other_cpus, &pmap->pm_active); 872 if (!CPU_EMPTY(&other_cpus)) 873 smp_masked_invltlb(other_cpus); 874 } 875 sched_unpin(); 876} 877 878void 879pmap_invalidate_cache(void) 880{ 881 882 sched_pin(); 883 wbinvd(); 884 smp_cache_flush(); 885 sched_unpin(); 886} 887#else /* !SMP */ 888/* 889 * Normal, non-SMP, 486+ invalidation functions. 890 * We inline these within pmap.c for speed. 891 */ 892PMAP_INLINE void 893pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 894{ 895 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 896 pmap, va); 897 898 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 899 invlpg(va); 900 PT_UPDATES_FLUSH(); 901} 902 903PMAP_INLINE void 904pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 905{ 906 vm_offset_t addr; 907 908 if (eva - sva > PAGE_SIZE) 909 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 910 pmap, sva, eva); 911 912 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 913 for (addr = sva; addr < eva; addr += PAGE_SIZE) 914 invlpg(addr); 915 PT_UPDATES_FLUSH(); 916} 917 918PMAP_INLINE void 919pmap_invalidate_all(pmap_t pmap) 920{ 921 922 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 923 924 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 925 invltlb(); 926} 927 928PMAP_INLINE void 929pmap_invalidate_cache(void) 930{ 931 932 wbinvd(); 933} 934#endif /* !SMP */ 935 936void 937pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 938{ 939 940 KASSERT((sva & PAGE_MASK) == 0, 941 ("pmap_invalidate_cache_range: sva not page-aligned")); 942 KASSERT((eva & PAGE_MASK) == 0, 943 ("pmap_invalidate_cache_range: eva not page-aligned")); 944 945 if (cpu_feature & CPUID_SS) 946 ; /* If "Self Snoop" is supported, do nothing. */ 947 else if (cpu_feature & CPUID_CLFSH) { 948 949 /* 950 * Otherwise, do per-cache line flush. Use the mfence 951 * instruction to insure that previous stores are 952 * included in the write-back. The processor 953 * propagates flush to other processors in the cache 954 * coherence domain. 955 */ 956 mfence(); 957 for (; sva < eva; sva += cpu_clflush_line_size) 958 clflush(sva); 959 mfence(); 960 } else { 961 962 /* 963 * No targeted cache flush methods are supported by CPU, 964 * globally invalidate cache as a last resort. 965 */ 966 pmap_invalidate_cache(); 967 } 968} 969 970/* 971 * Are we current address space or kernel? N.B. We return FALSE when 972 * a pmap's page table is in use because a kernel thread is borrowing 973 * it. The borrowed page table can change spontaneously, making any 974 * dependence on its continued use subject to a race condition. 975 */ 976static __inline int 977pmap_is_current(pmap_t pmap) 978{ 979 980 return (pmap == kernel_pmap || 981 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 982 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 983} 984 985/* 986 * If the given pmap is not the current or kernel pmap, the returned pte must 987 * be released by passing it to pmap_pte_release(). 988 */ 989pt_entry_t * 990pmap_pte(pmap_t pmap, vm_offset_t va) 991{ 992 pd_entry_t newpf; 993 pd_entry_t *pde; 994 995 pde = pmap_pde(pmap, va); 996 if (*pde & PG_PS) 997 return (pde); 998 if (*pde != 0) { 999 /* are we current address space or kernel? */ 1000 if (pmap_is_current(pmap)) 1001 return (vtopte(va)); 1002 mtx_lock(&PMAP2mutex); 1003 newpf = *pde & PG_FRAME; 1004 if ((*PMAP2 & PG_FRAME) != newpf) { 1005 vm_page_lock_queues(); 1006 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 1007 vm_page_unlock_queues(); 1008 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 1009 pmap, va, (*PMAP2 & 0xffffffff)); 1010 } 1011 1012 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1013 } 1014 return (0); 1015} 1016 1017/* 1018 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1019 * being NULL. 1020 */ 1021static __inline void 1022pmap_pte_release(pt_entry_t *pte) 1023{ 1024 1025 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 1026 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 1027 *PMAP2); 1028 vm_page_lock_queues(); 1029 PT_SET_VA(PMAP2, 0, TRUE); 1030 vm_page_unlock_queues(); 1031 mtx_unlock(&PMAP2mutex); 1032 } 1033} 1034 1035static __inline void 1036invlcaddr(void *caddr) 1037{ 1038 1039 invlpg((u_int)caddr); 1040 PT_UPDATES_FLUSH(); 1041} 1042 1043/* 1044 * Super fast pmap_pte routine best used when scanning 1045 * the pv lists. This eliminates many coarse-grained 1046 * invltlb calls. Note that many of the pv list 1047 * scans are across different pmaps. It is very wasteful 1048 * to do an entire invltlb for checking a single mapping. 1049 * 1050 * If the given pmap is not the current pmap, vm_page_queue_mtx 1051 * must be held and curthread pinned to a CPU. 1052 */ 1053static pt_entry_t * 1054pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1055{ 1056 pd_entry_t newpf; 1057 pd_entry_t *pde; 1058 1059 pde = pmap_pde(pmap, va); 1060 if (*pde & PG_PS) 1061 return (pde); 1062 if (*pde != 0) { 1063 /* are we current address space or kernel? */ 1064 if (pmap_is_current(pmap)) 1065 return (vtopte(va)); 1066 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1067 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1068 newpf = *pde & PG_FRAME; 1069 if ((*PMAP1 & PG_FRAME) != newpf) { 1070 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1071 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1072 pmap, va, (u_long)*PMAP1); 1073 1074#ifdef SMP 1075 PMAP1cpu = PCPU_GET(cpuid); 1076#endif 1077 PMAP1changed++; 1078 } else 1079#ifdef SMP 1080 if (PMAP1cpu != PCPU_GET(cpuid)) { 1081 PMAP1cpu = PCPU_GET(cpuid); 1082 invlcaddr(PADDR1); 1083 PMAP1changedcpu++; 1084 } else 1085#endif 1086 PMAP1unchanged++; 1087 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1088 } 1089 return (0); 1090} 1091 1092/* 1093 * Routine: pmap_extract 1094 * Function: 1095 * Extract the physical page address associated 1096 * with the given map/virtual_address pair. 1097 */ 1098vm_paddr_t 1099pmap_extract(pmap_t pmap, vm_offset_t va) 1100{ 1101 vm_paddr_t rtval; 1102 pt_entry_t *pte; 1103 pd_entry_t pde; 1104 pt_entry_t pteval; 1105 1106 rtval = 0; 1107 PMAP_LOCK(pmap); 1108 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1109 if (pde != 0) { 1110 if ((pde & PG_PS) != 0) { 1111 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1112 PMAP_UNLOCK(pmap); 1113 return rtval; 1114 } 1115 pte = pmap_pte(pmap, va); 1116 pteval = *pte ? xpmap_mtop(*pte) : 0; 1117 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1118 pmap_pte_release(pte); 1119 } 1120 PMAP_UNLOCK(pmap); 1121 return (rtval); 1122} 1123 1124/* 1125 * Routine: pmap_extract_ma 1126 * Function: 1127 * Like pmap_extract, but returns machine address 1128 */ 1129vm_paddr_t 1130pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1131{ 1132 vm_paddr_t rtval; 1133 pt_entry_t *pte; 1134 pd_entry_t pde; 1135 1136 rtval = 0; 1137 PMAP_LOCK(pmap); 1138 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1139 if (pde != 0) { 1140 if ((pde & PG_PS) != 0) { 1141 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1142 PMAP_UNLOCK(pmap); 1143 return rtval; 1144 } 1145 pte = pmap_pte(pmap, va); 1146 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1147 pmap_pte_release(pte); 1148 } 1149 PMAP_UNLOCK(pmap); 1150 return (rtval); 1151} 1152 1153/* 1154 * Routine: pmap_extract_and_hold 1155 * Function: 1156 * Atomically extract and hold the physical page 1157 * with the given pmap and virtual address pair 1158 * if that mapping permits the given protection. 1159 */ 1160vm_page_t 1161pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1162{ 1163 pd_entry_t pde; 1164 pt_entry_t pte; 1165 vm_page_t m; 1166 vm_paddr_t pa; 1167 1168 pa = 0; 1169 m = NULL; 1170 PMAP_LOCK(pmap); 1171retry: 1172 pde = PT_GET(pmap_pde(pmap, va)); 1173 if (pde != 0) { 1174 if (pde & PG_PS) { 1175 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1176 if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) | 1177 (va & PDRMASK), &pa)) 1178 goto retry; 1179 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1180 (va & PDRMASK)); 1181 vm_page_hold(m); 1182 } 1183 } else { 1184 sched_pin(); 1185 pte = PT_GET(pmap_pte_quick(pmap, va)); 1186 if (*PMAP1) 1187 PT_SET_MA(PADDR1, 0); 1188 if ((pte & PG_V) && 1189 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1190 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa)) 1191 goto retry; 1192 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1193 vm_page_hold(m); 1194 } 1195 sched_unpin(); 1196 } 1197 } 1198 PA_UNLOCK_COND(pa); 1199 PMAP_UNLOCK(pmap); 1200 return (m); 1201} 1202 1203/*************************************************** 1204 * Low level mapping routines..... 1205 ***************************************************/ 1206 1207/* 1208 * Add a wired page to the kva. 1209 * Note: not SMP coherent. 1210 */ 1211void 1212pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1213{ 1214 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1215} 1216 1217void 1218pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1219{ 1220 pt_entry_t *pte; 1221 1222 pte = vtopte(va); 1223 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1224} 1225 1226 1227static __inline void 1228pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1229{ 1230 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1231} 1232 1233/* 1234 * Remove a page from the kernel pagetables. 1235 * Note: not SMP coherent. 1236 */ 1237PMAP_INLINE void 1238pmap_kremove(vm_offset_t va) 1239{ 1240 pt_entry_t *pte; 1241 1242 pte = vtopte(va); 1243 PT_CLEAR_VA(pte, FALSE); 1244} 1245 1246/* 1247 * Used to map a range of physical addresses into kernel 1248 * virtual address space. 1249 * 1250 * The value passed in '*virt' is a suggested virtual address for 1251 * the mapping. Architectures which can support a direct-mapped 1252 * physical to virtual region can return the appropriate address 1253 * within that region, leaving '*virt' unchanged. Other 1254 * architectures should map the pages starting at '*virt' and 1255 * update '*virt' with the first usable address after the mapped 1256 * region. 1257 */ 1258vm_offset_t 1259pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1260{ 1261 vm_offset_t va, sva; 1262 1263 va = sva = *virt; 1264 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1265 va, start, end, prot); 1266 while (start < end) { 1267 pmap_kenter(va, start); 1268 va += PAGE_SIZE; 1269 start += PAGE_SIZE; 1270 } 1271 pmap_invalidate_range(kernel_pmap, sva, va); 1272 *virt = va; 1273 return (sva); 1274} 1275 1276 1277/* 1278 * Add a list of wired pages to the kva 1279 * this routine is only used for temporary 1280 * kernel mappings that do not need to have 1281 * page modification or references recorded. 1282 * Note that old mappings are simply written 1283 * over. The page *must* be wired. 1284 * Note: SMP coherent. Uses a ranged shootdown IPI. 1285 */ 1286void 1287pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1288{ 1289 pt_entry_t *endpte, *pte; 1290 vm_paddr_t pa; 1291 vm_offset_t va = sva; 1292 int mclcount = 0; 1293 multicall_entry_t mcl[16]; 1294 multicall_entry_t *mclp = mcl; 1295 int error; 1296 1297 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1298 pte = vtopte(sva); 1299 endpte = pte + count; 1300 while (pte < endpte) { 1301 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1302 1303 mclp->op = __HYPERVISOR_update_va_mapping; 1304 mclp->args[0] = va; 1305 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1306 mclp->args[2] = (uint32_t)(pa >> 32); 1307 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1308 1309 va += PAGE_SIZE; 1310 pte++; 1311 ma++; 1312 mclp++; 1313 mclcount++; 1314 if (mclcount == 16) { 1315 error = HYPERVISOR_multicall(mcl, mclcount); 1316 mclp = mcl; 1317 mclcount = 0; 1318 KASSERT(error == 0, ("bad multicall %d", error)); 1319 } 1320 } 1321 if (mclcount) { 1322 error = HYPERVISOR_multicall(mcl, mclcount); 1323 KASSERT(error == 0, ("bad multicall %d", error)); 1324 } 1325 1326#ifdef INVARIANTS 1327 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1328 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1329#endif 1330} 1331 1332 1333/* 1334 * This routine tears out page mappings from the 1335 * kernel -- it is meant only for temporary mappings. 1336 * Note: SMP coherent. Uses a ranged shootdown IPI. 1337 */ 1338void 1339pmap_qremove(vm_offset_t sva, int count) 1340{ 1341 vm_offset_t va; 1342 1343 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1344 va = sva; 1345 vm_page_lock_queues(); 1346 critical_enter(); 1347 while (count-- > 0) { 1348 pmap_kremove(va); 1349 va += PAGE_SIZE; 1350 } 1351 PT_UPDATES_FLUSH(); 1352 pmap_invalidate_range(kernel_pmap, sva, va); 1353 critical_exit(); 1354 vm_page_unlock_queues(); 1355} 1356 1357/*************************************************** 1358 * Page table page management routines..... 1359 ***************************************************/ 1360static __inline void 1361pmap_free_zero_pages(vm_page_t free) 1362{ 1363 vm_page_t m; 1364 1365 while (free != NULL) { 1366 m = free; 1367 free = m->right; 1368 vm_page_free_zero(m); 1369 } 1370} 1371 1372/* 1373 * This routine unholds page table pages, and if the hold count 1374 * drops to zero, then it decrements the wire count. 1375 */ 1376static __inline int 1377pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1378{ 1379 1380 --m->wire_count; 1381 if (m->wire_count == 0) 1382 return _pmap_unwire_pte_hold(pmap, m, free); 1383 else 1384 return 0; 1385} 1386 1387static int 1388_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1389{ 1390 vm_offset_t pteva; 1391 1392 PT_UPDATES_FLUSH(); 1393 /* 1394 * unmap the page table page 1395 */ 1396 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1397 /* 1398 * page *might* contain residual mapping :-/ 1399 */ 1400 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1401 pmap_zero_page(m); 1402 --pmap->pm_stats.resident_count; 1403 1404 /* 1405 * This is a release store so that the ordinary store unmapping 1406 * the page table page is globally performed before TLB shoot- 1407 * down is begun. 1408 */ 1409 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1410 1411 /* 1412 * Do an invltlb to make the invalidated mapping 1413 * take effect immediately. 1414 */ 1415 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1416 pmap_invalidate_page(pmap, pteva); 1417 1418 /* 1419 * Put page on a list so that it is released after 1420 * *ALL* TLB shootdown is done 1421 */ 1422 m->right = *free; 1423 *free = m; 1424 1425 return 1; 1426} 1427 1428/* 1429 * After removing a page table entry, this routine is used to 1430 * conditionally free the page, and manage the hold/wire counts. 1431 */ 1432static int 1433pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1434{ 1435 pd_entry_t ptepde; 1436 vm_page_t mpte; 1437 1438 if (va >= VM_MAXUSER_ADDRESS) 1439 return 0; 1440 ptepde = PT_GET(pmap_pde(pmap, va)); 1441 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1442 return pmap_unwire_pte_hold(pmap, mpte, free); 1443} 1444 1445void 1446pmap_pinit0(pmap_t pmap) 1447{ 1448 1449 PMAP_LOCK_INIT(pmap); 1450 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1451#ifdef PAE 1452 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1453#endif 1454 CPU_ZERO(&pmap->pm_active); 1455 PCPU_SET(curpmap, pmap); 1456 TAILQ_INIT(&pmap->pm_pvchunk); 1457 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1458 mtx_lock_spin(&allpmaps_lock); 1459 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1460 mtx_unlock_spin(&allpmaps_lock); 1461} 1462 1463/* 1464 * Initialize a preallocated and zeroed pmap structure, 1465 * such as one in a vmspace structure. 1466 */ 1467int 1468pmap_pinit(pmap_t pmap) 1469{ 1470 vm_page_t m, ptdpg[NPGPTD + 1]; 1471 int npgptd = NPGPTD + 1; 1472 static int color; 1473 int i; 1474 1475#ifdef HAMFISTED_LOCKING 1476 mtx_lock(&createdelete_lock); 1477#endif 1478 1479 PMAP_LOCK_INIT(pmap); 1480 1481 /* 1482 * No need to allocate page table space yet but we do need a valid 1483 * page directory table. 1484 */ 1485 if (pmap->pm_pdir == NULL) { 1486 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1487 NBPTD); 1488 if (pmap->pm_pdir == NULL) { 1489 PMAP_LOCK_DESTROY(pmap); 1490#ifdef HAMFISTED_LOCKING 1491 mtx_unlock(&createdelete_lock); 1492#endif 1493 return (0); 1494 } 1495#ifdef PAE 1496 pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1497#endif 1498 } 1499 1500 /* 1501 * allocate the page directory page(s) 1502 */ 1503 for (i = 0; i < npgptd;) { 1504 m = vm_page_alloc(NULL, color++, 1505 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1506 VM_ALLOC_ZERO); 1507 if (m == NULL) 1508 VM_WAIT; 1509 else { 1510 ptdpg[i++] = m; 1511 } 1512 } 1513 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1514 for (i = 0; i < NPGPTD; i++) { 1515 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1516 pagezero(&pmap->pm_pdir[i*NPTEPG]); 1517 } 1518 1519 mtx_lock_spin(&allpmaps_lock); 1520 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1521 mtx_unlock_spin(&allpmaps_lock); 1522 /* Wire in kernel global address entries. */ 1523 1524 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1525#ifdef PAE 1526 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1527 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1528 bzero(pmap->pm_pdpt, PAGE_SIZE); 1529 for (i = 0; i < NPGPTD; i++) { 1530 vm_paddr_t ma; 1531 1532 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1533 pmap->pm_pdpt[i] = ma | PG_V; 1534 1535 } 1536#endif 1537 for (i = 0; i < NPGPTD; i++) { 1538 pt_entry_t *pd; 1539 vm_paddr_t ma; 1540 1541 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1542 pd = pmap->pm_pdir + (i * NPDEPG); 1543 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1544#if 0 1545 xen_pgd_pin(ma); 1546#endif 1547 } 1548 1549#ifdef PAE 1550 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1551#endif 1552 vm_page_lock_queues(); 1553 xen_flush_queue(); 1554 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1555 for (i = 0; i < NPGPTD; i++) { 1556 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1557 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1558 } 1559 xen_flush_queue(); 1560 vm_page_unlock_queues(); 1561 CPU_ZERO(&pmap->pm_active); 1562 TAILQ_INIT(&pmap->pm_pvchunk); 1563 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1564 1565#ifdef HAMFISTED_LOCKING 1566 mtx_unlock(&createdelete_lock); 1567#endif 1568 return (1); 1569} 1570 1571/* 1572 * this routine is called if the page table page is not 1573 * mapped correctly. 1574 */ 1575static vm_page_t 1576_pmap_allocpte(pmap_t pmap, unsigned int ptepindex, int flags) 1577{ 1578 vm_paddr_t ptema; 1579 vm_page_t m; 1580 1581 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1582 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1583 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1584 1585 /* 1586 * Allocate a page table page. 1587 */ 1588 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1589 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1590 if (flags & M_WAITOK) { 1591 PMAP_UNLOCK(pmap); 1592 vm_page_unlock_queues(); 1593 VM_WAIT; 1594 vm_page_lock_queues(); 1595 PMAP_LOCK(pmap); 1596 } 1597 1598 /* 1599 * Indicate the need to retry. While waiting, the page table 1600 * page may have been allocated. 1601 */ 1602 return (NULL); 1603 } 1604 if ((m->flags & PG_ZERO) == 0) 1605 pmap_zero_page(m); 1606 1607 /* 1608 * Map the pagetable page into the process address space, if 1609 * it isn't already there. 1610 */ 1611 pmap->pm_stats.resident_count++; 1612 1613 ptema = VM_PAGE_TO_MACH(m); 1614 xen_pt_pin(ptema); 1615 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1616 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1617 1618 KASSERT(pmap->pm_pdir[ptepindex], 1619 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1620 return (m); 1621} 1622 1623static vm_page_t 1624pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1625{ 1626 unsigned ptepindex; 1627 pd_entry_t ptema; 1628 vm_page_t m; 1629 1630 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1631 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1632 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1633 1634 /* 1635 * Calculate pagetable page index 1636 */ 1637 ptepindex = va >> PDRSHIFT; 1638retry: 1639 /* 1640 * Get the page directory entry 1641 */ 1642 ptema = pmap->pm_pdir[ptepindex]; 1643 1644 /* 1645 * This supports switching from a 4MB page to a 1646 * normal 4K page. 1647 */ 1648 if (ptema & PG_PS) { 1649 /* 1650 * XXX 1651 */ 1652 pmap->pm_pdir[ptepindex] = 0; 1653 ptema = 0; 1654 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1655 pmap_invalidate_all(kernel_pmap); 1656 } 1657 1658 /* 1659 * If the page table page is mapped, we just increment the 1660 * hold count, and activate it. 1661 */ 1662 if (ptema & PG_V) { 1663 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1664 m->wire_count++; 1665 } else { 1666 /* 1667 * Here if the pte page isn't mapped, or if it has 1668 * been deallocated. 1669 */ 1670 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1671 pmap, va, flags); 1672 m = _pmap_allocpte(pmap, ptepindex, flags); 1673 if (m == NULL && (flags & M_WAITOK)) 1674 goto retry; 1675 1676 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1677 } 1678 return (m); 1679} 1680 1681 1682/*************************************************** 1683* Pmap allocation/deallocation routines. 1684 ***************************************************/ 1685 1686#ifdef SMP 1687/* 1688 * Deal with a SMP shootdown of other users of the pmap that we are 1689 * trying to dispose of. This can be a bit hairy. 1690 */ 1691static cpuset_t *lazymask; 1692static u_int lazyptd; 1693static volatile u_int lazywait; 1694 1695void pmap_lazyfix_action(void); 1696 1697void 1698pmap_lazyfix_action(void) 1699{ 1700 1701#ifdef COUNT_IPIS 1702 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1703#endif 1704 if (rcr3() == lazyptd) 1705 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1706 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1707 atomic_store_rel_int(&lazywait, 1); 1708} 1709 1710static void 1711pmap_lazyfix_self(cpuset_t mymask) 1712{ 1713 1714 if (rcr3() == lazyptd) 1715 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1716 CPU_NAND_ATOMIC(lazymask, &mymask); 1717} 1718 1719 1720static void 1721pmap_lazyfix(pmap_t pmap) 1722{ 1723 cpuset_t mymask, mask; 1724 u_int spins; 1725 int lsb; 1726 1727 mask = pmap->pm_active; 1728 while (!CPU_EMPTY(&mask)) { 1729 spins = 50000000; 1730 1731 /* Find least significant set bit. */ 1732 lsb = cpusetobj_ffs(&mask); 1733 MPASS(lsb != 0); 1734 lsb--; 1735 CPU_SETOF(lsb, &mask); 1736 mtx_lock_spin(&smp_ipi_mtx); 1737#ifdef PAE 1738 lazyptd = vtophys(pmap->pm_pdpt); 1739#else 1740 lazyptd = vtophys(pmap->pm_pdir); 1741#endif 1742 mymask = PCPU_GET(cpumask); 1743 if (!CPU_CMP(&mask, &mymask)) { 1744 lazymask = &pmap->pm_active; 1745 pmap_lazyfix_self(mymask); 1746 } else { 1747 atomic_store_rel_int((u_int *)&lazymask, 1748 (u_int)&pmap->pm_active); 1749 atomic_store_rel_int(&lazywait, 0); 1750 ipi_selected(mask, IPI_LAZYPMAP); 1751 while (lazywait == 0) { 1752 ia32_pause(); 1753 if (--spins == 0) 1754 break; 1755 } 1756 } 1757 mtx_unlock_spin(&smp_ipi_mtx); 1758 if (spins == 0) 1759 printf("pmap_lazyfix: spun for 50000000\n"); 1760 mask = pmap->pm_active; 1761 } 1762} 1763 1764#else /* SMP */ 1765 1766/* 1767 * Cleaning up on uniprocessor is easy. For various reasons, we're 1768 * unlikely to have to even execute this code, including the fact 1769 * that the cleanup is deferred until the parent does a wait(2), which 1770 * means that another userland process has run. 1771 */ 1772static void 1773pmap_lazyfix(pmap_t pmap) 1774{ 1775 u_int cr3; 1776 1777 cr3 = vtophys(pmap->pm_pdir); 1778 if (cr3 == rcr3()) { 1779 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1780 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 1781 } 1782} 1783#endif /* SMP */ 1784 1785/* 1786 * Release any resources held by the given physical map. 1787 * Called when a pmap initialized by pmap_pinit is being released. 1788 * Should only be called if the map contains no valid mappings. 1789 */ 1790void 1791pmap_release(pmap_t pmap) 1792{ 1793 vm_page_t m, ptdpg[2*NPGPTD+1]; 1794 vm_paddr_t ma; 1795 int i; 1796#ifdef PAE 1797 int npgptd = NPGPTD + 1; 1798#else 1799 int npgptd = NPGPTD; 1800#endif 1801 KASSERT(pmap->pm_stats.resident_count == 0, 1802 ("pmap_release: pmap resident count %ld != 0", 1803 pmap->pm_stats.resident_count)); 1804 PT_UPDATES_FLUSH(); 1805 1806#ifdef HAMFISTED_LOCKING 1807 mtx_lock(&createdelete_lock); 1808#endif 1809 1810 pmap_lazyfix(pmap); 1811 mtx_lock_spin(&allpmaps_lock); 1812 LIST_REMOVE(pmap, pm_list); 1813 mtx_unlock_spin(&allpmaps_lock); 1814 1815 for (i = 0; i < NPGPTD; i++) 1816 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1817 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1818#ifdef PAE 1819 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1820#endif 1821 1822 for (i = 0; i < npgptd; i++) { 1823 m = ptdpg[i]; 1824 ma = VM_PAGE_TO_MACH(m); 1825 /* unpinning L1 and L2 treated the same */ 1826#if 0 1827 xen_pgd_unpin(ma); 1828#else 1829 if (i == NPGPTD) 1830 xen_pgd_unpin(ma); 1831#endif 1832#ifdef PAE 1833 if (i < NPGPTD) 1834 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1835 ("pmap_release: got wrong ptd page")); 1836#endif 1837 m->wire_count--; 1838 atomic_subtract_int(&cnt.v_wire_count, 1); 1839 vm_page_free(m); 1840 } 1841#ifdef PAE 1842 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1843#endif 1844 PMAP_LOCK_DESTROY(pmap); 1845 1846#ifdef HAMFISTED_LOCKING 1847 mtx_unlock(&createdelete_lock); 1848#endif 1849} 1850 1851static int 1852kvm_size(SYSCTL_HANDLER_ARGS) 1853{ 1854 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1855 1856 return sysctl_handle_long(oidp, &ksize, 0, req); 1857} 1858SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1859 0, 0, kvm_size, "IU", "Size of KVM"); 1860 1861static int 1862kvm_free(SYSCTL_HANDLER_ARGS) 1863{ 1864 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1865 1866 return sysctl_handle_long(oidp, &kfree, 0, req); 1867} 1868SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1869 0, 0, kvm_free, "IU", "Amount of KVM free"); 1870 1871/* 1872 * grow the number of kernel page table entries, if needed 1873 */ 1874void 1875pmap_growkernel(vm_offset_t addr) 1876{ 1877 struct pmap *pmap; 1878 vm_paddr_t ptppaddr; 1879 vm_page_t nkpg; 1880 pd_entry_t newpdir; 1881 1882 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1883 if (kernel_vm_end == 0) { 1884 kernel_vm_end = KERNBASE; 1885 nkpt = 0; 1886 while (pdir_pde(PTD, kernel_vm_end)) { 1887 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1888 nkpt++; 1889 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1890 kernel_vm_end = kernel_map->max_offset; 1891 break; 1892 } 1893 } 1894 } 1895 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1896 if (addr - 1 >= kernel_map->max_offset) 1897 addr = kernel_map->max_offset; 1898 while (kernel_vm_end < addr) { 1899 if (pdir_pde(PTD, kernel_vm_end)) { 1900 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1901 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1902 kernel_vm_end = kernel_map->max_offset; 1903 break; 1904 } 1905 continue; 1906 } 1907 1908 /* 1909 * This index is bogus, but out of the way 1910 */ 1911 nkpg = vm_page_alloc(NULL, nkpt, 1912 VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED); 1913 if (!nkpg) 1914 panic("pmap_growkernel: no memory to grow kernel"); 1915 1916 nkpt++; 1917 1918 pmap_zero_page(nkpg); 1919 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1920 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1921 vm_page_lock_queues(); 1922 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1923 mtx_lock_spin(&allpmaps_lock); 1924 LIST_FOREACH(pmap, &allpmaps, pm_list) 1925 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1926 1927 mtx_unlock_spin(&allpmaps_lock); 1928 vm_page_unlock_queues(); 1929 1930 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1931 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1932 kernel_vm_end = kernel_map->max_offset; 1933 break; 1934 } 1935 } 1936} 1937 1938 1939/*************************************************** 1940 * page management routines. 1941 ***************************************************/ 1942 1943CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1944CTASSERT(_NPCM == 11); 1945 1946static __inline struct pv_chunk * 1947pv_to_chunk(pv_entry_t pv) 1948{ 1949 1950 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1951} 1952 1953#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1954 1955#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1956#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1957 1958static uint32_t pc_freemask[11] = { 1959 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1960 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1961 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1962 PC_FREE0_9, PC_FREE10 1963}; 1964 1965SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1966 "Current number of pv entries"); 1967 1968#ifdef PV_STATS 1969static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1970 1971SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1972 "Current number of pv entry chunks"); 1973SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1974 "Current number of pv entry chunks allocated"); 1975SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1976 "Current number of pv entry chunks frees"); 1977SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1978 "Number of times tried to get a chunk page but failed."); 1979 1980static long pv_entry_frees, pv_entry_allocs; 1981static int pv_entry_spare; 1982 1983SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1984 "Current number of pv entry frees"); 1985SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1986 "Current number of pv entry allocs"); 1987SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1988 "Current number of spare pv entries"); 1989 1990static int pmap_collect_inactive, pmap_collect_active; 1991 1992SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 1993 "Current number times pmap_collect called on inactive queue"); 1994SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 1995 "Current number times pmap_collect called on active queue"); 1996#endif 1997 1998/* 1999 * We are in a serious low memory condition. Resort to 2000 * drastic measures to free some pages so we can allocate 2001 * another pv entry chunk. This is normally called to 2002 * unmap inactive pages, and if necessary, active pages. 2003 */ 2004static void 2005pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 2006{ 2007 pmap_t pmap; 2008 pt_entry_t *pte, tpte; 2009 pv_entry_t next_pv, pv; 2010 vm_offset_t va; 2011 vm_page_t m, free; 2012 2013 sched_pin(); 2014 TAILQ_FOREACH(m, &vpq->pl, pageq) { 2015 if (m->hold_count || m->busy) 2016 continue; 2017 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 2018 va = pv->pv_va; 2019 pmap = PV_PMAP(pv); 2020 /* Avoid deadlock and lock recursion. */ 2021 if (pmap > locked_pmap) 2022 PMAP_LOCK(pmap); 2023 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 2024 continue; 2025 pmap->pm_stats.resident_count--; 2026 pte = pmap_pte_quick(pmap, va); 2027 tpte = pte_load_clear(pte); 2028 KASSERT((tpte & PG_W) == 0, 2029 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2030 if (tpte & PG_A) 2031 vm_page_flag_set(m, PG_REFERENCED); 2032 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2033 vm_page_dirty(m); 2034 free = NULL; 2035 pmap_unuse_pt(pmap, va, &free); 2036 pmap_invalidate_page(pmap, va); 2037 pmap_free_zero_pages(free); 2038 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2039 free_pv_entry(pmap, pv); 2040 if (pmap != locked_pmap) 2041 PMAP_UNLOCK(pmap); 2042 } 2043 if (TAILQ_EMPTY(&m->md.pv_list)) 2044 vm_page_flag_clear(m, PG_WRITEABLE); 2045 } 2046 sched_unpin(); 2047} 2048 2049 2050/* 2051 * free the pv_entry back to the free list 2052 */ 2053static void 2054free_pv_entry(pmap_t pmap, pv_entry_t pv) 2055{ 2056 vm_page_t m; 2057 struct pv_chunk *pc; 2058 int idx, field, bit; 2059 2060 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2061 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2062 PV_STAT(pv_entry_frees++); 2063 PV_STAT(pv_entry_spare++); 2064 pv_entry_count--; 2065 pc = pv_to_chunk(pv); 2066 idx = pv - &pc->pc_pventry[0]; 2067 field = idx / 32; 2068 bit = idx % 32; 2069 pc->pc_map[field] |= 1ul << bit; 2070 /* move to head of list */ 2071 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2072 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2073 for (idx = 0; idx < _NPCM; idx++) 2074 if (pc->pc_map[idx] != pc_freemask[idx]) 2075 return; 2076 PV_STAT(pv_entry_spare -= _NPCPV); 2077 PV_STAT(pc_chunk_count--); 2078 PV_STAT(pc_chunk_frees++); 2079 /* entire chunk is free, return it */ 2080 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2081 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2082 pmap_qremove((vm_offset_t)pc, 1); 2083 vm_page_unwire(m, 0); 2084 vm_page_free(m); 2085 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2086} 2087 2088/* 2089 * get a new pv_entry, allocating a block from the system 2090 * when needed. 2091 */ 2092static pv_entry_t 2093get_pv_entry(pmap_t pmap, int try) 2094{ 2095 static const struct timeval printinterval = { 60, 0 }; 2096 static struct timeval lastprint; 2097 static vm_pindex_t colour; 2098 struct vpgqueues *pq; 2099 int bit, field; 2100 pv_entry_t pv; 2101 struct pv_chunk *pc; 2102 vm_page_t m; 2103 2104 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2105 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2106 PV_STAT(pv_entry_allocs++); 2107 pv_entry_count++; 2108 if (pv_entry_count > pv_entry_high_water) 2109 if (ratecheck(&lastprint, &printinterval)) 2110 printf("Approaching the limit on PV entries, consider " 2111 "increasing either the vm.pmap.shpgperproc or the " 2112 "vm.pmap.pv_entry_max tunable.\n"); 2113 pq = NULL; 2114retry: 2115 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2116 if (pc != NULL) { 2117 for (field = 0; field < _NPCM; field++) { 2118 if (pc->pc_map[field]) { 2119 bit = bsfl(pc->pc_map[field]); 2120 break; 2121 } 2122 } 2123 if (field < _NPCM) { 2124 pv = &pc->pc_pventry[field * 32 + bit]; 2125 pc->pc_map[field] &= ~(1ul << bit); 2126 /* If this was the last item, move it to tail */ 2127 for (field = 0; field < _NPCM; field++) 2128 if (pc->pc_map[field] != 0) { 2129 PV_STAT(pv_entry_spare--); 2130 return (pv); /* not full, return */ 2131 } 2132 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2133 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2134 PV_STAT(pv_entry_spare--); 2135 return (pv); 2136 } 2137 } 2138 /* 2139 * Access to the ptelist "pv_vafree" is synchronized by the page 2140 * queues lock. If "pv_vafree" is currently non-empty, it will 2141 * remain non-empty until pmap_ptelist_alloc() completes. 2142 */ 2143 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2144 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2145 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2146 if (try) { 2147 pv_entry_count--; 2148 PV_STAT(pc_chunk_tryfail++); 2149 return (NULL); 2150 } 2151 /* 2152 * Reclaim pv entries: At first, destroy mappings to 2153 * inactive pages. After that, if a pv chunk entry 2154 * is still needed, destroy mappings to active pages. 2155 */ 2156 if (pq == NULL) { 2157 PV_STAT(pmap_collect_inactive++); 2158 pq = &vm_page_queues[PQ_INACTIVE]; 2159 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2160 PV_STAT(pmap_collect_active++); 2161 pq = &vm_page_queues[PQ_ACTIVE]; 2162 } else 2163 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2164 pmap_collect(pmap, pq); 2165 goto retry; 2166 } 2167 PV_STAT(pc_chunk_count++); 2168 PV_STAT(pc_chunk_allocs++); 2169 colour++; 2170 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2171 pmap_qenter((vm_offset_t)pc, &m, 1); 2172 if ((m->flags & PG_ZERO) == 0) 2173 pagezero(pc); 2174 pc->pc_pmap = pmap; 2175 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2176 for (field = 1; field < _NPCM; field++) 2177 pc->pc_map[field] = pc_freemask[field]; 2178 pv = &pc->pc_pventry[0]; 2179 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2180 PV_STAT(pv_entry_spare += _NPCPV - 1); 2181 return (pv); 2182} 2183 2184static __inline pv_entry_t 2185pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2186{ 2187 pv_entry_t pv; 2188 2189 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2190 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2191 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2192 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2193 break; 2194 } 2195 } 2196 return (pv); 2197} 2198 2199static void 2200pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2201{ 2202 pv_entry_t pv; 2203 2204 pv = pmap_pvh_remove(pvh, pmap, va); 2205 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2206 free_pv_entry(pmap, pv); 2207} 2208 2209static void 2210pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2211{ 2212 2213 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2214 pmap_pvh_free(&m->md, pmap, va); 2215 if (TAILQ_EMPTY(&m->md.pv_list)) 2216 vm_page_flag_clear(m, PG_WRITEABLE); 2217} 2218 2219/* 2220 * Conditionally create a pv entry. 2221 */ 2222static boolean_t 2223pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2224{ 2225 pv_entry_t pv; 2226 2227 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2228 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2229 if (pv_entry_count < pv_entry_high_water && 2230 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2231 pv->pv_va = va; 2232 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2233 return (TRUE); 2234 } else 2235 return (FALSE); 2236} 2237 2238/* 2239 * pmap_remove_pte: do the things to unmap a page in a process 2240 */ 2241static int 2242pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2243{ 2244 pt_entry_t oldpte; 2245 vm_page_t m; 2246 2247 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2248 pmap, (u_long)*ptq, va); 2249 2250 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2251 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2252 oldpte = *ptq; 2253 PT_SET_VA_MA(ptq, 0, TRUE); 2254 if (oldpte & PG_W) 2255 pmap->pm_stats.wired_count -= 1; 2256 /* 2257 * Machines that don't support invlpg, also don't support 2258 * PG_G. 2259 */ 2260 if (oldpte & PG_G) 2261 pmap_invalidate_page(kernel_pmap, va); 2262 pmap->pm_stats.resident_count -= 1; 2263 if (oldpte & PG_MANAGED) { 2264 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2265 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2266 vm_page_dirty(m); 2267 if (oldpte & PG_A) 2268 vm_page_flag_set(m, PG_REFERENCED); 2269 pmap_remove_entry(pmap, m, va); 2270 } 2271 return (pmap_unuse_pt(pmap, va, free)); 2272} 2273 2274/* 2275 * Remove a single page from a process address space 2276 */ 2277static void 2278pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2279{ 2280 pt_entry_t *pte; 2281 2282 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2283 pmap, va); 2284 2285 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2286 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2287 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2288 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2289 return; 2290 pmap_remove_pte(pmap, pte, va, free); 2291 pmap_invalidate_page(pmap, va); 2292 if (*PMAP1) 2293 PT_SET_MA(PADDR1, 0); 2294 2295} 2296 2297/* 2298 * Remove the given range of addresses from the specified map. 2299 * 2300 * It is assumed that the start and end are properly 2301 * rounded to the page size. 2302 */ 2303void 2304pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2305{ 2306 vm_offset_t pdnxt; 2307 pd_entry_t ptpaddr; 2308 pt_entry_t *pte; 2309 vm_page_t free = NULL; 2310 int anyvalid; 2311 2312 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2313 pmap, sva, eva); 2314 2315 /* 2316 * Perform an unsynchronized read. This is, however, safe. 2317 */ 2318 if (pmap->pm_stats.resident_count == 0) 2319 return; 2320 2321 anyvalid = 0; 2322 2323 vm_page_lock_queues(); 2324 sched_pin(); 2325 PMAP_LOCK(pmap); 2326 2327 /* 2328 * special handling of removing one page. a very 2329 * common operation and easy to short circuit some 2330 * code. 2331 */ 2332 if ((sva + PAGE_SIZE == eva) && 2333 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2334 pmap_remove_page(pmap, sva, &free); 2335 goto out; 2336 } 2337 2338 for (; sva < eva; sva = pdnxt) { 2339 unsigned pdirindex; 2340 2341 /* 2342 * Calculate index for next page table. 2343 */ 2344 pdnxt = (sva + NBPDR) & ~PDRMASK; 2345 if (pmap->pm_stats.resident_count == 0) 2346 break; 2347 2348 pdirindex = sva >> PDRSHIFT; 2349 ptpaddr = pmap->pm_pdir[pdirindex]; 2350 2351 /* 2352 * Weed out invalid mappings. Note: we assume that the page 2353 * directory table is always allocated, and in kernel virtual. 2354 */ 2355 if (ptpaddr == 0) 2356 continue; 2357 2358 /* 2359 * Check for large page. 2360 */ 2361 if ((ptpaddr & PG_PS) != 0) { 2362 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2363 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2364 anyvalid = 1; 2365 continue; 2366 } 2367 2368 /* 2369 * Limit our scan to either the end of the va represented 2370 * by the current page table page, or to the end of the 2371 * range being removed. 2372 */ 2373 if (pdnxt > eva) 2374 pdnxt = eva; 2375 2376 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2377 sva += PAGE_SIZE) { 2378 if ((*pte & PG_V) == 0) 2379 continue; 2380 2381 /* 2382 * The TLB entry for a PG_G mapping is invalidated 2383 * by pmap_remove_pte(). 2384 */ 2385 if ((*pte & PG_G) == 0) 2386 anyvalid = 1; 2387 if (pmap_remove_pte(pmap, pte, sva, &free)) 2388 break; 2389 } 2390 } 2391 PT_UPDATES_FLUSH(); 2392 if (*PMAP1) 2393 PT_SET_VA_MA(PMAP1, 0, TRUE); 2394out: 2395 if (anyvalid) 2396 pmap_invalidate_all(pmap); 2397 sched_unpin(); 2398 vm_page_unlock_queues(); 2399 PMAP_UNLOCK(pmap); 2400 pmap_free_zero_pages(free); 2401} 2402 2403/* 2404 * Routine: pmap_remove_all 2405 * Function: 2406 * Removes this physical page from 2407 * all physical maps in which it resides. 2408 * Reflects back modify bits to the pager. 2409 * 2410 * Notes: 2411 * Original versions of this routine were very 2412 * inefficient because they iteratively called 2413 * pmap_remove (slow...) 2414 */ 2415 2416void 2417pmap_remove_all(vm_page_t m) 2418{ 2419 pv_entry_t pv; 2420 pmap_t pmap; 2421 pt_entry_t *pte, tpte; 2422 vm_page_t free; 2423 2424 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2425 ("pmap_remove_all: page %p is fictitious", m)); 2426 free = NULL; 2427 vm_page_lock_queues(); 2428 sched_pin(); 2429 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2430 pmap = PV_PMAP(pv); 2431 PMAP_LOCK(pmap); 2432 pmap->pm_stats.resident_count--; 2433 pte = pmap_pte_quick(pmap, pv->pv_va); 2434 2435 tpte = *pte; 2436 PT_SET_VA_MA(pte, 0, TRUE); 2437 if (tpte & PG_W) 2438 pmap->pm_stats.wired_count--; 2439 if (tpte & PG_A) 2440 vm_page_flag_set(m, PG_REFERENCED); 2441 2442 /* 2443 * Update the vm_page_t clean and reference bits. 2444 */ 2445 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2446 vm_page_dirty(m); 2447 pmap_unuse_pt(pmap, pv->pv_va, &free); 2448 pmap_invalidate_page(pmap, pv->pv_va); 2449 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2450 free_pv_entry(pmap, pv); 2451 PMAP_UNLOCK(pmap); 2452 } 2453 vm_page_flag_clear(m, PG_WRITEABLE); 2454 PT_UPDATES_FLUSH(); 2455 if (*PMAP1) 2456 PT_SET_MA(PADDR1, 0); 2457 sched_unpin(); 2458 vm_page_unlock_queues(); 2459 pmap_free_zero_pages(free); 2460} 2461 2462/* 2463 * Set the physical protection on the 2464 * specified range of this map as requested. 2465 */ 2466void 2467pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2468{ 2469 vm_offset_t pdnxt; 2470 pd_entry_t ptpaddr; 2471 pt_entry_t *pte; 2472 int anychanged; 2473 2474 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2475 pmap, sva, eva, prot); 2476 2477 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2478 pmap_remove(pmap, sva, eva); 2479 return; 2480 } 2481 2482#ifdef PAE 2483 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2484 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2485 return; 2486#else 2487 if (prot & VM_PROT_WRITE) 2488 return; 2489#endif 2490 2491 anychanged = 0; 2492 2493 vm_page_lock_queues(); 2494 sched_pin(); 2495 PMAP_LOCK(pmap); 2496 for (; sva < eva; sva = pdnxt) { 2497 pt_entry_t obits, pbits; 2498 unsigned pdirindex; 2499 2500 pdnxt = (sva + NBPDR) & ~PDRMASK; 2501 2502 pdirindex = sva >> PDRSHIFT; 2503 ptpaddr = pmap->pm_pdir[pdirindex]; 2504 2505 /* 2506 * Weed out invalid mappings. Note: we assume that the page 2507 * directory table is always allocated, and in kernel virtual. 2508 */ 2509 if (ptpaddr == 0) 2510 continue; 2511 2512 /* 2513 * Check for large page. 2514 */ 2515 if ((ptpaddr & PG_PS) != 0) { 2516 if ((prot & VM_PROT_WRITE) == 0) 2517 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2518#ifdef PAE 2519 if ((prot & VM_PROT_EXECUTE) == 0) 2520 pmap->pm_pdir[pdirindex] |= pg_nx; 2521#endif 2522 anychanged = 1; 2523 continue; 2524 } 2525 2526 if (pdnxt > eva) 2527 pdnxt = eva; 2528 2529 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2530 sva += PAGE_SIZE) { 2531 vm_page_t m; 2532 2533retry: 2534 /* 2535 * Regardless of whether a pte is 32 or 64 bits in 2536 * size, PG_RW, PG_A, and PG_M are among the least 2537 * significant 32 bits. 2538 */ 2539 obits = pbits = *pte; 2540 if ((pbits & PG_V) == 0) 2541 continue; 2542 2543 if ((prot & VM_PROT_WRITE) == 0) { 2544 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2545 (PG_MANAGED | PG_M | PG_RW)) { 2546 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2547 PG_FRAME); 2548 vm_page_dirty(m); 2549 } 2550 pbits &= ~(PG_RW | PG_M); 2551 } 2552#ifdef PAE 2553 if ((prot & VM_PROT_EXECUTE) == 0) 2554 pbits |= pg_nx; 2555#endif 2556 2557 if (pbits != obits) { 2558 obits = *pte; 2559 PT_SET_VA_MA(pte, pbits, TRUE); 2560 if (*pte != pbits) 2561 goto retry; 2562 if (obits & PG_G) 2563 pmap_invalidate_page(pmap, sva); 2564 else 2565 anychanged = 1; 2566 } 2567 } 2568 } 2569 PT_UPDATES_FLUSH(); 2570 if (*PMAP1) 2571 PT_SET_VA_MA(PMAP1, 0, TRUE); 2572 if (anychanged) 2573 pmap_invalidate_all(pmap); 2574 sched_unpin(); 2575 vm_page_unlock_queues(); 2576 PMAP_UNLOCK(pmap); 2577} 2578 2579/* 2580 * Insert the given physical page (p) at 2581 * the specified virtual address (v) in the 2582 * target physical map with the protection requested. 2583 * 2584 * If specified, the page will be wired down, meaning 2585 * that the related pte can not be reclaimed. 2586 * 2587 * NB: This is the only routine which MAY NOT lazy-evaluate 2588 * or lose information. That is, this routine must actually 2589 * insert this page into the given map NOW. 2590 */ 2591void 2592pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2593 vm_prot_t prot, boolean_t wired) 2594{ 2595 pd_entry_t *pde; 2596 pt_entry_t *pte; 2597 pt_entry_t newpte, origpte; 2598 pv_entry_t pv; 2599 vm_paddr_t opa, pa; 2600 vm_page_t mpte, om; 2601 boolean_t invlva; 2602 2603 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2604 pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2605 va = trunc_page(va); 2606 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2607 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2608 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2609 va)); 2610 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 2611 (m->oflags & VPO_BUSY) != 0, 2612 ("pmap_enter: page %p is not busy", m)); 2613 2614 mpte = NULL; 2615 2616 vm_page_lock_queues(); 2617 PMAP_LOCK(pmap); 2618 sched_pin(); 2619 2620 /* 2621 * In the case that a page table page is not 2622 * resident, we are creating it here. 2623 */ 2624 if (va < VM_MAXUSER_ADDRESS) { 2625 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2626 } 2627 2628 pde = pmap_pde(pmap, va); 2629 if ((*pde & PG_PS) != 0) 2630 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2631 pte = pmap_pte_quick(pmap, va); 2632 2633 /* 2634 * Page Directory table entry not valid, we need a new PT page 2635 */ 2636 if (pte == NULL) { 2637 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2638 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2639 } 2640 2641 pa = VM_PAGE_TO_PHYS(m); 2642 om = NULL; 2643 opa = origpte = 0; 2644 2645#if 0 2646 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2647 pte, *pte)); 2648#endif 2649 origpte = *pte; 2650 if (origpte) 2651 origpte = xpmap_mtop(origpte); 2652 opa = origpte & PG_FRAME; 2653 2654 /* 2655 * Mapping has not changed, must be protection or wiring change. 2656 */ 2657 if (origpte && (opa == pa)) { 2658 /* 2659 * Wiring change, just update stats. We don't worry about 2660 * wiring PT pages as they remain resident as long as there 2661 * are valid mappings in them. Hence, if a user page is wired, 2662 * the PT page will be also. 2663 */ 2664 if (wired && ((origpte & PG_W) == 0)) 2665 pmap->pm_stats.wired_count++; 2666 else if (!wired && (origpte & PG_W)) 2667 pmap->pm_stats.wired_count--; 2668 2669 /* 2670 * Remove extra pte reference 2671 */ 2672 if (mpte) 2673 mpte->wire_count--; 2674 2675 if (origpte & PG_MANAGED) { 2676 om = m; 2677 pa |= PG_MANAGED; 2678 } 2679 goto validate; 2680 } 2681 2682 pv = NULL; 2683 2684 /* 2685 * Mapping has changed, invalidate old range and fall through to 2686 * handle validating new mapping. 2687 */ 2688 if (opa) { 2689 if (origpte & PG_W) 2690 pmap->pm_stats.wired_count--; 2691 if (origpte & PG_MANAGED) { 2692 om = PHYS_TO_VM_PAGE(opa); 2693 pv = pmap_pvh_remove(&om->md, pmap, va); 2694 } else if (va < VM_MAXUSER_ADDRESS) 2695 printf("va=0x%x is unmanaged :-( \n", va); 2696 2697 if (mpte != NULL) { 2698 mpte->wire_count--; 2699 KASSERT(mpte->wire_count > 0, 2700 ("pmap_enter: missing reference to page table page," 2701 " va: 0x%x", va)); 2702 } 2703 } else 2704 pmap->pm_stats.resident_count++; 2705 2706 /* 2707 * Enter on the PV list if part of our managed memory. 2708 */ 2709 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 2710 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2711 ("pmap_enter: managed mapping within the clean submap")); 2712 if (pv == NULL) 2713 pv = get_pv_entry(pmap, FALSE); 2714 pv->pv_va = va; 2715 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2716 pa |= PG_MANAGED; 2717 } else if (pv != NULL) 2718 free_pv_entry(pmap, pv); 2719 2720 /* 2721 * Increment counters 2722 */ 2723 if (wired) 2724 pmap->pm_stats.wired_count++; 2725 2726validate: 2727 /* 2728 * Now validate mapping with desired protection/wiring. 2729 */ 2730 newpte = (pt_entry_t)(pa | PG_V); 2731 if ((prot & VM_PROT_WRITE) != 0) { 2732 newpte |= PG_RW; 2733 if ((newpte & PG_MANAGED) != 0) 2734 vm_page_flag_set(m, PG_WRITEABLE); 2735 } 2736#ifdef PAE 2737 if ((prot & VM_PROT_EXECUTE) == 0) 2738 newpte |= pg_nx; 2739#endif 2740 if (wired) 2741 newpte |= PG_W; 2742 if (va < VM_MAXUSER_ADDRESS) 2743 newpte |= PG_U; 2744 if (pmap == kernel_pmap) 2745 newpte |= pgeflag; 2746 2747 critical_enter(); 2748 /* 2749 * if the mapping or permission bits are different, we need 2750 * to update the pte. 2751 */ 2752 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2753 if (origpte) { 2754 invlva = FALSE; 2755 origpte = *pte; 2756 PT_SET_VA(pte, newpte | PG_A, FALSE); 2757 if (origpte & PG_A) { 2758 if (origpte & PG_MANAGED) 2759 vm_page_flag_set(om, PG_REFERENCED); 2760 if (opa != VM_PAGE_TO_PHYS(m)) 2761 invlva = TRUE; 2762#ifdef PAE 2763 if ((origpte & PG_NX) == 0 && 2764 (newpte & PG_NX) != 0) 2765 invlva = TRUE; 2766#endif 2767 } 2768 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2769 if ((origpte & PG_MANAGED) != 0) 2770 vm_page_dirty(om); 2771 if ((prot & VM_PROT_WRITE) == 0) 2772 invlva = TRUE; 2773 } 2774 if ((origpte & PG_MANAGED) != 0 && 2775 TAILQ_EMPTY(&om->md.pv_list)) 2776 vm_page_flag_clear(om, PG_WRITEABLE); 2777 if (invlva) 2778 pmap_invalidate_page(pmap, va); 2779 } else{ 2780 PT_SET_VA(pte, newpte | PG_A, FALSE); 2781 } 2782 2783 } 2784 PT_UPDATES_FLUSH(); 2785 critical_exit(); 2786 if (*PMAP1) 2787 PT_SET_VA_MA(PMAP1, 0, TRUE); 2788 sched_unpin(); 2789 vm_page_unlock_queues(); 2790 PMAP_UNLOCK(pmap); 2791} 2792 2793/* 2794 * Maps a sequence of resident pages belonging to the same object. 2795 * The sequence begins with the given page m_start. This page is 2796 * mapped at the given virtual address start. Each subsequent page is 2797 * mapped at a virtual address that is offset from start by the same 2798 * amount as the page is offset from m_start within the object. The 2799 * last page in the sequence is the page with the largest offset from 2800 * m_start that can be mapped at a virtual address less than the given 2801 * virtual address end. Not every virtual page between start and end 2802 * is mapped; only those for which a resident page exists with the 2803 * corresponding offset from m_start are mapped. 2804 */ 2805void 2806pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2807 vm_page_t m_start, vm_prot_t prot) 2808{ 2809 vm_page_t m, mpte; 2810 vm_pindex_t diff, psize; 2811 multicall_entry_t mcl[16]; 2812 multicall_entry_t *mclp = mcl; 2813 int error, count = 0; 2814 2815 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2816 psize = atop(end - start); 2817 2818 mpte = NULL; 2819 m = m_start; 2820 vm_page_lock_queues(); 2821 PMAP_LOCK(pmap); 2822 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2823 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2824 prot, mpte); 2825 m = TAILQ_NEXT(m, listq); 2826 if (count == 16) { 2827 error = HYPERVISOR_multicall(mcl, count); 2828 KASSERT(error == 0, ("bad multicall %d", error)); 2829 mclp = mcl; 2830 count = 0; 2831 } 2832 } 2833 if (count) { 2834 error = HYPERVISOR_multicall(mcl, count); 2835 KASSERT(error == 0, ("bad multicall %d", error)); 2836 } 2837 vm_page_unlock_queues(); 2838 PMAP_UNLOCK(pmap); 2839} 2840 2841/* 2842 * this code makes some *MAJOR* assumptions: 2843 * 1. Current pmap & pmap exists. 2844 * 2. Not wired. 2845 * 3. Read access. 2846 * 4. No page table pages. 2847 * but is *MUCH* faster than pmap_enter... 2848 */ 2849 2850void 2851pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2852{ 2853 multicall_entry_t mcl, *mclp; 2854 int count = 0; 2855 mclp = &mcl; 2856 2857 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2858 pmap, va, m, prot); 2859 2860 vm_page_lock_queues(); 2861 PMAP_LOCK(pmap); 2862 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2863 if (count) 2864 HYPERVISOR_multicall(&mcl, count); 2865 vm_page_unlock_queues(); 2866 PMAP_UNLOCK(pmap); 2867} 2868 2869#ifdef notyet 2870void 2871pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2872{ 2873 int i, error, index = 0; 2874 multicall_entry_t mcl[16]; 2875 multicall_entry_t *mclp = mcl; 2876 2877 PMAP_LOCK(pmap); 2878 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2879 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2880 continue; 2881 2882 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2883 if (index == 16) { 2884 error = HYPERVISOR_multicall(mcl, index); 2885 mclp = mcl; 2886 index = 0; 2887 KASSERT(error == 0, ("bad multicall %d", error)); 2888 } 2889 } 2890 if (index) { 2891 error = HYPERVISOR_multicall(mcl, index); 2892 KASSERT(error == 0, ("bad multicall %d", error)); 2893 } 2894 2895 PMAP_UNLOCK(pmap); 2896} 2897#endif 2898 2899static vm_page_t 2900pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2901 vm_prot_t prot, vm_page_t mpte) 2902{ 2903 pt_entry_t *pte; 2904 vm_paddr_t pa; 2905 vm_page_t free; 2906 multicall_entry_t *mcl = *mclpp; 2907 2908 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2909 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 2910 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2911 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2912 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2913 2914 /* 2915 * In the case that a page table page is not 2916 * resident, we are creating it here. 2917 */ 2918 if (va < VM_MAXUSER_ADDRESS) { 2919 unsigned ptepindex; 2920 pd_entry_t ptema; 2921 2922 /* 2923 * Calculate pagetable page index 2924 */ 2925 ptepindex = va >> PDRSHIFT; 2926 if (mpte && (mpte->pindex == ptepindex)) { 2927 mpte->wire_count++; 2928 } else { 2929 /* 2930 * Get the page directory entry 2931 */ 2932 ptema = pmap->pm_pdir[ptepindex]; 2933 2934 /* 2935 * If the page table page is mapped, we just increment 2936 * the hold count, and activate it. 2937 */ 2938 if (ptema & PG_V) { 2939 if (ptema & PG_PS) 2940 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2941 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2942 mpte->wire_count++; 2943 } else { 2944 mpte = _pmap_allocpte(pmap, ptepindex, 2945 M_NOWAIT); 2946 if (mpte == NULL) 2947 return (mpte); 2948 } 2949 } 2950 } else { 2951 mpte = NULL; 2952 } 2953 2954 /* 2955 * This call to vtopte makes the assumption that we are 2956 * entering the page into the current pmap. In order to support 2957 * quick entry into any pmap, one would likely use pmap_pte_quick. 2958 * But that isn't as quick as vtopte. 2959 */ 2960 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 2961 pte = vtopte(va); 2962 if (*pte & PG_V) { 2963 if (mpte != NULL) { 2964 mpte->wire_count--; 2965 mpte = NULL; 2966 } 2967 return (mpte); 2968 } 2969 2970 /* 2971 * Enter on the PV list if part of our managed memory. 2972 */ 2973 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 2974 !pmap_try_insert_pv_entry(pmap, va, m)) { 2975 if (mpte != NULL) { 2976 free = NULL; 2977 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 2978 pmap_invalidate_page(pmap, va); 2979 pmap_free_zero_pages(free); 2980 } 2981 2982 mpte = NULL; 2983 } 2984 return (mpte); 2985 } 2986 2987 /* 2988 * Increment counters 2989 */ 2990 pmap->pm_stats.resident_count++; 2991 2992 pa = VM_PAGE_TO_PHYS(m); 2993#ifdef PAE 2994 if ((prot & VM_PROT_EXECUTE) == 0) 2995 pa |= pg_nx; 2996#endif 2997 2998#if 0 2999 /* 3000 * Now validate mapping with RO protection 3001 */ 3002 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3003 pte_store(pte, pa | PG_V | PG_U); 3004 else 3005 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3006#else 3007 /* 3008 * Now validate mapping with RO protection 3009 */ 3010 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3011 pa = xpmap_ptom(pa | PG_V | PG_U); 3012 else 3013 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3014 3015 mcl->op = __HYPERVISOR_update_va_mapping; 3016 mcl->args[0] = va; 3017 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3018 mcl->args[2] = (uint32_t)(pa >> 32); 3019 mcl->args[3] = 0; 3020 *mclpp = mcl + 1; 3021 *count = *count + 1; 3022#endif 3023 return mpte; 3024} 3025 3026/* 3027 * Make a temporary mapping for a physical address. This is only intended 3028 * to be used for panic dumps. 3029 */ 3030void * 3031pmap_kenter_temporary(vm_paddr_t pa, int i) 3032{ 3033 vm_offset_t va; 3034 vm_paddr_t ma = xpmap_ptom(pa); 3035 3036 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3037 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3038 invlpg(va); 3039 return ((void *)crashdumpmap); 3040} 3041 3042/* 3043 * This code maps large physical mmap regions into the 3044 * processor address space. Note that some shortcuts 3045 * are taken, but the code works. 3046 */ 3047void 3048pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 3049 vm_object_t object, vm_pindex_t pindex, 3050 vm_size_t size) 3051{ 3052 pd_entry_t *pde; 3053 vm_paddr_t pa, ptepa; 3054 vm_page_t p; 3055 int pat_mode; 3056 3057 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3058 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3059 ("pmap_object_init_pt: non-device object")); 3060 if (pseflag && 3061 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3062 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3063 return; 3064 p = vm_page_lookup(object, pindex); 3065 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3066 ("pmap_object_init_pt: invalid page %p", p)); 3067 pat_mode = p->md.pat_mode; 3068 /* 3069 * Abort the mapping if the first page is not physically 3070 * aligned to a 2/4MB page boundary. 3071 */ 3072 ptepa = VM_PAGE_TO_PHYS(p); 3073 if (ptepa & (NBPDR - 1)) 3074 return; 3075 /* 3076 * Skip the first page. Abort the mapping if the rest of 3077 * the pages are not physically contiguous or have differing 3078 * memory attributes. 3079 */ 3080 p = TAILQ_NEXT(p, listq); 3081 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3082 pa += PAGE_SIZE) { 3083 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3084 ("pmap_object_init_pt: invalid page %p", p)); 3085 if (pa != VM_PAGE_TO_PHYS(p) || 3086 pat_mode != p->md.pat_mode) 3087 return; 3088 p = TAILQ_NEXT(p, listq); 3089 } 3090 /* Map using 2/4MB pages. */ 3091 PMAP_LOCK(pmap); 3092 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3093 size; pa += NBPDR) { 3094 pde = pmap_pde(pmap, addr); 3095 if (*pde == 0) { 3096 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3097 PG_U | PG_RW | PG_V); 3098 pmap->pm_stats.resident_count += NBPDR / 3099 PAGE_SIZE; 3100 pmap_pde_mappings++; 3101 } 3102 /* Else continue on if the PDE is already valid. */ 3103 addr += NBPDR; 3104 } 3105 PMAP_UNLOCK(pmap); 3106 } 3107} 3108 3109/* 3110 * Routine: pmap_change_wiring 3111 * Function: Change the wiring attribute for a map/virtual-address 3112 * pair. 3113 * In/out conditions: 3114 * The mapping must already exist in the pmap. 3115 */ 3116void 3117pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3118{ 3119 pt_entry_t *pte; 3120 3121 vm_page_lock_queues(); 3122 PMAP_LOCK(pmap); 3123 pte = pmap_pte(pmap, va); 3124 3125 if (wired && !pmap_pte_w(pte)) { 3126 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3127 pmap->pm_stats.wired_count++; 3128 } else if (!wired && pmap_pte_w(pte)) { 3129 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3130 pmap->pm_stats.wired_count--; 3131 } 3132 3133 /* 3134 * Wiring is not a hardware characteristic so there is no need to 3135 * invalidate TLB. 3136 */ 3137 pmap_pte_release(pte); 3138 PMAP_UNLOCK(pmap); 3139 vm_page_unlock_queues(); 3140} 3141 3142 3143 3144/* 3145 * Copy the range specified by src_addr/len 3146 * from the source map to the range dst_addr/len 3147 * in the destination map. 3148 * 3149 * This routine is only advisory and need not do anything. 3150 */ 3151 3152void 3153pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3154 vm_offset_t src_addr) 3155{ 3156 vm_page_t free; 3157 vm_offset_t addr; 3158 vm_offset_t end_addr = src_addr + len; 3159 vm_offset_t pdnxt; 3160 3161 if (dst_addr != src_addr) 3162 return; 3163 3164 if (!pmap_is_current(src_pmap)) { 3165 CTR2(KTR_PMAP, 3166 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3167 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3168 3169 return; 3170 } 3171 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3172 dst_pmap, src_pmap, dst_addr, len, src_addr); 3173 3174#ifdef HAMFISTED_LOCKING 3175 mtx_lock(&createdelete_lock); 3176#endif 3177 3178 vm_page_lock_queues(); 3179 if (dst_pmap < src_pmap) { 3180 PMAP_LOCK(dst_pmap); 3181 PMAP_LOCK(src_pmap); 3182 } else { 3183 PMAP_LOCK(src_pmap); 3184 PMAP_LOCK(dst_pmap); 3185 } 3186 sched_pin(); 3187 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3188 pt_entry_t *src_pte, *dst_pte; 3189 vm_page_t dstmpte, srcmpte; 3190 pd_entry_t srcptepaddr; 3191 unsigned ptepindex; 3192 3193 KASSERT(addr < UPT_MIN_ADDRESS, 3194 ("pmap_copy: invalid to pmap_copy page tables")); 3195 3196 pdnxt = (addr + NBPDR) & ~PDRMASK; 3197 ptepindex = addr >> PDRSHIFT; 3198 3199 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3200 if (srcptepaddr == 0) 3201 continue; 3202 3203 if (srcptepaddr & PG_PS) { 3204 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3205 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3206 dst_pmap->pm_stats.resident_count += 3207 NBPDR / PAGE_SIZE; 3208 } 3209 continue; 3210 } 3211 3212 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3213 KASSERT(srcmpte->wire_count > 0, 3214 ("pmap_copy: source page table page is unused")); 3215 3216 if (pdnxt > end_addr) 3217 pdnxt = end_addr; 3218 3219 src_pte = vtopte(addr); 3220 while (addr < pdnxt) { 3221 pt_entry_t ptetemp; 3222 ptetemp = *src_pte; 3223 /* 3224 * we only virtual copy managed pages 3225 */ 3226 if ((ptetemp & PG_MANAGED) != 0) { 3227 dstmpte = pmap_allocpte(dst_pmap, addr, 3228 M_NOWAIT); 3229 if (dstmpte == NULL) 3230 break; 3231 dst_pte = pmap_pte_quick(dst_pmap, addr); 3232 if (*dst_pte == 0 && 3233 pmap_try_insert_pv_entry(dst_pmap, addr, 3234 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3235 /* 3236 * Clear the wired, modified, and 3237 * accessed (referenced) bits 3238 * during the copy. 3239 */ 3240 KASSERT(ptetemp != 0, ("src_pte not set")); 3241 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3242 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3243 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3244 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3245 dst_pmap->pm_stats.resident_count++; 3246 } else { 3247 free = NULL; 3248 if (pmap_unwire_pte_hold(dst_pmap, 3249 dstmpte, &free)) { 3250 pmap_invalidate_page(dst_pmap, 3251 addr); 3252 pmap_free_zero_pages(free); 3253 } 3254 } 3255 if (dstmpte->wire_count >= srcmpte->wire_count) 3256 break; 3257 } 3258 addr += PAGE_SIZE; 3259 src_pte++; 3260 } 3261 } 3262 PT_UPDATES_FLUSH(); 3263 sched_unpin(); 3264 vm_page_unlock_queues(); 3265 PMAP_UNLOCK(src_pmap); 3266 PMAP_UNLOCK(dst_pmap); 3267 3268#ifdef HAMFISTED_LOCKING 3269 mtx_unlock(&createdelete_lock); 3270#endif 3271} 3272 3273static __inline void 3274pagezero(void *page) 3275{ 3276#if defined(I686_CPU) 3277 if (cpu_class == CPUCLASS_686) { 3278#if defined(CPU_ENABLE_SSE) 3279 if (cpu_feature & CPUID_SSE2) 3280 sse2_pagezero(page); 3281 else 3282#endif 3283 i686_pagezero(page); 3284 } else 3285#endif 3286 bzero(page, PAGE_SIZE); 3287} 3288 3289/* 3290 * pmap_zero_page zeros the specified hardware page by mapping 3291 * the page into KVM and using bzero to clear its contents. 3292 */ 3293void 3294pmap_zero_page(vm_page_t m) 3295{ 3296 struct sysmaps *sysmaps; 3297 3298 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3299 mtx_lock(&sysmaps->lock); 3300 if (*sysmaps->CMAP2) 3301 panic("pmap_zero_page: CMAP2 busy"); 3302 sched_pin(); 3303 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3304 pagezero(sysmaps->CADDR2); 3305 PT_SET_MA(sysmaps->CADDR2, 0); 3306 sched_unpin(); 3307 mtx_unlock(&sysmaps->lock); 3308} 3309 3310/* 3311 * pmap_zero_page_area zeros the specified hardware page by mapping 3312 * the page into KVM and using bzero to clear its contents. 3313 * 3314 * off and size may not cover an area beyond a single hardware page. 3315 */ 3316void 3317pmap_zero_page_area(vm_page_t m, int off, int size) 3318{ 3319 struct sysmaps *sysmaps; 3320 3321 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3322 mtx_lock(&sysmaps->lock); 3323 if (*sysmaps->CMAP2) 3324 panic("pmap_zero_page: CMAP2 busy"); 3325 sched_pin(); 3326 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3327 3328 if (off == 0 && size == PAGE_SIZE) 3329 pagezero(sysmaps->CADDR2); 3330 else 3331 bzero((char *)sysmaps->CADDR2 + off, size); 3332 PT_SET_MA(sysmaps->CADDR2, 0); 3333 sched_unpin(); 3334 mtx_unlock(&sysmaps->lock); 3335} 3336 3337/* 3338 * pmap_zero_page_idle zeros the specified hardware page by mapping 3339 * the page into KVM and using bzero to clear its contents. This 3340 * is intended to be called from the vm_pagezero process only and 3341 * outside of Giant. 3342 */ 3343void 3344pmap_zero_page_idle(vm_page_t m) 3345{ 3346 3347 if (*CMAP3) 3348 panic("pmap_zero_page: CMAP3 busy"); 3349 sched_pin(); 3350 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3351 pagezero(CADDR3); 3352 PT_SET_MA(CADDR3, 0); 3353 sched_unpin(); 3354} 3355 3356/* 3357 * pmap_copy_page copies the specified (machine independent) 3358 * page by mapping the page into virtual memory and using 3359 * bcopy to copy the page, one machine dependent page at a 3360 * time. 3361 */ 3362void 3363pmap_copy_page(vm_page_t src, vm_page_t dst) 3364{ 3365 struct sysmaps *sysmaps; 3366 3367 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3368 mtx_lock(&sysmaps->lock); 3369 if (*sysmaps->CMAP1) 3370 panic("pmap_copy_page: CMAP1 busy"); 3371 if (*sysmaps->CMAP2) 3372 panic("pmap_copy_page: CMAP2 busy"); 3373 sched_pin(); 3374 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3375 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3376 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3377 PT_SET_MA(sysmaps->CADDR1, 0); 3378 PT_SET_MA(sysmaps->CADDR2, 0); 3379 sched_unpin(); 3380 mtx_unlock(&sysmaps->lock); 3381} 3382 3383/* 3384 * Returns true if the pmap's pv is one of the first 3385 * 16 pvs linked to from this page. This count may 3386 * be changed upwards or downwards in the future; it 3387 * is only necessary that true be returned for a small 3388 * subset of pmaps for proper page aging. 3389 */ 3390boolean_t 3391pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3392{ 3393 pv_entry_t pv; 3394 int loops = 0; 3395 boolean_t rv; 3396 3397 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3398 ("pmap_page_exists_quick: page %p is not managed", m)); 3399 rv = FALSE; 3400 vm_page_lock_queues(); 3401 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3402 if (PV_PMAP(pv) == pmap) { 3403 rv = TRUE; 3404 break; 3405 } 3406 loops++; 3407 if (loops >= 16) 3408 break; 3409 } 3410 vm_page_unlock_queues(); 3411 return (rv); 3412} 3413 3414/* 3415 * pmap_page_wired_mappings: 3416 * 3417 * Return the number of managed mappings to the given physical page 3418 * that are wired. 3419 */ 3420int 3421pmap_page_wired_mappings(vm_page_t m) 3422{ 3423 pv_entry_t pv; 3424 pt_entry_t *pte; 3425 pmap_t pmap; 3426 int count; 3427 3428 count = 0; 3429 if ((m->flags & PG_FICTITIOUS) != 0) 3430 return (count); 3431 vm_page_lock_queues(); 3432 sched_pin(); 3433 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3434 pmap = PV_PMAP(pv); 3435 PMAP_LOCK(pmap); 3436 pte = pmap_pte_quick(pmap, pv->pv_va); 3437 if ((*pte & PG_W) != 0) 3438 count++; 3439 PMAP_UNLOCK(pmap); 3440 } 3441 sched_unpin(); 3442 vm_page_unlock_queues(); 3443 return (count); 3444} 3445 3446/* 3447 * Returns TRUE if the given page is mapped individually or as part of 3448 * a 4mpage. Otherwise, returns FALSE. 3449 */ 3450boolean_t 3451pmap_page_is_mapped(vm_page_t m) 3452{ 3453 boolean_t rv; 3454 3455 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 3456 return (FALSE); 3457 vm_page_lock_queues(); 3458 rv = !TAILQ_EMPTY(&m->md.pv_list) || 3459 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list); 3460 vm_page_unlock_queues(); 3461 return (rv); 3462} 3463 3464/* 3465 * Remove all pages from specified address space 3466 * this aids process exit speeds. Also, this code 3467 * is special cased for current process only, but 3468 * can have the more generic (and slightly slower) 3469 * mode enabled. This is much faster than pmap_remove 3470 * in the case of running down an entire address space. 3471 */ 3472void 3473pmap_remove_pages(pmap_t pmap) 3474{ 3475 pt_entry_t *pte, tpte; 3476 vm_page_t m, free = NULL; 3477 pv_entry_t pv; 3478 struct pv_chunk *pc, *npc; 3479 int field, idx; 3480 int32_t bit; 3481 uint32_t inuse, bitmask; 3482 int allfree; 3483 3484 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3485 3486 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3487 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3488 return; 3489 } 3490 vm_page_lock_queues(); 3491 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3492 PMAP_LOCK(pmap); 3493 sched_pin(); 3494 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3495 allfree = 1; 3496 for (field = 0; field < _NPCM; field++) { 3497 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 3498 while (inuse != 0) { 3499 bit = bsfl(inuse); 3500 bitmask = 1UL << bit; 3501 idx = field * 32 + bit; 3502 pv = &pc->pc_pventry[idx]; 3503 inuse &= ~bitmask; 3504 3505 pte = vtopte(pv->pv_va); 3506 tpte = *pte ? xpmap_mtop(*pte) : 0; 3507 3508 if (tpte == 0) { 3509 printf( 3510 "TPTE at %p IS ZERO @ VA %08x\n", 3511 pte, pv->pv_va); 3512 panic("bad pte"); 3513 } 3514 3515/* 3516 * We cannot remove wired pages from a process' mapping at this time 3517 */ 3518 if (tpte & PG_W) { 3519 allfree = 0; 3520 continue; 3521 } 3522 3523 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3524 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3525 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3526 m, (uintmax_t)m->phys_addr, 3527 (uintmax_t)tpte)); 3528 3529 KASSERT(m < &vm_page_array[vm_page_array_size], 3530 ("pmap_remove_pages: bad tpte %#jx", 3531 (uintmax_t)tpte)); 3532 3533 3534 PT_CLEAR_VA(pte, FALSE); 3535 3536 /* 3537 * Update the vm_page_t clean/reference bits. 3538 */ 3539 if (tpte & PG_M) 3540 vm_page_dirty(m); 3541 3542 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3543 if (TAILQ_EMPTY(&m->md.pv_list)) 3544 vm_page_flag_clear(m, PG_WRITEABLE); 3545 3546 pmap_unuse_pt(pmap, pv->pv_va, &free); 3547 3548 /* Mark free */ 3549 PV_STAT(pv_entry_frees++); 3550 PV_STAT(pv_entry_spare++); 3551 pv_entry_count--; 3552 pc->pc_map[field] |= bitmask; 3553 pmap->pm_stats.resident_count--; 3554 } 3555 } 3556 PT_UPDATES_FLUSH(); 3557 if (allfree) { 3558 PV_STAT(pv_entry_spare -= _NPCPV); 3559 PV_STAT(pc_chunk_count--); 3560 PV_STAT(pc_chunk_frees++); 3561 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3562 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 3563 pmap_qremove((vm_offset_t)pc, 1); 3564 vm_page_unwire(m, 0); 3565 vm_page_free(m); 3566 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 3567 } 3568 } 3569 PT_UPDATES_FLUSH(); 3570 if (*PMAP1) 3571 PT_SET_MA(PADDR1, 0); 3572 3573 sched_unpin(); 3574 pmap_invalidate_all(pmap); 3575 vm_page_unlock_queues(); 3576 PMAP_UNLOCK(pmap); 3577 pmap_free_zero_pages(free); 3578} 3579 3580/* 3581 * pmap_is_modified: 3582 * 3583 * Return whether or not the specified physical page was modified 3584 * in any physical maps. 3585 */ 3586boolean_t 3587pmap_is_modified(vm_page_t m) 3588{ 3589 pv_entry_t pv; 3590 pt_entry_t *pte; 3591 pmap_t pmap; 3592 boolean_t rv; 3593 3594 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3595 ("pmap_is_modified: page %p is not managed", m)); 3596 rv = FALSE; 3597 3598 /* 3599 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 3600 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 3601 * is clear, no PTEs can have PG_M set. 3602 */ 3603 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3604 if ((m->oflags & VPO_BUSY) == 0 && 3605 (m->flags & PG_WRITEABLE) == 0) 3606 return (rv); 3607 vm_page_lock_queues(); 3608 sched_pin(); 3609 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3610 pmap = PV_PMAP(pv); 3611 PMAP_LOCK(pmap); 3612 pte = pmap_pte_quick(pmap, pv->pv_va); 3613 rv = (*pte & PG_M) != 0; 3614 PMAP_UNLOCK(pmap); 3615 if (rv) 3616 break; 3617 } 3618 if (*PMAP1) 3619 PT_SET_MA(PADDR1, 0); 3620 sched_unpin(); 3621 vm_page_unlock_queues(); 3622 return (rv); 3623} 3624 3625/* 3626 * pmap_is_prefaultable: 3627 * 3628 * Return whether or not the specified virtual address is elgible 3629 * for prefault. 3630 */ 3631static boolean_t 3632pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3633{ 3634 pt_entry_t *pte; 3635 boolean_t rv = FALSE; 3636 3637 return (rv); 3638 3639 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3640 pte = vtopte(addr); 3641 rv = (*pte == 0); 3642 } 3643 return (rv); 3644} 3645 3646boolean_t 3647pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3648{ 3649 boolean_t rv; 3650 3651 PMAP_LOCK(pmap); 3652 rv = pmap_is_prefaultable_locked(pmap, addr); 3653 PMAP_UNLOCK(pmap); 3654 return (rv); 3655} 3656 3657boolean_t 3658pmap_is_referenced(vm_page_t m) 3659{ 3660 pv_entry_t pv; 3661 pt_entry_t *pte; 3662 pmap_t pmap; 3663 boolean_t rv; 3664 3665 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3666 ("pmap_is_referenced: page %p is not managed", m)); 3667 rv = FALSE; 3668 vm_page_lock_queues(); 3669 sched_pin(); 3670 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3671 pmap = PV_PMAP(pv); 3672 PMAP_LOCK(pmap); 3673 pte = pmap_pte_quick(pmap, pv->pv_va); 3674 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3675 PMAP_UNLOCK(pmap); 3676 if (rv) 3677 break; 3678 } 3679 if (*PMAP1) 3680 PT_SET_MA(PADDR1, 0); 3681 sched_unpin(); 3682 vm_page_unlock_queues(); 3683 return (rv); 3684} 3685 3686void 3687pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3688{ 3689 int i, npages = round_page(len) >> PAGE_SHIFT; 3690 for (i = 0; i < npages; i++) { 3691 pt_entry_t *pte; 3692 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3693 vm_page_lock_queues(); 3694 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3695 vm_page_unlock_queues(); 3696 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3697 pmap_pte_release(pte); 3698 } 3699} 3700 3701void 3702pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3703{ 3704 int i, npages = round_page(len) >> PAGE_SHIFT; 3705 for (i = 0; i < npages; i++) { 3706 pt_entry_t *pte; 3707 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3708 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3709 vm_page_lock_queues(); 3710 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3711 vm_page_unlock_queues(); 3712 pmap_pte_release(pte); 3713 } 3714} 3715 3716/* 3717 * Clear the write and modified bits in each of the given page's mappings. 3718 */ 3719void 3720pmap_remove_write(vm_page_t m) 3721{ 3722 pv_entry_t pv; 3723 pmap_t pmap; 3724 pt_entry_t oldpte, *pte; 3725 3726 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3727 ("pmap_remove_write: page %p is not managed", m)); 3728 3729 /* 3730 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 3731 * another thread while the object is locked. Thus, if PG_WRITEABLE 3732 * is clear, no page table entries need updating. 3733 */ 3734 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3735 if ((m->oflags & VPO_BUSY) == 0 && 3736 (m->flags & PG_WRITEABLE) == 0) 3737 return; 3738 vm_page_lock_queues(); 3739 sched_pin(); 3740 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3741 pmap = PV_PMAP(pv); 3742 PMAP_LOCK(pmap); 3743 pte = pmap_pte_quick(pmap, pv->pv_va); 3744retry: 3745 oldpte = *pte; 3746 if ((oldpte & PG_RW) != 0) { 3747 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3748 3749 /* 3750 * Regardless of whether a pte is 32 or 64 bits 3751 * in size, PG_RW and PG_M are among the least 3752 * significant 32 bits. 3753 */ 3754 PT_SET_VA_MA(pte, newpte, TRUE); 3755 if (*pte != newpte) 3756 goto retry; 3757 3758 if ((oldpte & PG_M) != 0) 3759 vm_page_dirty(m); 3760 pmap_invalidate_page(pmap, pv->pv_va); 3761 } 3762 PMAP_UNLOCK(pmap); 3763 } 3764 vm_page_flag_clear(m, PG_WRITEABLE); 3765 PT_UPDATES_FLUSH(); 3766 if (*PMAP1) 3767 PT_SET_MA(PADDR1, 0); 3768 sched_unpin(); 3769 vm_page_unlock_queues(); 3770} 3771 3772/* 3773 * pmap_ts_referenced: 3774 * 3775 * Return a count of reference bits for a page, clearing those bits. 3776 * It is not necessary for every reference bit to be cleared, but it 3777 * is necessary that 0 only be returned when there are truly no 3778 * reference bits set. 3779 * 3780 * XXX: The exact number of bits to check and clear is a matter that 3781 * should be tested and standardized at some point in the future for 3782 * optimal aging of shared pages. 3783 */ 3784int 3785pmap_ts_referenced(vm_page_t m) 3786{ 3787 pv_entry_t pv, pvf, pvn; 3788 pmap_t pmap; 3789 pt_entry_t *pte; 3790 int rtval = 0; 3791 3792 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3793 ("pmap_ts_referenced: page %p is not managed", m)); 3794 vm_page_lock_queues(); 3795 sched_pin(); 3796 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3797 pvf = pv; 3798 do { 3799 pvn = TAILQ_NEXT(pv, pv_list); 3800 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3801 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3802 pmap = PV_PMAP(pv); 3803 PMAP_LOCK(pmap); 3804 pte = pmap_pte_quick(pmap, pv->pv_va); 3805 if ((*pte & PG_A) != 0) { 3806 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3807 pmap_invalidate_page(pmap, pv->pv_va); 3808 rtval++; 3809 if (rtval > 4) 3810 pvn = NULL; 3811 } 3812 PMAP_UNLOCK(pmap); 3813 } while ((pv = pvn) != NULL && pv != pvf); 3814 } 3815 PT_UPDATES_FLUSH(); 3816 if (*PMAP1) 3817 PT_SET_MA(PADDR1, 0); 3818 3819 sched_unpin(); 3820 vm_page_unlock_queues(); 3821 return (rtval); 3822} 3823 3824/* 3825 * Clear the modify bits on the specified physical page. 3826 */ 3827void 3828pmap_clear_modify(vm_page_t m) 3829{ 3830 pv_entry_t pv; 3831 pmap_t pmap; 3832 pt_entry_t *pte; 3833 3834 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3835 ("pmap_clear_modify: page %p is not managed", m)); 3836 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3837 KASSERT((m->oflags & VPO_BUSY) == 0, 3838 ("pmap_clear_modify: page %p is busy", m)); 3839 3840 /* 3841 * If the page is not PG_WRITEABLE, then no PTEs can have PG_M set. 3842 * If the object containing the page is locked and the page is not 3843 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 3844 */ 3845 if ((m->flags & PG_WRITEABLE) == 0) 3846 return; 3847 vm_page_lock_queues(); 3848 sched_pin(); 3849 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3850 pmap = PV_PMAP(pv); 3851 PMAP_LOCK(pmap); 3852 pte = pmap_pte_quick(pmap, pv->pv_va); 3853 if ((*pte & PG_M) != 0) { 3854 /* 3855 * Regardless of whether a pte is 32 or 64 bits 3856 * in size, PG_M is among the least significant 3857 * 32 bits. 3858 */ 3859 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3860 pmap_invalidate_page(pmap, pv->pv_va); 3861 } 3862 PMAP_UNLOCK(pmap); 3863 } 3864 sched_unpin(); 3865 vm_page_unlock_queues(); 3866} 3867 3868/* 3869 * pmap_clear_reference: 3870 * 3871 * Clear the reference bit on the specified physical page. 3872 */ 3873void 3874pmap_clear_reference(vm_page_t m) 3875{ 3876 pv_entry_t pv; 3877 pmap_t pmap; 3878 pt_entry_t *pte; 3879 3880 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3881 ("pmap_clear_reference: page %p is not managed", m)); 3882 vm_page_lock_queues(); 3883 sched_pin(); 3884 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3885 pmap = PV_PMAP(pv); 3886 PMAP_LOCK(pmap); 3887 pte = pmap_pte_quick(pmap, pv->pv_va); 3888 if ((*pte & PG_A) != 0) { 3889 /* 3890 * Regardless of whether a pte is 32 or 64 bits 3891 * in size, PG_A is among the least significant 3892 * 32 bits. 3893 */ 3894 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3895 pmap_invalidate_page(pmap, pv->pv_va); 3896 } 3897 PMAP_UNLOCK(pmap); 3898 } 3899 sched_unpin(); 3900 vm_page_unlock_queues(); 3901} 3902 3903/* 3904 * Miscellaneous support routines follow 3905 */ 3906 3907/* 3908 * Map a set of physical memory pages into the kernel virtual 3909 * address space. Return a pointer to where it is mapped. This 3910 * routine is intended to be used for mapping device memory, 3911 * NOT real memory. 3912 */ 3913void * 3914pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 3915{ 3916 vm_offset_t va, offset; 3917 vm_size_t tmpsize; 3918 3919 offset = pa & PAGE_MASK; 3920 size = roundup(offset + size, PAGE_SIZE); 3921 pa = pa & PG_FRAME; 3922 3923 if (pa < KERNLOAD && pa + size <= KERNLOAD) 3924 va = KERNBASE + pa; 3925 else 3926 va = kmem_alloc_nofault(kernel_map, size); 3927 if (!va) 3928 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3929 3930 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 3931 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 3932 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 3933 pmap_invalidate_cache_range(va, va + size); 3934 return ((void *)(va + offset)); 3935} 3936 3937void * 3938pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3939{ 3940 3941 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 3942} 3943 3944void * 3945pmap_mapbios(vm_paddr_t pa, vm_size_t size) 3946{ 3947 3948 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 3949} 3950 3951void 3952pmap_unmapdev(vm_offset_t va, vm_size_t size) 3953{ 3954 vm_offset_t base, offset, tmpva; 3955 3956 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 3957 return; 3958 base = trunc_page(va); 3959 offset = va & PAGE_MASK; 3960 size = roundup(offset + size, PAGE_SIZE); 3961 critical_enter(); 3962 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 3963 pmap_kremove(tmpva); 3964 pmap_invalidate_range(kernel_pmap, va, tmpva); 3965 critical_exit(); 3966 kmem_free(kernel_map, base, size); 3967} 3968 3969/* 3970 * Sets the memory attribute for the specified page. 3971 */ 3972void 3973pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 3974{ 3975 struct sysmaps *sysmaps; 3976 vm_offset_t sva, eva; 3977 3978 m->md.pat_mode = ma; 3979 if ((m->flags & PG_FICTITIOUS) != 0) 3980 return; 3981 3982 /* 3983 * If "m" is a normal page, flush it from the cache. 3984 * See pmap_invalidate_cache_range(). 3985 * 3986 * First, try to find an existing mapping of the page by sf 3987 * buffer. sf_buf_invalidate_cache() modifies mapping and 3988 * flushes the cache. 3989 */ 3990 if (sf_buf_invalidate_cache(m)) 3991 return; 3992 3993 /* 3994 * If page is not mapped by sf buffer, but CPU does not 3995 * support self snoop, map the page transient and do 3996 * invalidation. In the worst case, whole cache is flushed by 3997 * pmap_invalidate_cache_range(). 3998 */ 3999 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 4000 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4001 mtx_lock(&sysmaps->lock); 4002 if (*sysmaps->CMAP2) 4003 panic("pmap_page_set_memattr: CMAP2 busy"); 4004 sched_pin(); 4005 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 4006 VM_PAGE_TO_MACH(m) | PG_A | PG_M | 4007 pmap_cache_bits(m->md.pat_mode, 0)); 4008 invlcaddr(sysmaps->CADDR2); 4009 sva = (vm_offset_t)sysmaps->CADDR2; 4010 eva = sva + PAGE_SIZE; 4011 } else 4012 sva = eva = 0; /* gcc */ 4013 pmap_invalidate_cache_range(sva, eva); 4014 if (sva != 0) { 4015 PT_SET_MA(sysmaps->CADDR2, 0); 4016 sched_unpin(); 4017 mtx_unlock(&sysmaps->lock); 4018 } 4019} 4020 4021int 4022pmap_change_attr(va, size, mode) 4023 vm_offset_t va; 4024 vm_size_t size; 4025 int mode; 4026{ 4027 vm_offset_t base, offset, tmpva; 4028 pt_entry_t *pte; 4029 u_int opte, npte; 4030 pd_entry_t *pde; 4031 boolean_t changed; 4032 4033 base = trunc_page(va); 4034 offset = va & PAGE_MASK; 4035 size = roundup(offset + size, PAGE_SIZE); 4036 4037 /* Only supported on kernel virtual addresses. */ 4038 if (base <= VM_MAXUSER_ADDRESS) 4039 return (EINVAL); 4040 4041 /* 4MB pages and pages that aren't mapped aren't supported. */ 4042 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4043 pde = pmap_pde(kernel_pmap, tmpva); 4044 if (*pde & PG_PS) 4045 return (EINVAL); 4046 if ((*pde & PG_V) == 0) 4047 return (EINVAL); 4048 pte = vtopte(va); 4049 if ((*pte & PG_V) == 0) 4050 return (EINVAL); 4051 } 4052 4053 changed = FALSE; 4054 4055 /* 4056 * Ok, all the pages exist and are 4k, so run through them updating 4057 * their cache mode. 4058 */ 4059 for (tmpva = base; size > 0; ) { 4060 pte = vtopte(tmpva); 4061 4062 /* 4063 * The cache mode bits are all in the low 32-bits of the 4064 * PTE, so we can just spin on updating the low 32-bits. 4065 */ 4066 do { 4067 opte = *(u_int *)pte; 4068 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4069 npte |= pmap_cache_bits(mode, 0); 4070 PT_SET_VA_MA(pte, npte, TRUE); 4071 } while (npte != opte && (*pte != npte)); 4072 if (npte != opte) 4073 changed = TRUE; 4074 tmpva += PAGE_SIZE; 4075 size -= PAGE_SIZE; 4076 } 4077 4078 /* 4079 * Flush CPU caches to make sure any data isn't cached that shouldn't 4080 * be, etc. 4081 */ 4082 if (changed) { 4083 pmap_invalidate_range(kernel_pmap, base, tmpva); 4084 pmap_invalidate_cache_range(base, tmpva); 4085 } 4086 return (0); 4087} 4088 4089/* 4090 * perform the pmap work for mincore 4091 */ 4092int 4093pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4094{ 4095 pt_entry_t *ptep, pte; 4096 vm_paddr_t pa; 4097 int val; 4098 4099 PMAP_LOCK(pmap); 4100retry: 4101 ptep = pmap_pte(pmap, addr); 4102 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4103 pmap_pte_release(ptep); 4104 val = 0; 4105 if ((pte & PG_V) != 0) { 4106 val |= MINCORE_INCORE; 4107 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4108 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4109 if ((pte & PG_A) != 0) 4110 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4111 } 4112 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4113 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4114 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4115 pa = pte & PG_FRAME; 4116 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4117 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4118 goto retry; 4119 } else 4120 PA_UNLOCK_COND(*locked_pa); 4121 PMAP_UNLOCK(pmap); 4122 return (val); 4123} 4124 4125void 4126pmap_activate(struct thread *td) 4127{ 4128 pmap_t pmap, oldpmap; 4129 u_int32_t cr3; 4130 4131 critical_enter(); 4132 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4133 oldpmap = PCPU_GET(curpmap); 4134#if defined(SMP) 4135 CPU_NAND_ATOMIC(&oldpmap->pm_active, PCPU_PTR(cpumask)); 4136 CPU_OR_ATOMIC(&pmap->pm_active, PCPU_PTR(cpumask)); 4137#else 4138 CPU_NAND(&oldpmap->pm_active, PCPU_PTR(cpumask)); 4139 CPU_OR(&pmap->pm_active, PCPU_PTR(cpumask)); 4140#endif 4141#ifdef PAE 4142 cr3 = vtophys(pmap->pm_pdpt); 4143#else 4144 cr3 = vtophys(pmap->pm_pdir); 4145#endif 4146 /* 4147 * pmap_activate is for the current thread on the current cpu 4148 */ 4149 td->td_pcb->pcb_cr3 = cr3; 4150 PT_UPDATES_FLUSH(); 4151 load_cr3(cr3); 4152 PCPU_SET(curpmap, pmap); 4153 critical_exit(); 4154} 4155 4156void 4157pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4158{ 4159} 4160 4161/* 4162 * Increase the starting virtual address of the given mapping if a 4163 * different alignment might result in more superpage mappings. 4164 */ 4165void 4166pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4167 vm_offset_t *addr, vm_size_t size) 4168{ 4169 vm_offset_t superpage_offset; 4170 4171 if (size < NBPDR) 4172 return; 4173 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4174 offset += ptoa(object->pg_color); 4175 superpage_offset = offset & PDRMASK; 4176 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4177 (*addr & PDRMASK) == superpage_offset) 4178 return; 4179 if ((*addr & PDRMASK) < superpage_offset) 4180 *addr = (*addr & ~PDRMASK) + superpage_offset; 4181 else 4182 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4183} 4184 4185void 4186pmap_suspend() 4187{ 4188 pmap_t pmap; 4189 int i, pdir, offset; 4190 vm_paddr_t pdirma; 4191 mmu_update_t mu[4]; 4192 4193 /* 4194 * We need to remove the recursive mapping structure from all 4195 * our pmaps so that Xen doesn't get confused when it restores 4196 * the page tables. The recursive map lives at page directory 4197 * index PTDPTDI. We assume that the suspend code has stopped 4198 * the other vcpus (if any). 4199 */ 4200 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4201 for (i = 0; i < 4; i++) { 4202 /* 4203 * Figure out which page directory (L2) page 4204 * contains this bit of the recursive map and 4205 * the offset within that page of the map 4206 * entry 4207 */ 4208 pdir = (PTDPTDI + i) / NPDEPG; 4209 offset = (PTDPTDI + i) % NPDEPG; 4210 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4211 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4212 mu[i].val = 0; 4213 } 4214 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4215 } 4216} 4217 4218void 4219pmap_resume() 4220{ 4221 pmap_t pmap; 4222 int i, pdir, offset; 4223 vm_paddr_t pdirma; 4224 mmu_update_t mu[4]; 4225 4226 /* 4227 * Restore the recursive map that we removed on suspend. 4228 */ 4229 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4230 for (i = 0; i < 4; i++) { 4231 /* 4232 * Figure out which page directory (L2) page 4233 * contains this bit of the recursive map and 4234 * the offset within that page of the map 4235 * entry 4236 */ 4237 pdir = (PTDPTDI + i) / NPDEPG; 4238 offset = (PTDPTDI + i) % NPDEPG; 4239 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4240 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4241 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4242 } 4243 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4244 } 4245} 4246 4247#if defined(PMAP_DEBUG) 4248pmap_pid_dump(int pid) 4249{ 4250 pmap_t pmap; 4251 struct proc *p; 4252 int npte = 0; 4253 int index; 4254 4255 sx_slock(&allproc_lock); 4256 FOREACH_PROC_IN_SYSTEM(p) { 4257 if (p->p_pid != pid) 4258 continue; 4259 4260 if (p->p_vmspace) { 4261 int i,j; 4262 index = 0; 4263 pmap = vmspace_pmap(p->p_vmspace); 4264 for (i = 0; i < NPDEPTD; i++) { 4265 pd_entry_t *pde; 4266 pt_entry_t *pte; 4267 vm_offset_t base = i << PDRSHIFT; 4268 4269 pde = &pmap->pm_pdir[i]; 4270 if (pde && pmap_pde_v(pde)) { 4271 for (j = 0; j < NPTEPG; j++) { 4272 vm_offset_t va = base + (j << PAGE_SHIFT); 4273 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4274 if (index) { 4275 index = 0; 4276 printf("\n"); 4277 } 4278 sx_sunlock(&allproc_lock); 4279 return npte; 4280 } 4281 pte = pmap_pte(pmap, va); 4282 if (pte && pmap_pte_v(pte)) { 4283 pt_entry_t pa; 4284 vm_page_t m; 4285 pa = PT_GET(pte); 4286 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4287 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4288 va, pa, m->hold_count, m->wire_count, m->flags); 4289 npte++; 4290 index++; 4291 if (index >= 2) { 4292 index = 0; 4293 printf("\n"); 4294 } else { 4295 printf(" "); 4296 } 4297 } 4298 } 4299 } 4300 } 4301 } 4302 } 4303 sx_sunlock(&allproc_lock); 4304 return npte; 4305} 4306#endif 4307 4308#if defined(DEBUG) 4309 4310static void pads(pmap_t pm); 4311void pmap_pvdump(vm_paddr_t pa); 4312 4313/* print address space of pmap*/ 4314static void 4315pads(pmap_t pm) 4316{ 4317 int i, j; 4318 vm_paddr_t va; 4319 pt_entry_t *ptep; 4320 4321 if (pm == kernel_pmap) 4322 return; 4323 for (i = 0; i < NPDEPTD; i++) 4324 if (pm->pm_pdir[i]) 4325 for (j = 0; j < NPTEPG; j++) { 4326 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4327 if (pm == kernel_pmap && va < KERNBASE) 4328 continue; 4329 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4330 continue; 4331 ptep = pmap_pte(pm, va); 4332 if (pmap_pte_v(ptep)) 4333 printf("%x:%x ", va, *ptep); 4334 }; 4335 4336} 4337 4338void 4339pmap_pvdump(vm_paddr_t pa) 4340{ 4341 pv_entry_t pv; 4342 pmap_t pmap; 4343 vm_page_t m; 4344 4345 printf("pa %x", pa); 4346 m = PHYS_TO_VM_PAGE(pa); 4347 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4348 pmap = PV_PMAP(pv); 4349 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4350 pads(pmap); 4351 } 4352 printf(" "); 4353} 4354#endif 4355