pmap.c revision 217688
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 217688 2011-01-21 10:26:26Z pluknet $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_smp.h" 109#include "opt_xbox.h" 110 111#include <sys/param.h> 112#include <sys/systm.h> 113#include <sys/kernel.h> 114#include <sys/ktr.h> 115#include <sys/lock.h> 116#include <sys/malloc.h> 117#include <sys/mman.h> 118#include <sys/msgbuf.h> 119#include <sys/mutex.h> 120#include <sys/proc.h> 121#include <sys/sf_buf.h> 122#include <sys/sx.h> 123#include <sys/vmmeter.h> 124#include <sys/sched.h> 125#include <sys/sysctl.h> 126#ifdef SMP 127#include <sys/smp.h> 128#endif 129 130#include <vm/vm.h> 131#include <vm/vm_param.h> 132#include <vm/vm_kern.h> 133#include <vm/vm_page.h> 134#include <vm/vm_map.h> 135#include <vm/vm_object.h> 136#include <vm/vm_extern.h> 137#include <vm/vm_pageout.h> 138#include <vm/vm_pager.h> 139#include <vm/uma.h> 140 141#include <machine/cpu.h> 142#include <machine/cputypes.h> 143#include <machine/md_var.h> 144#include <machine/pcb.h> 145#include <machine/specialreg.h> 146#ifdef SMP 147#include <machine/smp.h> 148#endif 149 150#ifdef XBOX 151#include <machine/xbox.h> 152#endif 153 154#include <xen/interface/xen.h> 155#include <xen/hypervisor.h> 156#include <machine/xen/hypercall.h> 157#include <machine/xen/xenvar.h> 158#include <machine/xen/xenfunc.h> 159 160#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 161#define CPU_ENABLE_SSE 162#endif 163 164#ifndef PMAP_SHPGPERPROC 165#define PMAP_SHPGPERPROC 200 166#endif 167 168#define DIAGNOSTIC 169 170#if !defined(DIAGNOSTIC) 171#ifdef __GNUC_GNU_INLINE__ 172#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 173#else 174#define PMAP_INLINE extern inline 175#endif 176#else 177#define PMAP_INLINE 178#endif 179 180#define PV_STATS 181#ifdef PV_STATS 182#define PV_STAT(x) do { x ; } while (0) 183#else 184#define PV_STAT(x) do { } while (0) 185#endif 186 187#define pa_index(pa) ((pa) >> PDRSHIFT) 188#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 189 190/* 191 * Get PDEs and PTEs for user/kernel address space 192 */ 193#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 194#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 195 196#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 197#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 198#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 199#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 200#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 201 202#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 203 204#define HAMFISTED_LOCKING 205#ifdef HAMFISTED_LOCKING 206static struct mtx createdelete_lock; 207#endif 208 209struct pmap kernel_pmap_store; 210LIST_HEAD(pmaplist, pmap); 211static struct pmaplist allpmaps; 212static struct mtx allpmaps_lock; 213 214vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 215vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 216int pgeflag = 0; /* PG_G or-in */ 217int pseflag = 0; /* PG_PS or-in */ 218 219int nkpt; 220vm_offset_t kernel_vm_end; 221extern u_int32_t KERNend; 222 223#ifdef PAE 224pt_entry_t pg_nx; 225#endif 226 227static int pat_works; /* Is page attribute table sane? */ 228 229/* 230 * Data for the pv entry allocation mechanism 231 */ 232static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 233static struct md_page *pv_table; 234static int shpgperproc = PMAP_SHPGPERPROC; 235 236struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 237int pv_maxchunks; /* How many chunks we have KVA for */ 238vm_offset_t pv_vafree; /* freelist stored in the PTE */ 239 240/* 241 * All those kernel PT submaps that BSD is so fond of 242 */ 243struct sysmaps { 244 struct mtx lock; 245 pt_entry_t *CMAP1; 246 pt_entry_t *CMAP2; 247 caddr_t CADDR1; 248 caddr_t CADDR2; 249}; 250static struct sysmaps sysmaps_pcpu[MAXCPU]; 251static pt_entry_t *CMAP3; 252caddr_t ptvmmap = 0; 253static caddr_t CADDR3; 254struct msgbuf *msgbufp = 0; 255 256/* 257 * Crashdump maps. 258 */ 259static caddr_t crashdumpmap; 260 261static pt_entry_t *PMAP1 = 0, *PMAP2; 262static pt_entry_t *PADDR1 = 0, *PADDR2; 263#ifdef SMP 264static int PMAP1cpu; 265static int PMAP1changedcpu; 266SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 267 &PMAP1changedcpu, 0, 268 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 269#endif 270static int PMAP1changed; 271SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 272 &PMAP1changed, 0, 273 "Number of times pmap_pte_quick changed PMAP1"); 274static int PMAP1unchanged; 275SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 276 &PMAP1unchanged, 0, 277 "Number of times pmap_pte_quick didn't change PMAP1"); 278static struct mtx PMAP2mutex; 279 280SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 281static int pg_ps_enabled; 282SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 283 "Are large page mappings enabled?"); 284 285SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 286 "Max number of PV entries"); 287SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 288 "Page share factor per proc"); 289SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 290 "2/4MB page mapping counters"); 291 292static u_long pmap_pde_mappings; 293SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 294 &pmap_pde_mappings, 0, "2/4MB page mappings"); 295 296static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 297static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 298static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 299static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 300 vm_offset_t va); 301 302static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 303 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 304static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 305 vm_page_t *free); 306static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 307 vm_page_t *free); 308static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 309 vm_offset_t va); 310static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 311 vm_page_t m); 312 313static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 314 315static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 316static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 317static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 318static void pmap_pte_release(pt_entry_t *pte); 319static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 320static vm_offset_t pmap_kmem_choose(vm_offset_t addr); 321static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 322static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 323 324static __inline void pagezero(void *page); 325 326CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 327CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 328 329/* 330 * If you get an error here, then you set KVA_PAGES wrong! See the 331 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 332 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 333 */ 334CTASSERT(KERNBASE % (1 << 24) == 0); 335 336 337 338void 339pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 340{ 341 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 342 343 switch (type) { 344 case SH_PD_SET_VA: 345#if 0 346 xen_queue_pt_update(shadow_pdir_ma, 347 xpmap_ptom(val & ~(PG_RW))); 348#endif 349 xen_queue_pt_update(pdir_ma, 350 xpmap_ptom(val)); 351 break; 352 case SH_PD_SET_VA_MA: 353#if 0 354 xen_queue_pt_update(shadow_pdir_ma, 355 val & ~(PG_RW)); 356#endif 357 xen_queue_pt_update(pdir_ma, val); 358 break; 359 case SH_PD_SET_VA_CLEAR: 360#if 0 361 xen_queue_pt_update(shadow_pdir_ma, 0); 362#endif 363 xen_queue_pt_update(pdir_ma, 0); 364 break; 365 } 366} 367 368/* 369 * Move the kernel virtual free pointer to the next 370 * 4MB. This is used to help improve performance 371 * by using a large (4MB) page for much of the kernel 372 * (.text, .data, .bss) 373 */ 374static vm_offset_t 375pmap_kmem_choose(vm_offset_t addr) 376{ 377 vm_offset_t newaddr = addr; 378 379#ifndef DISABLE_PSE 380 if (cpu_feature & CPUID_PSE) 381 newaddr = (addr + PDRMASK) & ~PDRMASK; 382#endif 383 return newaddr; 384} 385 386/* 387 * Bootstrap the system enough to run with virtual memory. 388 * 389 * On the i386 this is called after mapping has already been enabled 390 * and just syncs the pmap module with what has already been done. 391 * [We can't call it easily with mapping off since the kernel is not 392 * mapped with PA == VA, hence we would have to relocate every address 393 * from the linked base (virtual) address "KERNBASE" to the actual 394 * (physical) address starting relative to 0] 395 */ 396void 397pmap_bootstrap(vm_paddr_t firstaddr) 398{ 399 vm_offset_t va; 400 pt_entry_t *pte, *unused; 401 struct sysmaps *sysmaps; 402 int i; 403 404 /* 405 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 406 * large. It should instead be correctly calculated in locore.s and 407 * not based on 'first' (which is a physical address, not a virtual 408 * address, for the start of unused physical memory). The kernel 409 * page tables are NOT double mapped and thus should not be included 410 * in this calculation. 411 */ 412 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 413 virtual_avail = pmap_kmem_choose(virtual_avail); 414 415 virtual_end = VM_MAX_KERNEL_ADDRESS; 416 417 /* 418 * Initialize the kernel pmap (which is statically allocated). 419 */ 420 PMAP_LOCK_INIT(kernel_pmap); 421 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 422#ifdef PAE 423 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 424#endif 425 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 426 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 427 LIST_INIT(&allpmaps); 428 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 429 mtx_lock_spin(&allpmaps_lock); 430 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 431 mtx_unlock_spin(&allpmaps_lock); 432 if (nkpt == 0) 433 nkpt = NKPT; 434 435 /* 436 * Reserve some special page table entries/VA space for temporary 437 * mapping of pages. 438 */ 439#define SYSMAP(c, p, v, n) \ 440 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 441 442 va = virtual_avail; 443 pte = vtopte(va); 444 445 /* 446 * CMAP1/CMAP2 are used for zeroing and copying pages. 447 * CMAP3 is used for the idle process page zeroing. 448 */ 449 for (i = 0; i < MAXCPU; i++) { 450 sysmaps = &sysmaps_pcpu[i]; 451 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 452 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 453 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 454 PT_SET_MA(sysmaps->CADDR1, 0); 455 PT_SET_MA(sysmaps->CADDR2, 0); 456 } 457 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 458 PT_SET_MA(CADDR3, 0); 459 460 /* 461 * Crashdump maps. 462 */ 463 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 464 465 /* 466 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 467 */ 468 SYSMAP(caddr_t, unused, ptvmmap, 1) 469 470 /* 471 * msgbufp is used to map the system message buffer. 472 */ 473 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 474 475 /* 476 * ptemap is used for pmap_pte_quick 477 */ 478 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1); 479 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1); 480 481 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 482 483 virtual_avail = va; 484 485 /* 486 * Leave in place an identity mapping (virt == phys) for the low 1 MB 487 * physical memory region that is used by the ACPI wakeup code. This 488 * mapping must not have PG_G set. 489 */ 490#ifndef XEN 491 /* 492 * leave here deliberately to show that this is not supported 493 */ 494#ifdef XBOX 495 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 496 * an early stadium, we cannot yet neatly map video memory ... :-( 497 * Better fixes are very welcome! */ 498 if (!arch_i386_is_xbox) 499#endif 500 for (i = 1; i < NKPT; i++) 501 PTD[i] = 0; 502 503 /* Initialize the PAT MSR if present. */ 504 pmap_init_pat(); 505 506 /* Turn on PG_G on kernel page(s) */ 507 pmap_set_pg(); 508#endif 509 510#ifdef HAMFISTED_LOCKING 511 mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF); 512#endif 513} 514 515/* 516 * Setup the PAT MSR. 517 */ 518void 519pmap_init_pat(void) 520{ 521 uint64_t pat_msr; 522 523 /* Bail if this CPU doesn't implement PAT. */ 524 if (!(cpu_feature & CPUID_PAT)) 525 return; 526 527 if (cpu_vendor_id != CPU_VENDOR_INTEL || 528 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 529 /* 530 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 531 * Program 4 and 5 as WP and WC. 532 * Leave 6 and 7 as UC and UC-. 533 */ 534 pat_msr = rdmsr(MSR_PAT); 535 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 536 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 537 PAT_VALUE(5, PAT_WRITE_COMBINING); 538 pat_works = 1; 539 } else { 540 /* 541 * Due to some Intel errata, we can only safely use the lower 4 542 * PAT entries. Thus, just replace PAT Index 2 with WC instead 543 * of UC-. 544 * 545 * Intel Pentium III Processor Specification Update 546 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 547 * or Mode C Paging) 548 * 549 * Intel Pentium IV Processor Specification Update 550 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 551 */ 552 pat_msr = rdmsr(MSR_PAT); 553 pat_msr &= ~PAT_MASK(2); 554 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 555 pat_works = 0; 556 } 557 wrmsr(MSR_PAT, pat_msr); 558} 559 560/* 561 * Initialize a vm_page's machine-dependent fields. 562 */ 563void 564pmap_page_init(vm_page_t m) 565{ 566 567 TAILQ_INIT(&m->md.pv_list); 568 m->md.pat_mode = PAT_WRITE_BACK; 569} 570 571/* 572 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 573 * Requirements: 574 * - Must deal with pages in order to ensure that none of the PG_* bits 575 * are ever set, PG_V in particular. 576 * - Assumes we can write to ptes without pte_store() atomic ops, even 577 * on PAE systems. This should be ok. 578 * - Assumes nothing will ever test these addresses for 0 to indicate 579 * no mapping instead of correctly checking PG_V. 580 * - Assumes a vm_offset_t will fit in a pte (true for i386). 581 * Because PG_V is never set, there can be no mappings to invalidate. 582 */ 583static int ptelist_count = 0; 584static vm_offset_t 585pmap_ptelist_alloc(vm_offset_t *head) 586{ 587 vm_offset_t va; 588 vm_offset_t *phead = (vm_offset_t *)*head; 589 590 if (ptelist_count == 0) { 591 printf("out of memory!!!!!!\n"); 592 return (0); /* Out of memory */ 593 } 594 ptelist_count--; 595 va = phead[ptelist_count]; 596 return (va); 597} 598 599static void 600pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 601{ 602 vm_offset_t *phead = (vm_offset_t *)*head; 603 604 phead[ptelist_count++] = va; 605} 606 607static void 608pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 609{ 610 int i, nstackpages; 611 vm_offset_t va; 612 vm_page_t m; 613 614 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 615 for (i = 0; i < nstackpages; i++) { 616 va = (vm_offset_t)base + i * PAGE_SIZE; 617 m = vm_page_alloc(NULL, i, 618 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 619 VM_ALLOC_ZERO); 620 pmap_qenter(va, &m, 1); 621 } 622 623 *head = (vm_offset_t)base; 624 for (i = npages - 1; i >= nstackpages; i--) { 625 va = (vm_offset_t)base + i * PAGE_SIZE; 626 pmap_ptelist_free(head, va); 627 } 628} 629 630 631/* 632 * Initialize the pmap module. 633 * Called by vm_init, to initialize any structures that the pmap 634 * system needs to map virtual memory. 635 */ 636void 637pmap_init(void) 638{ 639 vm_page_t mpte; 640 vm_size_t s; 641 int i, pv_npg; 642 643 /* 644 * Initialize the vm page array entries for the kernel pmap's 645 * page table pages. 646 */ 647 for (i = 0; i < nkpt; i++) { 648 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(PTD[i + KPTDI] & PG_FRAME)); 649 KASSERT(mpte >= vm_page_array && 650 mpte < &vm_page_array[vm_page_array_size], 651 ("pmap_init: page table page is out of range")); 652 mpte->pindex = i + KPTDI; 653 mpte->phys_addr = xpmap_mtop(PTD[i + KPTDI] & PG_FRAME); 654 } 655 656 /* 657 * Initialize the address space (zone) for the pv entries. Set a 658 * high water mark so that the system can recover from excessive 659 * numbers of pv entries. 660 */ 661 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 662 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 663 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 664 pv_entry_max = roundup(pv_entry_max, _NPCPV); 665 pv_entry_high_water = 9 * (pv_entry_max / 10); 666 667 /* 668 * Are large page mappings enabled? 669 */ 670 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 671 672 /* 673 * Calculate the size of the pv head table for superpages. 674 */ 675 for (i = 0; phys_avail[i + 1]; i += 2); 676 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 677 678 /* 679 * Allocate memory for the pv head table for superpages. 680 */ 681 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 682 s = round_page(s); 683 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 684 for (i = 0; i < pv_npg; i++) 685 TAILQ_INIT(&pv_table[i].pv_list); 686 687 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 688 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 689 PAGE_SIZE * pv_maxchunks); 690 if (pv_chunkbase == NULL) 691 panic("pmap_init: not enough kvm for pv chunks"); 692 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 693} 694 695 696/*************************************************** 697 * Low level helper routines..... 698 ***************************************************/ 699 700/* 701 * Determine the appropriate bits to set in a PTE or PDE for a specified 702 * caching mode. 703 */ 704int 705pmap_cache_bits(int mode, boolean_t is_pde) 706{ 707 int pat_flag, pat_index, cache_bits; 708 709 /* The PAT bit is different for PTE's and PDE's. */ 710 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 711 712 /* If we don't support PAT, map extended modes to older ones. */ 713 if (!(cpu_feature & CPUID_PAT)) { 714 switch (mode) { 715 case PAT_UNCACHEABLE: 716 case PAT_WRITE_THROUGH: 717 case PAT_WRITE_BACK: 718 break; 719 case PAT_UNCACHED: 720 case PAT_WRITE_COMBINING: 721 case PAT_WRITE_PROTECTED: 722 mode = PAT_UNCACHEABLE; 723 break; 724 } 725 } 726 727 /* Map the caching mode to a PAT index. */ 728 if (pat_works) { 729 switch (mode) { 730 case PAT_UNCACHEABLE: 731 pat_index = 3; 732 break; 733 case PAT_WRITE_THROUGH: 734 pat_index = 1; 735 break; 736 case PAT_WRITE_BACK: 737 pat_index = 0; 738 break; 739 case PAT_UNCACHED: 740 pat_index = 2; 741 break; 742 case PAT_WRITE_COMBINING: 743 pat_index = 5; 744 break; 745 case PAT_WRITE_PROTECTED: 746 pat_index = 4; 747 break; 748 default: 749 panic("Unknown caching mode %d\n", mode); 750 } 751 } else { 752 switch (mode) { 753 case PAT_UNCACHED: 754 case PAT_UNCACHEABLE: 755 case PAT_WRITE_PROTECTED: 756 pat_index = 3; 757 break; 758 case PAT_WRITE_THROUGH: 759 pat_index = 1; 760 break; 761 case PAT_WRITE_BACK: 762 pat_index = 0; 763 break; 764 case PAT_WRITE_COMBINING: 765 pat_index = 2; 766 break; 767 default: 768 panic("Unknown caching mode %d\n", mode); 769 } 770 } 771 772 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 773 cache_bits = 0; 774 if (pat_index & 0x4) 775 cache_bits |= pat_flag; 776 if (pat_index & 0x2) 777 cache_bits |= PG_NC_PCD; 778 if (pat_index & 0x1) 779 cache_bits |= PG_NC_PWT; 780 return (cache_bits); 781} 782#ifdef SMP 783/* 784 * For SMP, these functions have to use the IPI mechanism for coherence. 785 * 786 * N.B.: Before calling any of the following TLB invalidation functions, 787 * the calling processor must ensure that all stores updating a non- 788 * kernel page table are globally performed. Otherwise, another 789 * processor could cache an old, pre-update entry without being 790 * invalidated. This can happen one of two ways: (1) The pmap becomes 791 * active on another processor after its pm_active field is checked by 792 * one of the following functions but before a store updating the page 793 * table is globally performed. (2) The pmap becomes active on another 794 * processor before its pm_active field is checked but due to 795 * speculative loads one of the following functions stills reads the 796 * pmap as inactive on the other processor. 797 * 798 * The kernel page table is exempt because its pm_active field is 799 * immutable. The kernel page table is always active on every 800 * processor. 801 */ 802void 803pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 804{ 805 cpumask_t cpumask, other_cpus; 806 807 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 808 pmap, va); 809 810 sched_pin(); 811 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 812 invlpg(va); 813 smp_invlpg(va); 814 } else { 815 cpumask = PCPU_GET(cpumask); 816 other_cpus = PCPU_GET(other_cpus); 817 if (pmap->pm_active & cpumask) 818 invlpg(va); 819 if (pmap->pm_active & other_cpus) 820 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 821 } 822 sched_unpin(); 823 PT_UPDATES_FLUSH(); 824} 825 826void 827pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 828{ 829 cpumask_t cpumask, other_cpus; 830 vm_offset_t addr; 831 832 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 833 pmap, sva, eva); 834 835 sched_pin(); 836 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 837 for (addr = sva; addr < eva; addr += PAGE_SIZE) 838 invlpg(addr); 839 smp_invlpg_range(sva, eva); 840 } else { 841 cpumask = PCPU_GET(cpumask); 842 other_cpus = PCPU_GET(other_cpus); 843 if (pmap->pm_active & cpumask) 844 for (addr = sva; addr < eva; addr += PAGE_SIZE) 845 invlpg(addr); 846 if (pmap->pm_active & other_cpus) 847 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 848 sva, eva); 849 } 850 sched_unpin(); 851 PT_UPDATES_FLUSH(); 852} 853 854void 855pmap_invalidate_all(pmap_t pmap) 856{ 857 cpumask_t cpumask, other_cpus; 858 859 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 860 861 sched_pin(); 862 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 863 invltlb(); 864 smp_invltlb(); 865 } else { 866 cpumask = PCPU_GET(cpumask); 867 other_cpus = PCPU_GET(other_cpus); 868 if (pmap->pm_active & cpumask) 869 invltlb(); 870 if (pmap->pm_active & other_cpus) 871 smp_masked_invltlb(pmap->pm_active & other_cpus); 872 } 873 sched_unpin(); 874} 875 876void 877pmap_invalidate_cache(void) 878{ 879 880 sched_pin(); 881 wbinvd(); 882 smp_cache_flush(); 883 sched_unpin(); 884} 885#else /* !SMP */ 886/* 887 * Normal, non-SMP, 486+ invalidation functions. 888 * We inline these within pmap.c for speed. 889 */ 890PMAP_INLINE void 891pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 892{ 893 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 894 pmap, va); 895 896 if (pmap == kernel_pmap || pmap->pm_active) 897 invlpg(va); 898 PT_UPDATES_FLUSH(); 899} 900 901PMAP_INLINE void 902pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 903{ 904 vm_offset_t addr; 905 906 if (eva - sva > PAGE_SIZE) 907 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 908 pmap, sva, eva); 909 910 if (pmap == kernel_pmap || pmap->pm_active) 911 for (addr = sva; addr < eva; addr += PAGE_SIZE) 912 invlpg(addr); 913 PT_UPDATES_FLUSH(); 914} 915 916PMAP_INLINE void 917pmap_invalidate_all(pmap_t pmap) 918{ 919 920 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 921 922 if (pmap == kernel_pmap || pmap->pm_active) 923 invltlb(); 924} 925 926PMAP_INLINE void 927pmap_invalidate_cache(void) 928{ 929 930 wbinvd(); 931} 932#endif /* !SMP */ 933 934void 935pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 936{ 937 938 KASSERT((sva & PAGE_MASK) == 0, 939 ("pmap_invalidate_cache_range: sva not page-aligned")); 940 KASSERT((eva & PAGE_MASK) == 0, 941 ("pmap_invalidate_cache_range: eva not page-aligned")); 942 943 if (cpu_feature & CPUID_SS) 944 ; /* If "Self Snoop" is supported, do nothing. */ 945 else if (cpu_feature & CPUID_CLFSH) { 946 947 /* 948 * Otherwise, do per-cache line flush. Use the mfence 949 * instruction to insure that previous stores are 950 * included in the write-back. The processor 951 * propagates flush to other processors in the cache 952 * coherence domain. 953 */ 954 mfence(); 955 for (; sva < eva; sva += cpu_clflush_line_size) 956 clflush(sva); 957 mfence(); 958 } else { 959 960 /* 961 * No targeted cache flush methods are supported by CPU, 962 * globally invalidate cache as a last resort. 963 */ 964 pmap_invalidate_cache(); 965 } 966} 967 968/* 969 * Are we current address space or kernel? N.B. We return FALSE when 970 * a pmap's page table is in use because a kernel thread is borrowing 971 * it. The borrowed page table can change spontaneously, making any 972 * dependence on its continued use subject to a race condition. 973 */ 974static __inline int 975pmap_is_current(pmap_t pmap) 976{ 977 978 return (pmap == kernel_pmap || 979 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 980 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 981} 982 983/* 984 * If the given pmap is not the current or kernel pmap, the returned pte must 985 * be released by passing it to pmap_pte_release(). 986 */ 987pt_entry_t * 988pmap_pte(pmap_t pmap, vm_offset_t va) 989{ 990 pd_entry_t newpf; 991 pd_entry_t *pde; 992 993 pde = pmap_pde(pmap, va); 994 if (*pde & PG_PS) 995 return (pde); 996 if (*pde != 0) { 997 /* are we current address space or kernel? */ 998 if (pmap_is_current(pmap)) 999 return (vtopte(va)); 1000 mtx_lock(&PMAP2mutex); 1001 newpf = *pde & PG_FRAME; 1002 if ((*PMAP2 & PG_FRAME) != newpf) { 1003 vm_page_lock_queues(); 1004 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 1005 vm_page_unlock_queues(); 1006 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 1007 pmap, va, (*PMAP2 & 0xffffffff)); 1008 } 1009 1010 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1011 } 1012 return (0); 1013} 1014 1015/* 1016 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1017 * being NULL. 1018 */ 1019static __inline void 1020pmap_pte_release(pt_entry_t *pte) 1021{ 1022 1023 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 1024 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 1025 *PMAP2); 1026 vm_page_lock_queues(); 1027 PT_SET_VA(PMAP2, 0, TRUE); 1028 vm_page_unlock_queues(); 1029 mtx_unlock(&PMAP2mutex); 1030 } 1031} 1032 1033static __inline void 1034invlcaddr(void *caddr) 1035{ 1036 1037 invlpg((u_int)caddr); 1038 PT_UPDATES_FLUSH(); 1039} 1040 1041/* 1042 * Super fast pmap_pte routine best used when scanning 1043 * the pv lists. This eliminates many coarse-grained 1044 * invltlb calls. Note that many of the pv list 1045 * scans are across different pmaps. It is very wasteful 1046 * to do an entire invltlb for checking a single mapping. 1047 * 1048 * If the given pmap is not the current pmap, vm_page_queue_mtx 1049 * must be held and curthread pinned to a CPU. 1050 */ 1051static pt_entry_t * 1052pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1053{ 1054 pd_entry_t newpf; 1055 pd_entry_t *pde; 1056 1057 pde = pmap_pde(pmap, va); 1058 if (*pde & PG_PS) 1059 return (pde); 1060 if (*pde != 0) { 1061 /* are we current address space or kernel? */ 1062 if (pmap_is_current(pmap)) 1063 return (vtopte(va)); 1064 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1065 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1066 newpf = *pde & PG_FRAME; 1067 if ((*PMAP1 & PG_FRAME) != newpf) { 1068 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1069 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1070 pmap, va, (u_long)*PMAP1); 1071 1072#ifdef SMP 1073 PMAP1cpu = PCPU_GET(cpuid); 1074#endif 1075 PMAP1changed++; 1076 } else 1077#ifdef SMP 1078 if (PMAP1cpu != PCPU_GET(cpuid)) { 1079 PMAP1cpu = PCPU_GET(cpuid); 1080 invlcaddr(PADDR1); 1081 PMAP1changedcpu++; 1082 } else 1083#endif 1084 PMAP1unchanged++; 1085 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1086 } 1087 return (0); 1088} 1089 1090/* 1091 * Routine: pmap_extract 1092 * Function: 1093 * Extract the physical page address associated 1094 * with the given map/virtual_address pair. 1095 */ 1096vm_paddr_t 1097pmap_extract(pmap_t pmap, vm_offset_t va) 1098{ 1099 vm_paddr_t rtval; 1100 pt_entry_t *pte; 1101 pd_entry_t pde; 1102 pt_entry_t pteval; 1103 1104 rtval = 0; 1105 PMAP_LOCK(pmap); 1106 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1107 if (pde != 0) { 1108 if ((pde & PG_PS) != 0) { 1109 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1110 PMAP_UNLOCK(pmap); 1111 return rtval; 1112 } 1113 pte = pmap_pte(pmap, va); 1114 pteval = *pte ? xpmap_mtop(*pte) : 0; 1115 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1116 pmap_pte_release(pte); 1117 } 1118 PMAP_UNLOCK(pmap); 1119 return (rtval); 1120} 1121 1122/* 1123 * Routine: pmap_extract_ma 1124 * Function: 1125 * Like pmap_extract, but returns machine address 1126 */ 1127vm_paddr_t 1128pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1129{ 1130 vm_paddr_t rtval; 1131 pt_entry_t *pte; 1132 pd_entry_t pde; 1133 1134 rtval = 0; 1135 PMAP_LOCK(pmap); 1136 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1137 if (pde != 0) { 1138 if ((pde & PG_PS) != 0) { 1139 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1140 PMAP_UNLOCK(pmap); 1141 return rtval; 1142 } 1143 pte = pmap_pte(pmap, va); 1144 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1145 pmap_pte_release(pte); 1146 } 1147 PMAP_UNLOCK(pmap); 1148 return (rtval); 1149} 1150 1151/* 1152 * Routine: pmap_extract_and_hold 1153 * Function: 1154 * Atomically extract and hold the physical page 1155 * with the given pmap and virtual address pair 1156 * if that mapping permits the given protection. 1157 */ 1158vm_page_t 1159pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1160{ 1161 pd_entry_t pde; 1162 pt_entry_t pte; 1163 vm_page_t m; 1164 vm_paddr_t pa; 1165 1166 pa = 0; 1167 m = NULL; 1168 PMAP_LOCK(pmap); 1169retry: 1170 pde = PT_GET(pmap_pde(pmap, va)); 1171 if (pde != 0) { 1172 if (pde & PG_PS) { 1173 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1174 if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) | 1175 (va & PDRMASK), &pa)) 1176 goto retry; 1177 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1178 (va & PDRMASK)); 1179 vm_page_hold(m); 1180 } 1181 } else { 1182 sched_pin(); 1183 pte = PT_GET(pmap_pte_quick(pmap, va)); 1184 if (*PMAP1) 1185 PT_SET_MA(PADDR1, 0); 1186 if ((pte & PG_V) && 1187 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1188 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa)) 1189 goto retry; 1190 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1191 vm_page_hold(m); 1192 } 1193 sched_unpin(); 1194 } 1195 } 1196 PA_UNLOCK_COND(pa); 1197 PMAP_UNLOCK(pmap); 1198 return (m); 1199} 1200 1201/*************************************************** 1202 * Low level mapping routines..... 1203 ***************************************************/ 1204 1205/* 1206 * Add a wired page to the kva. 1207 * Note: not SMP coherent. 1208 */ 1209void 1210pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1211{ 1212 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1213} 1214 1215void 1216pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1217{ 1218 pt_entry_t *pte; 1219 1220 pte = vtopte(va); 1221 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1222} 1223 1224 1225static __inline void 1226pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1227{ 1228 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1229} 1230 1231/* 1232 * Remove a page from the kernel pagetables. 1233 * Note: not SMP coherent. 1234 */ 1235PMAP_INLINE void 1236pmap_kremove(vm_offset_t va) 1237{ 1238 pt_entry_t *pte; 1239 1240 pte = vtopte(va); 1241 PT_CLEAR_VA(pte, FALSE); 1242} 1243 1244/* 1245 * Used to map a range of physical addresses into kernel 1246 * virtual address space. 1247 * 1248 * The value passed in '*virt' is a suggested virtual address for 1249 * the mapping. Architectures which can support a direct-mapped 1250 * physical to virtual region can return the appropriate address 1251 * within that region, leaving '*virt' unchanged. Other 1252 * architectures should map the pages starting at '*virt' and 1253 * update '*virt' with the first usable address after the mapped 1254 * region. 1255 */ 1256vm_offset_t 1257pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1258{ 1259 vm_offset_t va, sva; 1260 1261 va = sva = *virt; 1262 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1263 va, start, end, prot); 1264 while (start < end) { 1265 pmap_kenter(va, start); 1266 va += PAGE_SIZE; 1267 start += PAGE_SIZE; 1268 } 1269 pmap_invalidate_range(kernel_pmap, sva, va); 1270 *virt = va; 1271 return (sva); 1272} 1273 1274 1275/* 1276 * Add a list of wired pages to the kva 1277 * this routine is only used for temporary 1278 * kernel mappings that do not need to have 1279 * page modification or references recorded. 1280 * Note that old mappings are simply written 1281 * over. The page *must* be wired. 1282 * Note: SMP coherent. Uses a ranged shootdown IPI. 1283 */ 1284void 1285pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1286{ 1287 pt_entry_t *endpte, *pte; 1288 vm_paddr_t pa; 1289 vm_offset_t va = sva; 1290 int mclcount = 0; 1291 multicall_entry_t mcl[16]; 1292 multicall_entry_t *mclp = mcl; 1293 int error; 1294 1295 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1296 pte = vtopte(sva); 1297 endpte = pte + count; 1298 while (pte < endpte) { 1299 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1300 1301 mclp->op = __HYPERVISOR_update_va_mapping; 1302 mclp->args[0] = va; 1303 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1304 mclp->args[2] = (uint32_t)(pa >> 32); 1305 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1306 1307 va += PAGE_SIZE; 1308 pte++; 1309 ma++; 1310 mclp++; 1311 mclcount++; 1312 if (mclcount == 16) { 1313 error = HYPERVISOR_multicall(mcl, mclcount); 1314 mclp = mcl; 1315 mclcount = 0; 1316 KASSERT(error == 0, ("bad multicall %d", error)); 1317 } 1318 } 1319 if (mclcount) { 1320 error = HYPERVISOR_multicall(mcl, mclcount); 1321 KASSERT(error == 0, ("bad multicall %d", error)); 1322 } 1323 1324#ifdef INVARIANTS 1325 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1326 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1327#endif 1328} 1329 1330 1331/* 1332 * This routine tears out page mappings from the 1333 * kernel -- it is meant only for temporary mappings. 1334 * Note: SMP coherent. Uses a ranged shootdown IPI. 1335 */ 1336void 1337pmap_qremove(vm_offset_t sva, int count) 1338{ 1339 vm_offset_t va; 1340 1341 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1342 va = sva; 1343 vm_page_lock_queues(); 1344 critical_enter(); 1345 while (count-- > 0) { 1346 pmap_kremove(va); 1347 va += PAGE_SIZE; 1348 } 1349 PT_UPDATES_FLUSH(); 1350 pmap_invalidate_range(kernel_pmap, sva, va); 1351 critical_exit(); 1352 vm_page_unlock_queues(); 1353} 1354 1355/*************************************************** 1356 * Page table page management routines..... 1357 ***************************************************/ 1358static __inline void 1359pmap_free_zero_pages(vm_page_t free) 1360{ 1361 vm_page_t m; 1362 1363 while (free != NULL) { 1364 m = free; 1365 free = m->right; 1366 vm_page_free_zero(m); 1367 } 1368} 1369 1370/* 1371 * This routine unholds page table pages, and if the hold count 1372 * drops to zero, then it decrements the wire count. 1373 */ 1374static __inline int 1375pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1376{ 1377 1378 --m->wire_count; 1379 if (m->wire_count == 0) 1380 return _pmap_unwire_pte_hold(pmap, m, free); 1381 else 1382 return 0; 1383} 1384 1385static int 1386_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1387{ 1388 vm_offset_t pteva; 1389 1390 PT_UPDATES_FLUSH(); 1391 /* 1392 * unmap the page table page 1393 */ 1394 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1395 /* 1396 * page *might* contain residual mapping :-/ 1397 */ 1398 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1399 pmap_zero_page(m); 1400 --pmap->pm_stats.resident_count; 1401 1402 /* 1403 * This is a release store so that the ordinary store unmapping 1404 * the page table page is globally performed before TLB shoot- 1405 * down is begun. 1406 */ 1407 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1408 1409 /* 1410 * Do an invltlb to make the invalidated mapping 1411 * take effect immediately. 1412 */ 1413 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1414 pmap_invalidate_page(pmap, pteva); 1415 1416 /* 1417 * Put page on a list so that it is released after 1418 * *ALL* TLB shootdown is done 1419 */ 1420 m->right = *free; 1421 *free = m; 1422 1423 return 1; 1424} 1425 1426/* 1427 * After removing a page table entry, this routine is used to 1428 * conditionally free the page, and manage the hold/wire counts. 1429 */ 1430static int 1431pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1432{ 1433 pd_entry_t ptepde; 1434 vm_page_t mpte; 1435 1436 if (va >= VM_MAXUSER_ADDRESS) 1437 return 0; 1438 ptepde = PT_GET(pmap_pde(pmap, va)); 1439 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1440 return pmap_unwire_pte_hold(pmap, mpte, free); 1441} 1442 1443void 1444pmap_pinit0(pmap_t pmap) 1445{ 1446 1447 PMAP_LOCK_INIT(pmap); 1448 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1449#ifdef PAE 1450 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1451#endif 1452 pmap->pm_active = 0; 1453 PCPU_SET(curpmap, pmap); 1454 TAILQ_INIT(&pmap->pm_pvchunk); 1455 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1456 mtx_lock_spin(&allpmaps_lock); 1457 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1458 mtx_unlock_spin(&allpmaps_lock); 1459} 1460 1461/* 1462 * Initialize a preallocated and zeroed pmap structure, 1463 * such as one in a vmspace structure. 1464 */ 1465int 1466pmap_pinit(pmap_t pmap) 1467{ 1468 vm_page_t m, ptdpg[NPGPTD + 1]; 1469 int npgptd = NPGPTD + 1; 1470 static int color; 1471 int i; 1472 1473#ifdef HAMFISTED_LOCKING 1474 mtx_lock(&createdelete_lock); 1475#endif 1476 1477 PMAP_LOCK_INIT(pmap); 1478 1479 /* 1480 * No need to allocate page table space yet but we do need a valid 1481 * page directory table. 1482 */ 1483 if (pmap->pm_pdir == NULL) { 1484 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1485 NBPTD); 1486 if (pmap->pm_pdir == NULL) { 1487 PMAP_LOCK_DESTROY(pmap); 1488#ifdef HAMFISTED_LOCKING 1489 mtx_unlock(&createdelete_lock); 1490#endif 1491 return (0); 1492 } 1493#ifdef PAE 1494 pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1495#endif 1496 } 1497 1498 /* 1499 * allocate the page directory page(s) 1500 */ 1501 for (i = 0; i < npgptd;) { 1502 m = vm_page_alloc(NULL, color++, 1503 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1504 VM_ALLOC_ZERO); 1505 if (m == NULL) 1506 VM_WAIT; 1507 else { 1508 ptdpg[i++] = m; 1509 } 1510 } 1511 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1512 for (i = 0; i < NPGPTD; i++) { 1513 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1514 pagezero(&pmap->pm_pdir[i*NPTEPG]); 1515 } 1516 1517 mtx_lock_spin(&allpmaps_lock); 1518 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1519 mtx_unlock_spin(&allpmaps_lock); 1520 /* Wire in kernel global address entries. */ 1521 1522 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1523#ifdef PAE 1524 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1525 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1526 bzero(pmap->pm_pdpt, PAGE_SIZE); 1527 for (i = 0; i < NPGPTD; i++) { 1528 vm_paddr_t ma; 1529 1530 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1531 pmap->pm_pdpt[i] = ma | PG_V; 1532 1533 } 1534#endif 1535 for (i = 0; i < NPGPTD; i++) { 1536 pt_entry_t *pd; 1537 vm_paddr_t ma; 1538 1539 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1540 pd = pmap->pm_pdir + (i * NPDEPG); 1541 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1542#if 0 1543 xen_pgd_pin(ma); 1544#endif 1545 } 1546 1547#ifdef PAE 1548 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1549#endif 1550 vm_page_lock_queues(); 1551 xen_flush_queue(); 1552 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1553 for (i = 0; i < NPGPTD; i++) { 1554 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1555 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1556 } 1557 xen_flush_queue(); 1558 vm_page_unlock_queues(); 1559 pmap->pm_active = 0; 1560 TAILQ_INIT(&pmap->pm_pvchunk); 1561 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1562 1563#ifdef HAMFISTED_LOCKING 1564 mtx_unlock(&createdelete_lock); 1565#endif 1566 return (1); 1567} 1568 1569/* 1570 * this routine is called if the page table page is not 1571 * mapped correctly. 1572 */ 1573static vm_page_t 1574_pmap_allocpte(pmap_t pmap, unsigned int ptepindex, int flags) 1575{ 1576 vm_paddr_t ptema; 1577 vm_page_t m; 1578 1579 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1580 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1581 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1582 1583 /* 1584 * Allocate a page table page. 1585 */ 1586 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1587 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1588 if (flags & M_WAITOK) { 1589 PMAP_UNLOCK(pmap); 1590 vm_page_unlock_queues(); 1591 VM_WAIT; 1592 vm_page_lock_queues(); 1593 PMAP_LOCK(pmap); 1594 } 1595 1596 /* 1597 * Indicate the need to retry. While waiting, the page table 1598 * page may have been allocated. 1599 */ 1600 return (NULL); 1601 } 1602 if ((m->flags & PG_ZERO) == 0) 1603 pmap_zero_page(m); 1604 1605 /* 1606 * Map the pagetable page into the process address space, if 1607 * it isn't already there. 1608 */ 1609 pmap->pm_stats.resident_count++; 1610 1611 ptema = VM_PAGE_TO_MACH(m); 1612 xen_pt_pin(ptema); 1613 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1614 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1615 1616 KASSERT(pmap->pm_pdir[ptepindex], 1617 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1618 return (m); 1619} 1620 1621static vm_page_t 1622pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1623{ 1624 unsigned ptepindex; 1625 pd_entry_t ptema; 1626 vm_page_t m; 1627 1628 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1629 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1630 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1631 1632 /* 1633 * Calculate pagetable page index 1634 */ 1635 ptepindex = va >> PDRSHIFT; 1636retry: 1637 /* 1638 * Get the page directory entry 1639 */ 1640 ptema = pmap->pm_pdir[ptepindex]; 1641 1642 /* 1643 * This supports switching from a 4MB page to a 1644 * normal 4K page. 1645 */ 1646 if (ptema & PG_PS) { 1647 /* 1648 * XXX 1649 */ 1650 pmap->pm_pdir[ptepindex] = 0; 1651 ptema = 0; 1652 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1653 pmap_invalidate_all(kernel_pmap); 1654 } 1655 1656 /* 1657 * If the page table page is mapped, we just increment the 1658 * hold count, and activate it. 1659 */ 1660 if (ptema & PG_V) { 1661 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1662 m->wire_count++; 1663 } else { 1664 /* 1665 * Here if the pte page isn't mapped, or if it has 1666 * been deallocated. 1667 */ 1668 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1669 pmap, va, flags); 1670 m = _pmap_allocpte(pmap, ptepindex, flags); 1671 if (m == NULL && (flags & M_WAITOK)) 1672 goto retry; 1673 1674 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1675 } 1676 return (m); 1677} 1678 1679 1680/*************************************************** 1681* Pmap allocation/deallocation routines. 1682 ***************************************************/ 1683 1684#ifdef SMP 1685/* 1686 * Deal with a SMP shootdown of other users of the pmap that we are 1687 * trying to dispose of. This can be a bit hairy. 1688 */ 1689static cpumask_t *lazymask; 1690static u_int lazyptd; 1691static volatile u_int lazywait; 1692 1693void pmap_lazyfix_action(void); 1694 1695void 1696pmap_lazyfix_action(void) 1697{ 1698 cpumask_t mymask = PCPU_GET(cpumask); 1699 1700#ifdef COUNT_IPIS 1701 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1702#endif 1703 if (rcr3() == lazyptd) 1704 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1705 atomic_clear_int(lazymask, mymask); 1706 atomic_store_rel_int(&lazywait, 1); 1707} 1708 1709static void 1710pmap_lazyfix_self(cpumask_t mymask) 1711{ 1712 1713 if (rcr3() == lazyptd) 1714 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1715 atomic_clear_int(lazymask, mymask); 1716} 1717 1718 1719static void 1720pmap_lazyfix(pmap_t pmap) 1721{ 1722 cpumask_t mymask, mask; 1723 u_int spins; 1724 1725 while ((mask = pmap->pm_active) != 0) { 1726 spins = 50000000; 1727 mask = mask & -mask; /* Find least significant set bit */ 1728 mtx_lock_spin(&smp_ipi_mtx); 1729#ifdef PAE 1730 lazyptd = vtophys(pmap->pm_pdpt); 1731#else 1732 lazyptd = vtophys(pmap->pm_pdir); 1733#endif 1734 mymask = PCPU_GET(cpumask); 1735 if (mask == mymask) { 1736 lazymask = &pmap->pm_active; 1737 pmap_lazyfix_self(mymask); 1738 } else { 1739 atomic_store_rel_int((u_int *)&lazymask, 1740 (u_int)&pmap->pm_active); 1741 atomic_store_rel_int(&lazywait, 0); 1742 ipi_selected(mask, IPI_LAZYPMAP); 1743 while (lazywait == 0) { 1744 ia32_pause(); 1745 if (--spins == 0) 1746 break; 1747 } 1748 } 1749 mtx_unlock_spin(&smp_ipi_mtx); 1750 if (spins == 0) 1751 printf("pmap_lazyfix: spun for 50000000\n"); 1752 } 1753} 1754 1755#else /* SMP */ 1756 1757/* 1758 * Cleaning up on uniprocessor is easy. For various reasons, we're 1759 * unlikely to have to even execute this code, including the fact 1760 * that the cleanup is deferred until the parent does a wait(2), which 1761 * means that another userland process has run. 1762 */ 1763static void 1764pmap_lazyfix(pmap_t pmap) 1765{ 1766 u_int cr3; 1767 1768 cr3 = vtophys(pmap->pm_pdir); 1769 if (cr3 == rcr3()) { 1770 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1771 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1772 } 1773} 1774#endif /* SMP */ 1775 1776/* 1777 * Release any resources held by the given physical map. 1778 * Called when a pmap initialized by pmap_pinit is being released. 1779 * Should only be called if the map contains no valid mappings. 1780 */ 1781void 1782pmap_release(pmap_t pmap) 1783{ 1784 vm_page_t m, ptdpg[2*NPGPTD+1]; 1785 vm_paddr_t ma; 1786 int i; 1787#ifdef PAE 1788 int npgptd = NPGPTD + 1; 1789#else 1790 int npgptd = NPGPTD; 1791#endif 1792 KASSERT(pmap->pm_stats.resident_count == 0, 1793 ("pmap_release: pmap resident count %ld != 0", 1794 pmap->pm_stats.resident_count)); 1795 PT_UPDATES_FLUSH(); 1796 1797#ifdef HAMFISTED_LOCKING 1798 mtx_lock(&createdelete_lock); 1799#endif 1800 1801 pmap_lazyfix(pmap); 1802 mtx_lock_spin(&allpmaps_lock); 1803 LIST_REMOVE(pmap, pm_list); 1804 mtx_unlock_spin(&allpmaps_lock); 1805 1806 for (i = 0; i < NPGPTD; i++) 1807 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1808 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1809#ifdef PAE 1810 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1811#endif 1812 1813 for (i = 0; i < npgptd; i++) { 1814 m = ptdpg[i]; 1815 ma = VM_PAGE_TO_MACH(m); 1816 /* unpinning L1 and L2 treated the same */ 1817#if 0 1818 xen_pgd_unpin(ma); 1819#else 1820 if (i == NPGPTD) 1821 xen_pgd_unpin(ma); 1822#endif 1823#ifdef PAE 1824 if (i < NPGPTD) 1825 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1826 ("pmap_release: got wrong ptd page")); 1827#endif 1828 m->wire_count--; 1829 atomic_subtract_int(&cnt.v_wire_count, 1); 1830 vm_page_free(m); 1831 } 1832#ifdef PAE 1833 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1834#endif 1835 PMAP_LOCK_DESTROY(pmap); 1836 1837#ifdef HAMFISTED_LOCKING 1838 mtx_unlock(&createdelete_lock); 1839#endif 1840} 1841 1842static int 1843kvm_size(SYSCTL_HANDLER_ARGS) 1844{ 1845 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1846 1847 return sysctl_handle_long(oidp, &ksize, 0, req); 1848} 1849SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1850 0, 0, kvm_size, "IU", "Size of KVM"); 1851 1852static int 1853kvm_free(SYSCTL_HANDLER_ARGS) 1854{ 1855 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1856 1857 return sysctl_handle_long(oidp, &kfree, 0, req); 1858} 1859SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1860 0, 0, kvm_free, "IU", "Amount of KVM free"); 1861 1862/* 1863 * grow the number of kernel page table entries, if needed 1864 */ 1865void 1866pmap_growkernel(vm_offset_t addr) 1867{ 1868 struct pmap *pmap; 1869 vm_paddr_t ptppaddr; 1870 vm_page_t nkpg; 1871 pd_entry_t newpdir; 1872 1873 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1874 if (kernel_vm_end == 0) { 1875 kernel_vm_end = KERNBASE; 1876 nkpt = 0; 1877 while (pdir_pde(PTD, kernel_vm_end)) { 1878 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1879 nkpt++; 1880 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1881 kernel_vm_end = kernel_map->max_offset; 1882 break; 1883 } 1884 } 1885 } 1886 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1887 if (addr - 1 >= kernel_map->max_offset) 1888 addr = kernel_map->max_offset; 1889 while (kernel_vm_end < addr) { 1890 if (pdir_pde(PTD, kernel_vm_end)) { 1891 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1892 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1893 kernel_vm_end = kernel_map->max_offset; 1894 break; 1895 } 1896 continue; 1897 } 1898 1899 /* 1900 * This index is bogus, but out of the way 1901 */ 1902 nkpg = vm_page_alloc(NULL, nkpt, 1903 VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED); 1904 if (!nkpg) 1905 panic("pmap_growkernel: no memory to grow kernel"); 1906 1907 nkpt++; 1908 1909 pmap_zero_page(nkpg); 1910 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1911 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1912 vm_page_lock_queues(); 1913 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1914 mtx_lock_spin(&allpmaps_lock); 1915 LIST_FOREACH(pmap, &allpmaps, pm_list) 1916 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1917 1918 mtx_unlock_spin(&allpmaps_lock); 1919 vm_page_unlock_queues(); 1920 1921 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1922 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1923 kernel_vm_end = kernel_map->max_offset; 1924 break; 1925 } 1926 } 1927} 1928 1929 1930/*************************************************** 1931 * page management routines. 1932 ***************************************************/ 1933 1934CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1935CTASSERT(_NPCM == 11); 1936 1937static __inline struct pv_chunk * 1938pv_to_chunk(pv_entry_t pv) 1939{ 1940 1941 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1942} 1943 1944#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1945 1946#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1947#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1948 1949static uint32_t pc_freemask[11] = { 1950 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1951 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1952 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1953 PC_FREE0_9, PC_FREE10 1954}; 1955 1956SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1957 "Current number of pv entries"); 1958 1959#ifdef PV_STATS 1960static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1961 1962SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1963 "Current number of pv entry chunks"); 1964SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1965 "Current number of pv entry chunks allocated"); 1966SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1967 "Current number of pv entry chunks frees"); 1968SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1969 "Number of times tried to get a chunk page but failed."); 1970 1971static long pv_entry_frees, pv_entry_allocs; 1972static int pv_entry_spare; 1973 1974SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1975 "Current number of pv entry frees"); 1976SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1977 "Current number of pv entry allocs"); 1978SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1979 "Current number of spare pv entries"); 1980 1981static int pmap_collect_inactive, pmap_collect_active; 1982 1983SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 1984 "Current number times pmap_collect called on inactive queue"); 1985SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 1986 "Current number times pmap_collect called on active queue"); 1987#endif 1988 1989/* 1990 * We are in a serious low memory condition. Resort to 1991 * drastic measures to free some pages so we can allocate 1992 * another pv entry chunk. This is normally called to 1993 * unmap inactive pages, and if necessary, active pages. 1994 */ 1995static void 1996pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 1997{ 1998 pmap_t pmap; 1999 pt_entry_t *pte, tpte; 2000 pv_entry_t next_pv, pv; 2001 vm_offset_t va; 2002 vm_page_t m, free; 2003 2004 sched_pin(); 2005 TAILQ_FOREACH(m, &vpq->pl, pageq) { 2006 if (m->hold_count || m->busy) 2007 continue; 2008 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 2009 va = pv->pv_va; 2010 pmap = PV_PMAP(pv); 2011 /* Avoid deadlock and lock recursion. */ 2012 if (pmap > locked_pmap) 2013 PMAP_LOCK(pmap); 2014 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 2015 continue; 2016 pmap->pm_stats.resident_count--; 2017 pte = pmap_pte_quick(pmap, va); 2018 tpte = pte_load_clear(pte); 2019 KASSERT((tpte & PG_W) == 0, 2020 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2021 if (tpte & PG_A) 2022 vm_page_flag_set(m, PG_REFERENCED); 2023 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2024 vm_page_dirty(m); 2025 free = NULL; 2026 pmap_unuse_pt(pmap, va, &free); 2027 pmap_invalidate_page(pmap, va); 2028 pmap_free_zero_pages(free); 2029 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2030 free_pv_entry(pmap, pv); 2031 if (pmap != locked_pmap) 2032 PMAP_UNLOCK(pmap); 2033 } 2034 if (TAILQ_EMPTY(&m->md.pv_list)) 2035 vm_page_flag_clear(m, PG_WRITEABLE); 2036 } 2037 sched_unpin(); 2038} 2039 2040 2041/* 2042 * free the pv_entry back to the free list 2043 */ 2044static void 2045free_pv_entry(pmap_t pmap, pv_entry_t pv) 2046{ 2047 vm_page_t m; 2048 struct pv_chunk *pc; 2049 int idx, field, bit; 2050 2051 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2052 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2053 PV_STAT(pv_entry_frees++); 2054 PV_STAT(pv_entry_spare++); 2055 pv_entry_count--; 2056 pc = pv_to_chunk(pv); 2057 idx = pv - &pc->pc_pventry[0]; 2058 field = idx / 32; 2059 bit = idx % 32; 2060 pc->pc_map[field] |= 1ul << bit; 2061 /* move to head of list */ 2062 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2063 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2064 for (idx = 0; idx < _NPCM; idx++) 2065 if (pc->pc_map[idx] != pc_freemask[idx]) 2066 return; 2067 PV_STAT(pv_entry_spare -= _NPCPV); 2068 PV_STAT(pc_chunk_count--); 2069 PV_STAT(pc_chunk_frees++); 2070 /* entire chunk is free, return it */ 2071 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2072 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2073 pmap_qremove((vm_offset_t)pc, 1); 2074 vm_page_unwire(m, 0); 2075 vm_page_free(m); 2076 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2077} 2078 2079/* 2080 * get a new pv_entry, allocating a block from the system 2081 * when needed. 2082 */ 2083static pv_entry_t 2084get_pv_entry(pmap_t pmap, int try) 2085{ 2086 static const struct timeval printinterval = { 60, 0 }; 2087 static struct timeval lastprint; 2088 static vm_pindex_t colour; 2089 struct vpgqueues *pq; 2090 int bit, field; 2091 pv_entry_t pv; 2092 struct pv_chunk *pc; 2093 vm_page_t m; 2094 2095 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2096 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2097 PV_STAT(pv_entry_allocs++); 2098 pv_entry_count++; 2099 if (pv_entry_count > pv_entry_high_water) 2100 if (ratecheck(&lastprint, &printinterval)) 2101 printf("Approaching the limit on PV entries, consider " 2102 "increasing either the vm.pmap.shpgperproc or the " 2103 "vm.pmap.pv_entry_max tunable.\n"); 2104 pq = NULL; 2105retry: 2106 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2107 if (pc != NULL) { 2108 for (field = 0; field < _NPCM; field++) { 2109 if (pc->pc_map[field]) { 2110 bit = bsfl(pc->pc_map[field]); 2111 break; 2112 } 2113 } 2114 if (field < _NPCM) { 2115 pv = &pc->pc_pventry[field * 32 + bit]; 2116 pc->pc_map[field] &= ~(1ul << bit); 2117 /* If this was the last item, move it to tail */ 2118 for (field = 0; field < _NPCM; field++) 2119 if (pc->pc_map[field] != 0) { 2120 PV_STAT(pv_entry_spare--); 2121 return (pv); /* not full, return */ 2122 } 2123 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2124 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2125 PV_STAT(pv_entry_spare--); 2126 return (pv); 2127 } 2128 } 2129 /* 2130 * Access to the ptelist "pv_vafree" is synchronized by the page 2131 * queues lock. If "pv_vafree" is currently non-empty, it will 2132 * remain non-empty until pmap_ptelist_alloc() completes. 2133 */ 2134 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2135 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2136 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2137 if (try) { 2138 pv_entry_count--; 2139 PV_STAT(pc_chunk_tryfail++); 2140 return (NULL); 2141 } 2142 /* 2143 * Reclaim pv entries: At first, destroy mappings to 2144 * inactive pages. After that, if a pv chunk entry 2145 * is still needed, destroy mappings to active pages. 2146 */ 2147 if (pq == NULL) { 2148 PV_STAT(pmap_collect_inactive++); 2149 pq = &vm_page_queues[PQ_INACTIVE]; 2150 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2151 PV_STAT(pmap_collect_active++); 2152 pq = &vm_page_queues[PQ_ACTIVE]; 2153 } else 2154 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2155 pmap_collect(pmap, pq); 2156 goto retry; 2157 } 2158 PV_STAT(pc_chunk_count++); 2159 PV_STAT(pc_chunk_allocs++); 2160 colour++; 2161 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2162 pmap_qenter((vm_offset_t)pc, &m, 1); 2163 if ((m->flags & PG_ZERO) == 0) 2164 pagezero(pc); 2165 pc->pc_pmap = pmap; 2166 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2167 for (field = 1; field < _NPCM; field++) 2168 pc->pc_map[field] = pc_freemask[field]; 2169 pv = &pc->pc_pventry[0]; 2170 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2171 PV_STAT(pv_entry_spare += _NPCPV - 1); 2172 return (pv); 2173} 2174 2175static __inline pv_entry_t 2176pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2177{ 2178 pv_entry_t pv; 2179 2180 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2181 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2182 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2183 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2184 break; 2185 } 2186 } 2187 return (pv); 2188} 2189 2190static void 2191pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2192{ 2193 pv_entry_t pv; 2194 2195 pv = pmap_pvh_remove(pvh, pmap, va); 2196 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2197 free_pv_entry(pmap, pv); 2198} 2199 2200static void 2201pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2202{ 2203 2204 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2205 pmap_pvh_free(&m->md, pmap, va); 2206 if (TAILQ_EMPTY(&m->md.pv_list)) 2207 vm_page_flag_clear(m, PG_WRITEABLE); 2208} 2209 2210/* 2211 * Conditionally create a pv entry. 2212 */ 2213static boolean_t 2214pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2215{ 2216 pv_entry_t pv; 2217 2218 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2219 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2220 if (pv_entry_count < pv_entry_high_water && 2221 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2222 pv->pv_va = va; 2223 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2224 return (TRUE); 2225 } else 2226 return (FALSE); 2227} 2228 2229/* 2230 * pmap_remove_pte: do the things to unmap a page in a process 2231 */ 2232static int 2233pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2234{ 2235 pt_entry_t oldpte; 2236 vm_page_t m; 2237 2238 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2239 pmap, (u_long)*ptq, va); 2240 2241 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2242 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2243 oldpte = *ptq; 2244 PT_SET_VA_MA(ptq, 0, TRUE); 2245 if (oldpte & PG_W) 2246 pmap->pm_stats.wired_count -= 1; 2247 /* 2248 * Machines that don't support invlpg, also don't support 2249 * PG_G. 2250 */ 2251 if (oldpte & PG_G) 2252 pmap_invalidate_page(kernel_pmap, va); 2253 pmap->pm_stats.resident_count -= 1; 2254 if (oldpte & PG_MANAGED) { 2255 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2256 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2257 vm_page_dirty(m); 2258 if (oldpte & PG_A) 2259 vm_page_flag_set(m, PG_REFERENCED); 2260 pmap_remove_entry(pmap, m, va); 2261 } 2262 return (pmap_unuse_pt(pmap, va, free)); 2263} 2264 2265/* 2266 * Remove a single page from a process address space 2267 */ 2268static void 2269pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2270{ 2271 pt_entry_t *pte; 2272 2273 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2274 pmap, va); 2275 2276 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2277 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2278 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2279 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2280 return; 2281 pmap_remove_pte(pmap, pte, va, free); 2282 pmap_invalidate_page(pmap, va); 2283 if (*PMAP1) 2284 PT_SET_MA(PADDR1, 0); 2285 2286} 2287 2288/* 2289 * Remove the given range of addresses from the specified map. 2290 * 2291 * It is assumed that the start and end are properly 2292 * rounded to the page size. 2293 */ 2294void 2295pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2296{ 2297 vm_offset_t pdnxt; 2298 pd_entry_t ptpaddr; 2299 pt_entry_t *pte; 2300 vm_page_t free = NULL; 2301 int anyvalid; 2302 2303 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2304 pmap, sva, eva); 2305 2306 /* 2307 * Perform an unsynchronized read. This is, however, safe. 2308 */ 2309 if (pmap->pm_stats.resident_count == 0) 2310 return; 2311 2312 anyvalid = 0; 2313 2314 vm_page_lock_queues(); 2315 sched_pin(); 2316 PMAP_LOCK(pmap); 2317 2318 /* 2319 * special handling of removing one page. a very 2320 * common operation and easy to short circuit some 2321 * code. 2322 */ 2323 if ((sva + PAGE_SIZE == eva) && 2324 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2325 pmap_remove_page(pmap, sva, &free); 2326 goto out; 2327 } 2328 2329 for (; sva < eva; sva = pdnxt) { 2330 unsigned pdirindex; 2331 2332 /* 2333 * Calculate index for next page table. 2334 */ 2335 pdnxt = (sva + NBPDR) & ~PDRMASK; 2336 if (pmap->pm_stats.resident_count == 0) 2337 break; 2338 2339 pdirindex = sva >> PDRSHIFT; 2340 ptpaddr = pmap->pm_pdir[pdirindex]; 2341 2342 /* 2343 * Weed out invalid mappings. Note: we assume that the page 2344 * directory table is always allocated, and in kernel virtual. 2345 */ 2346 if (ptpaddr == 0) 2347 continue; 2348 2349 /* 2350 * Check for large page. 2351 */ 2352 if ((ptpaddr & PG_PS) != 0) { 2353 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2354 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2355 anyvalid = 1; 2356 continue; 2357 } 2358 2359 /* 2360 * Limit our scan to either the end of the va represented 2361 * by the current page table page, or to the end of the 2362 * range being removed. 2363 */ 2364 if (pdnxt > eva) 2365 pdnxt = eva; 2366 2367 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2368 sva += PAGE_SIZE) { 2369 if ((*pte & PG_V) == 0) 2370 continue; 2371 2372 /* 2373 * The TLB entry for a PG_G mapping is invalidated 2374 * by pmap_remove_pte(). 2375 */ 2376 if ((*pte & PG_G) == 0) 2377 anyvalid = 1; 2378 if (pmap_remove_pte(pmap, pte, sva, &free)) 2379 break; 2380 } 2381 } 2382 PT_UPDATES_FLUSH(); 2383 if (*PMAP1) 2384 PT_SET_VA_MA(PMAP1, 0, TRUE); 2385out: 2386 if (anyvalid) 2387 pmap_invalidate_all(pmap); 2388 sched_unpin(); 2389 vm_page_unlock_queues(); 2390 PMAP_UNLOCK(pmap); 2391 pmap_free_zero_pages(free); 2392} 2393 2394/* 2395 * Routine: pmap_remove_all 2396 * Function: 2397 * Removes this physical page from 2398 * all physical maps in which it resides. 2399 * Reflects back modify bits to the pager. 2400 * 2401 * Notes: 2402 * Original versions of this routine were very 2403 * inefficient because they iteratively called 2404 * pmap_remove (slow...) 2405 */ 2406 2407void 2408pmap_remove_all(vm_page_t m) 2409{ 2410 pv_entry_t pv; 2411 pmap_t pmap; 2412 pt_entry_t *pte, tpte; 2413 vm_page_t free; 2414 2415 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2416 ("pmap_remove_all: page %p is fictitious", m)); 2417 free = NULL; 2418 vm_page_lock_queues(); 2419 sched_pin(); 2420 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2421 pmap = PV_PMAP(pv); 2422 PMAP_LOCK(pmap); 2423 pmap->pm_stats.resident_count--; 2424 pte = pmap_pte_quick(pmap, pv->pv_va); 2425 2426 tpte = *pte; 2427 PT_SET_VA_MA(pte, 0, TRUE); 2428 if (tpte & PG_W) 2429 pmap->pm_stats.wired_count--; 2430 if (tpte & PG_A) 2431 vm_page_flag_set(m, PG_REFERENCED); 2432 2433 /* 2434 * Update the vm_page_t clean and reference bits. 2435 */ 2436 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2437 vm_page_dirty(m); 2438 pmap_unuse_pt(pmap, pv->pv_va, &free); 2439 pmap_invalidate_page(pmap, pv->pv_va); 2440 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2441 free_pv_entry(pmap, pv); 2442 PMAP_UNLOCK(pmap); 2443 } 2444 vm_page_flag_clear(m, PG_WRITEABLE); 2445 PT_UPDATES_FLUSH(); 2446 if (*PMAP1) 2447 PT_SET_MA(PADDR1, 0); 2448 sched_unpin(); 2449 vm_page_unlock_queues(); 2450 pmap_free_zero_pages(free); 2451} 2452 2453/* 2454 * Set the physical protection on the 2455 * specified range of this map as requested. 2456 */ 2457void 2458pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2459{ 2460 vm_offset_t pdnxt; 2461 pd_entry_t ptpaddr; 2462 pt_entry_t *pte; 2463 int anychanged; 2464 2465 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2466 pmap, sva, eva, prot); 2467 2468 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2469 pmap_remove(pmap, sva, eva); 2470 return; 2471 } 2472 2473#ifdef PAE 2474 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2475 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2476 return; 2477#else 2478 if (prot & VM_PROT_WRITE) 2479 return; 2480#endif 2481 2482 anychanged = 0; 2483 2484 vm_page_lock_queues(); 2485 sched_pin(); 2486 PMAP_LOCK(pmap); 2487 for (; sva < eva; sva = pdnxt) { 2488 pt_entry_t obits, pbits; 2489 unsigned pdirindex; 2490 2491 pdnxt = (sva + NBPDR) & ~PDRMASK; 2492 2493 pdirindex = sva >> PDRSHIFT; 2494 ptpaddr = pmap->pm_pdir[pdirindex]; 2495 2496 /* 2497 * Weed out invalid mappings. Note: we assume that the page 2498 * directory table is always allocated, and in kernel virtual. 2499 */ 2500 if (ptpaddr == 0) 2501 continue; 2502 2503 /* 2504 * Check for large page. 2505 */ 2506 if ((ptpaddr & PG_PS) != 0) { 2507 if ((prot & VM_PROT_WRITE) == 0) 2508 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2509#ifdef PAE 2510 if ((prot & VM_PROT_EXECUTE) == 0) 2511 pmap->pm_pdir[pdirindex] |= pg_nx; 2512#endif 2513 anychanged = 1; 2514 continue; 2515 } 2516 2517 if (pdnxt > eva) 2518 pdnxt = eva; 2519 2520 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2521 sva += PAGE_SIZE) { 2522 vm_page_t m; 2523 2524retry: 2525 /* 2526 * Regardless of whether a pte is 32 or 64 bits in 2527 * size, PG_RW, PG_A, and PG_M are among the least 2528 * significant 32 bits. 2529 */ 2530 obits = pbits = *pte; 2531 if ((pbits & PG_V) == 0) 2532 continue; 2533 2534 if ((prot & VM_PROT_WRITE) == 0) { 2535 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2536 (PG_MANAGED | PG_M | PG_RW)) { 2537 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2538 PG_FRAME); 2539 vm_page_dirty(m); 2540 } 2541 pbits &= ~(PG_RW | PG_M); 2542 } 2543#ifdef PAE 2544 if ((prot & VM_PROT_EXECUTE) == 0) 2545 pbits |= pg_nx; 2546#endif 2547 2548 if (pbits != obits) { 2549 obits = *pte; 2550 PT_SET_VA_MA(pte, pbits, TRUE); 2551 if (*pte != pbits) 2552 goto retry; 2553 if (obits & PG_G) 2554 pmap_invalidate_page(pmap, sva); 2555 else 2556 anychanged = 1; 2557 } 2558 } 2559 } 2560 PT_UPDATES_FLUSH(); 2561 if (*PMAP1) 2562 PT_SET_VA_MA(PMAP1, 0, TRUE); 2563 if (anychanged) 2564 pmap_invalidate_all(pmap); 2565 sched_unpin(); 2566 vm_page_unlock_queues(); 2567 PMAP_UNLOCK(pmap); 2568} 2569 2570/* 2571 * Insert the given physical page (p) at 2572 * the specified virtual address (v) in the 2573 * target physical map with the protection requested. 2574 * 2575 * If specified, the page will be wired down, meaning 2576 * that the related pte can not be reclaimed. 2577 * 2578 * NB: This is the only routine which MAY NOT lazy-evaluate 2579 * or lose information. That is, this routine must actually 2580 * insert this page into the given map NOW. 2581 */ 2582void 2583pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2584 vm_prot_t prot, boolean_t wired) 2585{ 2586 pd_entry_t *pde; 2587 pt_entry_t *pte; 2588 pt_entry_t newpte, origpte; 2589 pv_entry_t pv; 2590 vm_paddr_t opa, pa; 2591 vm_page_t mpte, om; 2592 boolean_t invlva; 2593 2594 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2595 pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2596 va = trunc_page(va); 2597 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2598 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2599 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2600 va)); 2601 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 2602 (m->oflags & VPO_BUSY) != 0, 2603 ("pmap_enter: page %p is not busy", m)); 2604 2605 mpte = NULL; 2606 2607 vm_page_lock_queues(); 2608 PMAP_LOCK(pmap); 2609 sched_pin(); 2610 2611 /* 2612 * In the case that a page table page is not 2613 * resident, we are creating it here. 2614 */ 2615 if (va < VM_MAXUSER_ADDRESS) { 2616 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2617 } 2618 2619 pde = pmap_pde(pmap, va); 2620 if ((*pde & PG_PS) != 0) 2621 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2622 pte = pmap_pte_quick(pmap, va); 2623 2624 /* 2625 * Page Directory table entry not valid, we need a new PT page 2626 */ 2627 if (pte == NULL) { 2628 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2629 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2630 } 2631 2632 pa = VM_PAGE_TO_PHYS(m); 2633 om = NULL; 2634 opa = origpte = 0; 2635 2636#if 0 2637 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2638 pte, *pte)); 2639#endif 2640 origpte = *pte; 2641 if (origpte) 2642 origpte = xpmap_mtop(origpte); 2643 opa = origpte & PG_FRAME; 2644 2645 /* 2646 * Mapping has not changed, must be protection or wiring change. 2647 */ 2648 if (origpte && (opa == pa)) { 2649 /* 2650 * Wiring change, just update stats. We don't worry about 2651 * wiring PT pages as they remain resident as long as there 2652 * are valid mappings in them. Hence, if a user page is wired, 2653 * the PT page will be also. 2654 */ 2655 if (wired && ((origpte & PG_W) == 0)) 2656 pmap->pm_stats.wired_count++; 2657 else if (!wired && (origpte & PG_W)) 2658 pmap->pm_stats.wired_count--; 2659 2660 /* 2661 * Remove extra pte reference 2662 */ 2663 if (mpte) 2664 mpte->wire_count--; 2665 2666 if (origpte & PG_MANAGED) { 2667 om = m; 2668 pa |= PG_MANAGED; 2669 } 2670 goto validate; 2671 } 2672 2673 pv = NULL; 2674 2675 /* 2676 * Mapping has changed, invalidate old range and fall through to 2677 * handle validating new mapping. 2678 */ 2679 if (opa) { 2680 if (origpte & PG_W) 2681 pmap->pm_stats.wired_count--; 2682 if (origpte & PG_MANAGED) { 2683 om = PHYS_TO_VM_PAGE(opa); 2684 pv = pmap_pvh_remove(&om->md, pmap, va); 2685 } else if (va < VM_MAXUSER_ADDRESS) 2686 printf("va=0x%x is unmanaged :-( \n", va); 2687 2688 if (mpte != NULL) { 2689 mpte->wire_count--; 2690 KASSERT(mpte->wire_count > 0, 2691 ("pmap_enter: missing reference to page table page," 2692 " va: 0x%x", va)); 2693 } 2694 } else 2695 pmap->pm_stats.resident_count++; 2696 2697 /* 2698 * Enter on the PV list if part of our managed memory. 2699 */ 2700 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 2701 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2702 ("pmap_enter: managed mapping within the clean submap")); 2703 if (pv == NULL) 2704 pv = get_pv_entry(pmap, FALSE); 2705 pv->pv_va = va; 2706 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2707 pa |= PG_MANAGED; 2708 } else if (pv != NULL) 2709 free_pv_entry(pmap, pv); 2710 2711 /* 2712 * Increment counters 2713 */ 2714 if (wired) 2715 pmap->pm_stats.wired_count++; 2716 2717validate: 2718 /* 2719 * Now validate mapping with desired protection/wiring. 2720 */ 2721 newpte = (pt_entry_t)(pa | PG_V); 2722 if ((prot & VM_PROT_WRITE) != 0) { 2723 newpte |= PG_RW; 2724 if ((newpte & PG_MANAGED) != 0) 2725 vm_page_flag_set(m, PG_WRITEABLE); 2726 } 2727#ifdef PAE 2728 if ((prot & VM_PROT_EXECUTE) == 0) 2729 newpte |= pg_nx; 2730#endif 2731 if (wired) 2732 newpte |= PG_W; 2733 if (va < VM_MAXUSER_ADDRESS) 2734 newpte |= PG_U; 2735 if (pmap == kernel_pmap) 2736 newpte |= pgeflag; 2737 2738 critical_enter(); 2739 /* 2740 * if the mapping or permission bits are different, we need 2741 * to update the pte. 2742 */ 2743 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2744 if (origpte) { 2745 invlva = FALSE; 2746 origpte = *pte; 2747 PT_SET_VA(pte, newpte | PG_A, FALSE); 2748 if (origpte & PG_A) { 2749 if (origpte & PG_MANAGED) 2750 vm_page_flag_set(om, PG_REFERENCED); 2751 if (opa != VM_PAGE_TO_PHYS(m)) 2752 invlva = TRUE; 2753#ifdef PAE 2754 if ((origpte & PG_NX) == 0 && 2755 (newpte & PG_NX) != 0) 2756 invlva = TRUE; 2757#endif 2758 } 2759 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2760 if ((origpte & PG_MANAGED) != 0) 2761 vm_page_dirty(om); 2762 if ((prot & VM_PROT_WRITE) == 0) 2763 invlva = TRUE; 2764 } 2765 if ((origpte & PG_MANAGED) != 0 && 2766 TAILQ_EMPTY(&om->md.pv_list)) 2767 vm_page_flag_clear(om, PG_WRITEABLE); 2768 if (invlva) 2769 pmap_invalidate_page(pmap, va); 2770 } else{ 2771 PT_SET_VA(pte, newpte | PG_A, FALSE); 2772 } 2773 2774 } 2775 PT_UPDATES_FLUSH(); 2776 critical_exit(); 2777 if (*PMAP1) 2778 PT_SET_VA_MA(PMAP1, 0, TRUE); 2779 sched_unpin(); 2780 vm_page_unlock_queues(); 2781 PMAP_UNLOCK(pmap); 2782} 2783 2784/* 2785 * Maps a sequence of resident pages belonging to the same object. 2786 * The sequence begins with the given page m_start. This page is 2787 * mapped at the given virtual address start. Each subsequent page is 2788 * mapped at a virtual address that is offset from start by the same 2789 * amount as the page is offset from m_start within the object. The 2790 * last page in the sequence is the page with the largest offset from 2791 * m_start that can be mapped at a virtual address less than the given 2792 * virtual address end. Not every virtual page between start and end 2793 * is mapped; only those for which a resident page exists with the 2794 * corresponding offset from m_start are mapped. 2795 */ 2796void 2797pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2798 vm_page_t m_start, vm_prot_t prot) 2799{ 2800 vm_page_t m, mpte; 2801 vm_pindex_t diff, psize; 2802 multicall_entry_t mcl[16]; 2803 multicall_entry_t *mclp = mcl; 2804 int error, count = 0; 2805 2806 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2807 psize = atop(end - start); 2808 2809 mpte = NULL; 2810 m = m_start; 2811 vm_page_lock_queues(); 2812 PMAP_LOCK(pmap); 2813 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2814 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2815 prot, mpte); 2816 m = TAILQ_NEXT(m, listq); 2817 if (count == 16) { 2818 error = HYPERVISOR_multicall(mcl, count); 2819 KASSERT(error == 0, ("bad multicall %d", error)); 2820 mclp = mcl; 2821 count = 0; 2822 } 2823 } 2824 if (count) { 2825 error = HYPERVISOR_multicall(mcl, count); 2826 KASSERT(error == 0, ("bad multicall %d", error)); 2827 } 2828 vm_page_unlock_queues(); 2829 PMAP_UNLOCK(pmap); 2830} 2831 2832/* 2833 * this code makes some *MAJOR* assumptions: 2834 * 1. Current pmap & pmap exists. 2835 * 2. Not wired. 2836 * 3. Read access. 2837 * 4. No page table pages. 2838 * but is *MUCH* faster than pmap_enter... 2839 */ 2840 2841void 2842pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2843{ 2844 multicall_entry_t mcl, *mclp; 2845 int count = 0; 2846 mclp = &mcl; 2847 2848 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2849 pmap, va, m, prot); 2850 2851 vm_page_lock_queues(); 2852 PMAP_LOCK(pmap); 2853 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2854 if (count) 2855 HYPERVISOR_multicall(&mcl, count); 2856 vm_page_unlock_queues(); 2857 PMAP_UNLOCK(pmap); 2858} 2859 2860#ifdef notyet 2861void 2862pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2863{ 2864 int i, error, index = 0; 2865 multicall_entry_t mcl[16]; 2866 multicall_entry_t *mclp = mcl; 2867 2868 PMAP_LOCK(pmap); 2869 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2870 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2871 continue; 2872 2873 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2874 if (index == 16) { 2875 error = HYPERVISOR_multicall(mcl, index); 2876 mclp = mcl; 2877 index = 0; 2878 KASSERT(error == 0, ("bad multicall %d", error)); 2879 } 2880 } 2881 if (index) { 2882 error = HYPERVISOR_multicall(mcl, index); 2883 KASSERT(error == 0, ("bad multicall %d", error)); 2884 } 2885 2886 PMAP_UNLOCK(pmap); 2887} 2888#endif 2889 2890static vm_page_t 2891pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2892 vm_prot_t prot, vm_page_t mpte) 2893{ 2894 pt_entry_t *pte; 2895 vm_paddr_t pa; 2896 vm_page_t free; 2897 multicall_entry_t *mcl = *mclpp; 2898 2899 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2900 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 2901 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2902 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2903 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2904 2905 /* 2906 * In the case that a page table page is not 2907 * resident, we are creating it here. 2908 */ 2909 if (va < VM_MAXUSER_ADDRESS) { 2910 unsigned ptepindex; 2911 pd_entry_t ptema; 2912 2913 /* 2914 * Calculate pagetable page index 2915 */ 2916 ptepindex = va >> PDRSHIFT; 2917 if (mpte && (mpte->pindex == ptepindex)) { 2918 mpte->wire_count++; 2919 } else { 2920 /* 2921 * Get the page directory entry 2922 */ 2923 ptema = pmap->pm_pdir[ptepindex]; 2924 2925 /* 2926 * If the page table page is mapped, we just increment 2927 * the hold count, and activate it. 2928 */ 2929 if (ptema & PG_V) { 2930 if (ptema & PG_PS) 2931 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2932 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2933 mpte->wire_count++; 2934 } else { 2935 mpte = _pmap_allocpte(pmap, ptepindex, 2936 M_NOWAIT); 2937 if (mpte == NULL) 2938 return (mpte); 2939 } 2940 } 2941 } else { 2942 mpte = NULL; 2943 } 2944 2945 /* 2946 * This call to vtopte makes the assumption that we are 2947 * entering the page into the current pmap. In order to support 2948 * quick entry into any pmap, one would likely use pmap_pte_quick. 2949 * But that isn't as quick as vtopte. 2950 */ 2951 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 2952 pte = vtopte(va); 2953 if (*pte & PG_V) { 2954 if (mpte != NULL) { 2955 mpte->wire_count--; 2956 mpte = NULL; 2957 } 2958 return (mpte); 2959 } 2960 2961 /* 2962 * Enter on the PV list if part of our managed memory. 2963 */ 2964 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 2965 !pmap_try_insert_pv_entry(pmap, va, m)) { 2966 if (mpte != NULL) { 2967 free = NULL; 2968 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 2969 pmap_invalidate_page(pmap, va); 2970 pmap_free_zero_pages(free); 2971 } 2972 2973 mpte = NULL; 2974 } 2975 return (mpte); 2976 } 2977 2978 /* 2979 * Increment counters 2980 */ 2981 pmap->pm_stats.resident_count++; 2982 2983 pa = VM_PAGE_TO_PHYS(m); 2984#ifdef PAE 2985 if ((prot & VM_PROT_EXECUTE) == 0) 2986 pa |= pg_nx; 2987#endif 2988 2989#if 0 2990 /* 2991 * Now validate mapping with RO protection 2992 */ 2993 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 2994 pte_store(pte, pa | PG_V | PG_U); 2995 else 2996 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 2997#else 2998 /* 2999 * Now validate mapping with RO protection 3000 */ 3001 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3002 pa = xpmap_ptom(pa | PG_V | PG_U); 3003 else 3004 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3005 3006 mcl->op = __HYPERVISOR_update_va_mapping; 3007 mcl->args[0] = va; 3008 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3009 mcl->args[2] = (uint32_t)(pa >> 32); 3010 mcl->args[3] = 0; 3011 *mclpp = mcl + 1; 3012 *count = *count + 1; 3013#endif 3014 return mpte; 3015} 3016 3017/* 3018 * Make a temporary mapping for a physical address. This is only intended 3019 * to be used for panic dumps. 3020 */ 3021void * 3022pmap_kenter_temporary(vm_paddr_t pa, int i) 3023{ 3024 vm_offset_t va; 3025 vm_paddr_t ma = xpmap_ptom(pa); 3026 3027 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3028 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3029 invlpg(va); 3030 return ((void *)crashdumpmap); 3031} 3032 3033/* 3034 * This code maps large physical mmap regions into the 3035 * processor address space. Note that some shortcuts 3036 * are taken, but the code works. 3037 */ 3038void 3039pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 3040 vm_object_t object, vm_pindex_t pindex, 3041 vm_size_t size) 3042{ 3043 pd_entry_t *pde; 3044 vm_paddr_t pa, ptepa; 3045 vm_page_t p; 3046 int pat_mode; 3047 3048 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3049 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3050 ("pmap_object_init_pt: non-device object")); 3051 if (pseflag && 3052 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3053 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3054 return; 3055 p = vm_page_lookup(object, pindex); 3056 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3057 ("pmap_object_init_pt: invalid page %p", p)); 3058 pat_mode = p->md.pat_mode; 3059 /* 3060 * Abort the mapping if the first page is not physically 3061 * aligned to a 2/4MB page boundary. 3062 */ 3063 ptepa = VM_PAGE_TO_PHYS(p); 3064 if (ptepa & (NBPDR - 1)) 3065 return; 3066 /* 3067 * Skip the first page. Abort the mapping if the rest of 3068 * the pages are not physically contiguous or have differing 3069 * memory attributes. 3070 */ 3071 p = TAILQ_NEXT(p, listq); 3072 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3073 pa += PAGE_SIZE) { 3074 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3075 ("pmap_object_init_pt: invalid page %p", p)); 3076 if (pa != VM_PAGE_TO_PHYS(p) || 3077 pat_mode != p->md.pat_mode) 3078 return; 3079 p = TAILQ_NEXT(p, listq); 3080 } 3081 /* Map using 2/4MB pages. */ 3082 PMAP_LOCK(pmap); 3083 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3084 size; pa += NBPDR) { 3085 pde = pmap_pde(pmap, addr); 3086 if (*pde == 0) { 3087 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3088 PG_U | PG_RW | PG_V); 3089 pmap->pm_stats.resident_count += NBPDR / 3090 PAGE_SIZE; 3091 pmap_pde_mappings++; 3092 } 3093 /* Else continue on if the PDE is already valid. */ 3094 addr += NBPDR; 3095 } 3096 PMAP_UNLOCK(pmap); 3097 } 3098} 3099 3100/* 3101 * Routine: pmap_change_wiring 3102 * Function: Change the wiring attribute for a map/virtual-address 3103 * pair. 3104 * In/out conditions: 3105 * The mapping must already exist in the pmap. 3106 */ 3107void 3108pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3109{ 3110 pt_entry_t *pte; 3111 3112 vm_page_lock_queues(); 3113 PMAP_LOCK(pmap); 3114 pte = pmap_pte(pmap, va); 3115 3116 if (wired && !pmap_pte_w(pte)) { 3117 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3118 pmap->pm_stats.wired_count++; 3119 } else if (!wired && pmap_pte_w(pte)) { 3120 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3121 pmap->pm_stats.wired_count--; 3122 } 3123 3124 /* 3125 * Wiring is not a hardware characteristic so there is no need to 3126 * invalidate TLB. 3127 */ 3128 pmap_pte_release(pte); 3129 PMAP_UNLOCK(pmap); 3130 vm_page_unlock_queues(); 3131} 3132 3133 3134 3135/* 3136 * Copy the range specified by src_addr/len 3137 * from the source map to the range dst_addr/len 3138 * in the destination map. 3139 * 3140 * This routine is only advisory and need not do anything. 3141 */ 3142 3143void 3144pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3145 vm_offset_t src_addr) 3146{ 3147 vm_page_t free; 3148 vm_offset_t addr; 3149 vm_offset_t end_addr = src_addr + len; 3150 vm_offset_t pdnxt; 3151 3152 if (dst_addr != src_addr) 3153 return; 3154 3155 if (!pmap_is_current(src_pmap)) { 3156 CTR2(KTR_PMAP, 3157 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3158 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3159 3160 return; 3161 } 3162 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3163 dst_pmap, src_pmap, dst_addr, len, src_addr); 3164 3165#ifdef HAMFISTED_LOCKING 3166 mtx_lock(&createdelete_lock); 3167#endif 3168 3169 vm_page_lock_queues(); 3170 if (dst_pmap < src_pmap) { 3171 PMAP_LOCK(dst_pmap); 3172 PMAP_LOCK(src_pmap); 3173 } else { 3174 PMAP_LOCK(src_pmap); 3175 PMAP_LOCK(dst_pmap); 3176 } 3177 sched_pin(); 3178 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3179 pt_entry_t *src_pte, *dst_pte; 3180 vm_page_t dstmpte, srcmpte; 3181 pd_entry_t srcptepaddr; 3182 unsigned ptepindex; 3183 3184 KASSERT(addr < UPT_MIN_ADDRESS, 3185 ("pmap_copy: invalid to pmap_copy page tables")); 3186 3187 pdnxt = (addr + NBPDR) & ~PDRMASK; 3188 ptepindex = addr >> PDRSHIFT; 3189 3190 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3191 if (srcptepaddr == 0) 3192 continue; 3193 3194 if (srcptepaddr & PG_PS) { 3195 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3196 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3197 dst_pmap->pm_stats.resident_count += 3198 NBPDR / PAGE_SIZE; 3199 } 3200 continue; 3201 } 3202 3203 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3204 KASSERT(srcmpte->wire_count > 0, 3205 ("pmap_copy: source page table page is unused")); 3206 3207 if (pdnxt > end_addr) 3208 pdnxt = end_addr; 3209 3210 src_pte = vtopte(addr); 3211 while (addr < pdnxt) { 3212 pt_entry_t ptetemp; 3213 ptetemp = *src_pte; 3214 /* 3215 * we only virtual copy managed pages 3216 */ 3217 if ((ptetemp & PG_MANAGED) != 0) { 3218 dstmpte = pmap_allocpte(dst_pmap, addr, 3219 M_NOWAIT); 3220 if (dstmpte == NULL) 3221 break; 3222 dst_pte = pmap_pte_quick(dst_pmap, addr); 3223 if (*dst_pte == 0 && 3224 pmap_try_insert_pv_entry(dst_pmap, addr, 3225 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3226 /* 3227 * Clear the wired, modified, and 3228 * accessed (referenced) bits 3229 * during the copy. 3230 */ 3231 KASSERT(ptetemp != 0, ("src_pte not set")); 3232 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3233 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3234 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3235 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3236 dst_pmap->pm_stats.resident_count++; 3237 } else { 3238 free = NULL; 3239 if (pmap_unwire_pte_hold(dst_pmap, 3240 dstmpte, &free)) { 3241 pmap_invalidate_page(dst_pmap, 3242 addr); 3243 pmap_free_zero_pages(free); 3244 } 3245 } 3246 if (dstmpte->wire_count >= srcmpte->wire_count) 3247 break; 3248 } 3249 addr += PAGE_SIZE; 3250 src_pte++; 3251 } 3252 } 3253 PT_UPDATES_FLUSH(); 3254 sched_unpin(); 3255 vm_page_unlock_queues(); 3256 PMAP_UNLOCK(src_pmap); 3257 PMAP_UNLOCK(dst_pmap); 3258 3259#ifdef HAMFISTED_LOCKING 3260 mtx_unlock(&createdelete_lock); 3261#endif 3262} 3263 3264static __inline void 3265pagezero(void *page) 3266{ 3267#if defined(I686_CPU) 3268 if (cpu_class == CPUCLASS_686) { 3269#if defined(CPU_ENABLE_SSE) 3270 if (cpu_feature & CPUID_SSE2) 3271 sse2_pagezero(page); 3272 else 3273#endif 3274 i686_pagezero(page); 3275 } else 3276#endif 3277 bzero(page, PAGE_SIZE); 3278} 3279 3280/* 3281 * pmap_zero_page zeros the specified hardware page by mapping 3282 * the page into KVM and using bzero to clear its contents. 3283 */ 3284void 3285pmap_zero_page(vm_page_t m) 3286{ 3287 struct sysmaps *sysmaps; 3288 3289 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3290 mtx_lock(&sysmaps->lock); 3291 if (*sysmaps->CMAP2) 3292 panic("pmap_zero_page: CMAP2 busy"); 3293 sched_pin(); 3294 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3295 pagezero(sysmaps->CADDR2); 3296 PT_SET_MA(sysmaps->CADDR2, 0); 3297 sched_unpin(); 3298 mtx_unlock(&sysmaps->lock); 3299} 3300 3301/* 3302 * pmap_zero_page_area zeros the specified hardware page by mapping 3303 * the page into KVM and using bzero to clear its contents. 3304 * 3305 * off and size may not cover an area beyond a single hardware page. 3306 */ 3307void 3308pmap_zero_page_area(vm_page_t m, int off, int size) 3309{ 3310 struct sysmaps *sysmaps; 3311 3312 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3313 mtx_lock(&sysmaps->lock); 3314 if (*sysmaps->CMAP2) 3315 panic("pmap_zero_page: CMAP2 busy"); 3316 sched_pin(); 3317 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3318 3319 if (off == 0 && size == PAGE_SIZE) 3320 pagezero(sysmaps->CADDR2); 3321 else 3322 bzero((char *)sysmaps->CADDR2 + off, size); 3323 PT_SET_MA(sysmaps->CADDR2, 0); 3324 sched_unpin(); 3325 mtx_unlock(&sysmaps->lock); 3326} 3327 3328/* 3329 * pmap_zero_page_idle zeros the specified hardware page by mapping 3330 * the page into KVM and using bzero to clear its contents. This 3331 * is intended to be called from the vm_pagezero process only and 3332 * outside of Giant. 3333 */ 3334void 3335pmap_zero_page_idle(vm_page_t m) 3336{ 3337 3338 if (*CMAP3) 3339 panic("pmap_zero_page: CMAP3 busy"); 3340 sched_pin(); 3341 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3342 pagezero(CADDR3); 3343 PT_SET_MA(CADDR3, 0); 3344 sched_unpin(); 3345} 3346 3347/* 3348 * pmap_copy_page copies the specified (machine independent) 3349 * page by mapping the page into virtual memory and using 3350 * bcopy to copy the page, one machine dependent page at a 3351 * time. 3352 */ 3353void 3354pmap_copy_page(vm_page_t src, vm_page_t dst) 3355{ 3356 struct sysmaps *sysmaps; 3357 3358 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3359 mtx_lock(&sysmaps->lock); 3360 if (*sysmaps->CMAP1) 3361 panic("pmap_copy_page: CMAP1 busy"); 3362 if (*sysmaps->CMAP2) 3363 panic("pmap_copy_page: CMAP2 busy"); 3364 sched_pin(); 3365 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3366 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3367 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3368 PT_SET_MA(sysmaps->CADDR1, 0); 3369 PT_SET_MA(sysmaps->CADDR2, 0); 3370 sched_unpin(); 3371 mtx_unlock(&sysmaps->lock); 3372} 3373 3374/* 3375 * Returns true if the pmap's pv is one of the first 3376 * 16 pvs linked to from this page. This count may 3377 * be changed upwards or downwards in the future; it 3378 * is only necessary that true be returned for a small 3379 * subset of pmaps for proper page aging. 3380 */ 3381boolean_t 3382pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3383{ 3384 pv_entry_t pv; 3385 int loops = 0; 3386 boolean_t rv; 3387 3388 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3389 ("pmap_page_exists_quick: page %p is not managed", m)); 3390 rv = FALSE; 3391 vm_page_lock_queues(); 3392 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3393 if (PV_PMAP(pv) == pmap) { 3394 rv = TRUE; 3395 break; 3396 } 3397 loops++; 3398 if (loops >= 16) 3399 break; 3400 } 3401 vm_page_unlock_queues(); 3402 return (rv); 3403} 3404 3405/* 3406 * pmap_page_wired_mappings: 3407 * 3408 * Return the number of managed mappings to the given physical page 3409 * that are wired. 3410 */ 3411int 3412pmap_page_wired_mappings(vm_page_t m) 3413{ 3414 pv_entry_t pv; 3415 pt_entry_t *pte; 3416 pmap_t pmap; 3417 int count; 3418 3419 count = 0; 3420 if ((m->flags & PG_FICTITIOUS) != 0) 3421 return (count); 3422 vm_page_lock_queues(); 3423 sched_pin(); 3424 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3425 pmap = PV_PMAP(pv); 3426 PMAP_LOCK(pmap); 3427 pte = pmap_pte_quick(pmap, pv->pv_va); 3428 if ((*pte & PG_W) != 0) 3429 count++; 3430 PMAP_UNLOCK(pmap); 3431 } 3432 sched_unpin(); 3433 vm_page_unlock_queues(); 3434 return (count); 3435} 3436 3437/* 3438 * Returns TRUE if the given page is mapped individually or as part of 3439 * a 4mpage. Otherwise, returns FALSE. 3440 */ 3441boolean_t 3442pmap_page_is_mapped(vm_page_t m) 3443{ 3444 boolean_t rv; 3445 3446 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 3447 return (FALSE); 3448 vm_page_lock_queues(); 3449 rv = !TAILQ_EMPTY(&m->md.pv_list) || 3450 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list); 3451 vm_page_unlock_queues(); 3452 return (rv); 3453} 3454 3455/* 3456 * Remove all pages from specified address space 3457 * this aids process exit speeds. Also, this code 3458 * is special cased for current process only, but 3459 * can have the more generic (and slightly slower) 3460 * mode enabled. This is much faster than pmap_remove 3461 * in the case of running down an entire address space. 3462 */ 3463void 3464pmap_remove_pages(pmap_t pmap) 3465{ 3466 pt_entry_t *pte, tpte; 3467 vm_page_t m, free = NULL; 3468 pv_entry_t pv; 3469 struct pv_chunk *pc, *npc; 3470 int field, idx; 3471 int32_t bit; 3472 uint32_t inuse, bitmask; 3473 int allfree; 3474 3475 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3476 3477 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3478 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3479 return; 3480 } 3481 vm_page_lock_queues(); 3482 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3483 PMAP_LOCK(pmap); 3484 sched_pin(); 3485 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3486 allfree = 1; 3487 for (field = 0; field < _NPCM; field++) { 3488 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 3489 while (inuse != 0) { 3490 bit = bsfl(inuse); 3491 bitmask = 1UL << bit; 3492 idx = field * 32 + bit; 3493 pv = &pc->pc_pventry[idx]; 3494 inuse &= ~bitmask; 3495 3496 pte = vtopte(pv->pv_va); 3497 tpte = *pte ? xpmap_mtop(*pte) : 0; 3498 3499 if (tpte == 0) { 3500 printf( 3501 "TPTE at %p IS ZERO @ VA %08x\n", 3502 pte, pv->pv_va); 3503 panic("bad pte"); 3504 } 3505 3506/* 3507 * We cannot remove wired pages from a process' mapping at this time 3508 */ 3509 if (tpte & PG_W) { 3510 allfree = 0; 3511 continue; 3512 } 3513 3514 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3515 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3516 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3517 m, (uintmax_t)m->phys_addr, 3518 (uintmax_t)tpte)); 3519 3520 KASSERT(m < &vm_page_array[vm_page_array_size], 3521 ("pmap_remove_pages: bad tpte %#jx", 3522 (uintmax_t)tpte)); 3523 3524 3525 PT_CLEAR_VA(pte, FALSE); 3526 3527 /* 3528 * Update the vm_page_t clean/reference bits. 3529 */ 3530 if (tpte & PG_M) 3531 vm_page_dirty(m); 3532 3533 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3534 if (TAILQ_EMPTY(&m->md.pv_list)) 3535 vm_page_flag_clear(m, PG_WRITEABLE); 3536 3537 pmap_unuse_pt(pmap, pv->pv_va, &free); 3538 3539 /* Mark free */ 3540 PV_STAT(pv_entry_frees++); 3541 PV_STAT(pv_entry_spare++); 3542 pv_entry_count--; 3543 pc->pc_map[field] |= bitmask; 3544 pmap->pm_stats.resident_count--; 3545 } 3546 } 3547 PT_UPDATES_FLUSH(); 3548 if (allfree) { 3549 PV_STAT(pv_entry_spare -= _NPCPV); 3550 PV_STAT(pc_chunk_count--); 3551 PV_STAT(pc_chunk_frees++); 3552 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3553 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 3554 pmap_qremove((vm_offset_t)pc, 1); 3555 vm_page_unwire(m, 0); 3556 vm_page_free(m); 3557 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 3558 } 3559 } 3560 PT_UPDATES_FLUSH(); 3561 if (*PMAP1) 3562 PT_SET_MA(PADDR1, 0); 3563 3564 sched_unpin(); 3565 pmap_invalidate_all(pmap); 3566 vm_page_unlock_queues(); 3567 PMAP_UNLOCK(pmap); 3568 pmap_free_zero_pages(free); 3569} 3570 3571/* 3572 * pmap_is_modified: 3573 * 3574 * Return whether or not the specified physical page was modified 3575 * in any physical maps. 3576 */ 3577boolean_t 3578pmap_is_modified(vm_page_t m) 3579{ 3580 pv_entry_t pv; 3581 pt_entry_t *pte; 3582 pmap_t pmap; 3583 boolean_t rv; 3584 3585 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3586 ("pmap_is_modified: page %p is not managed", m)); 3587 rv = FALSE; 3588 3589 /* 3590 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 3591 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 3592 * is clear, no PTEs can have PG_M set. 3593 */ 3594 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3595 if ((m->oflags & VPO_BUSY) == 0 && 3596 (m->flags & PG_WRITEABLE) == 0) 3597 return (rv); 3598 vm_page_lock_queues(); 3599 sched_pin(); 3600 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3601 pmap = PV_PMAP(pv); 3602 PMAP_LOCK(pmap); 3603 pte = pmap_pte_quick(pmap, pv->pv_va); 3604 rv = (*pte & PG_M) != 0; 3605 PMAP_UNLOCK(pmap); 3606 if (rv) 3607 break; 3608 } 3609 if (*PMAP1) 3610 PT_SET_MA(PADDR1, 0); 3611 sched_unpin(); 3612 vm_page_unlock_queues(); 3613 return (rv); 3614} 3615 3616/* 3617 * pmap_is_prefaultable: 3618 * 3619 * Return whether or not the specified virtual address is elgible 3620 * for prefault. 3621 */ 3622static boolean_t 3623pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3624{ 3625 pt_entry_t *pte; 3626 boolean_t rv = FALSE; 3627 3628 return (rv); 3629 3630 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3631 pte = vtopte(addr); 3632 rv = (*pte == 0); 3633 } 3634 return (rv); 3635} 3636 3637boolean_t 3638pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3639{ 3640 boolean_t rv; 3641 3642 PMAP_LOCK(pmap); 3643 rv = pmap_is_prefaultable_locked(pmap, addr); 3644 PMAP_UNLOCK(pmap); 3645 return (rv); 3646} 3647 3648boolean_t 3649pmap_is_referenced(vm_page_t m) 3650{ 3651 pv_entry_t pv; 3652 pt_entry_t *pte; 3653 pmap_t pmap; 3654 boolean_t rv; 3655 3656 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3657 ("pmap_is_referenced: page %p is not managed", m)); 3658 rv = FALSE; 3659 vm_page_lock_queues(); 3660 sched_pin(); 3661 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3662 pmap = PV_PMAP(pv); 3663 PMAP_LOCK(pmap); 3664 pte = pmap_pte_quick(pmap, pv->pv_va); 3665 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3666 PMAP_UNLOCK(pmap); 3667 if (rv) 3668 break; 3669 } 3670 if (*PMAP1) 3671 PT_SET_MA(PADDR1, 0); 3672 sched_unpin(); 3673 vm_page_unlock_queues(); 3674 return (rv); 3675} 3676 3677void 3678pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3679{ 3680 int i, npages = round_page(len) >> PAGE_SHIFT; 3681 for (i = 0; i < npages; i++) { 3682 pt_entry_t *pte; 3683 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3684 vm_page_lock_queues(); 3685 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3686 vm_page_unlock_queues(); 3687 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3688 pmap_pte_release(pte); 3689 } 3690} 3691 3692void 3693pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3694{ 3695 int i, npages = round_page(len) >> PAGE_SHIFT; 3696 for (i = 0; i < npages; i++) { 3697 pt_entry_t *pte; 3698 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3699 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3700 vm_page_lock_queues(); 3701 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3702 vm_page_unlock_queues(); 3703 pmap_pte_release(pte); 3704 } 3705} 3706 3707/* 3708 * Clear the write and modified bits in each of the given page's mappings. 3709 */ 3710void 3711pmap_remove_write(vm_page_t m) 3712{ 3713 pv_entry_t pv; 3714 pmap_t pmap; 3715 pt_entry_t oldpte, *pte; 3716 3717 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3718 ("pmap_remove_write: page %p is not managed", m)); 3719 3720 /* 3721 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 3722 * another thread while the object is locked. Thus, if PG_WRITEABLE 3723 * is clear, no page table entries need updating. 3724 */ 3725 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3726 if ((m->oflags & VPO_BUSY) == 0 && 3727 (m->flags & PG_WRITEABLE) == 0) 3728 return; 3729 vm_page_lock_queues(); 3730 sched_pin(); 3731 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3732 pmap = PV_PMAP(pv); 3733 PMAP_LOCK(pmap); 3734 pte = pmap_pte_quick(pmap, pv->pv_va); 3735retry: 3736 oldpte = *pte; 3737 if ((oldpte & PG_RW) != 0) { 3738 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3739 3740 /* 3741 * Regardless of whether a pte is 32 or 64 bits 3742 * in size, PG_RW and PG_M are among the least 3743 * significant 32 bits. 3744 */ 3745 PT_SET_VA_MA(pte, newpte, TRUE); 3746 if (*pte != newpte) 3747 goto retry; 3748 3749 if ((oldpte & PG_M) != 0) 3750 vm_page_dirty(m); 3751 pmap_invalidate_page(pmap, pv->pv_va); 3752 } 3753 PMAP_UNLOCK(pmap); 3754 } 3755 vm_page_flag_clear(m, PG_WRITEABLE); 3756 PT_UPDATES_FLUSH(); 3757 if (*PMAP1) 3758 PT_SET_MA(PADDR1, 0); 3759 sched_unpin(); 3760 vm_page_unlock_queues(); 3761} 3762 3763/* 3764 * pmap_ts_referenced: 3765 * 3766 * Return a count of reference bits for a page, clearing those bits. 3767 * It is not necessary for every reference bit to be cleared, but it 3768 * is necessary that 0 only be returned when there are truly no 3769 * reference bits set. 3770 * 3771 * XXX: The exact number of bits to check and clear is a matter that 3772 * should be tested and standardized at some point in the future for 3773 * optimal aging of shared pages. 3774 */ 3775int 3776pmap_ts_referenced(vm_page_t m) 3777{ 3778 pv_entry_t pv, pvf, pvn; 3779 pmap_t pmap; 3780 pt_entry_t *pte; 3781 int rtval = 0; 3782 3783 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3784 ("pmap_ts_referenced: page %p is not managed", m)); 3785 vm_page_lock_queues(); 3786 sched_pin(); 3787 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3788 pvf = pv; 3789 do { 3790 pvn = TAILQ_NEXT(pv, pv_list); 3791 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3792 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3793 pmap = PV_PMAP(pv); 3794 PMAP_LOCK(pmap); 3795 pte = pmap_pte_quick(pmap, pv->pv_va); 3796 if ((*pte & PG_A) != 0) { 3797 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3798 pmap_invalidate_page(pmap, pv->pv_va); 3799 rtval++; 3800 if (rtval > 4) 3801 pvn = NULL; 3802 } 3803 PMAP_UNLOCK(pmap); 3804 } while ((pv = pvn) != NULL && pv != pvf); 3805 } 3806 PT_UPDATES_FLUSH(); 3807 if (*PMAP1) 3808 PT_SET_MA(PADDR1, 0); 3809 3810 sched_unpin(); 3811 vm_page_unlock_queues(); 3812 return (rtval); 3813} 3814 3815/* 3816 * Clear the modify bits on the specified physical page. 3817 */ 3818void 3819pmap_clear_modify(vm_page_t m) 3820{ 3821 pv_entry_t pv; 3822 pmap_t pmap; 3823 pt_entry_t *pte; 3824 3825 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3826 ("pmap_clear_modify: page %p is not managed", m)); 3827 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3828 KASSERT((m->oflags & VPO_BUSY) == 0, 3829 ("pmap_clear_modify: page %p is busy", m)); 3830 3831 /* 3832 * If the page is not PG_WRITEABLE, then no PTEs can have PG_M set. 3833 * If the object containing the page is locked and the page is not 3834 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 3835 */ 3836 if ((m->flags & PG_WRITEABLE) == 0) 3837 return; 3838 vm_page_lock_queues(); 3839 sched_pin(); 3840 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3841 pmap = PV_PMAP(pv); 3842 PMAP_LOCK(pmap); 3843 pte = pmap_pte_quick(pmap, pv->pv_va); 3844 if ((*pte & PG_M) != 0) { 3845 /* 3846 * Regardless of whether a pte is 32 or 64 bits 3847 * in size, PG_M is among the least significant 3848 * 32 bits. 3849 */ 3850 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3851 pmap_invalidate_page(pmap, pv->pv_va); 3852 } 3853 PMAP_UNLOCK(pmap); 3854 } 3855 sched_unpin(); 3856 vm_page_unlock_queues(); 3857} 3858 3859/* 3860 * pmap_clear_reference: 3861 * 3862 * Clear the reference bit on the specified physical page. 3863 */ 3864void 3865pmap_clear_reference(vm_page_t m) 3866{ 3867 pv_entry_t pv; 3868 pmap_t pmap; 3869 pt_entry_t *pte; 3870 3871 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3872 ("pmap_clear_reference: page %p is not managed", m)); 3873 vm_page_lock_queues(); 3874 sched_pin(); 3875 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3876 pmap = PV_PMAP(pv); 3877 PMAP_LOCK(pmap); 3878 pte = pmap_pte_quick(pmap, pv->pv_va); 3879 if ((*pte & PG_A) != 0) { 3880 /* 3881 * Regardless of whether a pte is 32 or 64 bits 3882 * in size, PG_A is among the least significant 3883 * 32 bits. 3884 */ 3885 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3886 pmap_invalidate_page(pmap, pv->pv_va); 3887 } 3888 PMAP_UNLOCK(pmap); 3889 } 3890 sched_unpin(); 3891 vm_page_unlock_queues(); 3892} 3893 3894/* 3895 * Miscellaneous support routines follow 3896 */ 3897 3898/* 3899 * Map a set of physical memory pages into the kernel virtual 3900 * address space. Return a pointer to where it is mapped. This 3901 * routine is intended to be used for mapping device memory, 3902 * NOT real memory. 3903 */ 3904void * 3905pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 3906{ 3907 vm_offset_t va, offset; 3908 vm_size_t tmpsize; 3909 3910 offset = pa & PAGE_MASK; 3911 size = roundup(offset + size, PAGE_SIZE); 3912 pa = pa & PG_FRAME; 3913 3914 if (pa < KERNLOAD && pa + size <= KERNLOAD) 3915 va = KERNBASE + pa; 3916 else 3917 va = kmem_alloc_nofault(kernel_map, size); 3918 if (!va) 3919 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3920 3921 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 3922 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 3923 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 3924 pmap_invalidate_cache_range(va, va + size); 3925 return ((void *)(va + offset)); 3926} 3927 3928void * 3929pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3930{ 3931 3932 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 3933} 3934 3935void * 3936pmap_mapbios(vm_paddr_t pa, vm_size_t size) 3937{ 3938 3939 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 3940} 3941 3942void 3943pmap_unmapdev(vm_offset_t va, vm_size_t size) 3944{ 3945 vm_offset_t base, offset, tmpva; 3946 3947 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 3948 return; 3949 base = trunc_page(va); 3950 offset = va & PAGE_MASK; 3951 size = roundup(offset + size, PAGE_SIZE); 3952 critical_enter(); 3953 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 3954 pmap_kremove(tmpva); 3955 pmap_invalidate_range(kernel_pmap, va, tmpva); 3956 critical_exit(); 3957 kmem_free(kernel_map, base, size); 3958} 3959 3960/* 3961 * Sets the memory attribute for the specified page. 3962 */ 3963void 3964pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 3965{ 3966 struct sysmaps *sysmaps; 3967 vm_offset_t sva, eva; 3968 3969 m->md.pat_mode = ma; 3970 if ((m->flags & PG_FICTITIOUS) != 0) 3971 return; 3972 3973 /* 3974 * If "m" is a normal page, flush it from the cache. 3975 * See pmap_invalidate_cache_range(). 3976 * 3977 * First, try to find an existing mapping of the page by sf 3978 * buffer. sf_buf_invalidate_cache() modifies mapping and 3979 * flushes the cache. 3980 */ 3981 if (sf_buf_invalidate_cache(m)) 3982 return; 3983 3984 /* 3985 * If page is not mapped by sf buffer, but CPU does not 3986 * support self snoop, map the page transient and do 3987 * invalidation. In the worst case, whole cache is flushed by 3988 * pmap_invalidate_cache_range(). 3989 */ 3990 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 3991 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3992 mtx_lock(&sysmaps->lock); 3993 if (*sysmaps->CMAP2) 3994 panic("pmap_page_set_memattr: CMAP2 busy"); 3995 sched_pin(); 3996 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 3997 VM_PAGE_TO_MACH(m) | PG_A | PG_M | 3998 pmap_cache_bits(m->md.pat_mode, 0)); 3999 invlcaddr(sysmaps->CADDR2); 4000 sva = (vm_offset_t)sysmaps->CADDR2; 4001 eva = sva + PAGE_SIZE; 4002 } else 4003 sva = eva = 0; /* gcc */ 4004 pmap_invalidate_cache_range(sva, eva); 4005 if (sva != 0) { 4006 PT_SET_MA(sysmaps->CADDR2, 0); 4007 sched_unpin(); 4008 mtx_unlock(&sysmaps->lock); 4009 } 4010} 4011 4012int 4013pmap_change_attr(va, size, mode) 4014 vm_offset_t va; 4015 vm_size_t size; 4016 int mode; 4017{ 4018 vm_offset_t base, offset, tmpva; 4019 pt_entry_t *pte; 4020 u_int opte, npte; 4021 pd_entry_t *pde; 4022 boolean_t changed; 4023 4024 base = trunc_page(va); 4025 offset = va & PAGE_MASK; 4026 size = roundup(offset + size, PAGE_SIZE); 4027 4028 /* Only supported on kernel virtual addresses. */ 4029 if (base <= VM_MAXUSER_ADDRESS) 4030 return (EINVAL); 4031 4032 /* 4MB pages and pages that aren't mapped aren't supported. */ 4033 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4034 pde = pmap_pde(kernel_pmap, tmpva); 4035 if (*pde & PG_PS) 4036 return (EINVAL); 4037 if ((*pde & PG_V) == 0) 4038 return (EINVAL); 4039 pte = vtopte(va); 4040 if ((*pte & PG_V) == 0) 4041 return (EINVAL); 4042 } 4043 4044 changed = FALSE; 4045 4046 /* 4047 * Ok, all the pages exist and are 4k, so run through them updating 4048 * their cache mode. 4049 */ 4050 for (tmpva = base; size > 0; ) { 4051 pte = vtopte(tmpva); 4052 4053 /* 4054 * The cache mode bits are all in the low 32-bits of the 4055 * PTE, so we can just spin on updating the low 32-bits. 4056 */ 4057 do { 4058 opte = *(u_int *)pte; 4059 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4060 npte |= pmap_cache_bits(mode, 0); 4061 PT_SET_VA_MA(pte, npte, TRUE); 4062 } while (npte != opte && (*pte != npte)); 4063 if (npte != opte) 4064 changed = TRUE; 4065 tmpva += PAGE_SIZE; 4066 size -= PAGE_SIZE; 4067 } 4068 4069 /* 4070 * Flush CPU caches to make sure any data isn't cached that shouldn't 4071 * be, etc. 4072 */ 4073 if (changed) { 4074 pmap_invalidate_range(kernel_pmap, base, tmpva); 4075 pmap_invalidate_cache_range(base, tmpva); 4076 } 4077 return (0); 4078} 4079 4080/* 4081 * perform the pmap work for mincore 4082 */ 4083int 4084pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4085{ 4086 pt_entry_t *ptep, pte; 4087 vm_paddr_t pa; 4088 int val; 4089 4090 PMAP_LOCK(pmap); 4091retry: 4092 ptep = pmap_pte(pmap, addr); 4093 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4094 pmap_pte_release(ptep); 4095 val = 0; 4096 if ((pte & PG_V) != 0) { 4097 val |= MINCORE_INCORE; 4098 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4099 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4100 if ((pte & PG_A) != 0) 4101 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4102 } 4103 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4104 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4105 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4106 pa = pte & PG_FRAME; 4107 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4108 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4109 goto retry; 4110 } else 4111 PA_UNLOCK_COND(*locked_pa); 4112 PMAP_UNLOCK(pmap); 4113 return (val); 4114} 4115 4116void 4117pmap_activate(struct thread *td) 4118{ 4119 pmap_t pmap, oldpmap; 4120 u_int32_t cr3; 4121 4122 critical_enter(); 4123 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4124 oldpmap = PCPU_GET(curpmap); 4125#if defined(SMP) 4126 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 4127 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 4128#else 4129 oldpmap->pm_active &= ~1; 4130 pmap->pm_active |= 1; 4131#endif 4132#ifdef PAE 4133 cr3 = vtophys(pmap->pm_pdpt); 4134#else 4135 cr3 = vtophys(pmap->pm_pdir); 4136#endif 4137 /* 4138 * pmap_activate is for the current thread on the current cpu 4139 */ 4140 td->td_pcb->pcb_cr3 = cr3; 4141 PT_UPDATES_FLUSH(); 4142 load_cr3(cr3); 4143 PCPU_SET(curpmap, pmap); 4144 critical_exit(); 4145} 4146 4147void 4148pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4149{ 4150} 4151 4152/* 4153 * Increase the starting virtual address of the given mapping if a 4154 * different alignment might result in more superpage mappings. 4155 */ 4156void 4157pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4158 vm_offset_t *addr, vm_size_t size) 4159{ 4160 vm_offset_t superpage_offset; 4161 4162 if (size < NBPDR) 4163 return; 4164 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4165 offset += ptoa(object->pg_color); 4166 superpage_offset = offset & PDRMASK; 4167 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4168 (*addr & PDRMASK) == superpage_offset) 4169 return; 4170 if ((*addr & PDRMASK) < superpage_offset) 4171 *addr = (*addr & ~PDRMASK) + superpage_offset; 4172 else 4173 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4174} 4175 4176void 4177pmap_suspend() 4178{ 4179 pmap_t pmap; 4180 int i, pdir, offset; 4181 vm_paddr_t pdirma; 4182 mmu_update_t mu[4]; 4183 4184 /* 4185 * We need to remove the recursive mapping structure from all 4186 * our pmaps so that Xen doesn't get confused when it restores 4187 * the page tables. The recursive map lives at page directory 4188 * index PTDPTDI. We assume that the suspend code has stopped 4189 * the other vcpus (if any). 4190 */ 4191 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4192 for (i = 0; i < 4; i++) { 4193 /* 4194 * Figure out which page directory (L2) page 4195 * contains this bit of the recursive map and 4196 * the offset within that page of the map 4197 * entry 4198 */ 4199 pdir = (PTDPTDI + i) / NPDEPG; 4200 offset = (PTDPTDI + i) % NPDEPG; 4201 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4202 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4203 mu[i].val = 0; 4204 } 4205 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4206 } 4207} 4208 4209void 4210pmap_resume() 4211{ 4212 pmap_t pmap; 4213 int i, pdir, offset; 4214 vm_paddr_t pdirma; 4215 mmu_update_t mu[4]; 4216 4217 /* 4218 * Restore the recursive map that we removed on suspend. 4219 */ 4220 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4221 for (i = 0; i < 4; i++) { 4222 /* 4223 * Figure out which page directory (L2) page 4224 * contains this bit of the recursive map and 4225 * the offset within that page of the map 4226 * entry 4227 */ 4228 pdir = (PTDPTDI + i) / NPDEPG; 4229 offset = (PTDPTDI + i) % NPDEPG; 4230 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4231 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4232 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4233 } 4234 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4235 } 4236} 4237 4238#if defined(PMAP_DEBUG) 4239pmap_pid_dump(int pid) 4240{ 4241 pmap_t pmap; 4242 struct proc *p; 4243 int npte = 0; 4244 int index; 4245 4246 sx_slock(&allproc_lock); 4247 FOREACH_PROC_IN_SYSTEM(p) { 4248 if (p->p_pid != pid) 4249 continue; 4250 4251 if (p->p_vmspace) { 4252 int i,j; 4253 index = 0; 4254 pmap = vmspace_pmap(p->p_vmspace); 4255 for (i = 0; i < NPDEPTD; i++) { 4256 pd_entry_t *pde; 4257 pt_entry_t *pte; 4258 vm_offset_t base = i << PDRSHIFT; 4259 4260 pde = &pmap->pm_pdir[i]; 4261 if (pde && pmap_pde_v(pde)) { 4262 for (j = 0; j < NPTEPG; j++) { 4263 vm_offset_t va = base + (j << PAGE_SHIFT); 4264 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4265 if (index) { 4266 index = 0; 4267 printf("\n"); 4268 } 4269 sx_sunlock(&allproc_lock); 4270 return npte; 4271 } 4272 pte = pmap_pte(pmap, va); 4273 if (pte && pmap_pte_v(pte)) { 4274 pt_entry_t pa; 4275 vm_page_t m; 4276 pa = PT_GET(pte); 4277 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4278 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4279 va, pa, m->hold_count, m->wire_count, m->flags); 4280 npte++; 4281 index++; 4282 if (index >= 2) { 4283 index = 0; 4284 printf("\n"); 4285 } else { 4286 printf(" "); 4287 } 4288 } 4289 } 4290 } 4291 } 4292 } 4293 } 4294 sx_sunlock(&allproc_lock); 4295 return npte; 4296} 4297#endif 4298 4299#if defined(DEBUG) 4300 4301static void pads(pmap_t pm); 4302void pmap_pvdump(vm_paddr_t pa); 4303 4304/* print address space of pmap*/ 4305static void 4306pads(pmap_t pm) 4307{ 4308 int i, j; 4309 vm_paddr_t va; 4310 pt_entry_t *ptep; 4311 4312 if (pm == kernel_pmap) 4313 return; 4314 for (i = 0; i < NPDEPTD; i++) 4315 if (pm->pm_pdir[i]) 4316 for (j = 0; j < NPTEPG; j++) { 4317 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4318 if (pm == kernel_pmap && va < KERNBASE) 4319 continue; 4320 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4321 continue; 4322 ptep = pmap_pte(pm, va); 4323 if (pmap_pte_v(ptep)) 4324 printf("%x:%x ", va, *ptep); 4325 }; 4326 4327} 4328 4329void 4330pmap_pvdump(vm_paddr_t pa) 4331{ 4332 pv_entry_t pv; 4333 pmap_t pmap; 4334 vm_page_t m; 4335 4336 printf("pa %x", pa); 4337 m = PHYS_TO_VM_PAGE(pa); 4338 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4339 pmap = PV_PMAP(pv); 4340 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4341 pads(pmap); 4342 } 4343 printf(" "); 4344} 4345#endif 4346