pmap.c revision 216762
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 216762 2010-12-28 14:36:32Z cperciva $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_msgbuf.h" 109#include "opt_smp.h" 110#include "opt_xbox.h" 111 112#include <sys/param.h> 113#include <sys/systm.h> 114#include <sys/kernel.h> 115#include <sys/ktr.h> 116#include <sys/lock.h> 117#include <sys/malloc.h> 118#include <sys/mman.h> 119#include <sys/msgbuf.h> 120#include <sys/mutex.h> 121#include <sys/proc.h> 122#include <sys/sf_buf.h> 123#include <sys/sx.h> 124#include <sys/vmmeter.h> 125#include <sys/sched.h> 126#include <sys/sysctl.h> 127#ifdef SMP 128#include <sys/smp.h> 129#endif 130 131#include <vm/vm.h> 132#include <vm/vm_param.h> 133#include <vm/vm_kern.h> 134#include <vm/vm_page.h> 135#include <vm/vm_map.h> 136#include <vm/vm_object.h> 137#include <vm/vm_extern.h> 138#include <vm/vm_pageout.h> 139#include <vm/vm_pager.h> 140#include <vm/uma.h> 141 142#include <machine/cpu.h> 143#include <machine/cputypes.h> 144#include <machine/md_var.h> 145#include <machine/pcb.h> 146#include <machine/specialreg.h> 147#ifdef SMP 148#include <machine/smp.h> 149#endif 150 151#ifdef XBOX 152#include <machine/xbox.h> 153#endif 154 155#include <xen/interface/xen.h> 156#include <xen/hypervisor.h> 157#include <machine/xen/hypercall.h> 158#include <machine/xen/xenvar.h> 159#include <machine/xen/xenfunc.h> 160 161#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 162#define CPU_ENABLE_SSE 163#endif 164 165#ifndef PMAP_SHPGPERPROC 166#define PMAP_SHPGPERPROC 200 167#endif 168 169#define DIAGNOSTIC 170 171#if !defined(DIAGNOSTIC) 172#ifdef __GNUC_GNU_INLINE__ 173#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 174#else 175#define PMAP_INLINE extern inline 176#endif 177#else 178#define PMAP_INLINE 179#endif 180 181#define PV_STATS 182#ifdef PV_STATS 183#define PV_STAT(x) do { x ; } while (0) 184#else 185#define PV_STAT(x) do { } while (0) 186#endif 187 188#define pa_index(pa) ((pa) >> PDRSHIFT) 189#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 190 191/* 192 * Get PDEs and PTEs for user/kernel address space 193 */ 194#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 195#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 196 197#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 198#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 199#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 200#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 201#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 202 203#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 204 205struct pmap kernel_pmap_store; 206LIST_HEAD(pmaplist, pmap); 207static struct pmaplist allpmaps; 208static struct mtx allpmaps_lock; 209 210vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 211vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 212int pgeflag = 0; /* PG_G or-in */ 213int pseflag = 0; /* PG_PS or-in */ 214 215int nkpt; 216vm_offset_t kernel_vm_end; 217extern u_int32_t KERNend; 218 219#ifdef PAE 220pt_entry_t pg_nx; 221#endif 222 223static int pat_works; /* Is page attribute table sane? */ 224 225/* 226 * Data for the pv entry allocation mechanism 227 */ 228static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 229static struct md_page *pv_table; 230static int shpgperproc = PMAP_SHPGPERPROC; 231 232struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 233int pv_maxchunks; /* How many chunks we have KVA for */ 234vm_offset_t pv_vafree; /* freelist stored in the PTE */ 235 236/* 237 * All those kernel PT submaps that BSD is so fond of 238 */ 239struct sysmaps { 240 struct mtx lock; 241 pt_entry_t *CMAP1; 242 pt_entry_t *CMAP2; 243 caddr_t CADDR1; 244 caddr_t CADDR2; 245}; 246static struct sysmaps sysmaps_pcpu[MAXCPU]; 247static pt_entry_t *CMAP3; 248caddr_t ptvmmap = 0; 249static caddr_t CADDR3; 250struct msgbuf *msgbufp = 0; 251 252/* 253 * Crashdump maps. 254 */ 255static caddr_t crashdumpmap; 256 257static pt_entry_t *PMAP1 = 0, *PMAP2; 258static pt_entry_t *PADDR1 = 0, *PADDR2; 259#ifdef SMP 260static int PMAP1cpu; 261static int PMAP1changedcpu; 262SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 263 &PMAP1changedcpu, 0, 264 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 265#endif 266static int PMAP1changed; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 268 &PMAP1changed, 0, 269 "Number of times pmap_pte_quick changed PMAP1"); 270static int PMAP1unchanged; 271SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 272 &PMAP1unchanged, 0, 273 "Number of times pmap_pte_quick didn't change PMAP1"); 274static struct mtx PMAP2mutex; 275 276SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 277static int pg_ps_enabled; 278SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 279 "Are large page mappings enabled?"); 280 281SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 282 "Max number of PV entries"); 283SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 284 "Page share factor per proc"); 285SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 286 "2/4MB page mapping counters"); 287 288static u_long pmap_pde_mappings; 289SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 290 &pmap_pde_mappings, 0, "2/4MB page mappings"); 291 292static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 293static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 294static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 295static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 296 vm_offset_t va); 297 298static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 299 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 300static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 301 vm_page_t *free); 302static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 303 vm_page_t *free); 304static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 305 vm_offset_t va); 306static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 307 vm_page_t m); 308 309static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 310 311static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 312static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 313static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 314static void pmap_pte_release(pt_entry_t *pte); 315static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 316static vm_offset_t pmap_kmem_choose(vm_offset_t addr); 317static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 318static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 319 320static __inline void pagezero(void *page); 321 322CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 323CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 324 325/* 326 * If you get an error here, then you set KVA_PAGES wrong! See the 327 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 328 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 329 */ 330CTASSERT(KERNBASE % (1 << 24) == 0); 331 332 333 334void 335pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 336{ 337 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 338 339 switch (type) { 340 case SH_PD_SET_VA: 341#if 0 342 xen_queue_pt_update(shadow_pdir_ma, 343 xpmap_ptom(val & ~(PG_RW))); 344#endif 345 xen_queue_pt_update(pdir_ma, 346 xpmap_ptom(val)); 347 break; 348 case SH_PD_SET_VA_MA: 349#if 0 350 xen_queue_pt_update(shadow_pdir_ma, 351 val & ~(PG_RW)); 352#endif 353 xen_queue_pt_update(pdir_ma, val); 354 break; 355 case SH_PD_SET_VA_CLEAR: 356#if 0 357 xen_queue_pt_update(shadow_pdir_ma, 0); 358#endif 359 xen_queue_pt_update(pdir_ma, 0); 360 break; 361 } 362} 363 364/* 365 * Move the kernel virtual free pointer to the next 366 * 4MB. This is used to help improve performance 367 * by using a large (4MB) page for much of the kernel 368 * (.text, .data, .bss) 369 */ 370static vm_offset_t 371pmap_kmem_choose(vm_offset_t addr) 372{ 373 vm_offset_t newaddr = addr; 374 375#ifndef DISABLE_PSE 376 if (cpu_feature & CPUID_PSE) 377 newaddr = (addr + PDRMASK) & ~PDRMASK; 378#endif 379 return newaddr; 380} 381 382/* 383 * Bootstrap the system enough to run with virtual memory. 384 * 385 * On the i386 this is called after mapping has already been enabled 386 * and just syncs the pmap module with what has already been done. 387 * [We can't call it easily with mapping off since the kernel is not 388 * mapped with PA == VA, hence we would have to relocate every address 389 * from the linked base (virtual) address "KERNBASE" to the actual 390 * (physical) address starting relative to 0] 391 */ 392void 393pmap_bootstrap(vm_paddr_t firstaddr) 394{ 395 vm_offset_t va; 396 pt_entry_t *pte, *unused; 397 struct sysmaps *sysmaps; 398 int i; 399 400 /* 401 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 402 * large. It should instead be correctly calculated in locore.s and 403 * not based on 'first' (which is a physical address, not a virtual 404 * address, for the start of unused physical memory). The kernel 405 * page tables are NOT double mapped and thus should not be included 406 * in this calculation. 407 */ 408 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 409 virtual_avail = pmap_kmem_choose(virtual_avail); 410 411 virtual_end = VM_MAX_KERNEL_ADDRESS; 412 413 /* 414 * Initialize the kernel pmap (which is statically allocated). 415 */ 416 PMAP_LOCK_INIT(kernel_pmap); 417 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 418#ifdef PAE 419 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 420#endif 421 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 422 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 423 LIST_INIT(&allpmaps); 424 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 425 mtx_lock_spin(&allpmaps_lock); 426 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 427 mtx_unlock_spin(&allpmaps_lock); 428 if (nkpt == 0) 429 nkpt = NKPT; 430 431 /* 432 * Reserve some special page table entries/VA space for temporary 433 * mapping of pages. 434 */ 435#define SYSMAP(c, p, v, n) \ 436 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 437 438 va = virtual_avail; 439 pte = vtopte(va); 440 441 /* 442 * CMAP1/CMAP2 are used for zeroing and copying pages. 443 * CMAP3 is used for the idle process page zeroing. 444 */ 445 for (i = 0; i < MAXCPU; i++) { 446 sysmaps = &sysmaps_pcpu[i]; 447 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 448 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 449 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 450 PT_SET_MA(sysmaps->CADDR1, 0); 451 PT_SET_MA(sysmaps->CADDR2, 0); 452 } 453 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 454 PT_SET_MA(CADDR3, 0); 455 456 /* 457 * Crashdump maps. 458 */ 459 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 460 461 /* 462 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 463 */ 464 SYSMAP(caddr_t, unused, ptvmmap, 1) 465 466 /* 467 * msgbufp is used to map the system message buffer. 468 */ 469 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 470 471 /* 472 * ptemap is used for pmap_pte_quick 473 */ 474 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1); 475 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1); 476 477 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 478 479 virtual_avail = va; 480 481 /* 482 * Leave in place an identity mapping (virt == phys) for the low 1 MB 483 * physical memory region that is used by the ACPI wakeup code. This 484 * mapping must not have PG_G set. 485 */ 486#ifndef XEN 487 /* 488 * leave here deliberately to show that this is not supported 489 */ 490#ifdef XBOX 491 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 492 * an early stadium, we cannot yet neatly map video memory ... :-( 493 * Better fixes are very welcome! */ 494 if (!arch_i386_is_xbox) 495#endif 496 for (i = 1; i < NKPT; i++) 497 PTD[i] = 0; 498 499 /* Initialize the PAT MSR if present. */ 500 pmap_init_pat(); 501 502 /* Turn on PG_G on kernel page(s) */ 503 pmap_set_pg(); 504#endif 505} 506 507/* 508 * Setup the PAT MSR. 509 */ 510void 511pmap_init_pat(void) 512{ 513 uint64_t pat_msr; 514 515 /* Bail if this CPU doesn't implement PAT. */ 516 if (!(cpu_feature & CPUID_PAT)) 517 return; 518 519 if (cpu_vendor_id != CPU_VENDOR_INTEL || 520 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 521 /* 522 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 523 * Program 4 and 5 as WP and WC. 524 * Leave 6 and 7 as UC and UC-. 525 */ 526 pat_msr = rdmsr(MSR_PAT); 527 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 528 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 529 PAT_VALUE(5, PAT_WRITE_COMBINING); 530 pat_works = 1; 531 } else { 532 /* 533 * Due to some Intel errata, we can only safely use the lower 4 534 * PAT entries. Thus, just replace PAT Index 2 with WC instead 535 * of UC-. 536 * 537 * Intel Pentium III Processor Specification Update 538 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 539 * or Mode C Paging) 540 * 541 * Intel Pentium IV Processor Specification Update 542 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 543 */ 544 pat_msr = rdmsr(MSR_PAT); 545 pat_msr &= ~PAT_MASK(2); 546 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 547 pat_works = 0; 548 } 549 wrmsr(MSR_PAT, pat_msr); 550} 551 552/* 553 * Initialize a vm_page's machine-dependent fields. 554 */ 555void 556pmap_page_init(vm_page_t m) 557{ 558 559 TAILQ_INIT(&m->md.pv_list); 560 m->md.pat_mode = PAT_WRITE_BACK; 561} 562 563/* 564 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 565 * Requirements: 566 * - Must deal with pages in order to ensure that none of the PG_* bits 567 * are ever set, PG_V in particular. 568 * - Assumes we can write to ptes without pte_store() atomic ops, even 569 * on PAE systems. This should be ok. 570 * - Assumes nothing will ever test these addresses for 0 to indicate 571 * no mapping instead of correctly checking PG_V. 572 * - Assumes a vm_offset_t will fit in a pte (true for i386). 573 * Because PG_V is never set, there can be no mappings to invalidate. 574 */ 575static int ptelist_count = 0; 576static vm_offset_t 577pmap_ptelist_alloc(vm_offset_t *head) 578{ 579 vm_offset_t va; 580 vm_offset_t *phead = (vm_offset_t *)*head; 581 582 if (ptelist_count == 0) { 583 printf("out of memory!!!!!!\n"); 584 return (0); /* Out of memory */ 585 } 586 ptelist_count--; 587 va = phead[ptelist_count]; 588 return (va); 589} 590 591static void 592pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 593{ 594 vm_offset_t *phead = (vm_offset_t *)*head; 595 596 phead[ptelist_count++] = va; 597} 598 599static void 600pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 601{ 602 int i, nstackpages; 603 vm_offset_t va; 604 vm_page_t m; 605 606 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 607 for (i = 0; i < nstackpages; i++) { 608 va = (vm_offset_t)base + i * PAGE_SIZE; 609 m = vm_page_alloc(NULL, i, 610 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 611 VM_ALLOC_ZERO); 612 pmap_qenter(va, &m, 1); 613 } 614 615 *head = (vm_offset_t)base; 616 for (i = npages - 1; i >= nstackpages; i--) { 617 va = (vm_offset_t)base + i * PAGE_SIZE; 618 pmap_ptelist_free(head, va); 619 } 620} 621 622 623/* 624 * Initialize the pmap module. 625 * Called by vm_init, to initialize any structures that the pmap 626 * system needs to map virtual memory. 627 */ 628void 629pmap_init(void) 630{ 631 vm_page_t mpte; 632 vm_size_t s; 633 int i, pv_npg; 634 635 /* 636 * Initialize the vm page array entries for the kernel pmap's 637 * page table pages. 638 */ 639 for (i = 0; i < nkpt; i++) { 640 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(PTD[i + KPTDI] & PG_FRAME)); 641 KASSERT(mpte >= vm_page_array && 642 mpte < &vm_page_array[vm_page_array_size], 643 ("pmap_init: page table page is out of range")); 644 mpte->pindex = i + KPTDI; 645 mpte->phys_addr = xpmap_mtop(PTD[i + KPTDI] & PG_FRAME); 646 } 647 648 /* 649 * Initialize the address space (zone) for the pv entries. Set a 650 * high water mark so that the system can recover from excessive 651 * numbers of pv entries. 652 */ 653 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 654 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 655 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 656 pv_entry_max = roundup(pv_entry_max, _NPCPV); 657 pv_entry_high_water = 9 * (pv_entry_max / 10); 658 659 /* 660 * Are large page mappings enabled? 661 */ 662 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 663 664 /* 665 * Calculate the size of the pv head table for superpages. 666 */ 667 for (i = 0; phys_avail[i + 1]; i += 2); 668 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 669 670 /* 671 * Allocate memory for the pv head table for superpages. 672 */ 673 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 674 s = round_page(s); 675 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 676 for (i = 0; i < pv_npg; i++) 677 TAILQ_INIT(&pv_table[i].pv_list); 678 679 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 680 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 681 PAGE_SIZE * pv_maxchunks); 682 if (pv_chunkbase == NULL) 683 panic("pmap_init: not enough kvm for pv chunks"); 684 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 685} 686 687 688/*************************************************** 689 * Low level helper routines..... 690 ***************************************************/ 691 692/* 693 * Determine the appropriate bits to set in a PTE or PDE for a specified 694 * caching mode. 695 */ 696int 697pmap_cache_bits(int mode, boolean_t is_pde) 698{ 699 int pat_flag, pat_index, cache_bits; 700 701 /* The PAT bit is different for PTE's and PDE's. */ 702 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 703 704 /* If we don't support PAT, map extended modes to older ones. */ 705 if (!(cpu_feature & CPUID_PAT)) { 706 switch (mode) { 707 case PAT_UNCACHEABLE: 708 case PAT_WRITE_THROUGH: 709 case PAT_WRITE_BACK: 710 break; 711 case PAT_UNCACHED: 712 case PAT_WRITE_COMBINING: 713 case PAT_WRITE_PROTECTED: 714 mode = PAT_UNCACHEABLE; 715 break; 716 } 717 } 718 719 /* Map the caching mode to a PAT index. */ 720 if (pat_works) { 721 switch (mode) { 722 case PAT_UNCACHEABLE: 723 pat_index = 3; 724 break; 725 case PAT_WRITE_THROUGH: 726 pat_index = 1; 727 break; 728 case PAT_WRITE_BACK: 729 pat_index = 0; 730 break; 731 case PAT_UNCACHED: 732 pat_index = 2; 733 break; 734 case PAT_WRITE_COMBINING: 735 pat_index = 5; 736 break; 737 case PAT_WRITE_PROTECTED: 738 pat_index = 4; 739 break; 740 default: 741 panic("Unknown caching mode %d\n", mode); 742 } 743 } else { 744 switch (mode) { 745 case PAT_UNCACHED: 746 case PAT_UNCACHEABLE: 747 case PAT_WRITE_PROTECTED: 748 pat_index = 3; 749 break; 750 case PAT_WRITE_THROUGH: 751 pat_index = 1; 752 break; 753 case PAT_WRITE_BACK: 754 pat_index = 0; 755 break; 756 case PAT_WRITE_COMBINING: 757 pat_index = 2; 758 break; 759 default: 760 panic("Unknown caching mode %d\n", mode); 761 } 762 } 763 764 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 765 cache_bits = 0; 766 if (pat_index & 0x4) 767 cache_bits |= pat_flag; 768 if (pat_index & 0x2) 769 cache_bits |= PG_NC_PCD; 770 if (pat_index & 0x1) 771 cache_bits |= PG_NC_PWT; 772 return (cache_bits); 773} 774#ifdef SMP 775/* 776 * For SMP, these functions have to use the IPI mechanism for coherence. 777 * 778 * N.B.: Before calling any of the following TLB invalidation functions, 779 * the calling processor must ensure that all stores updating a non- 780 * kernel page table are globally performed. Otherwise, another 781 * processor could cache an old, pre-update entry without being 782 * invalidated. This can happen one of two ways: (1) The pmap becomes 783 * active on another processor after its pm_active field is checked by 784 * one of the following functions but before a store updating the page 785 * table is globally performed. (2) The pmap becomes active on another 786 * processor before its pm_active field is checked but due to 787 * speculative loads one of the following functions stills reads the 788 * pmap as inactive on the other processor. 789 * 790 * The kernel page table is exempt because its pm_active field is 791 * immutable. The kernel page table is always active on every 792 * processor. 793 */ 794void 795pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 796{ 797 cpumask_t cpumask, other_cpus; 798 799 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 800 pmap, va); 801 802 sched_pin(); 803 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 804 invlpg(va); 805 smp_invlpg(va); 806 } else { 807 cpumask = PCPU_GET(cpumask); 808 other_cpus = PCPU_GET(other_cpus); 809 if (pmap->pm_active & cpumask) 810 invlpg(va); 811 if (pmap->pm_active & other_cpus) 812 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 813 } 814 sched_unpin(); 815 PT_UPDATES_FLUSH(); 816} 817 818void 819pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 820{ 821 cpumask_t cpumask, other_cpus; 822 vm_offset_t addr; 823 824 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 825 pmap, sva, eva); 826 827 sched_pin(); 828 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 829 for (addr = sva; addr < eva; addr += PAGE_SIZE) 830 invlpg(addr); 831 smp_invlpg_range(sva, eva); 832 } else { 833 cpumask = PCPU_GET(cpumask); 834 other_cpus = PCPU_GET(other_cpus); 835 if (pmap->pm_active & cpumask) 836 for (addr = sva; addr < eva; addr += PAGE_SIZE) 837 invlpg(addr); 838 if (pmap->pm_active & other_cpus) 839 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 840 sva, eva); 841 } 842 sched_unpin(); 843 PT_UPDATES_FLUSH(); 844} 845 846void 847pmap_invalidate_all(pmap_t pmap) 848{ 849 cpumask_t cpumask, other_cpus; 850 851 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 852 853 sched_pin(); 854 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 855 invltlb(); 856 smp_invltlb(); 857 } else { 858 cpumask = PCPU_GET(cpumask); 859 other_cpus = PCPU_GET(other_cpus); 860 if (pmap->pm_active & cpumask) 861 invltlb(); 862 if (pmap->pm_active & other_cpus) 863 smp_masked_invltlb(pmap->pm_active & other_cpus); 864 } 865 sched_unpin(); 866} 867 868void 869pmap_invalidate_cache(void) 870{ 871 872 sched_pin(); 873 wbinvd(); 874 smp_cache_flush(); 875 sched_unpin(); 876} 877#else /* !SMP */ 878/* 879 * Normal, non-SMP, 486+ invalidation functions. 880 * We inline these within pmap.c for speed. 881 */ 882PMAP_INLINE void 883pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 884{ 885 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 886 pmap, va); 887 888 if (pmap == kernel_pmap || pmap->pm_active) 889 invlpg(va); 890 PT_UPDATES_FLUSH(); 891} 892 893PMAP_INLINE void 894pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 895{ 896 vm_offset_t addr; 897 898 if (eva - sva > PAGE_SIZE) 899 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 900 pmap, sva, eva); 901 902 if (pmap == kernel_pmap || pmap->pm_active) 903 for (addr = sva; addr < eva; addr += PAGE_SIZE) 904 invlpg(addr); 905 PT_UPDATES_FLUSH(); 906} 907 908PMAP_INLINE void 909pmap_invalidate_all(pmap_t pmap) 910{ 911 912 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 913 914 if (pmap == kernel_pmap || pmap->pm_active) 915 invltlb(); 916} 917 918PMAP_INLINE void 919pmap_invalidate_cache(void) 920{ 921 922 wbinvd(); 923} 924#endif /* !SMP */ 925 926void 927pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 928{ 929 930 KASSERT((sva & PAGE_MASK) == 0, 931 ("pmap_invalidate_cache_range: sva not page-aligned")); 932 KASSERT((eva & PAGE_MASK) == 0, 933 ("pmap_invalidate_cache_range: eva not page-aligned")); 934 935 if (cpu_feature & CPUID_SS) 936 ; /* If "Self Snoop" is supported, do nothing. */ 937 else if (cpu_feature & CPUID_CLFSH) { 938 939 /* 940 * Otherwise, do per-cache line flush. Use the mfence 941 * instruction to insure that previous stores are 942 * included in the write-back. The processor 943 * propagates flush to other processors in the cache 944 * coherence domain. 945 */ 946 mfence(); 947 for (; sva < eva; sva += cpu_clflush_line_size) 948 clflush(sva); 949 mfence(); 950 } else { 951 952 /* 953 * No targeted cache flush methods are supported by CPU, 954 * globally invalidate cache as a last resort. 955 */ 956 pmap_invalidate_cache(); 957 } 958} 959 960/* 961 * Are we current address space or kernel? N.B. We return FALSE when 962 * a pmap's page table is in use because a kernel thread is borrowing 963 * it. The borrowed page table can change spontaneously, making any 964 * dependence on its continued use subject to a race condition. 965 */ 966static __inline int 967pmap_is_current(pmap_t pmap) 968{ 969 970 return (pmap == kernel_pmap || 971 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 972 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 973} 974 975/* 976 * If the given pmap is not the current or kernel pmap, the returned pte must 977 * be released by passing it to pmap_pte_release(). 978 */ 979pt_entry_t * 980pmap_pte(pmap_t pmap, vm_offset_t va) 981{ 982 pd_entry_t newpf; 983 pd_entry_t *pde; 984 985 pde = pmap_pde(pmap, va); 986 if (*pde & PG_PS) 987 return (pde); 988 if (*pde != 0) { 989 /* are we current address space or kernel? */ 990 if (pmap_is_current(pmap)) 991 return (vtopte(va)); 992 mtx_lock(&PMAP2mutex); 993 newpf = *pde & PG_FRAME; 994 if ((*PMAP2 & PG_FRAME) != newpf) { 995 vm_page_lock_queues(); 996 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 997 vm_page_unlock_queues(); 998 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 999 pmap, va, (*PMAP2 & 0xffffffff)); 1000 } 1001 1002 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1003 } 1004 return (0); 1005} 1006 1007/* 1008 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1009 * being NULL. 1010 */ 1011static __inline void 1012pmap_pte_release(pt_entry_t *pte) 1013{ 1014 1015 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 1016 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 1017 *PMAP2); 1018 vm_page_lock_queues(); 1019 PT_SET_VA(PMAP2, 0, TRUE); 1020 vm_page_unlock_queues(); 1021 mtx_unlock(&PMAP2mutex); 1022 } 1023} 1024 1025static __inline void 1026invlcaddr(void *caddr) 1027{ 1028 1029 invlpg((u_int)caddr); 1030 PT_UPDATES_FLUSH(); 1031} 1032 1033/* 1034 * Super fast pmap_pte routine best used when scanning 1035 * the pv lists. This eliminates many coarse-grained 1036 * invltlb calls. Note that many of the pv list 1037 * scans are across different pmaps. It is very wasteful 1038 * to do an entire invltlb for checking a single mapping. 1039 * 1040 * If the given pmap is not the current pmap, vm_page_queue_mtx 1041 * must be held and curthread pinned to a CPU. 1042 */ 1043static pt_entry_t * 1044pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1045{ 1046 pd_entry_t newpf; 1047 pd_entry_t *pde; 1048 1049 pde = pmap_pde(pmap, va); 1050 if (*pde & PG_PS) 1051 return (pde); 1052 if (*pde != 0) { 1053 /* are we current address space or kernel? */ 1054 if (pmap_is_current(pmap)) 1055 return (vtopte(va)); 1056 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1057 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1058 newpf = *pde & PG_FRAME; 1059 if ((*PMAP1 & PG_FRAME) != newpf) { 1060 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1061 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1062 pmap, va, (u_long)*PMAP1); 1063 1064#ifdef SMP 1065 PMAP1cpu = PCPU_GET(cpuid); 1066#endif 1067 PMAP1changed++; 1068 } else 1069#ifdef SMP 1070 if (PMAP1cpu != PCPU_GET(cpuid)) { 1071 PMAP1cpu = PCPU_GET(cpuid); 1072 invlcaddr(PADDR1); 1073 PMAP1changedcpu++; 1074 } else 1075#endif 1076 PMAP1unchanged++; 1077 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1078 } 1079 return (0); 1080} 1081 1082/* 1083 * Routine: pmap_extract 1084 * Function: 1085 * Extract the physical page address associated 1086 * with the given map/virtual_address pair. 1087 */ 1088vm_paddr_t 1089pmap_extract(pmap_t pmap, vm_offset_t va) 1090{ 1091 vm_paddr_t rtval; 1092 pt_entry_t *pte; 1093 pd_entry_t pde; 1094 pt_entry_t pteval; 1095 1096 rtval = 0; 1097 PMAP_LOCK(pmap); 1098 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1099 if (pde != 0) { 1100 if ((pde & PG_PS) != 0) { 1101 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1102 PMAP_UNLOCK(pmap); 1103 return rtval; 1104 } 1105 pte = pmap_pte(pmap, va); 1106 pteval = *pte ? xpmap_mtop(*pte) : 0; 1107 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1108 pmap_pte_release(pte); 1109 } 1110 PMAP_UNLOCK(pmap); 1111 return (rtval); 1112} 1113 1114/* 1115 * Routine: pmap_extract_ma 1116 * Function: 1117 * Like pmap_extract, but returns machine address 1118 */ 1119vm_paddr_t 1120pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1121{ 1122 vm_paddr_t rtval; 1123 pt_entry_t *pte; 1124 pd_entry_t pde; 1125 1126 rtval = 0; 1127 PMAP_LOCK(pmap); 1128 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1129 if (pde != 0) { 1130 if ((pde & PG_PS) != 0) { 1131 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1132 PMAP_UNLOCK(pmap); 1133 return rtval; 1134 } 1135 pte = pmap_pte(pmap, va); 1136 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1137 pmap_pte_release(pte); 1138 } 1139 PMAP_UNLOCK(pmap); 1140 return (rtval); 1141} 1142 1143/* 1144 * Routine: pmap_extract_and_hold 1145 * Function: 1146 * Atomically extract and hold the physical page 1147 * with the given pmap and virtual address pair 1148 * if that mapping permits the given protection. 1149 */ 1150vm_page_t 1151pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1152{ 1153 pd_entry_t pde; 1154 pt_entry_t pte; 1155 vm_page_t m; 1156 vm_paddr_t pa; 1157 1158 pa = 0; 1159 m = NULL; 1160 PMAP_LOCK(pmap); 1161retry: 1162 pde = PT_GET(pmap_pde(pmap, va)); 1163 if (pde != 0) { 1164 if (pde & PG_PS) { 1165 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1166 if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) | 1167 (va & PDRMASK), &pa)) 1168 goto retry; 1169 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1170 (va & PDRMASK)); 1171 vm_page_hold(m); 1172 } 1173 } else { 1174 sched_pin(); 1175 pte = PT_GET(pmap_pte_quick(pmap, va)); 1176 if (*PMAP1) 1177 PT_SET_MA(PADDR1, 0); 1178 if ((pte & PG_V) && 1179 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1180 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa)) 1181 goto retry; 1182 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1183 vm_page_hold(m); 1184 } 1185 sched_unpin(); 1186 } 1187 } 1188 PA_UNLOCK_COND(pa); 1189 PMAP_UNLOCK(pmap); 1190 return (m); 1191} 1192 1193/*************************************************** 1194 * Low level mapping routines..... 1195 ***************************************************/ 1196 1197/* 1198 * Add a wired page to the kva. 1199 * Note: not SMP coherent. 1200 */ 1201void 1202pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1203{ 1204 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1205} 1206 1207void 1208pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1209{ 1210 pt_entry_t *pte; 1211 1212 pte = vtopte(va); 1213 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1214} 1215 1216 1217static __inline void 1218pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1219{ 1220 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1221} 1222 1223/* 1224 * Remove a page from the kernel pagetables. 1225 * Note: not SMP coherent. 1226 */ 1227PMAP_INLINE void 1228pmap_kremove(vm_offset_t va) 1229{ 1230 pt_entry_t *pte; 1231 1232 pte = vtopte(va); 1233 PT_CLEAR_VA(pte, FALSE); 1234} 1235 1236/* 1237 * Used to map a range of physical addresses into kernel 1238 * virtual address space. 1239 * 1240 * The value passed in '*virt' is a suggested virtual address for 1241 * the mapping. Architectures which can support a direct-mapped 1242 * physical to virtual region can return the appropriate address 1243 * within that region, leaving '*virt' unchanged. Other 1244 * architectures should map the pages starting at '*virt' and 1245 * update '*virt' with the first usable address after the mapped 1246 * region. 1247 */ 1248vm_offset_t 1249pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1250{ 1251 vm_offset_t va, sva; 1252 1253 va = sva = *virt; 1254 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1255 va, start, end, prot); 1256 while (start < end) { 1257 pmap_kenter(va, start); 1258 va += PAGE_SIZE; 1259 start += PAGE_SIZE; 1260 } 1261 pmap_invalidate_range(kernel_pmap, sva, va); 1262 *virt = va; 1263 return (sva); 1264} 1265 1266 1267/* 1268 * Add a list of wired pages to the kva 1269 * this routine is only used for temporary 1270 * kernel mappings that do not need to have 1271 * page modification or references recorded. 1272 * Note that old mappings are simply written 1273 * over. The page *must* be wired. 1274 * Note: SMP coherent. Uses a ranged shootdown IPI. 1275 */ 1276void 1277pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1278{ 1279 pt_entry_t *endpte, *pte; 1280 vm_paddr_t pa; 1281 vm_offset_t va = sva; 1282 int mclcount = 0; 1283 multicall_entry_t mcl[16]; 1284 multicall_entry_t *mclp = mcl; 1285 int error; 1286 1287 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1288 pte = vtopte(sva); 1289 endpte = pte + count; 1290 while (pte < endpte) { 1291 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1292 1293 mclp->op = __HYPERVISOR_update_va_mapping; 1294 mclp->args[0] = va; 1295 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1296 mclp->args[2] = (uint32_t)(pa >> 32); 1297 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1298 1299 va += PAGE_SIZE; 1300 pte++; 1301 ma++; 1302 mclp++; 1303 mclcount++; 1304 if (mclcount == 16) { 1305 error = HYPERVISOR_multicall(mcl, mclcount); 1306 mclp = mcl; 1307 mclcount = 0; 1308 KASSERT(error == 0, ("bad multicall %d", error)); 1309 } 1310 } 1311 if (mclcount) { 1312 error = HYPERVISOR_multicall(mcl, mclcount); 1313 KASSERT(error == 0, ("bad multicall %d", error)); 1314 } 1315 1316#ifdef INVARIANTS 1317 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1318 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1319#endif 1320} 1321 1322 1323/* 1324 * This routine tears out page mappings from the 1325 * kernel -- it is meant only for temporary mappings. 1326 * Note: SMP coherent. Uses a ranged shootdown IPI. 1327 */ 1328void 1329pmap_qremove(vm_offset_t sva, int count) 1330{ 1331 vm_offset_t va; 1332 1333 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1334 va = sva; 1335 vm_page_lock_queues(); 1336 critical_enter(); 1337 while (count-- > 0) { 1338 pmap_kremove(va); 1339 va += PAGE_SIZE; 1340 } 1341 PT_UPDATES_FLUSH(); 1342 pmap_invalidate_range(kernel_pmap, sva, va); 1343 critical_exit(); 1344 vm_page_unlock_queues(); 1345} 1346 1347/*************************************************** 1348 * Page table page management routines..... 1349 ***************************************************/ 1350static __inline void 1351pmap_free_zero_pages(vm_page_t free) 1352{ 1353 vm_page_t m; 1354 1355 while (free != NULL) { 1356 m = free; 1357 free = m->right; 1358 vm_page_free_zero(m); 1359 } 1360} 1361 1362/* 1363 * This routine unholds page table pages, and if the hold count 1364 * drops to zero, then it decrements the wire count. 1365 */ 1366static __inline int 1367pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1368{ 1369 1370 --m->wire_count; 1371 if (m->wire_count == 0) 1372 return _pmap_unwire_pte_hold(pmap, m, free); 1373 else 1374 return 0; 1375} 1376 1377static int 1378_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1379{ 1380 vm_offset_t pteva; 1381 1382 PT_UPDATES_FLUSH(); 1383 /* 1384 * unmap the page table page 1385 */ 1386 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1387 /* 1388 * page *might* contain residual mapping :-/ 1389 */ 1390 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1391 pmap_zero_page(m); 1392 --pmap->pm_stats.resident_count; 1393 1394 /* 1395 * This is a release store so that the ordinary store unmapping 1396 * the page table page is globally performed before TLB shoot- 1397 * down is begun. 1398 */ 1399 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1400 1401 /* 1402 * Do an invltlb to make the invalidated mapping 1403 * take effect immediately. 1404 */ 1405 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1406 pmap_invalidate_page(pmap, pteva); 1407 1408 /* 1409 * Put page on a list so that it is released after 1410 * *ALL* TLB shootdown is done 1411 */ 1412 m->right = *free; 1413 *free = m; 1414 1415 return 1; 1416} 1417 1418/* 1419 * After removing a page table entry, this routine is used to 1420 * conditionally free the page, and manage the hold/wire counts. 1421 */ 1422static int 1423pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1424{ 1425 pd_entry_t ptepde; 1426 vm_page_t mpte; 1427 1428 if (va >= VM_MAXUSER_ADDRESS) 1429 return 0; 1430 ptepde = PT_GET(pmap_pde(pmap, va)); 1431 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1432 return pmap_unwire_pte_hold(pmap, mpte, free); 1433} 1434 1435void 1436pmap_pinit0(pmap_t pmap) 1437{ 1438 1439 PMAP_LOCK_INIT(pmap); 1440 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1441#ifdef PAE 1442 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1443#endif 1444 pmap->pm_active = 0; 1445 PCPU_SET(curpmap, pmap); 1446 TAILQ_INIT(&pmap->pm_pvchunk); 1447 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1448 mtx_lock_spin(&allpmaps_lock); 1449 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1450 mtx_unlock_spin(&allpmaps_lock); 1451} 1452 1453/* 1454 * Initialize a preallocated and zeroed pmap structure, 1455 * such as one in a vmspace structure. 1456 */ 1457int 1458pmap_pinit(pmap_t pmap) 1459{ 1460 vm_page_t m, ptdpg[NPGPTD + 1]; 1461 int npgptd = NPGPTD + 1; 1462 static int color; 1463 int i; 1464 1465 PMAP_LOCK_INIT(pmap); 1466 1467 /* 1468 * No need to allocate page table space yet but we do need a valid 1469 * page directory table. 1470 */ 1471 if (pmap->pm_pdir == NULL) { 1472 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1473 NBPTD); 1474 if (pmap->pm_pdir == NULL) { 1475 PMAP_LOCK_DESTROY(pmap); 1476 return (0); 1477 } 1478#ifdef PAE 1479 pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1480#endif 1481 } 1482 1483 /* 1484 * allocate the page directory page(s) 1485 */ 1486 for (i = 0; i < npgptd;) { 1487 m = vm_page_alloc(NULL, color++, 1488 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1489 VM_ALLOC_ZERO); 1490 if (m == NULL) 1491 VM_WAIT; 1492 else { 1493 ptdpg[i++] = m; 1494 } 1495 } 1496 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1497 for (i = 0; i < NPGPTD; i++) { 1498 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1499 pagezero(&pmap->pm_pdir[i*NPTEPG]); 1500 } 1501 1502 mtx_lock_spin(&allpmaps_lock); 1503 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1504 mtx_unlock_spin(&allpmaps_lock); 1505 /* Wire in kernel global address entries. */ 1506 1507 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1508#ifdef PAE 1509 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1510 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1511 bzero(pmap->pm_pdpt, PAGE_SIZE); 1512 for (i = 0; i < NPGPTD; i++) { 1513 vm_paddr_t ma; 1514 1515 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1516 pmap->pm_pdpt[i] = ma | PG_V; 1517 1518 } 1519#endif 1520 for (i = 0; i < NPGPTD; i++) { 1521 pt_entry_t *pd; 1522 vm_paddr_t ma; 1523 1524 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1525 pd = pmap->pm_pdir + (i * NPDEPG); 1526 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1527#if 0 1528 xen_pgd_pin(ma); 1529#endif 1530 } 1531 1532#ifdef PAE 1533 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1534#endif 1535 vm_page_lock_queues(); 1536 xen_flush_queue(); 1537 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1538 for (i = 0; i < NPGPTD; i++) { 1539 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1540 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1541 } 1542 xen_flush_queue(); 1543 vm_page_unlock_queues(); 1544 pmap->pm_active = 0; 1545 TAILQ_INIT(&pmap->pm_pvchunk); 1546 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1547 1548 return (1); 1549} 1550 1551/* 1552 * this routine is called if the page table page is not 1553 * mapped correctly. 1554 */ 1555static vm_page_t 1556_pmap_allocpte(pmap_t pmap, unsigned int ptepindex, int flags) 1557{ 1558 vm_paddr_t ptema; 1559 vm_page_t m; 1560 1561 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1562 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1563 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1564 1565 /* 1566 * Allocate a page table page. 1567 */ 1568 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1569 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1570 if (flags & M_WAITOK) { 1571 PMAP_UNLOCK(pmap); 1572 vm_page_unlock_queues(); 1573 VM_WAIT; 1574 vm_page_lock_queues(); 1575 PMAP_LOCK(pmap); 1576 } 1577 1578 /* 1579 * Indicate the need to retry. While waiting, the page table 1580 * page may have been allocated. 1581 */ 1582 return (NULL); 1583 } 1584 if ((m->flags & PG_ZERO) == 0) 1585 pmap_zero_page(m); 1586 1587 /* 1588 * Map the pagetable page into the process address space, if 1589 * it isn't already there. 1590 */ 1591 pmap->pm_stats.resident_count++; 1592 1593 ptema = VM_PAGE_TO_MACH(m); 1594 xen_pt_pin(ptema); 1595 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1596 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1597 1598 KASSERT(pmap->pm_pdir[ptepindex], 1599 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1600 return (m); 1601} 1602 1603static vm_page_t 1604pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1605{ 1606 unsigned ptepindex; 1607 pd_entry_t ptema; 1608 vm_page_t m; 1609 1610 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1611 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1612 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1613 1614 /* 1615 * Calculate pagetable page index 1616 */ 1617 ptepindex = va >> PDRSHIFT; 1618retry: 1619 /* 1620 * Get the page directory entry 1621 */ 1622 ptema = pmap->pm_pdir[ptepindex]; 1623 1624 /* 1625 * This supports switching from a 4MB page to a 1626 * normal 4K page. 1627 */ 1628 if (ptema & PG_PS) { 1629 /* 1630 * XXX 1631 */ 1632 pmap->pm_pdir[ptepindex] = 0; 1633 ptema = 0; 1634 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1635 pmap_invalidate_all(kernel_pmap); 1636 } 1637 1638 /* 1639 * If the page table page is mapped, we just increment the 1640 * hold count, and activate it. 1641 */ 1642 if (ptema & PG_V) { 1643 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1644 m->wire_count++; 1645 } else { 1646 /* 1647 * Here if the pte page isn't mapped, or if it has 1648 * been deallocated. 1649 */ 1650 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1651 pmap, va, flags); 1652 m = _pmap_allocpte(pmap, ptepindex, flags); 1653 if (m == NULL && (flags & M_WAITOK)) 1654 goto retry; 1655 1656 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1657 } 1658 return (m); 1659} 1660 1661 1662/*************************************************** 1663* Pmap allocation/deallocation routines. 1664 ***************************************************/ 1665 1666#ifdef SMP 1667/* 1668 * Deal with a SMP shootdown of other users of the pmap that we are 1669 * trying to dispose of. This can be a bit hairy. 1670 */ 1671static cpumask_t *lazymask; 1672static u_int lazyptd; 1673static volatile u_int lazywait; 1674 1675void pmap_lazyfix_action(void); 1676 1677void 1678pmap_lazyfix_action(void) 1679{ 1680 cpumask_t mymask = PCPU_GET(cpumask); 1681 1682#ifdef COUNT_IPIS 1683 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1684#endif 1685 if (rcr3() == lazyptd) 1686 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1687 atomic_clear_int(lazymask, mymask); 1688 atomic_store_rel_int(&lazywait, 1); 1689} 1690 1691static void 1692pmap_lazyfix_self(cpumask_t mymask) 1693{ 1694 1695 if (rcr3() == lazyptd) 1696 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1697 atomic_clear_int(lazymask, mymask); 1698} 1699 1700 1701static void 1702pmap_lazyfix(pmap_t pmap) 1703{ 1704 cpumask_t mymask, mask; 1705 u_int spins; 1706 1707 while ((mask = pmap->pm_active) != 0) { 1708 spins = 50000000; 1709 mask = mask & -mask; /* Find least significant set bit */ 1710 mtx_lock_spin(&smp_ipi_mtx); 1711#ifdef PAE 1712 lazyptd = vtophys(pmap->pm_pdpt); 1713#else 1714 lazyptd = vtophys(pmap->pm_pdir); 1715#endif 1716 mymask = PCPU_GET(cpumask); 1717 if (mask == mymask) { 1718 lazymask = &pmap->pm_active; 1719 pmap_lazyfix_self(mymask); 1720 } else { 1721 atomic_store_rel_int((u_int *)&lazymask, 1722 (u_int)&pmap->pm_active); 1723 atomic_store_rel_int(&lazywait, 0); 1724 ipi_selected(mask, IPI_LAZYPMAP); 1725 while (lazywait == 0) { 1726 ia32_pause(); 1727 if (--spins == 0) 1728 break; 1729 } 1730 } 1731 mtx_unlock_spin(&smp_ipi_mtx); 1732 if (spins == 0) 1733 printf("pmap_lazyfix: spun for 50000000\n"); 1734 } 1735} 1736 1737#else /* SMP */ 1738 1739/* 1740 * Cleaning up on uniprocessor is easy. For various reasons, we're 1741 * unlikely to have to even execute this code, including the fact 1742 * that the cleanup is deferred until the parent does a wait(2), which 1743 * means that another userland process has run. 1744 */ 1745static void 1746pmap_lazyfix(pmap_t pmap) 1747{ 1748 u_int cr3; 1749 1750 cr3 = vtophys(pmap->pm_pdir); 1751 if (cr3 == rcr3()) { 1752 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1753 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1754 } 1755} 1756#endif /* SMP */ 1757 1758/* 1759 * Release any resources held by the given physical map. 1760 * Called when a pmap initialized by pmap_pinit is being released. 1761 * Should only be called if the map contains no valid mappings. 1762 */ 1763void 1764pmap_release(pmap_t pmap) 1765{ 1766 vm_page_t m, ptdpg[2*NPGPTD+1]; 1767 vm_paddr_t ma; 1768 int i; 1769#ifdef PAE 1770 int npgptd = NPGPTD + 1; 1771#else 1772 int npgptd = NPGPTD; 1773#endif 1774 KASSERT(pmap->pm_stats.resident_count == 0, 1775 ("pmap_release: pmap resident count %ld != 0", 1776 pmap->pm_stats.resident_count)); 1777 PT_UPDATES_FLUSH(); 1778 1779 pmap_lazyfix(pmap); 1780 mtx_lock_spin(&allpmaps_lock); 1781 LIST_REMOVE(pmap, pm_list); 1782 mtx_unlock_spin(&allpmaps_lock); 1783 1784 for (i = 0; i < NPGPTD; i++) 1785 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1786 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1787#ifdef PAE 1788 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1789#endif 1790 1791 for (i = 0; i < npgptd; i++) { 1792 m = ptdpg[i]; 1793 ma = VM_PAGE_TO_MACH(m); 1794 /* unpinning L1 and L2 treated the same */ 1795#if 0 1796 xen_pgd_unpin(ma); 1797#else 1798 if (i == NPGPTD) 1799 xen_pgd_unpin(ma); 1800#endif 1801#ifdef PAE 1802 if (i < NPGPTD) 1803 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1804 ("pmap_release: got wrong ptd page")); 1805#endif 1806 m->wire_count--; 1807 atomic_subtract_int(&cnt.v_wire_count, 1); 1808 vm_page_free(m); 1809 } 1810#ifdef PAE 1811 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1812#endif 1813 PMAP_LOCK_DESTROY(pmap); 1814} 1815 1816static int 1817kvm_size(SYSCTL_HANDLER_ARGS) 1818{ 1819 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1820 1821 return sysctl_handle_long(oidp, &ksize, 0, req); 1822} 1823SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1824 0, 0, kvm_size, "IU", "Size of KVM"); 1825 1826static int 1827kvm_free(SYSCTL_HANDLER_ARGS) 1828{ 1829 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1830 1831 return sysctl_handle_long(oidp, &kfree, 0, req); 1832} 1833SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1834 0, 0, kvm_free, "IU", "Amount of KVM free"); 1835 1836/* 1837 * grow the number of kernel page table entries, if needed 1838 */ 1839void 1840pmap_growkernel(vm_offset_t addr) 1841{ 1842 struct pmap *pmap; 1843 vm_paddr_t ptppaddr; 1844 vm_page_t nkpg; 1845 pd_entry_t newpdir; 1846 1847 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1848 if (kernel_vm_end == 0) { 1849 kernel_vm_end = KERNBASE; 1850 nkpt = 0; 1851 while (pdir_pde(PTD, kernel_vm_end)) { 1852 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1853 nkpt++; 1854 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1855 kernel_vm_end = kernel_map->max_offset; 1856 break; 1857 } 1858 } 1859 } 1860 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1861 if (addr - 1 >= kernel_map->max_offset) 1862 addr = kernel_map->max_offset; 1863 while (kernel_vm_end < addr) { 1864 if (pdir_pde(PTD, kernel_vm_end)) { 1865 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1866 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1867 kernel_vm_end = kernel_map->max_offset; 1868 break; 1869 } 1870 continue; 1871 } 1872 1873 /* 1874 * This index is bogus, but out of the way 1875 */ 1876 nkpg = vm_page_alloc(NULL, nkpt, 1877 VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED); 1878 if (!nkpg) 1879 panic("pmap_growkernel: no memory to grow kernel"); 1880 1881 nkpt++; 1882 1883 pmap_zero_page(nkpg); 1884 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1885 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1886 vm_page_lock_queues(); 1887 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1888 mtx_lock_spin(&allpmaps_lock); 1889 LIST_FOREACH(pmap, &allpmaps, pm_list) 1890 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1891 1892 mtx_unlock_spin(&allpmaps_lock); 1893 vm_page_unlock_queues(); 1894 1895 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1896 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1897 kernel_vm_end = kernel_map->max_offset; 1898 break; 1899 } 1900 } 1901} 1902 1903 1904/*************************************************** 1905 * page management routines. 1906 ***************************************************/ 1907 1908CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1909CTASSERT(_NPCM == 11); 1910 1911static __inline struct pv_chunk * 1912pv_to_chunk(pv_entry_t pv) 1913{ 1914 1915 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1916} 1917 1918#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1919 1920#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1921#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1922 1923static uint32_t pc_freemask[11] = { 1924 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1925 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1926 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1927 PC_FREE0_9, PC_FREE10 1928}; 1929 1930SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1931 "Current number of pv entries"); 1932 1933#ifdef PV_STATS 1934static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1935 1936SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1937 "Current number of pv entry chunks"); 1938SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1939 "Current number of pv entry chunks allocated"); 1940SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1941 "Current number of pv entry chunks frees"); 1942SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1943 "Number of times tried to get a chunk page but failed."); 1944 1945static long pv_entry_frees, pv_entry_allocs; 1946static int pv_entry_spare; 1947 1948SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1949 "Current number of pv entry frees"); 1950SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1951 "Current number of pv entry allocs"); 1952SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1953 "Current number of spare pv entries"); 1954 1955static int pmap_collect_inactive, pmap_collect_active; 1956 1957SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 1958 "Current number times pmap_collect called on inactive queue"); 1959SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 1960 "Current number times pmap_collect called on active queue"); 1961#endif 1962 1963/* 1964 * We are in a serious low memory condition. Resort to 1965 * drastic measures to free some pages so we can allocate 1966 * another pv entry chunk. This is normally called to 1967 * unmap inactive pages, and if necessary, active pages. 1968 */ 1969static void 1970pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 1971{ 1972 pmap_t pmap; 1973 pt_entry_t *pte, tpte; 1974 pv_entry_t next_pv, pv; 1975 vm_offset_t va; 1976 vm_page_t m, free; 1977 1978 sched_pin(); 1979 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1980 if (m->hold_count || m->busy) 1981 continue; 1982 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1983 va = pv->pv_va; 1984 pmap = PV_PMAP(pv); 1985 /* Avoid deadlock and lock recursion. */ 1986 if (pmap > locked_pmap) 1987 PMAP_LOCK(pmap); 1988 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1989 continue; 1990 pmap->pm_stats.resident_count--; 1991 pte = pmap_pte_quick(pmap, va); 1992 tpte = pte_load_clear(pte); 1993 KASSERT((tpte & PG_W) == 0, 1994 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 1995 if (tpte & PG_A) 1996 vm_page_flag_set(m, PG_REFERENCED); 1997 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 1998 vm_page_dirty(m); 1999 free = NULL; 2000 pmap_unuse_pt(pmap, va, &free); 2001 pmap_invalidate_page(pmap, va); 2002 pmap_free_zero_pages(free); 2003 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2004 free_pv_entry(pmap, pv); 2005 if (pmap != locked_pmap) 2006 PMAP_UNLOCK(pmap); 2007 } 2008 if (TAILQ_EMPTY(&m->md.pv_list)) 2009 vm_page_flag_clear(m, PG_WRITEABLE); 2010 } 2011 sched_unpin(); 2012} 2013 2014 2015/* 2016 * free the pv_entry back to the free list 2017 */ 2018static void 2019free_pv_entry(pmap_t pmap, pv_entry_t pv) 2020{ 2021 vm_page_t m; 2022 struct pv_chunk *pc; 2023 int idx, field, bit; 2024 2025 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2026 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2027 PV_STAT(pv_entry_frees++); 2028 PV_STAT(pv_entry_spare++); 2029 pv_entry_count--; 2030 pc = pv_to_chunk(pv); 2031 idx = pv - &pc->pc_pventry[0]; 2032 field = idx / 32; 2033 bit = idx % 32; 2034 pc->pc_map[field] |= 1ul << bit; 2035 /* move to head of list */ 2036 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2037 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2038 for (idx = 0; idx < _NPCM; idx++) 2039 if (pc->pc_map[idx] != pc_freemask[idx]) 2040 return; 2041 PV_STAT(pv_entry_spare -= _NPCPV); 2042 PV_STAT(pc_chunk_count--); 2043 PV_STAT(pc_chunk_frees++); 2044 /* entire chunk is free, return it */ 2045 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2046 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2047 pmap_qremove((vm_offset_t)pc, 1); 2048 vm_page_unwire(m, 0); 2049 vm_page_free(m); 2050 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2051} 2052 2053/* 2054 * get a new pv_entry, allocating a block from the system 2055 * when needed. 2056 */ 2057static pv_entry_t 2058get_pv_entry(pmap_t pmap, int try) 2059{ 2060 static const struct timeval printinterval = { 60, 0 }; 2061 static struct timeval lastprint; 2062 static vm_pindex_t colour; 2063 struct vpgqueues *pq; 2064 int bit, field; 2065 pv_entry_t pv; 2066 struct pv_chunk *pc; 2067 vm_page_t m; 2068 2069 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2070 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2071 PV_STAT(pv_entry_allocs++); 2072 pv_entry_count++; 2073 if (pv_entry_count > pv_entry_high_water) 2074 if (ratecheck(&lastprint, &printinterval)) 2075 printf("Approaching the limit on PV entries, consider " 2076 "increasing either the vm.pmap.shpgperproc or the " 2077 "vm.pmap.pv_entry_max tunable.\n"); 2078 pq = NULL; 2079retry: 2080 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2081 if (pc != NULL) { 2082 for (field = 0; field < _NPCM; field++) { 2083 if (pc->pc_map[field]) { 2084 bit = bsfl(pc->pc_map[field]); 2085 break; 2086 } 2087 } 2088 if (field < _NPCM) { 2089 pv = &pc->pc_pventry[field * 32 + bit]; 2090 pc->pc_map[field] &= ~(1ul << bit); 2091 /* If this was the last item, move it to tail */ 2092 for (field = 0; field < _NPCM; field++) 2093 if (pc->pc_map[field] != 0) { 2094 PV_STAT(pv_entry_spare--); 2095 return (pv); /* not full, return */ 2096 } 2097 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2098 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2099 PV_STAT(pv_entry_spare--); 2100 return (pv); 2101 } 2102 } 2103 /* 2104 * Access to the ptelist "pv_vafree" is synchronized by the page 2105 * queues lock. If "pv_vafree" is currently non-empty, it will 2106 * remain non-empty until pmap_ptelist_alloc() completes. 2107 */ 2108 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2109 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2110 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2111 if (try) { 2112 pv_entry_count--; 2113 PV_STAT(pc_chunk_tryfail++); 2114 return (NULL); 2115 } 2116 /* 2117 * Reclaim pv entries: At first, destroy mappings to 2118 * inactive pages. After that, if a pv chunk entry 2119 * is still needed, destroy mappings to active pages. 2120 */ 2121 if (pq == NULL) { 2122 PV_STAT(pmap_collect_inactive++); 2123 pq = &vm_page_queues[PQ_INACTIVE]; 2124 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2125 PV_STAT(pmap_collect_active++); 2126 pq = &vm_page_queues[PQ_ACTIVE]; 2127 } else 2128 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2129 pmap_collect(pmap, pq); 2130 goto retry; 2131 } 2132 PV_STAT(pc_chunk_count++); 2133 PV_STAT(pc_chunk_allocs++); 2134 colour++; 2135 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2136 pmap_qenter((vm_offset_t)pc, &m, 1); 2137 if ((m->flags & PG_ZERO) == 0) 2138 pagezero(pc); 2139 pc->pc_pmap = pmap; 2140 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2141 for (field = 1; field < _NPCM; field++) 2142 pc->pc_map[field] = pc_freemask[field]; 2143 pv = &pc->pc_pventry[0]; 2144 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2145 PV_STAT(pv_entry_spare += _NPCPV - 1); 2146 return (pv); 2147} 2148 2149static __inline pv_entry_t 2150pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2151{ 2152 pv_entry_t pv; 2153 2154 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2155 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2156 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2157 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2158 break; 2159 } 2160 } 2161 return (pv); 2162} 2163 2164static void 2165pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2166{ 2167 pv_entry_t pv; 2168 2169 pv = pmap_pvh_remove(pvh, pmap, va); 2170 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2171 free_pv_entry(pmap, pv); 2172} 2173 2174static void 2175pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2176{ 2177 2178 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2179 pmap_pvh_free(&m->md, pmap, va); 2180 if (TAILQ_EMPTY(&m->md.pv_list)) 2181 vm_page_flag_clear(m, PG_WRITEABLE); 2182} 2183 2184/* 2185 * Conditionally create a pv entry. 2186 */ 2187static boolean_t 2188pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2189{ 2190 pv_entry_t pv; 2191 2192 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2193 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2194 if (pv_entry_count < pv_entry_high_water && 2195 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2196 pv->pv_va = va; 2197 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2198 return (TRUE); 2199 } else 2200 return (FALSE); 2201} 2202 2203/* 2204 * pmap_remove_pte: do the things to unmap a page in a process 2205 */ 2206static int 2207pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2208{ 2209 pt_entry_t oldpte; 2210 vm_page_t m; 2211 2212 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2213 pmap, (u_long)*ptq, va); 2214 2215 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2216 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2217 oldpte = *ptq; 2218 PT_SET_VA_MA(ptq, 0, TRUE); 2219 if (oldpte & PG_W) 2220 pmap->pm_stats.wired_count -= 1; 2221 /* 2222 * Machines that don't support invlpg, also don't support 2223 * PG_G. 2224 */ 2225 if (oldpte & PG_G) 2226 pmap_invalidate_page(kernel_pmap, va); 2227 pmap->pm_stats.resident_count -= 1; 2228 if (oldpte & PG_MANAGED) { 2229 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2230 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2231 vm_page_dirty(m); 2232 if (oldpte & PG_A) 2233 vm_page_flag_set(m, PG_REFERENCED); 2234 pmap_remove_entry(pmap, m, va); 2235 } 2236 return (pmap_unuse_pt(pmap, va, free)); 2237} 2238 2239/* 2240 * Remove a single page from a process address space 2241 */ 2242static void 2243pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2244{ 2245 pt_entry_t *pte; 2246 2247 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2248 pmap, va); 2249 2250 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2251 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2252 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2253 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2254 return; 2255 pmap_remove_pte(pmap, pte, va, free); 2256 pmap_invalidate_page(pmap, va); 2257 if (*PMAP1) 2258 PT_SET_MA(PADDR1, 0); 2259 2260} 2261 2262/* 2263 * Remove the given range of addresses from the specified map. 2264 * 2265 * It is assumed that the start and end are properly 2266 * rounded to the page size. 2267 */ 2268void 2269pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2270{ 2271 vm_offset_t pdnxt; 2272 pd_entry_t ptpaddr; 2273 pt_entry_t *pte; 2274 vm_page_t free = NULL; 2275 int anyvalid; 2276 2277 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2278 pmap, sva, eva); 2279 2280 /* 2281 * Perform an unsynchronized read. This is, however, safe. 2282 */ 2283 if (pmap->pm_stats.resident_count == 0) 2284 return; 2285 2286 anyvalid = 0; 2287 2288 vm_page_lock_queues(); 2289 sched_pin(); 2290 PMAP_LOCK(pmap); 2291 2292 /* 2293 * special handling of removing one page. a very 2294 * common operation and easy to short circuit some 2295 * code. 2296 */ 2297 if ((sva + PAGE_SIZE == eva) && 2298 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2299 pmap_remove_page(pmap, sva, &free); 2300 goto out; 2301 } 2302 2303 for (; sva < eva; sva = pdnxt) { 2304 unsigned pdirindex; 2305 2306 /* 2307 * Calculate index for next page table. 2308 */ 2309 pdnxt = (sva + NBPDR) & ~PDRMASK; 2310 if (pmap->pm_stats.resident_count == 0) 2311 break; 2312 2313 pdirindex = sva >> PDRSHIFT; 2314 ptpaddr = pmap->pm_pdir[pdirindex]; 2315 2316 /* 2317 * Weed out invalid mappings. Note: we assume that the page 2318 * directory table is always allocated, and in kernel virtual. 2319 */ 2320 if (ptpaddr == 0) 2321 continue; 2322 2323 /* 2324 * Check for large page. 2325 */ 2326 if ((ptpaddr & PG_PS) != 0) { 2327 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2328 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2329 anyvalid = 1; 2330 continue; 2331 } 2332 2333 /* 2334 * Limit our scan to either the end of the va represented 2335 * by the current page table page, or to the end of the 2336 * range being removed. 2337 */ 2338 if (pdnxt > eva) 2339 pdnxt = eva; 2340 2341 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2342 sva += PAGE_SIZE) { 2343 if ((*pte & PG_V) == 0) 2344 continue; 2345 2346 /* 2347 * The TLB entry for a PG_G mapping is invalidated 2348 * by pmap_remove_pte(). 2349 */ 2350 if ((*pte & PG_G) == 0) 2351 anyvalid = 1; 2352 if (pmap_remove_pte(pmap, pte, sva, &free)) 2353 break; 2354 } 2355 } 2356 PT_UPDATES_FLUSH(); 2357 if (*PMAP1) 2358 PT_SET_VA_MA(PMAP1, 0, TRUE); 2359out: 2360 if (anyvalid) 2361 pmap_invalidate_all(pmap); 2362 sched_unpin(); 2363 vm_page_unlock_queues(); 2364 PMAP_UNLOCK(pmap); 2365 pmap_free_zero_pages(free); 2366} 2367 2368/* 2369 * Routine: pmap_remove_all 2370 * Function: 2371 * Removes this physical page from 2372 * all physical maps in which it resides. 2373 * Reflects back modify bits to the pager. 2374 * 2375 * Notes: 2376 * Original versions of this routine were very 2377 * inefficient because they iteratively called 2378 * pmap_remove (slow...) 2379 */ 2380 2381void 2382pmap_remove_all(vm_page_t m) 2383{ 2384 pv_entry_t pv; 2385 pmap_t pmap; 2386 pt_entry_t *pte, tpte; 2387 vm_page_t free; 2388 2389 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2390 ("pmap_remove_all: page %p is fictitious", m)); 2391 free = NULL; 2392 vm_page_lock_queues(); 2393 sched_pin(); 2394 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2395 pmap = PV_PMAP(pv); 2396 PMAP_LOCK(pmap); 2397 pmap->pm_stats.resident_count--; 2398 pte = pmap_pte_quick(pmap, pv->pv_va); 2399 2400 tpte = *pte; 2401 PT_SET_VA_MA(pte, 0, TRUE); 2402 if (tpte & PG_W) 2403 pmap->pm_stats.wired_count--; 2404 if (tpte & PG_A) 2405 vm_page_flag_set(m, PG_REFERENCED); 2406 2407 /* 2408 * Update the vm_page_t clean and reference bits. 2409 */ 2410 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2411 vm_page_dirty(m); 2412 pmap_unuse_pt(pmap, pv->pv_va, &free); 2413 pmap_invalidate_page(pmap, pv->pv_va); 2414 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2415 free_pv_entry(pmap, pv); 2416 PMAP_UNLOCK(pmap); 2417 } 2418 vm_page_flag_clear(m, PG_WRITEABLE); 2419 PT_UPDATES_FLUSH(); 2420 if (*PMAP1) 2421 PT_SET_MA(PADDR1, 0); 2422 sched_unpin(); 2423 vm_page_unlock_queues(); 2424 pmap_free_zero_pages(free); 2425} 2426 2427/* 2428 * Set the physical protection on the 2429 * specified range of this map as requested. 2430 */ 2431void 2432pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2433{ 2434 vm_offset_t pdnxt; 2435 pd_entry_t ptpaddr; 2436 pt_entry_t *pte; 2437 int anychanged; 2438 2439 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2440 pmap, sva, eva, prot); 2441 2442 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2443 pmap_remove(pmap, sva, eva); 2444 return; 2445 } 2446 2447#ifdef PAE 2448 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2449 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2450 return; 2451#else 2452 if (prot & VM_PROT_WRITE) 2453 return; 2454#endif 2455 2456 anychanged = 0; 2457 2458 vm_page_lock_queues(); 2459 sched_pin(); 2460 PMAP_LOCK(pmap); 2461 for (; sva < eva; sva = pdnxt) { 2462 pt_entry_t obits, pbits; 2463 unsigned pdirindex; 2464 2465 pdnxt = (sva + NBPDR) & ~PDRMASK; 2466 2467 pdirindex = sva >> PDRSHIFT; 2468 ptpaddr = pmap->pm_pdir[pdirindex]; 2469 2470 /* 2471 * Weed out invalid mappings. Note: we assume that the page 2472 * directory table is always allocated, and in kernel virtual. 2473 */ 2474 if (ptpaddr == 0) 2475 continue; 2476 2477 /* 2478 * Check for large page. 2479 */ 2480 if ((ptpaddr & PG_PS) != 0) { 2481 if ((prot & VM_PROT_WRITE) == 0) 2482 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2483#ifdef PAE 2484 if ((prot & VM_PROT_EXECUTE) == 0) 2485 pmap->pm_pdir[pdirindex] |= pg_nx; 2486#endif 2487 anychanged = 1; 2488 continue; 2489 } 2490 2491 if (pdnxt > eva) 2492 pdnxt = eva; 2493 2494 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2495 sva += PAGE_SIZE) { 2496 vm_page_t m; 2497 2498retry: 2499 /* 2500 * Regardless of whether a pte is 32 or 64 bits in 2501 * size, PG_RW, PG_A, and PG_M are among the least 2502 * significant 32 bits. 2503 */ 2504 obits = pbits = *pte; 2505 if ((pbits & PG_V) == 0) 2506 continue; 2507 2508 if ((prot & VM_PROT_WRITE) == 0) { 2509 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2510 (PG_MANAGED | PG_M | PG_RW)) { 2511 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2512 PG_FRAME); 2513 vm_page_dirty(m); 2514 } 2515 pbits &= ~(PG_RW | PG_M); 2516 } 2517#ifdef PAE 2518 if ((prot & VM_PROT_EXECUTE) == 0) 2519 pbits |= pg_nx; 2520#endif 2521 2522 if (pbits != obits) { 2523 obits = *pte; 2524 PT_SET_VA_MA(pte, pbits, TRUE); 2525 if (*pte != pbits) 2526 goto retry; 2527 if (obits & PG_G) 2528 pmap_invalidate_page(pmap, sva); 2529 else 2530 anychanged = 1; 2531 } 2532 } 2533 } 2534 PT_UPDATES_FLUSH(); 2535 if (*PMAP1) 2536 PT_SET_VA_MA(PMAP1, 0, TRUE); 2537 if (anychanged) 2538 pmap_invalidate_all(pmap); 2539 sched_unpin(); 2540 vm_page_unlock_queues(); 2541 PMAP_UNLOCK(pmap); 2542} 2543 2544/* 2545 * Insert the given physical page (p) at 2546 * the specified virtual address (v) in the 2547 * target physical map with the protection requested. 2548 * 2549 * If specified, the page will be wired down, meaning 2550 * that the related pte can not be reclaimed. 2551 * 2552 * NB: This is the only routine which MAY NOT lazy-evaluate 2553 * or lose information. That is, this routine must actually 2554 * insert this page into the given map NOW. 2555 */ 2556void 2557pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2558 vm_prot_t prot, boolean_t wired) 2559{ 2560 pd_entry_t *pde; 2561 pt_entry_t *pte; 2562 pt_entry_t newpte, origpte; 2563 pv_entry_t pv; 2564 vm_paddr_t opa, pa; 2565 vm_page_t mpte, om; 2566 boolean_t invlva; 2567 2568 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2569 pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2570 va = trunc_page(va); 2571 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2572 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2573 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2574 va)); 2575 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 2576 (m->oflags & VPO_BUSY) != 0, 2577 ("pmap_enter: page %p is not busy", m)); 2578 2579 mpte = NULL; 2580 2581 vm_page_lock_queues(); 2582 PMAP_LOCK(pmap); 2583 sched_pin(); 2584 2585 /* 2586 * In the case that a page table page is not 2587 * resident, we are creating it here. 2588 */ 2589 if (va < VM_MAXUSER_ADDRESS) { 2590 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2591 } 2592 2593 pde = pmap_pde(pmap, va); 2594 if ((*pde & PG_PS) != 0) 2595 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2596 pte = pmap_pte_quick(pmap, va); 2597 2598 /* 2599 * Page Directory table entry not valid, we need a new PT page 2600 */ 2601 if (pte == NULL) { 2602 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2603 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2604 } 2605 2606 pa = VM_PAGE_TO_PHYS(m); 2607 om = NULL; 2608 opa = origpte = 0; 2609 2610#if 0 2611 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2612 pte, *pte)); 2613#endif 2614 origpte = *pte; 2615 if (origpte) 2616 origpte = xpmap_mtop(origpte); 2617 opa = origpte & PG_FRAME; 2618 2619 /* 2620 * Mapping has not changed, must be protection or wiring change. 2621 */ 2622 if (origpte && (opa == pa)) { 2623 /* 2624 * Wiring change, just update stats. We don't worry about 2625 * wiring PT pages as they remain resident as long as there 2626 * are valid mappings in them. Hence, if a user page is wired, 2627 * the PT page will be also. 2628 */ 2629 if (wired && ((origpte & PG_W) == 0)) 2630 pmap->pm_stats.wired_count++; 2631 else if (!wired && (origpte & PG_W)) 2632 pmap->pm_stats.wired_count--; 2633 2634 /* 2635 * Remove extra pte reference 2636 */ 2637 if (mpte) 2638 mpte->wire_count--; 2639 2640 if (origpte & PG_MANAGED) { 2641 om = m; 2642 pa |= PG_MANAGED; 2643 } 2644 goto validate; 2645 } 2646 2647 pv = NULL; 2648 2649 /* 2650 * Mapping has changed, invalidate old range and fall through to 2651 * handle validating new mapping. 2652 */ 2653 if (opa) { 2654 if (origpte & PG_W) 2655 pmap->pm_stats.wired_count--; 2656 if (origpte & PG_MANAGED) { 2657 om = PHYS_TO_VM_PAGE(opa); 2658 pv = pmap_pvh_remove(&om->md, pmap, va); 2659 } else if (va < VM_MAXUSER_ADDRESS) 2660 printf("va=0x%x is unmanaged :-( \n", va); 2661 2662 if (mpte != NULL) { 2663 mpte->wire_count--; 2664 KASSERT(mpte->wire_count > 0, 2665 ("pmap_enter: missing reference to page table page," 2666 " va: 0x%x", va)); 2667 } 2668 } else 2669 pmap->pm_stats.resident_count++; 2670 2671 /* 2672 * Enter on the PV list if part of our managed memory. 2673 */ 2674 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 2675 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2676 ("pmap_enter: managed mapping within the clean submap")); 2677 if (pv == NULL) 2678 pv = get_pv_entry(pmap, FALSE); 2679 pv->pv_va = va; 2680 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2681 pa |= PG_MANAGED; 2682 } else if (pv != NULL) 2683 free_pv_entry(pmap, pv); 2684 2685 /* 2686 * Increment counters 2687 */ 2688 if (wired) 2689 pmap->pm_stats.wired_count++; 2690 2691validate: 2692 /* 2693 * Now validate mapping with desired protection/wiring. 2694 */ 2695 newpte = (pt_entry_t)(pa | PG_V); 2696 if ((prot & VM_PROT_WRITE) != 0) { 2697 newpte |= PG_RW; 2698 if ((newpte & PG_MANAGED) != 0) 2699 vm_page_flag_set(m, PG_WRITEABLE); 2700 } 2701#ifdef PAE 2702 if ((prot & VM_PROT_EXECUTE) == 0) 2703 newpte |= pg_nx; 2704#endif 2705 if (wired) 2706 newpte |= PG_W; 2707 if (va < VM_MAXUSER_ADDRESS) 2708 newpte |= PG_U; 2709 if (pmap == kernel_pmap) 2710 newpte |= pgeflag; 2711 2712 critical_enter(); 2713 /* 2714 * if the mapping or permission bits are different, we need 2715 * to update the pte. 2716 */ 2717 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2718 if (origpte) { 2719 invlva = FALSE; 2720 origpte = *pte; 2721 PT_SET_VA(pte, newpte | PG_A, FALSE); 2722 if (origpte & PG_A) { 2723 if (origpte & PG_MANAGED) 2724 vm_page_flag_set(om, PG_REFERENCED); 2725 if (opa != VM_PAGE_TO_PHYS(m)) 2726 invlva = TRUE; 2727#ifdef PAE 2728 if ((origpte & PG_NX) == 0 && 2729 (newpte & PG_NX) != 0) 2730 invlva = TRUE; 2731#endif 2732 } 2733 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2734 if ((origpte & PG_MANAGED) != 0) 2735 vm_page_dirty(om); 2736 if ((prot & VM_PROT_WRITE) == 0) 2737 invlva = TRUE; 2738 } 2739 if ((origpte & PG_MANAGED) != 0 && 2740 TAILQ_EMPTY(&om->md.pv_list)) 2741 vm_page_flag_clear(om, PG_WRITEABLE); 2742 if (invlva) 2743 pmap_invalidate_page(pmap, va); 2744 } else{ 2745 PT_SET_VA(pte, newpte | PG_A, FALSE); 2746 } 2747 2748 } 2749 PT_UPDATES_FLUSH(); 2750 critical_exit(); 2751 if (*PMAP1) 2752 PT_SET_VA_MA(PMAP1, 0, TRUE); 2753 sched_unpin(); 2754 vm_page_unlock_queues(); 2755 PMAP_UNLOCK(pmap); 2756} 2757 2758/* 2759 * Maps a sequence of resident pages belonging to the same object. 2760 * The sequence begins with the given page m_start. This page is 2761 * mapped at the given virtual address start. Each subsequent page is 2762 * mapped at a virtual address that is offset from start by the same 2763 * amount as the page is offset from m_start within the object. The 2764 * last page in the sequence is the page with the largest offset from 2765 * m_start that can be mapped at a virtual address less than the given 2766 * virtual address end. Not every virtual page between start and end 2767 * is mapped; only those for which a resident page exists with the 2768 * corresponding offset from m_start are mapped. 2769 */ 2770void 2771pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2772 vm_page_t m_start, vm_prot_t prot) 2773{ 2774 vm_page_t m, mpte; 2775 vm_pindex_t diff, psize; 2776 multicall_entry_t mcl[16]; 2777 multicall_entry_t *mclp = mcl; 2778 int error, count = 0; 2779 2780 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2781 psize = atop(end - start); 2782 2783 mpte = NULL; 2784 m = m_start; 2785 vm_page_lock_queues(); 2786 PMAP_LOCK(pmap); 2787 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2788 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2789 prot, mpte); 2790 m = TAILQ_NEXT(m, listq); 2791 if (count == 16) { 2792 error = HYPERVISOR_multicall(mcl, count); 2793 KASSERT(error == 0, ("bad multicall %d", error)); 2794 mclp = mcl; 2795 count = 0; 2796 } 2797 } 2798 if (count) { 2799 error = HYPERVISOR_multicall(mcl, count); 2800 KASSERT(error == 0, ("bad multicall %d", error)); 2801 } 2802 vm_page_unlock_queues(); 2803 PMAP_UNLOCK(pmap); 2804} 2805 2806/* 2807 * this code makes some *MAJOR* assumptions: 2808 * 1. Current pmap & pmap exists. 2809 * 2. Not wired. 2810 * 3. Read access. 2811 * 4. No page table pages. 2812 * but is *MUCH* faster than pmap_enter... 2813 */ 2814 2815void 2816pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2817{ 2818 multicall_entry_t mcl, *mclp; 2819 int count = 0; 2820 mclp = &mcl; 2821 2822 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2823 pmap, va, m, prot); 2824 2825 vm_page_lock_queues(); 2826 PMAP_LOCK(pmap); 2827 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2828 if (count) 2829 HYPERVISOR_multicall(&mcl, count); 2830 vm_page_unlock_queues(); 2831 PMAP_UNLOCK(pmap); 2832} 2833 2834#ifdef notyet 2835void 2836pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2837{ 2838 int i, error, index = 0; 2839 multicall_entry_t mcl[16]; 2840 multicall_entry_t *mclp = mcl; 2841 2842 PMAP_LOCK(pmap); 2843 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2844 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2845 continue; 2846 2847 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2848 if (index == 16) { 2849 error = HYPERVISOR_multicall(mcl, index); 2850 mclp = mcl; 2851 index = 0; 2852 KASSERT(error == 0, ("bad multicall %d", error)); 2853 } 2854 } 2855 if (index) { 2856 error = HYPERVISOR_multicall(mcl, index); 2857 KASSERT(error == 0, ("bad multicall %d", error)); 2858 } 2859 2860 PMAP_UNLOCK(pmap); 2861} 2862#endif 2863 2864static vm_page_t 2865pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2866 vm_prot_t prot, vm_page_t mpte) 2867{ 2868 pt_entry_t *pte; 2869 vm_paddr_t pa; 2870 vm_page_t free; 2871 multicall_entry_t *mcl = *mclpp; 2872 2873 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2874 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 2875 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2876 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2877 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2878 2879 /* 2880 * In the case that a page table page is not 2881 * resident, we are creating it here. 2882 */ 2883 if (va < VM_MAXUSER_ADDRESS) { 2884 unsigned ptepindex; 2885 pd_entry_t ptema; 2886 2887 /* 2888 * Calculate pagetable page index 2889 */ 2890 ptepindex = va >> PDRSHIFT; 2891 if (mpte && (mpte->pindex == ptepindex)) { 2892 mpte->wire_count++; 2893 } else { 2894 /* 2895 * Get the page directory entry 2896 */ 2897 ptema = pmap->pm_pdir[ptepindex]; 2898 2899 /* 2900 * If the page table page is mapped, we just increment 2901 * the hold count, and activate it. 2902 */ 2903 if (ptema & PG_V) { 2904 if (ptema & PG_PS) 2905 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2906 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2907 mpte->wire_count++; 2908 } else { 2909 mpte = _pmap_allocpte(pmap, ptepindex, 2910 M_NOWAIT); 2911 if (mpte == NULL) 2912 return (mpte); 2913 } 2914 } 2915 } else { 2916 mpte = NULL; 2917 } 2918 2919 /* 2920 * This call to vtopte makes the assumption that we are 2921 * entering the page into the current pmap. In order to support 2922 * quick entry into any pmap, one would likely use pmap_pte_quick. 2923 * But that isn't as quick as vtopte. 2924 */ 2925 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 2926 pte = vtopte(va); 2927 if (*pte & PG_V) { 2928 if (mpte != NULL) { 2929 mpte->wire_count--; 2930 mpte = NULL; 2931 } 2932 return (mpte); 2933 } 2934 2935 /* 2936 * Enter on the PV list if part of our managed memory. 2937 */ 2938 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 2939 !pmap_try_insert_pv_entry(pmap, va, m)) { 2940 if (mpte != NULL) { 2941 free = NULL; 2942 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 2943 pmap_invalidate_page(pmap, va); 2944 pmap_free_zero_pages(free); 2945 } 2946 2947 mpte = NULL; 2948 } 2949 return (mpte); 2950 } 2951 2952 /* 2953 * Increment counters 2954 */ 2955 pmap->pm_stats.resident_count++; 2956 2957 pa = VM_PAGE_TO_PHYS(m); 2958#ifdef PAE 2959 if ((prot & VM_PROT_EXECUTE) == 0) 2960 pa |= pg_nx; 2961#endif 2962 2963#if 0 2964 /* 2965 * Now validate mapping with RO protection 2966 */ 2967 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 2968 pte_store(pte, pa | PG_V | PG_U); 2969 else 2970 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 2971#else 2972 /* 2973 * Now validate mapping with RO protection 2974 */ 2975 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 2976 pa = xpmap_ptom(pa | PG_V | PG_U); 2977 else 2978 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 2979 2980 mcl->op = __HYPERVISOR_update_va_mapping; 2981 mcl->args[0] = va; 2982 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 2983 mcl->args[2] = (uint32_t)(pa >> 32); 2984 mcl->args[3] = 0; 2985 *mclpp = mcl + 1; 2986 *count = *count + 1; 2987#endif 2988 return mpte; 2989} 2990 2991/* 2992 * Make a temporary mapping for a physical address. This is only intended 2993 * to be used for panic dumps. 2994 */ 2995void * 2996pmap_kenter_temporary(vm_paddr_t pa, int i) 2997{ 2998 vm_offset_t va; 2999 vm_paddr_t ma = xpmap_ptom(pa); 3000 3001 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3002 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3003 invlpg(va); 3004 return ((void *)crashdumpmap); 3005} 3006 3007/* 3008 * This code maps large physical mmap regions into the 3009 * processor address space. Note that some shortcuts 3010 * are taken, but the code works. 3011 */ 3012void 3013pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 3014 vm_object_t object, vm_pindex_t pindex, 3015 vm_size_t size) 3016{ 3017 pd_entry_t *pde; 3018 vm_paddr_t pa, ptepa; 3019 vm_page_t p; 3020 int pat_mode; 3021 3022 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3023 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3024 ("pmap_object_init_pt: non-device object")); 3025 if (pseflag && 3026 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3027 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3028 return; 3029 p = vm_page_lookup(object, pindex); 3030 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3031 ("pmap_object_init_pt: invalid page %p", p)); 3032 pat_mode = p->md.pat_mode; 3033 /* 3034 * Abort the mapping if the first page is not physically 3035 * aligned to a 2/4MB page boundary. 3036 */ 3037 ptepa = VM_PAGE_TO_PHYS(p); 3038 if (ptepa & (NBPDR - 1)) 3039 return; 3040 /* 3041 * Skip the first page. Abort the mapping if the rest of 3042 * the pages are not physically contiguous or have differing 3043 * memory attributes. 3044 */ 3045 p = TAILQ_NEXT(p, listq); 3046 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3047 pa += PAGE_SIZE) { 3048 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3049 ("pmap_object_init_pt: invalid page %p", p)); 3050 if (pa != VM_PAGE_TO_PHYS(p) || 3051 pat_mode != p->md.pat_mode) 3052 return; 3053 p = TAILQ_NEXT(p, listq); 3054 } 3055 /* Map using 2/4MB pages. */ 3056 PMAP_LOCK(pmap); 3057 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3058 size; pa += NBPDR) { 3059 pde = pmap_pde(pmap, addr); 3060 if (*pde == 0) { 3061 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3062 PG_U | PG_RW | PG_V); 3063 pmap->pm_stats.resident_count += NBPDR / 3064 PAGE_SIZE; 3065 pmap_pde_mappings++; 3066 } 3067 /* Else continue on if the PDE is already valid. */ 3068 addr += NBPDR; 3069 } 3070 PMAP_UNLOCK(pmap); 3071 } 3072} 3073 3074/* 3075 * Routine: pmap_change_wiring 3076 * Function: Change the wiring attribute for a map/virtual-address 3077 * pair. 3078 * In/out conditions: 3079 * The mapping must already exist in the pmap. 3080 */ 3081void 3082pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3083{ 3084 pt_entry_t *pte; 3085 3086 vm_page_lock_queues(); 3087 PMAP_LOCK(pmap); 3088 pte = pmap_pte(pmap, va); 3089 3090 if (wired && !pmap_pte_w(pte)) { 3091 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3092 pmap->pm_stats.wired_count++; 3093 } else if (!wired && pmap_pte_w(pte)) { 3094 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3095 pmap->pm_stats.wired_count--; 3096 } 3097 3098 /* 3099 * Wiring is not a hardware characteristic so there is no need to 3100 * invalidate TLB. 3101 */ 3102 pmap_pte_release(pte); 3103 PMAP_UNLOCK(pmap); 3104 vm_page_unlock_queues(); 3105} 3106 3107 3108 3109/* 3110 * Copy the range specified by src_addr/len 3111 * from the source map to the range dst_addr/len 3112 * in the destination map. 3113 * 3114 * This routine is only advisory and need not do anything. 3115 */ 3116 3117void 3118pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3119 vm_offset_t src_addr) 3120{ 3121 vm_page_t free; 3122 vm_offset_t addr; 3123 vm_offset_t end_addr = src_addr + len; 3124 vm_offset_t pdnxt; 3125 3126 if (dst_addr != src_addr) 3127 return; 3128 3129 if (!pmap_is_current(src_pmap)) { 3130 CTR2(KTR_PMAP, 3131 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3132 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3133 3134 return; 3135 } 3136 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3137 dst_pmap, src_pmap, dst_addr, len, src_addr); 3138 3139 vm_page_lock_queues(); 3140 if (dst_pmap < src_pmap) { 3141 PMAP_LOCK(dst_pmap); 3142 PMAP_LOCK(src_pmap); 3143 } else { 3144 PMAP_LOCK(src_pmap); 3145 PMAP_LOCK(dst_pmap); 3146 } 3147 sched_pin(); 3148 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3149 pt_entry_t *src_pte, *dst_pte; 3150 vm_page_t dstmpte, srcmpte; 3151 pd_entry_t srcptepaddr; 3152 unsigned ptepindex; 3153 3154 KASSERT(addr < UPT_MIN_ADDRESS, 3155 ("pmap_copy: invalid to pmap_copy page tables")); 3156 3157 pdnxt = (addr + NBPDR) & ~PDRMASK; 3158 ptepindex = addr >> PDRSHIFT; 3159 3160 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3161 if (srcptepaddr == 0) 3162 continue; 3163 3164 if (srcptepaddr & PG_PS) { 3165 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3166 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3167 dst_pmap->pm_stats.resident_count += 3168 NBPDR / PAGE_SIZE; 3169 } 3170 continue; 3171 } 3172 3173 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3174 KASSERT(srcmpte->wire_count > 0, 3175 ("pmap_copy: source page table page is unused")); 3176 3177 if (pdnxt > end_addr) 3178 pdnxt = end_addr; 3179 3180 src_pte = vtopte(addr); 3181 while (addr < pdnxt) { 3182 pt_entry_t ptetemp; 3183 ptetemp = *src_pte; 3184 /* 3185 * we only virtual copy managed pages 3186 */ 3187 if ((ptetemp & PG_MANAGED) != 0) { 3188 dstmpte = pmap_allocpte(dst_pmap, addr, 3189 M_NOWAIT); 3190 if (dstmpte == NULL) 3191 break; 3192 dst_pte = pmap_pte_quick(dst_pmap, addr); 3193 if (*dst_pte == 0 && 3194 pmap_try_insert_pv_entry(dst_pmap, addr, 3195 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3196 /* 3197 * Clear the wired, modified, and 3198 * accessed (referenced) bits 3199 * during the copy. 3200 */ 3201 KASSERT(ptetemp != 0, ("src_pte not set")); 3202 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3203 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3204 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3205 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3206 dst_pmap->pm_stats.resident_count++; 3207 } else { 3208 free = NULL; 3209 if (pmap_unwire_pte_hold(dst_pmap, 3210 dstmpte, &free)) { 3211 pmap_invalidate_page(dst_pmap, 3212 addr); 3213 pmap_free_zero_pages(free); 3214 } 3215 } 3216 if (dstmpte->wire_count >= srcmpte->wire_count) 3217 break; 3218 } 3219 addr += PAGE_SIZE; 3220 src_pte++; 3221 } 3222 } 3223 PT_UPDATES_FLUSH(); 3224 sched_unpin(); 3225 vm_page_unlock_queues(); 3226 PMAP_UNLOCK(src_pmap); 3227 PMAP_UNLOCK(dst_pmap); 3228} 3229 3230static __inline void 3231pagezero(void *page) 3232{ 3233#if defined(I686_CPU) 3234 if (cpu_class == CPUCLASS_686) { 3235#if defined(CPU_ENABLE_SSE) 3236 if (cpu_feature & CPUID_SSE2) 3237 sse2_pagezero(page); 3238 else 3239#endif 3240 i686_pagezero(page); 3241 } else 3242#endif 3243 bzero(page, PAGE_SIZE); 3244} 3245 3246/* 3247 * pmap_zero_page zeros the specified hardware page by mapping 3248 * the page into KVM and using bzero to clear its contents. 3249 */ 3250void 3251pmap_zero_page(vm_page_t m) 3252{ 3253 struct sysmaps *sysmaps; 3254 3255 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3256 mtx_lock(&sysmaps->lock); 3257 if (*sysmaps->CMAP2) 3258 panic("pmap_zero_page: CMAP2 busy"); 3259 sched_pin(); 3260 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3261 pagezero(sysmaps->CADDR2); 3262 PT_SET_MA(sysmaps->CADDR2, 0); 3263 sched_unpin(); 3264 mtx_unlock(&sysmaps->lock); 3265} 3266 3267/* 3268 * pmap_zero_page_area zeros the specified hardware page by mapping 3269 * the page into KVM and using bzero to clear its contents. 3270 * 3271 * off and size may not cover an area beyond a single hardware page. 3272 */ 3273void 3274pmap_zero_page_area(vm_page_t m, int off, int size) 3275{ 3276 struct sysmaps *sysmaps; 3277 3278 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3279 mtx_lock(&sysmaps->lock); 3280 if (*sysmaps->CMAP2) 3281 panic("pmap_zero_page: CMAP2 busy"); 3282 sched_pin(); 3283 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3284 3285 if (off == 0 && size == PAGE_SIZE) 3286 pagezero(sysmaps->CADDR2); 3287 else 3288 bzero((char *)sysmaps->CADDR2 + off, size); 3289 PT_SET_MA(sysmaps->CADDR2, 0); 3290 sched_unpin(); 3291 mtx_unlock(&sysmaps->lock); 3292} 3293 3294/* 3295 * pmap_zero_page_idle zeros the specified hardware page by mapping 3296 * the page into KVM and using bzero to clear its contents. This 3297 * is intended to be called from the vm_pagezero process only and 3298 * outside of Giant. 3299 */ 3300void 3301pmap_zero_page_idle(vm_page_t m) 3302{ 3303 3304 if (*CMAP3) 3305 panic("pmap_zero_page: CMAP3 busy"); 3306 sched_pin(); 3307 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3308 pagezero(CADDR3); 3309 PT_SET_MA(CADDR3, 0); 3310 sched_unpin(); 3311} 3312 3313/* 3314 * pmap_copy_page copies the specified (machine independent) 3315 * page by mapping the page into virtual memory and using 3316 * bcopy to copy the page, one machine dependent page at a 3317 * time. 3318 */ 3319void 3320pmap_copy_page(vm_page_t src, vm_page_t dst) 3321{ 3322 struct sysmaps *sysmaps; 3323 3324 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3325 mtx_lock(&sysmaps->lock); 3326 if (*sysmaps->CMAP1) 3327 panic("pmap_copy_page: CMAP1 busy"); 3328 if (*sysmaps->CMAP2) 3329 panic("pmap_copy_page: CMAP2 busy"); 3330 sched_pin(); 3331 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3332 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3333 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3334 PT_SET_MA(sysmaps->CADDR1, 0); 3335 PT_SET_MA(sysmaps->CADDR2, 0); 3336 sched_unpin(); 3337 mtx_unlock(&sysmaps->lock); 3338} 3339 3340/* 3341 * Returns true if the pmap's pv is one of the first 3342 * 16 pvs linked to from this page. This count may 3343 * be changed upwards or downwards in the future; it 3344 * is only necessary that true be returned for a small 3345 * subset of pmaps for proper page aging. 3346 */ 3347boolean_t 3348pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3349{ 3350 pv_entry_t pv; 3351 int loops = 0; 3352 boolean_t rv; 3353 3354 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3355 ("pmap_page_exists_quick: page %p is not managed", m)); 3356 rv = FALSE; 3357 vm_page_lock_queues(); 3358 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3359 if (PV_PMAP(pv) == pmap) { 3360 rv = TRUE; 3361 break; 3362 } 3363 loops++; 3364 if (loops >= 16) 3365 break; 3366 } 3367 vm_page_unlock_queues(); 3368 return (rv); 3369} 3370 3371/* 3372 * pmap_page_wired_mappings: 3373 * 3374 * Return the number of managed mappings to the given physical page 3375 * that are wired. 3376 */ 3377int 3378pmap_page_wired_mappings(vm_page_t m) 3379{ 3380 pv_entry_t pv; 3381 pt_entry_t *pte; 3382 pmap_t pmap; 3383 int count; 3384 3385 count = 0; 3386 if ((m->flags & PG_FICTITIOUS) != 0) 3387 return (count); 3388 vm_page_lock_queues(); 3389 sched_pin(); 3390 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3391 pmap = PV_PMAP(pv); 3392 PMAP_LOCK(pmap); 3393 pte = pmap_pte_quick(pmap, pv->pv_va); 3394 if ((*pte & PG_W) != 0) 3395 count++; 3396 PMAP_UNLOCK(pmap); 3397 } 3398 sched_unpin(); 3399 vm_page_unlock_queues(); 3400 return (count); 3401} 3402 3403/* 3404 * Returns TRUE if the given page is mapped individually or as part of 3405 * a 4mpage. Otherwise, returns FALSE. 3406 */ 3407boolean_t 3408pmap_page_is_mapped(vm_page_t m) 3409{ 3410 boolean_t rv; 3411 3412 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 3413 return (FALSE); 3414 vm_page_lock_queues(); 3415 rv = !TAILQ_EMPTY(&m->md.pv_list) || 3416 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list); 3417 vm_page_unlock_queues(); 3418 return (rv); 3419} 3420 3421/* 3422 * Remove all pages from specified address space 3423 * this aids process exit speeds. Also, this code 3424 * is special cased for current process only, but 3425 * can have the more generic (and slightly slower) 3426 * mode enabled. This is much faster than pmap_remove 3427 * in the case of running down an entire address space. 3428 */ 3429void 3430pmap_remove_pages(pmap_t pmap) 3431{ 3432 pt_entry_t *pte, tpte; 3433 vm_page_t m, free = NULL; 3434 pv_entry_t pv; 3435 struct pv_chunk *pc, *npc; 3436 int field, idx; 3437 int32_t bit; 3438 uint32_t inuse, bitmask; 3439 int allfree; 3440 3441 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3442 3443 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3444 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3445 return; 3446 } 3447 vm_page_lock_queues(); 3448 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3449 PMAP_LOCK(pmap); 3450 sched_pin(); 3451 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3452 allfree = 1; 3453 for (field = 0; field < _NPCM; field++) { 3454 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 3455 while (inuse != 0) { 3456 bit = bsfl(inuse); 3457 bitmask = 1UL << bit; 3458 idx = field * 32 + bit; 3459 pv = &pc->pc_pventry[idx]; 3460 inuse &= ~bitmask; 3461 3462 pte = vtopte(pv->pv_va); 3463 tpte = *pte ? xpmap_mtop(*pte) : 0; 3464 3465 if (tpte == 0) { 3466 printf( 3467 "TPTE at %p IS ZERO @ VA %08x\n", 3468 pte, pv->pv_va); 3469 panic("bad pte"); 3470 } 3471 3472/* 3473 * We cannot remove wired pages from a process' mapping at this time 3474 */ 3475 if (tpte & PG_W) { 3476 allfree = 0; 3477 continue; 3478 } 3479 3480 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3481 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3482 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3483 m, (uintmax_t)m->phys_addr, 3484 (uintmax_t)tpte)); 3485 3486 KASSERT(m < &vm_page_array[vm_page_array_size], 3487 ("pmap_remove_pages: bad tpte %#jx", 3488 (uintmax_t)tpte)); 3489 3490 3491 PT_CLEAR_VA(pte, FALSE); 3492 3493 /* 3494 * Update the vm_page_t clean/reference bits. 3495 */ 3496 if (tpte & PG_M) 3497 vm_page_dirty(m); 3498 3499 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3500 if (TAILQ_EMPTY(&m->md.pv_list)) 3501 vm_page_flag_clear(m, PG_WRITEABLE); 3502 3503 pmap_unuse_pt(pmap, pv->pv_va, &free); 3504 3505 /* Mark free */ 3506 PV_STAT(pv_entry_frees++); 3507 PV_STAT(pv_entry_spare++); 3508 pv_entry_count--; 3509 pc->pc_map[field] |= bitmask; 3510 pmap->pm_stats.resident_count--; 3511 } 3512 } 3513 PT_UPDATES_FLUSH(); 3514 if (allfree) { 3515 PV_STAT(pv_entry_spare -= _NPCPV); 3516 PV_STAT(pc_chunk_count--); 3517 PV_STAT(pc_chunk_frees++); 3518 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3519 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 3520 pmap_qremove((vm_offset_t)pc, 1); 3521 vm_page_unwire(m, 0); 3522 vm_page_free(m); 3523 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 3524 } 3525 } 3526 PT_UPDATES_FLUSH(); 3527 if (*PMAP1) 3528 PT_SET_MA(PADDR1, 0); 3529 3530 sched_unpin(); 3531 pmap_invalidate_all(pmap); 3532 vm_page_unlock_queues(); 3533 PMAP_UNLOCK(pmap); 3534 pmap_free_zero_pages(free); 3535} 3536 3537/* 3538 * pmap_is_modified: 3539 * 3540 * Return whether or not the specified physical page was modified 3541 * in any physical maps. 3542 */ 3543boolean_t 3544pmap_is_modified(vm_page_t m) 3545{ 3546 pv_entry_t pv; 3547 pt_entry_t *pte; 3548 pmap_t pmap; 3549 boolean_t rv; 3550 3551 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3552 ("pmap_is_modified: page %p is not managed", m)); 3553 rv = FALSE; 3554 3555 /* 3556 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 3557 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 3558 * is clear, no PTEs can have PG_M set. 3559 */ 3560 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3561 if ((m->oflags & VPO_BUSY) == 0 && 3562 (m->flags & PG_WRITEABLE) == 0) 3563 return (rv); 3564 vm_page_lock_queues(); 3565 sched_pin(); 3566 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3567 pmap = PV_PMAP(pv); 3568 PMAP_LOCK(pmap); 3569 pte = pmap_pte_quick(pmap, pv->pv_va); 3570 rv = (*pte & PG_M) != 0; 3571 PMAP_UNLOCK(pmap); 3572 if (rv) 3573 break; 3574 } 3575 if (*PMAP1) 3576 PT_SET_MA(PADDR1, 0); 3577 sched_unpin(); 3578 vm_page_unlock_queues(); 3579 return (rv); 3580} 3581 3582/* 3583 * pmap_is_prefaultable: 3584 * 3585 * Return whether or not the specified virtual address is elgible 3586 * for prefault. 3587 */ 3588static boolean_t 3589pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3590{ 3591 pt_entry_t *pte; 3592 boolean_t rv = FALSE; 3593 3594 return (rv); 3595 3596 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3597 pte = vtopte(addr); 3598 rv = (*pte == 0); 3599 } 3600 return (rv); 3601} 3602 3603boolean_t 3604pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3605{ 3606 boolean_t rv; 3607 3608 PMAP_LOCK(pmap); 3609 rv = pmap_is_prefaultable_locked(pmap, addr); 3610 PMAP_UNLOCK(pmap); 3611 return (rv); 3612} 3613 3614boolean_t 3615pmap_is_referenced(vm_page_t m) 3616{ 3617 pv_entry_t pv; 3618 pt_entry_t *pte; 3619 pmap_t pmap; 3620 boolean_t rv; 3621 3622 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3623 ("pmap_is_referenced: page %p is not managed", m)); 3624 rv = FALSE; 3625 vm_page_lock_queues(); 3626 sched_pin(); 3627 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3628 pmap = PV_PMAP(pv); 3629 PMAP_LOCK(pmap); 3630 pte = pmap_pte_quick(pmap, pv->pv_va); 3631 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3632 PMAP_UNLOCK(pmap); 3633 if (rv) 3634 break; 3635 } 3636 if (*PMAP1) 3637 PT_SET_MA(PADDR1, 0); 3638 sched_unpin(); 3639 vm_page_unlock_queues(); 3640 return (rv); 3641} 3642 3643void 3644pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3645{ 3646 int i, npages = round_page(len) >> PAGE_SHIFT; 3647 for (i = 0; i < npages; i++) { 3648 pt_entry_t *pte; 3649 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3650 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3651 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3652 pmap_pte_release(pte); 3653 } 3654} 3655 3656void 3657pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3658{ 3659 int i, npages = round_page(len) >> PAGE_SHIFT; 3660 for (i = 0; i < npages; i++) { 3661 pt_entry_t *pte; 3662 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3663 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3664 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3665 pmap_pte_release(pte); 3666 } 3667} 3668 3669/* 3670 * Clear the write and modified bits in each of the given page's mappings. 3671 */ 3672void 3673pmap_remove_write(vm_page_t m) 3674{ 3675 pv_entry_t pv; 3676 pmap_t pmap; 3677 pt_entry_t oldpte, *pte; 3678 3679 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3680 ("pmap_remove_write: page %p is not managed", m)); 3681 3682 /* 3683 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 3684 * another thread while the object is locked. Thus, if PG_WRITEABLE 3685 * is clear, no page table entries need updating. 3686 */ 3687 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3688 if ((m->oflags & VPO_BUSY) == 0 && 3689 (m->flags & PG_WRITEABLE) == 0) 3690 return; 3691 vm_page_lock_queues(); 3692 sched_pin(); 3693 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3694 pmap = PV_PMAP(pv); 3695 PMAP_LOCK(pmap); 3696 pte = pmap_pte_quick(pmap, pv->pv_va); 3697retry: 3698 oldpte = *pte; 3699 if ((oldpte & PG_RW) != 0) { 3700 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3701 3702 /* 3703 * Regardless of whether a pte is 32 or 64 bits 3704 * in size, PG_RW and PG_M are among the least 3705 * significant 32 bits. 3706 */ 3707 PT_SET_VA_MA(pte, newpte, TRUE); 3708 if (*pte != newpte) 3709 goto retry; 3710 3711 if ((oldpte & PG_M) != 0) 3712 vm_page_dirty(m); 3713 pmap_invalidate_page(pmap, pv->pv_va); 3714 } 3715 PMAP_UNLOCK(pmap); 3716 } 3717 vm_page_flag_clear(m, PG_WRITEABLE); 3718 PT_UPDATES_FLUSH(); 3719 if (*PMAP1) 3720 PT_SET_MA(PADDR1, 0); 3721 sched_unpin(); 3722 vm_page_unlock_queues(); 3723} 3724 3725/* 3726 * pmap_ts_referenced: 3727 * 3728 * Return a count of reference bits for a page, clearing those bits. 3729 * It is not necessary for every reference bit to be cleared, but it 3730 * is necessary that 0 only be returned when there are truly no 3731 * reference bits set. 3732 * 3733 * XXX: The exact number of bits to check and clear is a matter that 3734 * should be tested and standardized at some point in the future for 3735 * optimal aging of shared pages. 3736 */ 3737int 3738pmap_ts_referenced(vm_page_t m) 3739{ 3740 pv_entry_t pv, pvf, pvn; 3741 pmap_t pmap; 3742 pt_entry_t *pte; 3743 int rtval = 0; 3744 3745 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3746 ("pmap_ts_referenced: page %p is not managed", m)); 3747 vm_page_lock_queues(); 3748 sched_pin(); 3749 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3750 pvf = pv; 3751 do { 3752 pvn = TAILQ_NEXT(pv, pv_list); 3753 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3754 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3755 pmap = PV_PMAP(pv); 3756 PMAP_LOCK(pmap); 3757 pte = pmap_pte_quick(pmap, pv->pv_va); 3758 if ((*pte & PG_A) != 0) { 3759 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3760 pmap_invalidate_page(pmap, pv->pv_va); 3761 rtval++; 3762 if (rtval > 4) 3763 pvn = NULL; 3764 } 3765 PMAP_UNLOCK(pmap); 3766 } while ((pv = pvn) != NULL && pv != pvf); 3767 } 3768 PT_UPDATES_FLUSH(); 3769 if (*PMAP1) 3770 PT_SET_MA(PADDR1, 0); 3771 3772 sched_unpin(); 3773 vm_page_unlock_queues(); 3774 return (rtval); 3775} 3776 3777/* 3778 * Clear the modify bits on the specified physical page. 3779 */ 3780void 3781pmap_clear_modify(vm_page_t m) 3782{ 3783 pv_entry_t pv; 3784 pmap_t pmap; 3785 pt_entry_t *pte; 3786 3787 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3788 ("pmap_clear_modify: page %p is not managed", m)); 3789 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3790 KASSERT((m->oflags & VPO_BUSY) == 0, 3791 ("pmap_clear_modify: page %p is busy", m)); 3792 3793 /* 3794 * If the page is not PG_WRITEABLE, then no PTEs can have PG_M set. 3795 * If the object containing the page is locked and the page is not 3796 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 3797 */ 3798 if ((m->flags & PG_WRITEABLE) == 0) 3799 return; 3800 vm_page_lock_queues(); 3801 sched_pin(); 3802 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3803 pmap = PV_PMAP(pv); 3804 PMAP_LOCK(pmap); 3805 pte = pmap_pte_quick(pmap, pv->pv_va); 3806 if ((*pte & PG_M) != 0) { 3807 /* 3808 * Regardless of whether a pte is 32 or 64 bits 3809 * in size, PG_M is among the least significant 3810 * 32 bits. 3811 */ 3812 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3813 pmap_invalidate_page(pmap, pv->pv_va); 3814 } 3815 PMAP_UNLOCK(pmap); 3816 } 3817 sched_unpin(); 3818 vm_page_unlock_queues(); 3819} 3820 3821/* 3822 * pmap_clear_reference: 3823 * 3824 * Clear the reference bit on the specified physical page. 3825 */ 3826void 3827pmap_clear_reference(vm_page_t m) 3828{ 3829 pv_entry_t pv; 3830 pmap_t pmap; 3831 pt_entry_t *pte; 3832 3833 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3834 ("pmap_clear_reference: page %p is not managed", m)); 3835 vm_page_lock_queues(); 3836 sched_pin(); 3837 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3838 pmap = PV_PMAP(pv); 3839 PMAP_LOCK(pmap); 3840 pte = pmap_pte_quick(pmap, pv->pv_va); 3841 if ((*pte & PG_A) != 0) { 3842 /* 3843 * Regardless of whether a pte is 32 or 64 bits 3844 * in size, PG_A is among the least significant 3845 * 32 bits. 3846 */ 3847 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3848 pmap_invalidate_page(pmap, pv->pv_va); 3849 } 3850 PMAP_UNLOCK(pmap); 3851 } 3852 sched_unpin(); 3853 vm_page_unlock_queues(); 3854} 3855 3856/* 3857 * Miscellaneous support routines follow 3858 */ 3859 3860/* 3861 * Map a set of physical memory pages into the kernel virtual 3862 * address space. Return a pointer to where it is mapped. This 3863 * routine is intended to be used for mapping device memory, 3864 * NOT real memory. 3865 */ 3866void * 3867pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 3868{ 3869 vm_offset_t va, offset; 3870 vm_size_t tmpsize; 3871 3872 offset = pa & PAGE_MASK; 3873 size = roundup(offset + size, PAGE_SIZE); 3874 pa = pa & PG_FRAME; 3875 3876 if (pa < KERNLOAD && pa + size <= KERNLOAD) 3877 va = KERNBASE + pa; 3878 else 3879 va = kmem_alloc_nofault(kernel_map, size); 3880 if (!va) 3881 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3882 3883 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 3884 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 3885 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 3886 pmap_invalidate_cache_range(va, va + size); 3887 return ((void *)(va + offset)); 3888} 3889 3890void * 3891pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3892{ 3893 3894 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 3895} 3896 3897void * 3898pmap_mapbios(vm_paddr_t pa, vm_size_t size) 3899{ 3900 3901 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 3902} 3903 3904void 3905pmap_unmapdev(vm_offset_t va, vm_size_t size) 3906{ 3907 vm_offset_t base, offset, tmpva; 3908 3909 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 3910 return; 3911 base = trunc_page(va); 3912 offset = va & PAGE_MASK; 3913 size = roundup(offset + size, PAGE_SIZE); 3914 critical_enter(); 3915 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 3916 pmap_kremove(tmpva); 3917 pmap_invalidate_range(kernel_pmap, va, tmpva); 3918 critical_exit(); 3919 kmem_free(kernel_map, base, size); 3920} 3921 3922/* 3923 * Sets the memory attribute for the specified page. 3924 */ 3925void 3926pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 3927{ 3928 struct sysmaps *sysmaps; 3929 vm_offset_t sva, eva; 3930 3931 m->md.pat_mode = ma; 3932 if ((m->flags & PG_FICTITIOUS) != 0) 3933 return; 3934 3935 /* 3936 * If "m" is a normal page, flush it from the cache. 3937 * See pmap_invalidate_cache_range(). 3938 * 3939 * First, try to find an existing mapping of the page by sf 3940 * buffer. sf_buf_invalidate_cache() modifies mapping and 3941 * flushes the cache. 3942 */ 3943 if (sf_buf_invalidate_cache(m)) 3944 return; 3945 3946 /* 3947 * If page is not mapped by sf buffer, but CPU does not 3948 * support self snoop, map the page transient and do 3949 * invalidation. In the worst case, whole cache is flushed by 3950 * pmap_invalidate_cache_range(). 3951 */ 3952 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 3953 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3954 mtx_lock(&sysmaps->lock); 3955 if (*sysmaps->CMAP2) 3956 panic("pmap_page_set_memattr: CMAP2 busy"); 3957 sched_pin(); 3958 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 3959 VM_PAGE_TO_MACH(m) | PG_A | PG_M | 3960 pmap_cache_bits(m->md.pat_mode, 0)); 3961 invlcaddr(sysmaps->CADDR2); 3962 sva = (vm_offset_t)sysmaps->CADDR2; 3963 eva = sva + PAGE_SIZE; 3964 } else 3965 sva = eva = 0; /* gcc */ 3966 pmap_invalidate_cache_range(sva, eva); 3967 if (sva != 0) { 3968 PT_SET_MA(sysmaps->CADDR2, 0); 3969 sched_unpin(); 3970 mtx_unlock(&sysmaps->lock); 3971 } 3972} 3973 3974int 3975pmap_change_attr(va, size, mode) 3976 vm_offset_t va; 3977 vm_size_t size; 3978 int mode; 3979{ 3980 vm_offset_t base, offset, tmpva; 3981 pt_entry_t *pte; 3982 u_int opte, npte; 3983 pd_entry_t *pde; 3984 boolean_t changed; 3985 3986 base = trunc_page(va); 3987 offset = va & PAGE_MASK; 3988 size = roundup(offset + size, PAGE_SIZE); 3989 3990 /* Only supported on kernel virtual addresses. */ 3991 if (base <= VM_MAXUSER_ADDRESS) 3992 return (EINVAL); 3993 3994 /* 4MB pages and pages that aren't mapped aren't supported. */ 3995 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 3996 pde = pmap_pde(kernel_pmap, tmpva); 3997 if (*pde & PG_PS) 3998 return (EINVAL); 3999 if ((*pde & PG_V) == 0) 4000 return (EINVAL); 4001 pte = vtopte(va); 4002 if ((*pte & PG_V) == 0) 4003 return (EINVAL); 4004 } 4005 4006 changed = FALSE; 4007 4008 /* 4009 * Ok, all the pages exist and are 4k, so run through them updating 4010 * their cache mode. 4011 */ 4012 for (tmpva = base; size > 0; ) { 4013 pte = vtopte(tmpva); 4014 4015 /* 4016 * The cache mode bits are all in the low 32-bits of the 4017 * PTE, so we can just spin on updating the low 32-bits. 4018 */ 4019 do { 4020 opte = *(u_int *)pte; 4021 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4022 npte |= pmap_cache_bits(mode, 0); 4023 PT_SET_VA_MA(pte, npte, TRUE); 4024 } while (npte != opte && (*pte != npte)); 4025 if (npte != opte) 4026 changed = TRUE; 4027 tmpva += PAGE_SIZE; 4028 size -= PAGE_SIZE; 4029 } 4030 4031 /* 4032 * Flush CPU caches to make sure any data isn't cached that shouldn't 4033 * be, etc. 4034 */ 4035 if (changed) { 4036 pmap_invalidate_range(kernel_pmap, base, tmpva); 4037 pmap_invalidate_cache_range(base, tmpva); 4038 } 4039 return (0); 4040} 4041 4042/* 4043 * perform the pmap work for mincore 4044 */ 4045int 4046pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4047{ 4048 pt_entry_t *ptep, pte; 4049 vm_paddr_t pa; 4050 int val; 4051 4052 PMAP_LOCK(pmap); 4053retry: 4054 ptep = pmap_pte(pmap, addr); 4055 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4056 pmap_pte_release(ptep); 4057 val = 0; 4058 if ((pte & PG_V) != 0) { 4059 val |= MINCORE_INCORE; 4060 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4061 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4062 if ((pte & PG_A) != 0) 4063 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4064 } 4065 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4066 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4067 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4068 pa = pte & PG_FRAME; 4069 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4070 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4071 goto retry; 4072 } else 4073 PA_UNLOCK_COND(*locked_pa); 4074 PMAP_UNLOCK(pmap); 4075 return (val); 4076} 4077 4078void 4079pmap_activate(struct thread *td) 4080{ 4081 pmap_t pmap, oldpmap; 4082 u_int32_t cr3; 4083 4084 critical_enter(); 4085 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4086 oldpmap = PCPU_GET(curpmap); 4087#if defined(SMP) 4088 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 4089 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 4090#else 4091 oldpmap->pm_active &= ~1; 4092 pmap->pm_active |= 1; 4093#endif 4094#ifdef PAE 4095 cr3 = vtophys(pmap->pm_pdpt); 4096#else 4097 cr3 = vtophys(pmap->pm_pdir); 4098#endif 4099 /* 4100 * pmap_activate is for the current thread on the current cpu 4101 */ 4102 td->td_pcb->pcb_cr3 = cr3; 4103 PT_UPDATES_FLUSH(); 4104 load_cr3(cr3); 4105 PCPU_SET(curpmap, pmap); 4106 critical_exit(); 4107} 4108 4109void 4110pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4111{ 4112} 4113 4114/* 4115 * Increase the starting virtual address of the given mapping if a 4116 * different alignment might result in more superpage mappings. 4117 */ 4118void 4119pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4120 vm_offset_t *addr, vm_size_t size) 4121{ 4122 vm_offset_t superpage_offset; 4123 4124 if (size < NBPDR) 4125 return; 4126 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4127 offset += ptoa(object->pg_color); 4128 superpage_offset = offset & PDRMASK; 4129 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4130 (*addr & PDRMASK) == superpage_offset) 4131 return; 4132 if ((*addr & PDRMASK) < superpage_offset) 4133 *addr = (*addr & ~PDRMASK) + superpage_offset; 4134 else 4135 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4136} 4137 4138void 4139pmap_suspend() 4140{ 4141 pmap_t pmap; 4142 int i, pdir, offset; 4143 vm_paddr_t pdirma; 4144 mmu_update_t mu[4]; 4145 4146 /* 4147 * We need to remove the recursive mapping structure from all 4148 * our pmaps so that Xen doesn't get confused when it restores 4149 * the page tables. The recursive map lives at page directory 4150 * index PTDPTDI. We assume that the suspend code has stopped 4151 * the other vcpus (if any). 4152 */ 4153 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4154 for (i = 0; i < 4; i++) { 4155 /* 4156 * Figure out which page directory (L2) page 4157 * contains this bit of the recursive map and 4158 * the offset within that page of the map 4159 * entry 4160 */ 4161 pdir = (PTDPTDI + i) / NPDEPG; 4162 offset = (PTDPTDI + i) % NPDEPG; 4163 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4164 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4165 mu[i].val = 0; 4166 } 4167 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4168 } 4169} 4170 4171void 4172pmap_resume() 4173{ 4174 pmap_t pmap; 4175 int i, pdir, offset; 4176 vm_paddr_t pdirma; 4177 mmu_update_t mu[4]; 4178 4179 /* 4180 * Restore the recursive map that we removed on suspend. 4181 */ 4182 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4183 for (i = 0; i < 4; i++) { 4184 /* 4185 * Figure out which page directory (L2) page 4186 * contains this bit of the recursive map and 4187 * the offset within that page of the map 4188 * entry 4189 */ 4190 pdir = (PTDPTDI + i) / NPDEPG; 4191 offset = (PTDPTDI + i) % NPDEPG; 4192 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4193 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4194 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4195 } 4196 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4197 } 4198} 4199 4200#if defined(PMAP_DEBUG) 4201pmap_pid_dump(int pid) 4202{ 4203 pmap_t pmap; 4204 struct proc *p; 4205 int npte = 0; 4206 int index; 4207 4208 sx_slock(&allproc_lock); 4209 FOREACH_PROC_IN_SYSTEM(p) { 4210 if (p->p_pid != pid) 4211 continue; 4212 4213 if (p->p_vmspace) { 4214 int i,j; 4215 index = 0; 4216 pmap = vmspace_pmap(p->p_vmspace); 4217 for (i = 0; i < NPDEPTD; i++) { 4218 pd_entry_t *pde; 4219 pt_entry_t *pte; 4220 vm_offset_t base = i << PDRSHIFT; 4221 4222 pde = &pmap->pm_pdir[i]; 4223 if (pde && pmap_pde_v(pde)) { 4224 for (j = 0; j < NPTEPG; j++) { 4225 vm_offset_t va = base + (j << PAGE_SHIFT); 4226 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4227 if (index) { 4228 index = 0; 4229 printf("\n"); 4230 } 4231 sx_sunlock(&allproc_lock); 4232 return npte; 4233 } 4234 pte = pmap_pte(pmap, va); 4235 if (pte && pmap_pte_v(pte)) { 4236 pt_entry_t pa; 4237 vm_page_t m; 4238 pa = PT_GET(pte); 4239 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4240 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4241 va, pa, m->hold_count, m->wire_count, m->flags); 4242 npte++; 4243 index++; 4244 if (index >= 2) { 4245 index = 0; 4246 printf("\n"); 4247 } else { 4248 printf(" "); 4249 } 4250 } 4251 } 4252 } 4253 } 4254 } 4255 } 4256 sx_sunlock(&allproc_lock); 4257 return npte; 4258} 4259#endif 4260 4261#if defined(DEBUG) 4262 4263static void pads(pmap_t pm); 4264void pmap_pvdump(vm_paddr_t pa); 4265 4266/* print address space of pmap*/ 4267static void 4268pads(pmap_t pm) 4269{ 4270 int i, j; 4271 vm_paddr_t va; 4272 pt_entry_t *ptep; 4273 4274 if (pm == kernel_pmap) 4275 return; 4276 for (i = 0; i < NPDEPTD; i++) 4277 if (pm->pm_pdir[i]) 4278 for (j = 0; j < NPTEPG; j++) { 4279 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4280 if (pm == kernel_pmap && va < KERNBASE) 4281 continue; 4282 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4283 continue; 4284 ptep = pmap_pte(pm, va); 4285 if (pmap_pte_v(ptep)) 4286 printf("%x:%x ", va, *ptep); 4287 }; 4288 4289} 4290 4291void 4292pmap_pvdump(vm_paddr_t pa) 4293{ 4294 pv_entry_t pv; 4295 pmap_t pmap; 4296 vm_page_t m; 4297 4298 printf("pa %x", pa); 4299 m = PHYS_TO_VM_PAGE(pa); 4300 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4301 pmap = PV_PMAP(pv); 4302 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4303 pads(pmap); 4304 } 4305 printf(" "); 4306} 4307#endif 4308