pmap.c revision 215819
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 215819 2010-11-25 15:41:34Z cperciva $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_msgbuf.h" 109#include "opt_smp.h" 110#include "opt_xbox.h" 111 112#include <sys/param.h> 113#include <sys/systm.h> 114#include <sys/kernel.h> 115#include <sys/ktr.h> 116#include <sys/lock.h> 117#include <sys/malloc.h> 118#include <sys/mman.h> 119#include <sys/msgbuf.h> 120#include <sys/mutex.h> 121#include <sys/proc.h> 122#include <sys/sf_buf.h> 123#include <sys/sx.h> 124#include <sys/vmmeter.h> 125#include <sys/sched.h> 126#include <sys/sysctl.h> 127#ifdef SMP 128#include <sys/smp.h> 129#endif 130 131#include <vm/vm.h> 132#include <vm/vm_param.h> 133#include <vm/vm_kern.h> 134#include <vm/vm_page.h> 135#include <vm/vm_map.h> 136#include <vm/vm_object.h> 137#include <vm/vm_extern.h> 138#include <vm/vm_pageout.h> 139#include <vm/vm_pager.h> 140#include <vm/uma.h> 141 142#include <machine/cpu.h> 143#include <machine/cputypes.h> 144#include <machine/md_var.h> 145#include <machine/pcb.h> 146#include <machine/specialreg.h> 147#ifdef SMP 148#include <machine/smp.h> 149#endif 150 151#ifdef XBOX 152#include <machine/xbox.h> 153#endif 154 155#include <xen/interface/xen.h> 156#include <xen/hypervisor.h> 157#include <machine/xen/hypercall.h> 158#include <machine/xen/xenvar.h> 159#include <machine/xen/xenfunc.h> 160 161#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 162#define CPU_ENABLE_SSE 163#endif 164 165#ifndef PMAP_SHPGPERPROC 166#define PMAP_SHPGPERPROC 200 167#endif 168 169#define DIAGNOSTIC 170 171#if !defined(DIAGNOSTIC) 172#ifdef __GNUC_GNU_INLINE__ 173#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 174#else 175#define PMAP_INLINE extern inline 176#endif 177#else 178#define PMAP_INLINE 179#endif 180 181#define PV_STATS 182#ifdef PV_STATS 183#define PV_STAT(x) do { x ; } while (0) 184#else 185#define PV_STAT(x) do { } while (0) 186#endif 187 188#define pa_index(pa) ((pa) >> PDRSHIFT) 189#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 190 191/* 192 * Get PDEs and PTEs for user/kernel address space 193 */ 194#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 195#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 196 197#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 198#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 199#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 200#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 201#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 202 203#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 204 205struct pmap kernel_pmap_store; 206LIST_HEAD(pmaplist, pmap); 207static struct pmaplist allpmaps; 208static struct mtx allpmaps_lock; 209 210vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 211vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 212int pgeflag = 0; /* PG_G or-in */ 213int pseflag = 0; /* PG_PS or-in */ 214 215int nkpt; 216vm_offset_t kernel_vm_end; 217extern u_int32_t KERNend; 218 219#ifdef PAE 220pt_entry_t pg_nx; 221#endif 222 223static int pat_works; /* Is page attribute table sane? */ 224 225/* 226 * Data for the pv entry allocation mechanism 227 */ 228static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 229static struct md_page *pv_table; 230static int shpgperproc = PMAP_SHPGPERPROC; 231 232struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 233int pv_maxchunks; /* How many chunks we have KVA for */ 234vm_offset_t pv_vafree; /* freelist stored in the PTE */ 235 236/* 237 * All those kernel PT submaps that BSD is so fond of 238 */ 239struct sysmaps { 240 struct mtx lock; 241 pt_entry_t *CMAP1; 242 pt_entry_t *CMAP2; 243 caddr_t CADDR1; 244 caddr_t CADDR2; 245}; 246static struct sysmaps sysmaps_pcpu[MAXCPU]; 247static pt_entry_t *CMAP3; 248caddr_t ptvmmap = 0; 249static caddr_t CADDR3; 250struct msgbuf *msgbufp = 0; 251 252/* 253 * Crashdump maps. 254 */ 255static caddr_t crashdumpmap; 256 257static pt_entry_t *PMAP1 = 0, *PMAP2; 258static pt_entry_t *PADDR1 = 0, *PADDR2; 259#ifdef SMP 260static int PMAP1cpu; 261static int PMAP1changedcpu; 262SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 263 &PMAP1changedcpu, 0, 264 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 265#endif 266static int PMAP1changed; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 268 &PMAP1changed, 0, 269 "Number of times pmap_pte_quick changed PMAP1"); 270static int PMAP1unchanged; 271SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 272 &PMAP1unchanged, 0, 273 "Number of times pmap_pte_quick didn't change PMAP1"); 274static struct mtx PMAP2mutex; 275 276SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 277static int pg_ps_enabled; 278SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 279 "Are large page mappings enabled?"); 280 281SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 282 "Max number of PV entries"); 283SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 284 "Page share factor per proc"); 285SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 286 "2/4MB page mapping counters"); 287 288static u_long pmap_pde_mappings; 289SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 290 &pmap_pde_mappings, 0, "2/4MB page mappings"); 291 292static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 293static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 294static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 295static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 296 vm_offset_t va); 297 298static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 299 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 300static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 301 vm_page_t *free); 302static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 303 vm_page_t *free); 304static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 305 vm_offset_t va); 306static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 307 vm_page_t m); 308 309static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 310 311static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 312static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 313static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 314static void pmap_pte_release(pt_entry_t *pte); 315static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 316static vm_offset_t pmap_kmem_choose(vm_offset_t addr); 317static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 318static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 319 320static __inline void pagezero(void *page); 321 322CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 323CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 324 325/* 326 * If you get an error here, then you set KVA_PAGES wrong! See the 327 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 328 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 329 */ 330CTASSERT(KERNBASE % (1 << 24) == 0); 331 332 333 334void 335pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 336{ 337 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 338 339 switch (type) { 340 case SH_PD_SET_VA: 341#if 0 342 xen_queue_pt_update(shadow_pdir_ma, 343 xpmap_ptom(val & ~(PG_RW))); 344#endif 345 xen_queue_pt_update(pdir_ma, 346 xpmap_ptom(val)); 347 break; 348 case SH_PD_SET_VA_MA: 349#if 0 350 xen_queue_pt_update(shadow_pdir_ma, 351 val & ~(PG_RW)); 352#endif 353 xen_queue_pt_update(pdir_ma, val); 354 break; 355 case SH_PD_SET_VA_CLEAR: 356#if 0 357 xen_queue_pt_update(shadow_pdir_ma, 0); 358#endif 359 xen_queue_pt_update(pdir_ma, 0); 360 break; 361 } 362} 363 364/* 365 * Move the kernel virtual free pointer to the next 366 * 4MB. This is used to help improve performance 367 * by using a large (4MB) page for much of the kernel 368 * (.text, .data, .bss) 369 */ 370static vm_offset_t 371pmap_kmem_choose(vm_offset_t addr) 372{ 373 vm_offset_t newaddr = addr; 374 375#ifndef DISABLE_PSE 376 if (cpu_feature & CPUID_PSE) 377 newaddr = (addr + PDRMASK) & ~PDRMASK; 378#endif 379 return newaddr; 380} 381 382/* 383 * Bootstrap the system enough to run with virtual memory. 384 * 385 * On the i386 this is called after mapping has already been enabled 386 * and just syncs the pmap module with what has already been done. 387 * [We can't call it easily with mapping off since the kernel is not 388 * mapped with PA == VA, hence we would have to relocate every address 389 * from the linked base (virtual) address "KERNBASE" to the actual 390 * (physical) address starting relative to 0] 391 */ 392void 393pmap_bootstrap(vm_paddr_t firstaddr) 394{ 395 vm_offset_t va; 396 pt_entry_t *pte, *unused; 397 struct sysmaps *sysmaps; 398 int i; 399 400 /* 401 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 402 * large. It should instead be correctly calculated in locore.s and 403 * not based on 'first' (which is a physical address, not a virtual 404 * address, for the start of unused physical memory). The kernel 405 * page tables are NOT double mapped and thus should not be included 406 * in this calculation. 407 */ 408 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 409 virtual_avail = pmap_kmem_choose(virtual_avail); 410 411 virtual_end = VM_MAX_KERNEL_ADDRESS; 412 413 /* 414 * Initialize the kernel pmap (which is statically allocated). 415 */ 416 PMAP_LOCK_INIT(kernel_pmap); 417 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 418#ifdef PAE 419 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 420#endif 421 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 422 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 423 LIST_INIT(&allpmaps); 424 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 425 mtx_lock_spin(&allpmaps_lock); 426 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 427 mtx_unlock_spin(&allpmaps_lock); 428 if (nkpt == 0) 429 nkpt = NKPT; 430 431 /* 432 * Reserve some special page table entries/VA space for temporary 433 * mapping of pages. 434 */ 435#define SYSMAP(c, p, v, n) \ 436 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 437 438 va = virtual_avail; 439 pte = vtopte(va); 440 441 /* 442 * CMAP1/CMAP2 are used for zeroing and copying pages. 443 * CMAP3 is used for the idle process page zeroing. 444 */ 445 for (i = 0; i < MAXCPU; i++) { 446 sysmaps = &sysmaps_pcpu[i]; 447 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 448 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 449 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 450 PT_SET_MA(sysmaps->CADDR1, 0); 451 PT_SET_MA(sysmaps->CADDR2, 0); 452 } 453 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 454 PT_SET_MA(CADDR3, 0); 455 456 /* 457 * Crashdump maps. 458 */ 459 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 460 461 /* 462 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 463 */ 464 SYSMAP(caddr_t, unused, ptvmmap, 1) 465 466 /* 467 * msgbufp is used to map the system message buffer. 468 */ 469 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 470 471 /* 472 * ptemap is used for pmap_pte_quick 473 */ 474 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1); 475 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1); 476 477 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 478 479 virtual_avail = va; 480 481 /* 482 * Leave in place an identity mapping (virt == phys) for the low 1 MB 483 * physical memory region that is used by the ACPI wakeup code. This 484 * mapping must not have PG_G set. 485 */ 486#ifndef XEN 487 /* 488 * leave here deliberately to show that this is not supported 489 */ 490#ifdef XBOX 491 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 492 * an early stadium, we cannot yet neatly map video memory ... :-( 493 * Better fixes are very welcome! */ 494 if (!arch_i386_is_xbox) 495#endif 496 for (i = 1; i < NKPT; i++) 497 PTD[i] = 0; 498 499 /* Initialize the PAT MSR if present. */ 500 pmap_init_pat(); 501 502 /* Turn on PG_G on kernel page(s) */ 503 pmap_set_pg(); 504#endif 505} 506 507/* 508 * Setup the PAT MSR. 509 */ 510void 511pmap_init_pat(void) 512{ 513 uint64_t pat_msr; 514 515 /* Bail if this CPU doesn't implement PAT. */ 516 if (!(cpu_feature & CPUID_PAT)) 517 return; 518 519 if (cpu_vendor_id != CPU_VENDOR_INTEL || 520 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 521 /* 522 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 523 * Program 4 and 5 as WP and WC. 524 * Leave 6 and 7 as UC and UC-. 525 */ 526 pat_msr = rdmsr(MSR_PAT); 527 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 528 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 529 PAT_VALUE(5, PAT_WRITE_COMBINING); 530 pat_works = 1; 531 } else { 532 /* 533 * Due to some Intel errata, we can only safely use the lower 4 534 * PAT entries. Thus, just replace PAT Index 2 with WC instead 535 * of UC-. 536 * 537 * Intel Pentium III Processor Specification Update 538 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 539 * or Mode C Paging) 540 * 541 * Intel Pentium IV Processor Specification Update 542 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 543 */ 544 pat_msr = rdmsr(MSR_PAT); 545 pat_msr &= ~PAT_MASK(2); 546 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 547 pat_works = 0; 548 } 549 wrmsr(MSR_PAT, pat_msr); 550} 551 552/* 553 * Initialize a vm_page's machine-dependent fields. 554 */ 555void 556pmap_page_init(vm_page_t m) 557{ 558 559 TAILQ_INIT(&m->md.pv_list); 560 m->md.pat_mode = PAT_WRITE_BACK; 561} 562 563/* 564 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 565 * Requirements: 566 * - Must deal with pages in order to ensure that none of the PG_* bits 567 * are ever set, PG_V in particular. 568 * - Assumes we can write to ptes without pte_store() atomic ops, even 569 * on PAE systems. This should be ok. 570 * - Assumes nothing will ever test these addresses for 0 to indicate 571 * no mapping instead of correctly checking PG_V. 572 * - Assumes a vm_offset_t will fit in a pte (true for i386). 573 * Because PG_V is never set, there can be no mappings to invalidate. 574 */ 575static int ptelist_count = 0; 576static vm_offset_t 577pmap_ptelist_alloc(vm_offset_t *head) 578{ 579 vm_offset_t va; 580 vm_offset_t *phead = (vm_offset_t *)*head; 581 582 if (ptelist_count == 0) { 583 printf("out of memory!!!!!!\n"); 584 return (0); /* Out of memory */ 585 } 586 ptelist_count--; 587 va = phead[ptelist_count]; 588 return (va); 589} 590 591static void 592pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 593{ 594 vm_offset_t *phead = (vm_offset_t *)*head; 595 596 phead[ptelist_count++] = va; 597} 598 599static void 600pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 601{ 602 int i, nstackpages; 603 vm_offset_t va; 604 vm_page_t m; 605 606 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 607 for (i = 0; i < nstackpages; i++) { 608 va = (vm_offset_t)base + i * PAGE_SIZE; 609 m = vm_page_alloc(NULL, i, 610 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 611 VM_ALLOC_ZERO); 612 pmap_qenter(va, &m, 1); 613 } 614 615 *head = (vm_offset_t)base; 616 for (i = npages - 1; i >= nstackpages; i--) { 617 va = (vm_offset_t)base + i * PAGE_SIZE; 618 pmap_ptelist_free(head, va); 619 } 620} 621 622 623/* 624 * Initialize the pmap module. 625 * Called by vm_init, to initialize any structures that the pmap 626 * system needs to map virtual memory. 627 */ 628void 629pmap_init(void) 630{ 631 vm_page_t mpte; 632 vm_size_t s; 633 int i, pv_npg; 634 635 /* 636 * Initialize the vm page array entries for the kernel pmap's 637 * page table pages. 638 */ 639 for (i = 0; i < nkpt; i++) { 640 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(PTD[i + KPTDI] & PG_FRAME)); 641 KASSERT(mpte >= vm_page_array && 642 mpte < &vm_page_array[vm_page_array_size], 643 ("pmap_init: page table page is out of range")); 644 mpte->pindex = i + KPTDI; 645 mpte->phys_addr = xpmap_mtop(PTD[i + KPTDI] & PG_FRAME); 646 } 647 648 /* 649 * Initialize the address space (zone) for the pv entries. Set a 650 * high water mark so that the system can recover from excessive 651 * numbers of pv entries. 652 */ 653 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 654 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 655 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 656 pv_entry_max = roundup(pv_entry_max, _NPCPV); 657 pv_entry_high_water = 9 * (pv_entry_max / 10); 658 659 /* 660 * Are large page mappings enabled? 661 */ 662 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 663 664 /* 665 * Calculate the size of the pv head table for superpages. 666 */ 667 for (i = 0; phys_avail[i + 1]; i += 2); 668 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 669 670 /* 671 * Allocate memory for the pv head table for superpages. 672 */ 673 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 674 s = round_page(s); 675 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 676 for (i = 0; i < pv_npg; i++) 677 TAILQ_INIT(&pv_table[i].pv_list); 678 679 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 680 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 681 PAGE_SIZE * pv_maxchunks); 682 if (pv_chunkbase == NULL) 683 panic("pmap_init: not enough kvm for pv chunks"); 684 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 685} 686 687 688/*************************************************** 689 * Low level helper routines..... 690 ***************************************************/ 691 692/* 693 * Determine the appropriate bits to set in a PTE or PDE for a specified 694 * caching mode. 695 */ 696int 697pmap_cache_bits(int mode, boolean_t is_pde) 698{ 699 int pat_flag, pat_index, cache_bits; 700 701 /* The PAT bit is different for PTE's and PDE's. */ 702 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 703 704 /* If we don't support PAT, map extended modes to older ones. */ 705 if (!(cpu_feature & CPUID_PAT)) { 706 switch (mode) { 707 case PAT_UNCACHEABLE: 708 case PAT_WRITE_THROUGH: 709 case PAT_WRITE_BACK: 710 break; 711 case PAT_UNCACHED: 712 case PAT_WRITE_COMBINING: 713 case PAT_WRITE_PROTECTED: 714 mode = PAT_UNCACHEABLE; 715 break; 716 } 717 } 718 719 /* Map the caching mode to a PAT index. */ 720 if (pat_works) { 721 switch (mode) { 722 case PAT_UNCACHEABLE: 723 pat_index = 3; 724 break; 725 case PAT_WRITE_THROUGH: 726 pat_index = 1; 727 break; 728 case PAT_WRITE_BACK: 729 pat_index = 0; 730 break; 731 case PAT_UNCACHED: 732 pat_index = 2; 733 break; 734 case PAT_WRITE_COMBINING: 735 pat_index = 5; 736 break; 737 case PAT_WRITE_PROTECTED: 738 pat_index = 4; 739 break; 740 default: 741 panic("Unknown caching mode %d\n", mode); 742 } 743 } else { 744 switch (mode) { 745 case PAT_UNCACHED: 746 case PAT_UNCACHEABLE: 747 case PAT_WRITE_PROTECTED: 748 pat_index = 3; 749 break; 750 case PAT_WRITE_THROUGH: 751 pat_index = 1; 752 break; 753 case PAT_WRITE_BACK: 754 pat_index = 0; 755 break; 756 case PAT_WRITE_COMBINING: 757 pat_index = 2; 758 break; 759 default: 760 panic("Unknown caching mode %d\n", mode); 761 } 762 } 763 764 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 765 cache_bits = 0; 766 if (pat_index & 0x4) 767 cache_bits |= pat_flag; 768 if (pat_index & 0x2) 769 cache_bits |= PG_NC_PCD; 770 if (pat_index & 0x1) 771 cache_bits |= PG_NC_PWT; 772 return (cache_bits); 773} 774#ifdef SMP 775/* 776 * For SMP, these functions have to use the IPI mechanism for coherence. 777 * 778 * N.B.: Before calling any of the following TLB invalidation functions, 779 * the calling processor must ensure that all stores updating a non- 780 * kernel page table are globally performed. Otherwise, another 781 * processor could cache an old, pre-update entry without being 782 * invalidated. This can happen one of two ways: (1) The pmap becomes 783 * active on another processor after its pm_active field is checked by 784 * one of the following functions but before a store updating the page 785 * table is globally performed. (2) The pmap becomes active on another 786 * processor before its pm_active field is checked but due to 787 * speculative loads one of the following functions stills reads the 788 * pmap as inactive on the other processor. 789 * 790 * The kernel page table is exempt because its pm_active field is 791 * immutable. The kernel page table is always active on every 792 * processor. 793 */ 794void 795pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 796{ 797 cpumask_t cpumask, other_cpus; 798 799 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 800 pmap, va); 801 802 sched_pin(); 803 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 804 invlpg(va); 805 smp_invlpg(va); 806 } else { 807 cpumask = PCPU_GET(cpumask); 808 other_cpus = PCPU_GET(other_cpus); 809 if (pmap->pm_active & cpumask) 810 invlpg(va); 811 if (pmap->pm_active & other_cpus) 812 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 813 } 814 sched_unpin(); 815 PT_UPDATES_FLUSH(); 816} 817 818void 819pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 820{ 821 cpumask_t cpumask, other_cpus; 822 vm_offset_t addr; 823 824 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 825 pmap, sva, eva); 826 827 sched_pin(); 828 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 829 for (addr = sva; addr < eva; addr += PAGE_SIZE) 830 invlpg(addr); 831 smp_invlpg_range(sva, eva); 832 } else { 833 cpumask = PCPU_GET(cpumask); 834 other_cpus = PCPU_GET(other_cpus); 835 if (pmap->pm_active & cpumask) 836 for (addr = sva; addr < eva; addr += PAGE_SIZE) 837 invlpg(addr); 838 if (pmap->pm_active & other_cpus) 839 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 840 sva, eva); 841 } 842 sched_unpin(); 843 PT_UPDATES_FLUSH(); 844} 845 846void 847pmap_invalidate_all(pmap_t pmap) 848{ 849 cpumask_t cpumask, other_cpus; 850 851 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 852 853 sched_pin(); 854 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 855 invltlb(); 856 smp_invltlb(); 857 } else { 858 cpumask = PCPU_GET(cpumask); 859 other_cpus = PCPU_GET(other_cpus); 860 if (pmap->pm_active & cpumask) 861 invltlb(); 862 if (pmap->pm_active & other_cpus) 863 smp_masked_invltlb(pmap->pm_active & other_cpus); 864 } 865 sched_unpin(); 866} 867 868void 869pmap_invalidate_cache(void) 870{ 871 872 sched_pin(); 873 wbinvd(); 874 smp_cache_flush(); 875 sched_unpin(); 876} 877#else /* !SMP */ 878/* 879 * Normal, non-SMP, 486+ invalidation functions. 880 * We inline these within pmap.c for speed. 881 */ 882PMAP_INLINE void 883pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 884{ 885 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 886 pmap, va); 887 888 if (pmap == kernel_pmap || pmap->pm_active) 889 invlpg(va); 890 PT_UPDATES_FLUSH(); 891} 892 893PMAP_INLINE void 894pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 895{ 896 vm_offset_t addr; 897 898 if (eva - sva > PAGE_SIZE) 899 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 900 pmap, sva, eva); 901 902 if (pmap == kernel_pmap || pmap->pm_active) 903 for (addr = sva; addr < eva; addr += PAGE_SIZE) 904 invlpg(addr); 905 PT_UPDATES_FLUSH(); 906} 907 908PMAP_INLINE void 909pmap_invalidate_all(pmap_t pmap) 910{ 911 912 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 913 914 if (pmap == kernel_pmap || pmap->pm_active) 915 invltlb(); 916} 917 918PMAP_INLINE void 919pmap_invalidate_cache(void) 920{ 921 922 wbinvd(); 923} 924#endif /* !SMP */ 925 926void 927pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 928{ 929 930 KASSERT((sva & PAGE_MASK) == 0, 931 ("pmap_invalidate_cache_range: sva not page-aligned")); 932 KASSERT((eva & PAGE_MASK) == 0, 933 ("pmap_invalidate_cache_range: eva not page-aligned")); 934 935 if (cpu_feature & CPUID_SS) 936 ; /* If "Self Snoop" is supported, do nothing. */ 937 else if (cpu_feature & CPUID_CLFSH) { 938 939 /* 940 * Otherwise, do per-cache line flush. Use the mfence 941 * instruction to insure that previous stores are 942 * included in the write-back. The processor 943 * propagates flush to other processors in the cache 944 * coherence domain. 945 */ 946 mfence(); 947 for (; sva < eva; sva += cpu_clflush_line_size) 948 clflush(sva); 949 mfence(); 950 } else { 951 952 /* 953 * No targeted cache flush methods are supported by CPU, 954 * globally invalidate cache as a last resort. 955 */ 956 pmap_invalidate_cache(); 957 } 958} 959 960/* 961 * Are we current address space or kernel? N.B. We return FALSE when 962 * a pmap's page table is in use because a kernel thread is borrowing 963 * it. The borrowed page table can change spontaneously, making any 964 * dependence on its continued use subject to a race condition. 965 */ 966static __inline int 967pmap_is_current(pmap_t pmap) 968{ 969 970 return (pmap == kernel_pmap || 971 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 972 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 973} 974 975/* 976 * If the given pmap is not the current or kernel pmap, the returned pte must 977 * be released by passing it to pmap_pte_release(). 978 */ 979pt_entry_t * 980pmap_pte(pmap_t pmap, vm_offset_t va) 981{ 982 pd_entry_t newpf; 983 pd_entry_t *pde; 984 985 pde = pmap_pde(pmap, va); 986 if (*pde & PG_PS) 987 return (pde); 988 if (*pde != 0) { 989 /* are we current address space or kernel? */ 990 if (pmap_is_current(pmap)) 991 return (vtopte(va)); 992 mtx_lock(&PMAP2mutex); 993 newpf = *pde & PG_FRAME; 994 if ((*PMAP2 & PG_FRAME) != newpf) { 995 vm_page_lock_queues(); 996 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 997 vm_page_unlock_queues(); 998 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 999 pmap, va, (*PMAP2 & 0xffffffff)); 1000 } 1001 1002 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1003 } 1004 return (0); 1005} 1006 1007/* 1008 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1009 * being NULL. 1010 */ 1011static __inline void 1012pmap_pte_release(pt_entry_t *pte) 1013{ 1014 1015 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 1016 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 1017 *PMAP2); 1018 PT_SET_VA(PMAP2, 0, TRUE); 1019 mtx_unlock(&PMAP2mutex); 1020 } 1021} 1022 1023static __inline void 1024invlcaddr(void *caddr) 1025{ 1026 1027 invlpg((u_int)caddr); 1028 PT_UPDATES_FLUSH(); 1029} 1030 1031/* 1032 * Super fast pmap_pte routine best used when scanning 1033 * the pv lists. This eliminates many coarse-grained 1034 * invltlb calls. Note that many of the pv list 1035 * scans are across different pmaps. It is very wasteful 1036 * to do an entire invltlb for checking a single mapping. 1037 * 1038 * If the given pmap is not the current pmap, vm_page_queue_mtx 1039 * must be held and curthread pinned to a CPU. 1040 */ 1041static pt_entry_t * 1042pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1043{ 1044 pd_entry_t newpf; 1045 pd_entry_t *pde; 1046 1047 pde = pmap_pde(pmap, va); 1048 if (*pde & PG_PS) 1049 return (pde); 1050 if (*pde != 0) { 1051 /* are we current address space or kernel? */ 1052 if (pmap_is_current(pmap)) 1053 return (vtopte(va)); 1054 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1055 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1056 newpf = *pde & PG_FRAME; 1057 if ((*PMAP1 & PG_FRAME) != newpf) { 1058 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1059 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1060 pmap, va, (u_long)*PMAP1); 1061 1062#ifdef SMP 1063 PMAP1cpu = PCPU_GET(cpuid); 1064#endif 1065 PMAP1changed++; 1066 } else 1067#ifdef SMP 1068 if (PMAP1cpu != PCPU_GET(cpuid)) { 1069 PMAP1cpu = PCPU_GET(cpuid); 1070 invlcaddr(PADDR1); 1071 PMAP1changedcpu++; 1072 } else 1073#endif 1074 PMAP1unchanged++; 1075 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1076 } 1077 return (0); 1078} 1079 1080/* 1081 * Routine: pmap_extract 1082 * Function: 1083 * Extract the physical page address associated 1084 * with the given map/virtual_address pair. 1085 */ 1086vm_paddr_t 1087pmap_extract(pmap_t pmap, vm_offset_t va) 1088{ 1089 vm_paddr_t rtval; 1090 pt_entry_t *pte; 1091 pd_entry_t pde; 1092 pt_entry_t pteval; 1093 1094 rtval = 0; 1095 PMAP_LOCK(pmap); 1096 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1097 if (pde != 0) { 1098 if ((pde & PG_PS) != 0) { 1099 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1100 PMAP_UNLOCK(pmap); 1101 return rtval; 1102 } 1103 pte = pmap_pte(pmap, va); 1104 pteval = *pte ? xpmap_mtop(*pte) : 0; 1105 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1106 pmap_pte_release(pte); 1107 } 1108 PMAP_UNLOCK(pmap); 1109 return (rtval); 1110} 1111 1112/* 1113 * Routine: pmap_extract_ma 1114 * Function: 1115 * Like pmap_extract, but returns machine address 1116 */ 1117vm_paddr_t 1118pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1119{ 1120 vm_paddr_t rtval; 1121 pt_entry_t *pte; 1122 pd_entry_t pde; 1123 1124 rtval = 0; 1125 PMAP_LOCK(pmap); 1126 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1127 if (pde != 0) { 1128 if ((pde & PG_PS) != 0) { 1129 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1130 PMAP_UNLOCK(pmap); 1131 return rtval; 1132 } 1133 pte = pmap_pte(pmap, va); 1134 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1135 pmap_pte_release(pte); 1136 } 1137 PMAP_UNLOCK(pmap); 1138 return (rtval); 1139} 1140 1141/* 1142 * Routine: pmap_extract_and_hold 1143 * Function: 1144 * Atomically extract and hold the physical page 1145 * with the given pmap and virtual address pair 1146 * if that mapping permits the given protection. 1147 */ 1148vm_page_t 1149pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1150{ 1151 pd_entry_t pde; 1152 pt_entry_t pte; 1153 vm_page_t m; 1154 vm_paddr_t pa; 1155 1156 pa = 0; 1157 m = NULL; 1158 PMAP_LOCK(pmap); 1159retry: 1160 pde = PT_GET(pmap_pde(pmap, va)); 1161 if (pde != 0) { 1162 if (pde & PG_PS) { 1163 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1164 if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) | 1165 (va & PDRMASK), &pa)) 1166 goto retry; 1167 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1168 (va & PDRMASK)); 1169 vm_page_hold(m); 1170 } 1171 } else { 1172 sched_pin(); 1173 pte = PT_GET(pmap_pte_quick(pmap, va)); 1174 if (*PMAP1) 1175 PT_SET_MA(PADDR1, 0); 1176 if ((pte & PG_V) && 1177 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1178 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa)) 1179 goto retry; 1180 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1181 vm_page_hold(m); 1182 } 1183 sched_unpin(); 1184 } 1185 } 1186 PA_UNLOCK_COND(pa); 1187 PMAP_UNLOCK(pmap); 1188 return (m); 1189} 1190 1191/*************************************************** 1192 * Low level mapping routines..... 1193 ***************************************************/ 1194 1195/* 1196 * Add a wired page to the kva. 1197 * Note: not SMP coherent. 1198 */ 1199void 1200pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1201{ 1202 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1203} 1204 1205void 1206pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1207{ 1208 pt_entry_t *pte; 1209 1210 pte = vtopte(va); 1211 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1212} 1213 1214 1215static __inline void 1216pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1217{ 1218 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1219} 1220 1221/* 1222 * Remove a page from the kernel pagetables. 1223 * Note: not SMP coherent. 1224 */ 1225PMAP_INLINE void 1226pmap_kremove(vm_offset_t va) 1227{ 1228 pt_entry_t *pte; 1229 1230 pte = vtopte(va); 1231 PT_CLEAR_VA(pte, FALSE); 1232} 1233 1234/* 1235 * Used to map a range of physical addresses into kernel 1236 * virtual address space. 1237 * 1238 * The value passed in '*virt' is a suggested virtual address for 1239 * the mapping. Architectures which can support a direct-mapped 1240 * physical to virtual region can return the appropriate address 1241 * within that region, leaving '*virt' unchanged. Other 1242 * architectures should map the pages starting at '*virt' and 1243 * update '*virt' with the first usable address after the mapped 1244 * region. 1245 */ 1246vm_offset_t 1247pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1248{ 1249 vm_offset_t va, sva; 1250 1251 va = sva = *virt; 1252 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1253 va, start, end, prot); 1254 while (start < end) { 1255 pmap_kenter(va, start); 1256 va += PAGE_SIZE; 1257 start += PAGE_SIZE; 1258 } 1259 pmap_invalidate_range(kernel_pmap, sva, va); 1260 *virt = va; 1261 return (sva); 1262} 1263 1264 1265/* 1266 * Add a list of wired pages to the kva 1267 * this routine is only used for temporary 1268 * kernel mappings that do not need to have 1269 * page modification or references recorded. 1270 * Note that old mappings are simply written 1271 * over. The page *must* be wired. 1272 * Note: SMP coherent. Uses a ranged shootdown IPI. 1273 */ 1274void 1275pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1276{ 1277 pt_entry_t *endpte, *pte; 1278 vm_paddr_t pa; 1279 vm_offset_t va = sva; 1280 int mclcount = 0; 1281 multicall_entry_t mcl[16]; 1282 multicall_entry_t *mclp = mcl; 1283 int error; 1284 1285 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1286 pte = vtopte(sva); 1287 endpte = pte + count; 1288 while (pte < endpte) { 1289 pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1290 1291 mclp->op = __HYPERVISOR_update_va_mapping; 1292 mclp->args[0] = va; 1293 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1294 mclp->args[2] = (uint32_t)(pa >> 32); 1295#if 0 1296 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1297#else 1298 /* 1299 * Somehow we seem to be ending up with pages which are in 1300 * the TLB in spite of not having PG_V set, resulting in 1301 * pages newly loaded into the bufcache not showing up 1302 * immediately (i.e., accessing them provides the old data). 1303 * As a workaround, always perform a TLB flush, even if the 1304 * old page didn't have PG_V. 1305 */ 1306 mclp->args[3] = UVMF_INVLPG|UVMF_ALL; 1307#endif 1308 1309 va += PAGE_SIZE; 1310 pte++; 1311 ma++; 1312 mclp++; 1313 mclcount++; 1314 if (mclcount == 16) { 1315 error = HYPERVISOR_multicall(mcl, mclcount); 1316 mclp = mcl; 1317 mclcount = 0; 1318 KASSERT(error == 0, ("bad multicall %d", error)); 1319 } 1320 } 1321 if (mclcount) { 1322 error = HYPERVISOR_multicall(mcl, mclcount); 1323 KASSERT(error == 0, ("bad multicall %d", error)); 1324 } 1325 1326#ifdef INVARIANTS 1327 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1328 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1329#endif 1330} 1331 1332 1333/* 1334 * This routine tears out page mappings from the 1335 * kernel -- it is meant only for temporary mappings. 1336 * Note: SMP coherent. Uses a ranged shootdown IPI. 1337 */ 1338void 1339pmap_qremove(vm_offset_t sva, int count) 1340{ 1341 vm_offset_t va; 1342 1343 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1344 va = sva; 1345 vm_page_lock_queues(); 1346 critical_enter(); 1347 while (count-- > 0) { 1348 pmap_kremove(va); 1349 va += PAGE_SIZE; 1350 } 1351 pmap_invalidate_range(kernel_pmap, sva, va); 1352 critical_exit(); 1353 vm_page_unlock_queues(); 1354} 1355 1356/*************************************************** 1357 * Page table page management routines..... 1358 ***************************************************/ 1359static __inline void 1360pmap_free_zero_pages(vm_page_t free) 1361{ 1362 vm_page_t m; 1363 1364 while (free != NULL) { 1365 m = free; 1366 free = m->right; 1367 vm_page_free_zero(m); 1368 } 1369} 1370 1371/* 1372 * This routine unholds page table pages, and if the hold count 1373 * drops to zero, then it decrements the wire count. 1374 */ 1375static __inline int 1376pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1377{ 1378 1379 --m->wire_count; 1380 if (m->wire_count == 0) 1381 return _pmap_unwire_pte_hold(pmap, m, free); 1382 else 1383 return 0; 1384} 1385 1386static int 1387_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1388{ 1389 vm_offset_t pteva; 1390 1391 PT_UPDATES_FLUSH(); 1392 /* 1393 * unmap the page table page 1394 */ 1395 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1396 /* 1397 * page *might* contain residual mapping :-/ 1398 */ 1399 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1400 pmap_zero_page(m); 1401 --pmap->pm_stats.resident_count; 1402 1403 /* 1404 * This is a release store so that the ordinary store unmapping 1405 * the page table page is globally performed before TLB shoot- 1406 * down is begun. 1407 */ 1408 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1409 1410 /* 1411 * Do an invltlb to make the invalidated mapping 1412 * take effect immediately. 1413 */ 1414 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1415 pmap_invalidate_page(pmap, pteva); 1416 1417 /* 1418 * Put page on a list so that it is released after 1419 * *ALL* TLB shootdown is done 1420 */ 1421 m->right = *free; 1422 *free = m; 1423 1424 return 1; 1425} 1426 1427/* 1428 * After removing a page table entry, this routine is used to 1429 * conditionally free the page, and manage the hold/wire counts. 1430 */ 1431static int 1432pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1433{ 1434 pd_entry_t ptepde; 1435 vm_page_t mpte; 1436 1437 if (va >= VM_MAXUSER_ADDRESS) 1438 return 0; 1439 ptepde = PT_GET(pmap_pde(pmap, va)); 1440 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1441 return pmap_unwire_pte_hold(pmap, mpte, free); 1442} 1443 1444void 1445pmap_pinit0(pmap_t pmap) 1446{ 1447 1448 PMAP_LOCK_INIT(pmap); 1449 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1450#ifdef PAE 1451 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1452#endif 1453 pmap->pm_active = 0; 1454 PCPU_SET(curpmap, pmap); 1455 TAILQ_INIT(&pmap->pm_pvchunk); 1456 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1457 mtx_lock_spin(&allpmaps_lock); 1458 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1459 mtx_unlock_spin(&allpmaps_lock); 1460} 1461 1462/* 1463 * Initialize a preallocated and zeroed pmap structure, 1464 * such as one in a vmspace structure. 1465 */ 1466int 1467pmap_pinit(pmap_t pmap) 1468{ 1469 vm_page_t m, ptdpg[NPGPTD + 1]; 1470 int npgptd = NPGPTD + 1; 1471 static int color; 1472 int i; 1473 1474 PMAP_LOCK_INIT(pmap); 1475 1476 /* 1477 * No need to allocate page table space yet but we do need a valid 1478 * page directory table. 1479 */ 1480 if (pmap->pm_pdir == NULL) { 1481 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1482 NBPTD); 1483 if (pmap->pm_pdir == NULL) { 1484 PMAP_LOCK_DESTROY(pmap); 1485 return (0); 1486 } 1487#ifdef PAE 1488 pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1489#endif 1490 } 1491 1492 /* 1493 * allocate the page directory page(s) 1494 */ 1495 for (i = 0; i < npgptd;) { 1496 m = vm_page_alloc(NULL, color++, 1497 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1498 VM_ALLOC_ZERO); 1499 if (m == NULL) 1500 VM_WAIT; 1501 else { 1502 ptdpg[i++] = m; 1503 } 1504 } 1505 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1506 for (i = 0; i < NPGPTD; i++) { 1507 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1508 pagezero(&pmap->pm_pdir[i*NPTEPG]); 1509 } 1510 1511 mtx_lock_spin(&allpmaps_lock); 1512 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1513 mtx_unlock_spin(&allpmaps_lock); 1514 /* Wire in kernel global address entries. */ 1515 1516 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1517#ifdef PAE 1518 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1519 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1520 bzero(pmap->pm_pdpt, PAGE_SIZE); 1521 for (i = 0; i < NPGPTD; i++) { 1522 vm_paddr_t ma; 1523 1524 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1525 pmap->pm_pdpt[i] = ma | PG_V; 1526 1527 } 1528#endif 1529 for (i = 0; i < NPGPTD; i++) { 1530 pt_entry_t *pd; 1531 vm_paddr_t ma; 1532 1533 ma = VM_PAGE_TO_MACH(ptdpg[i]); 1534 pd = pmap->pm_pdir + (i * NPDEPG); 1535 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1536#if 0 1537 xen_pgd_pin(ma); 1538#endif 1539 } 1540 1541#ifdef PAE 1542 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1543#endif 1544 vm_page_lock_queues(); 1545 xen_flush_queue(); 1546 xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1547 for (i = 0; i < NPGPTD; i++) { 1548 vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1549 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1550 } 1551 xen_flush_queue(); 1552 vm_page_unlock_queues(); 1553 pmap->pm_active = 0; 1554 TAILQ_INIT(&pmap->pm_pvchunk); 1555 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1556 1557 return (1); 1558} 1559 1560/* 1561 * this routine is called if the page table page is not 1562 * mapped correctly. 1563 */ 1564static vm_page_t 1565_pmap_allocpte(pmap_t pmap, unsigned int ptepindex, int flags) 1566{ 1567 vm_paddr_t ptema; 1568 vm_page_t m; 1569 1570 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1571 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1572 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1573 1574 /* 1575 * Allocate a page table page. 1576 */ 1577 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1578 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1579 if (flags & M_WAITOK) { 1580 PMAP_UNLOCK(pmap); 1581 vm_page_unlock_queues(); 1582 VM_WAIT; 1583 vm_page_lock_queues(); 1584 PMAP_LOCK(pmap); 1585 } 1586 1587 /* 1588 * Indicate the need to retry. While waiting, the page table 1589 * page may have been allocated. 1590 */ 1591 return (NULL); 1592 } 1593 if ((m->flags & PG_ZERO) == 0) 1594 pmap_zero_page(m); 1595 1596 /* 1597 * Map the pagetable page into the process address space, if 1598 * it isn't already there. 1599 */ 1600 pmap->pm_stats.resident_count++; 1601 1602 ptema = VM_PAGE_TO_MACH(m); 1603 xen_pt_pin(ptema); 1604 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1605 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1606 1607 KASSERT(pmap->pm_pdir[ptepindex], 1608 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1609 return (m); 1610} 1611 1612static vm_page_t 1613pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1614{ 1615 unsigned ptepindex; 1616 pd_entry_t ptema; 1617 vm_page_t m; 1618 1619 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1620 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1621 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1622 1623 /* 1624 * Calculate pagetable page index 1625 */ 1626 ptepindex = va >> PDRSHIFT; 1627retry: 1628 /* 1629 * Get the page directory entry 1630 */ 1631 ptema = pmap->pm_pdir[ptepindex]; 1632 1633 /* 1634 * This supports switching from a 4MB page to a 1635 * normal 4K page. 1636 */ 1637 if (ptema & PG_PS) { 1638 /* 1639 * XXX 1640 */ 1641 pmap->pm_pdir[ptepindex] = 0; 1642 ptema = 0; 1643 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1644 pmap_invalidate_all(kernel_pmap); 1645 } 1646 1647 /* 1648 * If the page table page is mapped, we just increment the 1649 * hold count, and activate it. 1650 */ 1651 if (ptema & PG_V) { 1652 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1653 m->wire_count++; 1654 } else { 1655 /* 1656 * Here if the pte page isn't mapped, or if it has 1657 * been deallocated. 1658 */ 1659 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1660 pmap, va, flags); 1661 m = _pmap_allocpte(pmap, ptepindex, flags); 1662 if (m == NULL && (flags & M_WAITOK)) 1663 goto retry; 1664 1665 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1666 } 1667 return (m); 1668} 1669 1670 1671/*************************************************** 1672* Pmap allocation/deallocation routines. 1673 ***************************************************/ 1674 1675#ifdef SMP 1676/* 1677 * Deal with a SMP shootdown of other users of the pmap that we are 1678 * trying to dispose of. This can be a bit hairy. 1679 */ 1680static cpumask_t *lazymask; 1681static u_int lazyptd; 1682static volatile u_int lazywait; 1683 1684void pmap_lazyfix_action(void); 1685 1686void 1687pmap_lazyfix_action(void) 1688{ 1689 cpumask_t mymask = PCPU_GET(cpumask); 1690 1691#ifdef COUNT_IPIS 1692 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1693#endif 1694 if (rcr3() == lazyptd) 1695 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1696 atomic_clear_int(lazymask, mymask); 1697 atomic_store_rel_int(&lazywait, 1); 1698} 1699 1700static void 1701pmap_lazyfix_self(cpumask_t mymask) 1702{ 1703 1704 if (rcr3() == lazyptd) 1705 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1706 atomic_clear_int(lazymask, mymask); 1707} 1708 1709 1710static void 1711pmap_lazyfix(pmap_t pmap) 1712{ 1713 cpumask_t mymask, mask; 1714 u_int spins; 1715 1716 while ((mask = pmap->pm_active) != 0) { 1717 spins = 50000000; 1718 mask = mask & -mask; /* Find least significant set bit */ 1719 mtx_lock_spin(&smp_ipi_mtx); 1720#ifdef PAE 1721 lazyptd = vtophys(pmap->pm_pdpt); 1722#else 1723 lazyptd = vtophys(pmap->pm_pdir); 1724#endif 1725 mymask = PCPU_GET(cpumask); 1726 if (mask == mymask) { 1727 lazymask = &pmap->pm_active; 1728 pmap_lazyfix_self(mymask); 1729 } else { 1730 atomic_store_rel_int((u_int *)&lazymask, 1731 (u_int)&pmap->pm_active); 1732 atomic_store_rel_int(&lazywait, 0); 1733 ipi_selected(mask, IPI_LAZYPMAP); 1734 while (lazywait == 0) { 1735 ia32_pause(); 1736 if (--spins == 0) 1737 break; 1738 } 1739 } 1740 mtx_unlock_spin(&smp_ipi_mtx); 1741 if (spins == 0) 1742 printf("pmap_lazyfix: spun for 50000000\n"); 1743 } 1744} 1745 1746#else /* SMP */ 1747 1748/* 1749 * Cleaning up on uniprocessor is easy. For various reasons, we're 1750 * unlikely to have to even execute this code, including the fact 1751 * that the cleanup is deferred until the parent does a wait(2), which 1752 * means that another userland process has run. 1753 */ 1754static void 1755pmap_lazyfix(pmap_t pmap) 1756{ 1757 u_int cr3; 1758 1759 cr3 = vtophys(pmap->pm_pdir); 1760 if (cr3 == rcr3()) { 1761 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1762 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1763 } 1764} 1765#endif /* SMP */ 1766 1767/* 1768 * Release any resources held by the given physical map. 1769 * Called when a pmap initialized by pmap_pinit is being released. 1770 * Should only be called if the map contains no valid mappings. 1771 */ 1772void 1773pmap_release(pmap_t pmap) 1774{ 1775 vm_page_t m, ptdpg[2*NPGPTD+1]; 1776 vm_paddr_t ma; 1777 int i; 1778#ifdef PAE 1779 int npgptd = NPGPTD + 1; 1780#else 1781 int npgptd = NPGPTD; 1782#endif 1783 KASSERT(pmap->pm_stats.resident_count == 0, 1784 ("pmap_release: pmap resident count %ld != 0", 1785 pmap->pm_stats.resident_count)); 1786 PT_UPDATES_FLUSH(); 1787 1788 pmap_lazyfix(pmap); 1789 mtx_lock_spin(&allpmaps_lock); 1790 LIST_REMOVE(pmap, pm_list); 1791 mtx_unlock_spin(&allpmaps_lock); 1792 1793 for (i = 0; i < NPGPTD; i++) 1794 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1795 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1796#ifdef PAE 1797 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1798#endif 1799 1800 for (i = 0; i < npgptd; i++) { 1801 m = ptdpg[i]; 1802 ma = VM_PAGE_TO_MACH(m); 1803 /* unpinning L1 and L2 treated the same */ 1804#if 0 1805 xen_pgd_unpin(ma); 1806#else 1807 if (i == NPGPTD) 1808 xen_pgd_unpin(ma); 1809#endif 1810#ifdef PAE 1811 if (i < NPGPTD) 1812 KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1813 ("pmap_release: got wrong ptd page")); 1814#endif 1815 m->wire_count--; 1816 atomic_subtract_int(&cnt.v_wire_count, 1); 1817 vm_page_free(m); 1818 } 1819#ifdef PAE 1820 pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1821#endif 1822 PMAP_LOCK_DESTROY(pmap); 1823} 1824 1825static int 1826kvm_size(SYSCTL_HANDLER_ARGS) 1827{ 1828 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1829 1830 return sysctl_handle_long(oidp, &ksize, 0, req); 1831} 1832SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1833 0, 0, kvm_size, "IU", "Size of KVM"); 1834 1835static int 1836kvm_free(SYSCTL_HANDLER_ARGS) 1837{ 1838 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1839 1840 return sysctl_handle_long(oidp, &kfree, 0, req); 1841} 1842SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1843 0, 0, kvm_free, "IU", "Amount of KVM free"); 1844 1845/* 1846 * grow the number of kernel page table entries, if needed 1847 */ 1848void 1849pmap_growkernel(vm_offset_t addr) 1850{ 1851 struct pmap *pmap; 1852 vm_paddr_t ptppaddr; 1853 vm_page_t nkpg; 1854 pd_entry_t newpdir; 1855 1856 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1857 if (kernel_vm_end == 0) { 1858 kernel_vm_end = KERNBASE; 1859 nkpt = 0; 1860 while (pdir_pde(PTD, kernel_vm_end)) { 1861 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1862 nkpt++; 1863 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1864 kernel_vm_end = kernel_map->max_offset; 1865 break; 1866 } 1867 } 1868 } 1869 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1870 if (addr - 1 >= kernel_map->max_offset) 1871 addr = kernel_map->max_offset; 1872 while (kernel_vm_end < addr) { 1873 if (pdir_pde(PTD, kernel_vm_end)) { 1874 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1875 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1876 kernel_vm_end = kernel_map->max_offset; 1877 break; 1878 } 1879 continue; 1880 } 1881 1882 /* 1883 * This index is bogus, but out of the way 1884 */ 1885 nkpg = vm_page_alloc(NULL, nkpt, 1886 VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED); 1887 if (!nkpg) 1888 panic("pmap_growkernel: no memory to grow kernel"); 1889 1890 nkpt++; 1891 1892 pmap_zero_page(nkpg); 1893 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1894 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1895 vm_page_lock_queues(); 1896 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1897 mtx_lock_spin(&allpmaps_lock); 1898 LIST_FOREACH(pmap, &allpmaps, pm_list) 1899 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1900 1901 mtx_unlock_spin(&allpmaps_lock); 1902 vm_page_unlock_queues(); 1903 1904 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1905 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1906 kernel_vm_end = kernel_map->max_offset; 1907 break; 1908 } 1909 } 1910} 1911 1912 1913/*************************************************** 1914 * page management routines. 1915 ***************************************************/ 1916 1917CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1918CTASSERT(_NPCM == 11); 1919 1920static __inline struct pv_chunk * 1921pv_to_chunk(pv_entry_t pv) 1922{ 1923 1924 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1925} 1926 1927#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1928 1929#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1930#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1931 1932static uint32_t pc_freemask[11] = { 1933 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1934 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1935 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1936 PC_FREE0_9, PC_FREE10 1937}; 1938 1939SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1940 "Current number of pv entries"); 1941 1942#ifdef PV_STATS 1943static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1944 1945SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1946 "Current number of pv entry chunks"); 1947SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1948 "Current number of pv entry chunks allocated"); 1949SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1950 "Current number of pv entry chunks frees"); 1951SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1952 "Number of times tried to get a chunk page but failed."); 1953 1954static long pv_entry_frees, pv_entry_allocs; 1955static int pv_entry_spare; 1956 1957SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1958 "Current number of pv entry frees"); 1959SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1960 "Current number of pv entry allocs"); 1961SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1962 "Current number of spare pv entries"); 1963 1964static int pmap_collect_inactive, pmap_collect_active; 1965 1966SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 1967 "Current number times pmap_collect called on inactive queue"); 1968SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 1969 "Current number times pmap_collect called on active queue"); 1970#endif 1971 1972/* 1973 * We are in a serious low memory condition. Resort to 1974 * drastic measures to free some pages so we can allocate 1975 * another pv entry chunk. This is normally called to 1976 * unmap inactive pages, and if necessary, active pages. 1977 */ 1978static void 1979pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 1980{ 1981 pmap_t pmap; 1982 pt_entry_t *pte, tpte; 1983 pv_entry_t next_pv, pv; 1984 vm_offset_t va; 1985 vm_page_t m, free; 1986 1987 sched_pin(); 1988 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1989 if (m->hold_count || m->busy) 1990 continue; 1991 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1992 va = pv->pv_va; 1993 pmap = PV_PMAP(pv); 1994 /* Avoid deadlock and lock recursion. */ 1995 if (pmap > locked_pmap) 1996 PMAP_LOCK(pmap); 1997 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1998 continue; 1999 pmap->pm_stats.resident_count--; 2000 pte = pmap_pte_quick(pmap, va); 2001 tpte = pte_load_clear(pte); 2002 KASSERT((tpte & PG_W) == 0, 2003 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2004 if (tpte & PG_A) 2005 vm_page_flag_set(m, PG_REFERENCED); 2006 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2007 vm_page_dirty(m); 2008 free = NULL; 2009 pmap_unuse_pt(pmap, va, &free); 2010 pmap_invalidate_page(pmap, va); 2011 pmap_free_zero_pages(free); 2012 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2013 free_pv_entry(pmap, pv); 2014 if (pmap != locked_pmap) 2015 PMAP_UNLOCK(pmap); 2016 } 2017 if (TAILQ_EMPTY(&m->md.pv_list)) 2018 vm_page_flag_clear(m, PG_WRITEABLE); 2019 } 2020 sched_unpin(); 2021} 2022 2023 2024/* 2025 * free the pv_entry back to the free list 2026 */ 2027static void 2028free_pv_entry(pmap_t pmap, pv_entry_t pv) 2029{ 2030 vm_page_t m; 2031 struct pv_chunk *pc; 2032 int idx, field, bit; 2033 2034 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2035 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2036 PV_STAT(pv_entry_frees++); 2037 PV_STAT(pv_entry_spare++); 2038 pv_entry_count--; 2039 pc = pv_to_chunk(pv); 2040 idx = pv - &pc->pc_pventry[0]; 2041 field = idx / 32; 2042 bit = idx % 32; 2043 pc->pc_map[field] |= 1ul << bit; 2044 /* move to head of list */ 2045 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2046 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2047 for (idx = 0; idx < _NPCM; idx++) 2048 if (pc->pc_map[idx] != pc_freemask[idx]) 2049 return; 2050 PV_STAT(pv_entry_spare -= _NPCPV); 2051 PV_STAT(pc_chunk_count--); 2052 PV_STAT(pc_chunk_frees++); 2053 /* entire chunk is free, return it */ 2054 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2055 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2056 pmap_qremove((vm_offset_t)pc, 1); 2057 vm_page_unwire(m, 0); 2058 vm_page_free(m); 2059 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2060} 2061 2062/* 2063 * get a new pv_entry, allocating a block from the system 2064 * when needed. 2065 */ 2066static pv_entry_t 2067get_pv_entry(pmap_t pmap, int try) 2068{ 2069 static const struct timeval printinterval = { 60, 0 }; 2070 static struct timeval lastprint; 2071 static vm_pindex_t colour; 2072 struct vpgqueues *pq; 2073 int bit, field; 2074 pv_entry_t pv; 2075 struct pv_chunk *pc; 2076 vm_page_t m; 2077 2078 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2079 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2080 PV_STAT(pv_entry_allocs++); 2081 pv_entry_count++; 2082 if (pv_entry_count > pv_entry_high_water) 2083 if (ratecheck(&lastprint, &printinterval)) 2084 printf("Approaching the limit on PV entries, consider " 2085 "increasing either the vm.pmap.shpgperproc or the " 2086 "vm.pmap.pv_entry_max tunable.\n"); 2087 pq = NULL; 2088retry: 2089 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2090 if (pc != NULL) { 2091 for (field = 0; field < _NPCM; field++) { 2092 if (pc->pc_map[field]) { 2093 bit = bsfl(pc->pc_map[field]); 2094 break; 2095 } 2096 } 2097 if (field < _NPCM) { 2098 pv = &pc->pc_pventry[field * 32 + bit]; 2099 pc->pc_map[field] &= ~(1ul << bit); 2100 /* If this was the last item, move it to tail */ 2101 for (field = 0; field < _NPCM; field++) 2102 if (pc->pc_map[field] != 0) { 2103 PV_STAT(pv_entry_spare--); 2104 return (pv); /* not full, return */ 2105 } 2106 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2107 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2108 PV_STAT(pv_entry_spare--); 2109 return (pv); 2110 } 2111 } 2112 /* 2113 * Access to the ptelist "pv_vafree" is synchronized by the page 2114 * queues lock. If "pv_vafree" is currently non-empty, it will 2115 * remain non-empty until pmap_ptelist_alloc() completes. 2116 */ 2117 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2118 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2119 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2120 if (try) { 2121 pv_entry_count--; 2122 PV_STAT(pc_chunk_tryfail++); 2123 return (NULL); 2124 } 2125 /* 2126 * Reclaim pv entries: At first, destroy mappings to 2127 * inactive pages. After that, if a pv chunk entry 2128 * is still needed, destroy mappings to active pages. 2129 */ 2130 if (pq == NULL) { 2131 PV_STAT(pmap_collect_inactive++); 2132 pq = &vm_page_queues[PQ_INACTIVE]; 2133 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2134 PV_STAT(pmap_collect_active++); 2135 pq = &vm_page_queues[PQ_ACTIVE]; 2136 } else 2137 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2138 pmap_collect(pmap, pq); 2139 goto retry; 2140 } 2141 PV_STAT(pc_chunk_count++); 2142 PV_STAT(pc_chunk_allocs++); 2143 colour++; 2144 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2145 pmap_qenter((vm_offset_t)pc, &m, 1); 2146 if ((m->flags & PG_ZERO) == 0) 2147 pagezero(pc); 2148 pc->pc_pmap = pmap; 2149 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2150 for (field = 1; field < _NPCM; field++) 2151 pc->pc_map[field] = pc_freemask[field]; 2152 pv = &pc->pc_pventry[0]; 2153 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2154 PV_STAT(pv_entry_spare += _NPCPV - 1); 2155 return (pv); 2156} 2157 2158static __inline pv_entry_t 2159pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2160{ 2161 pv_entry_t pv; 2162 2163 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2164 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2165 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2166 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2167 break; 2168 } 2169 } 2170 return (pv); 2171} 2172 2173static void 2174pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2175{ 2176 pv_entry_t pv; 2177 2178 pv = pmap_pvh_remove(pvh, pmap, va); 2179 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2180 free_pv_entry(pmap, pv); 2181} 2182 2183static void 2184pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2185{ 2186 2187 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2188 pmap_pvh_free(&m->md, pmap, va); 2189 if (TAILQ_EMPTY(&m->md.pv_list)) 2190 vm_page_flag_clear(m, PG_WRITEABLE); 2191} 2192 2193/* 2194 * Conditionally create a pv entry. 2195 */ 2196static boolean_t 2197pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2198{ 2199 pv_entry_t pv; 2200 2201 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2202 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2203 if (pv_entry_count < pv_entry_high_water && 2204 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2205 pv->pv_va = va; 2206 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2207 return (TRUE); 2208 } else 2209 return (FALSE); 2210} 2211 2212/* 2213 * pmap_remove_pte: do the things to unmap a page in a process 2214 */ 2215static int 2216pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2217{ 2218 pt_entry_t oldpte; 2219 vm_page_t m; 2220 2221 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2222 pmap, (u_long)*ptq, va); 2223 2224 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2225 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2226 oldpte = *ptq; 2227 PT_SET_VA_MA(ptq, 0, TRUE); 2228 if (oldpte & PG_W) 2229 pmap->pm_stats.wired_count -= 1; 2230 /* 2231 * Machines that don't support invlpg, also don't support 2232 * PG_G. 2233 */ 2234 if (oldpte & PG_G) 2235 pmap_invalidate_page(kernel_pmap, va); 2236 pmap->pm_stats.resident_count -= 1; 2237 /* 2238 * XXX This is not strictly correctly, but somewhere along the line 2239 * we are losing the managed bit on some pages. It is unclear to me 2240 * why, but I think the most likely explanation is that xen's writable 2241 * page table implementation doesn't respect the unused bits. 2242 */ 2243 if ((oldpte & PG_MANAGED) || ((oldpte & PG_V) && (va < VM_MAXUSER_ADDRESS)) 2244 ) { 2245 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2246 2247 if (!(oldpte & PG_MANAGED)) 2248 printf("va=0x%x is unmanaged :-( pte=0x%llx\n", va, oldpte); 2249 2250 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2251 vm_page_dirty(m); 2252 if (oldpte & PG_A) 2253 vm_page_flag_set(m, PG_REFERENCED); 2254 pmap_remove_entry(pmap, m, va); 2255 } else if ((va < VM_MAXUSER_ADDRESS) && (oldpte & PG_V)) 2256 printf("va=0x%x is unmanaged :-( pte=0x%llx\n", va, oldpte); 2257 2258 return (pmap_unuse_pt(pmap, va, free)); 2259} 2260 2261/* 2262 * Remove a single page from a process address space 2263 */ 2264static void 2265pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2266{ 2267 pt_entry_t *pte; 2268 2269 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2270 pmap, va); 2271 2272 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2273 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2274 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2275 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2276 return; 2277 pmap_remove_pte(pmap, pte, va, free); 2278 pmap_invalidate_page(pmap, va); 2279 if (*PMAP1) 2280 PT_SET_MA(PADDR1, 0); 2281 2282} 2283 2284/* 2285 * Remove the given range of addresses from the specified map. 2286 * 2287 * It is assumed that the start and end are properly 2288 * rounded to the page size. 2289 */ 2290void 2291pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2292{ 2293 vm_offset_t pdnxt; 2294 pd_entry_t ptpaddr; 2295 pt_entry_t *pte; 2296 vm_page_t free = NULL; 2297 int anyvalid; 2298 2299 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2300 pmap, sva, eva); 2301 2302 /* 2303 * Perform an unsynchronized read. This is, however, safe. 2304 */ 2305 if (pmap->pm_stats.resident_count == 0) 2306 return; 2307 2308 anyvalid = 0; 2309 2310 vm_page_lock_queues(); 2311 sched_pin(); 2312 PMAP_LOCK(pmap); 2313 2314 /* 2315 * special handling of removing one page. a very 2316 * common operation and easy to short circuit some 2317 * code. 2318 */ 2319 if ((sva + PAGE_SIZE == eva) && 2320 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2321 pmap_remove_page(pmap, sva, &free); 2322 goto out; 2323 } 2324 2325 for (; sva < eva; sva = pdnxt) { 2326 unsigned pdirindex; 2327 2328 /* 2329 * Calculate index for next page table. 2330 */ 2331 pdnxt = (sva + NBPDR) & ~PDRMASK; 2332 if (pmap->pm_stats.resident_count == 0) 2333 break; 2334 2335 pdirindex = sva >> PDRSHIFT; 2336 ptpaddr = pmap->pm_pdir[pdirindex]; 2337 2338 /* 2339 * Weed out invalid mappings. Note: we assume that the page 2340 * directory table is always allocated, and in kernel virtual. 2341 */ 2342 if (ptpaddr == 0) 2343 continue; 2344 2345 /* 2346 * Check for large page. 2347 */ 2348 if ((ptpaddr & PG_PS) != 0) { 2349 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2350 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2351 anyvalid = 1; 2352 continue; 2353 } 2354 2355 /* 2356 * Limit our scan to either the end of the va represented 2357 * by the current page table page, or to the end of the 2358 * range being removed. 2359 */ 2360 if (pdnxt > eva) 2361 pdnxt = eva; 2362 2363 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2364 sva += PAGE_SIZE) { 2365 if ((*pte & PG_V) == 0) 2366 continue; 2367 2368 /* 2369 * The TLB entry for a PG_G mapping is invalidated 2370 * by pmap_remove_pte(). 2371 */ 2372 if ((*pte & PG_G) == 0) 2373 anyvalid = 1; 2374 if (pmap_remove_pte(pmap, pte, sva, &free)) 2375 break; 2376 } 2377 } 2378 PT_UPDATES_FLUSH(); 2379 if (*PMAP1) 2380 PT_SET_VA_MA(PMAP1, 0, TRUE); 2381out: 2382 if (anyvalid) 2383 pmap_invalidate_all(pmap); 2384 sched_unpin(); 2385 vm_page_unlock_queues(); 2386 PMAP_UNLOCK(pmap); 2387 pmap_free_zero_pages(free); 2388} 2389 2390/* 2391 * Routine: pmap_remove_all 2392 * Function: 2393 * Removes this physical page from 2394 * all physical maps in which it resides. 2395 * Reflects back modify bits to the pager. 2396 * 2397 * Notes: 2398 * Original versions of this routine were very 2399 * inefficient because they iteratively called 2400 * pmap_remove (slow...) 2401 */ 2402 2403void 2404pmap_remove_all(vm_page_t m) 2405{ 2406 pv_entry_t pv; 2407 pmap_t pmap; 2408 pt_entry_t *pte, tpte; 2409 vm_page_t free; 2410 2411 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2412 ("pmap_remove_all: page %p is fictitious", m)); 2413 free = NULL; 2414 vm_page_lock_queues(); 2415 sched_pin(); 2416 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2417 pmap = PV_PMAP(pv); 2418 PMAP_LOCK(pmap); 2419 pmap->pm_stats.resident_count--; 2420 pte = pmap_pte_quick(pmap, pv->pv_va); 2421 2422 tpte = *pte; 2423 PT_SET_VA_MA(pte, 0, TRUE); 2424 if (tpte & PG_W) 2425 pmap->pm_stats.wired_count--; 2426 if (tpte & PG_A) 2427 vm_page_flag_set(m, PG_REFERENCED); 2428 2429 /* 2430 * Update the vm_page_t clean and reference bits. 2431 */ 2432 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2433 vm_page_dirty(m); 2434 pmap_unuse_pt(pmap, pv->pv_va, &free); 2435 pmap_invalidate_page(pmap, pv->pv_va); 2436 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2437 free_pv_entry(pmap, pv); 2438 PMAP_UNLOCK(pmap); 2439 } 2440 vm_page_flag_clear(m, PG_WRITEABLE); 2441 PT_UPDATES_FLUSH(); 2442 if (*PMAP1) 2443 PT_SET_MA(PADDR1, 0); 2444 sched_unpin(); 2445 vm_page_unlock_queues(); 2446 pmap_free_zero_pages(free); 2447} 2448 2449/* 2450 * Set the physical protection on the 2451 * specified range of this map as requested. 2452 */ 2453void 2454pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2455{ 2456 vm_offset_t pdnxt; 2457 pd_entry_t ptpaddr; 2458 pt_entry_t *pte; 2459 int anychanged; 2460 2461 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2462 pmap, sva, eva, prot); 2463 2464 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2465 pmap_remove(pmap, sva, eva); 2466 return; 2467 } 2468 2469#ifdef PAE 2470 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2471 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2472 return; 2473#else 2474 if (prot & VM_PROT_WRITE) 2475 return; 2476#endif 2477 2478 anychanged = 0; 2479 2480 vm_page_lock_queues(); 2481 sched_pin(); 2482 PMAP_LOCK(pmap); 2483 for (; sva < eva; sva = pdnxt) { 2484 pt_entry_t obits, pbits; 2485 unsigned pdirindex; 2486 2487 pdnxt = (sva + NBPDR) & ~PDRMASK; 2488 2489 pdirindex = sva >> PDRSHIFT; 2490 ptpaddr = pmap->pm_pdir[pdirindex]; 2491 2492 /* 2493 * Weed out invalid mappings. Note: we assume that the page 2494 * directory table is always allocated, and in kernel virtual. 2495 */ 2496 if (ptpaddr == 0) 2497 continue; 2498 2499 /* 2500 * Check for large page. 2501 */ 2502 if ((ptpaddr & PG_PS) != 0) { 2503 if ((prot & VM_PROT_WRITE) == 0) 2504 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2505#ifdef PAE 2506 if ((prot & VM_PROT_EXECUTE) == 0) 2507 pmap->pm_pdir[pdirindex] |= pg_nx; 2508#endif 2509 anychanged = 1; 2510 continue; 2511 } 2512 2513 if (pdnxt > eva) 2514 pdnxt = eva; 2515 2516 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2517 sva += PAGE_SIZE) { 2518 vm_page_t m; 2519 2520retry: 2521 /* 2522 * Regardless of whether a pte is 32 or 64 bits in 2523 * size, PG_RW, PG_A, and PG_M are among the least 2524 * significant 32 bits. 2525 */ 2526 obits = pbits = *pte; 2527 if ((pbits & PG_V) == 0) 2528 continue; 2529 2530 if ((prot & VM_PROT_WRITE) == 0) { 2531 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2532 (PG_MANAGED | PG_M | PG_RW)) { 2533 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2534 PG_FRAME); 2535 vm_page_dirty(m); 2536 } 2537 pbits &= ~(PG_RW | PG_M); 2538 } 2539#ifdef PAE 2540 if ((prot & VM_PROT_EXECUTE) == 0) 2541 pbits |= pg_nx; 2542#endif 2543 2544 if (pbits != obits) { 2545 obits = *pte; 2546 PT_SET_VA_MA(pte, pbits, TRUE); 2547 if (*pte != pbits) 2548 goto retry; 2549 if (obits & PG_G) 2550 pmap_invalidate_page(pmap, sva); 2551 else 2552 anychanged = 1; 2553 } 2554 } 2555 } 2556 PT_UPDATES_FLUSH(); 2557 if (*PMAP1) 2558 PT_SET_VA_MA(PMAP1, 0, TRUE); 2559 if (anychanged) 2560 pmap_invalidate_all(pmap); 2561 sched_unpin(); 2562 vm_page_unlock_queues(); 2563 PMAP_UNLOCK(pmap); 2564} 2565 2566/* 2567 * Insert the given physical page (p) at 2568 * the specified virtual address (v) in the 2569 * target physical map with the protection requested. 2570 * 2571 * If specified, the page will be wired down, meaning 2572 * that the related pte can not be reclaimed. 2573 * 2574 * NB: This is the only routine which MAY NOT lazy-evaluate 2575 * or lose information. That is, this routine must actually 2576 * insert this page into the given map NOW. 2577 */ 2578void 2579pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2580 vm_prot_t prot, boolean_t wired) 2581{ 2582 pd_entry_t *pde; 2583 pt_entry_t *pte; 2584 pt_entry_t newpte, origpte; 2585 pv_entry_t pv; 2586 vm_paddr_t opa, pa; 2587 vm_page_t mpte, om; 2588 boolean_t invlva; 2589 2590 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2591 pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2592 va = trunc_page(va); 2593 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2594 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2595 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2596 va)); 2597 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 2598 (m->oflags & VPO_BUSY) != 0, 2599 ("pmap_enter: page %p is not busy", m)); 2600 2601 mpte = NULL; 2602 2603 vm_page_lock_queues(); 2604 PMAP_LOCK(pmap); 2605 sched_pin(); 2606 2607 /* 2608 * In the case that a page table page is not 2609 * resident, we are creating it here. 2610 */ 2611 if (va < VM_MAXUSER_ADDRESS) { 2612 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2613 } 2614 2615 pde = pmap_pde(pmap, va); 2616 if ((*pde & PG_PS) != 0) 2617 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2618 pte = pmap_pte_quick(pmap, va); 2619 2620 /* 2621 * Page Directory table entry not valid, we need a new PT page 2622 */ 2623 if (pte == NULL) { 2624 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2625 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2626 } 2627 2628 pa = VM_PAGE_TO_PHYS(m); 2629 om = NULL; 2630 opa = origpte = 0; 2631 2632#if 0 2633 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2634 pte, *pte)); 2635#endif 2636 origpte = *pte; 2637 if (origpte) 2638 origpte = xpmap_mtop(origpte); 2639 opa = origpte & PG_FRAME; 2640 2641 /* 2642 * Mapping has not changed, must be protection or wiring change. 2643 */ 2644 if (origpte && (opa == pa)) { 2645 /* 2646 * Wiring change, just update stats. We don't worry about 2647 * wiring PT pages as they remain resident as long as there 2648 * are valid mappings in them. Hence, if a user page is wired, 2649 * the PT page will be also. 2650 */ 2651 if (wired && ((origpte & PG_W) == 0)) 2652 pmap->pm_stats.wired_count++; 2653 else if (!wired && (origpte & PG_W)) 2654 pmap->pm_stats.wired_count--; 2655 2656 /* 2657 * Remove extra pte reference 2658 */ 2659 if (mpte) 2660 mpte->wire_count--; 2661 2662 if (origpte & PG_MANAGED) { 2663 om = m; 2664 pa |= PG_MANAGED; 2665 } 2666 goto validate; 2667 } 2668 2669 pv = NULL; 2670 2671 /* 2672 * Mapping has changed, invalidate old range and fall through to 2673 * handle validating new mapping. 2674 */ 2675 if (opa) { 2676 if (origpte & PG_W) 2677 pmap->pm_stats.wired_count--; 2678 if (origpte & PG_MANAGED) { 2679 om = PHYS_TO_VM_PAGE(opa); 2680 pv = pmap_pvh_remove(&om->md, pmap, va); 2681 } else if (va < VM_MAXUSER_ADDRESS) 2682 printf("va=0x%x is unmanaged :-( \n", va); 2683 2684 if (mpte != NULL) { 2685 mpte->wire_count--; 2686 KASSERT(mpte->wire_count > 0, 2687 ("pmap_enter: missing reference to page table page," 2688 " va: 0x%x", va)); 2689 } 2690 } else 2691 pmap->pm_stats.resident_count++; 2692 2693 /* 2694 * Enter on the PV list if part of our managed memory. 2695 */ 2696 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 2697 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2698 ("pmap_enter: managed mapping within the clean submap")); 2699 if (pv == NULL) 2700 pv = get_pv_entry(pmap, FALSE); 2701 pv->pv_va = va; 2702 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2703 pa |= PG_MANAGED; 2704 } else if (pv != NULL) 2705 free_pv_entry(pmap, pv); 2706 2707 /* 2708 * Increment counters 2709 */ 2710 if (wired) 2711 pmap->pm_stats.wired_count++; 2712 2713validate: 2714 /* 2715 * Now validate mapping with desired protection/wiring. 2716 */ 2717 newpte = (pt_entry_t)(pa | PG_V); 2718 if ((prot & VM_PROT_WRITE) != 0) { 2719 newpte |= PG_RW; 2720 if ((newpte & PG_MANAGED) != 0) 2721 vm_page_flag_set(m, PG_WRITEABLE); 2722 } 2723#ifdef PAE 2724 if ((prot & VM_PROT_EXECUTE) == 0) 2725 newpte |= pg_nx; 2726#endif 2727 if (wired) 2728 newpte |= PG_W; 2729 if (va < VM_MAXUSER_ADDRESS) 2730 newpte |= PG_U; 2731 if (pmap == kernel_pmap) 2732 newpte |= pgeflag; 2733 2734 critical_enter(); 2735 /* 2736 * if the mapping or permission bits are different, we need 2737 * to update the pte. 2738 */ 2739 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2740 if (origpte) { 2741 invlva = FALSE; 2742 origpte = *pte; 2743 PT_SET_VA(pte, newpte | PG_A, FALSE); 2744 if (origpte & PG_A) { 2745 if (origpte & PG_MANAGED) 2746 vm_page_flag_set(om, PG_REFERENCED); 2747 if (opa != VM_PAGE_TO_PHYS(m)) 2748 invlva = TRUE; 2749#ifdef PAE 2750 if ((origpte & PG_NX) == 0 && 2751 (newpte & PG_NX) != 0) 2752 invlva = TRUE; 2753#endif 2754 } 2755 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2756 if ((origpte & PG_MANAGED) != 0) 2757 vm_page_dirty(om); 2758 if ((prot & VM_PROT_WRITE) == 0) 2759 invlva = TRUE; 2760 } 2761 if ((origpte & PG_MANAGED) != 0 && 2762 TAILQ_EMPTY(&om->md.pv_list)) 2763 vm_page_flag_clear(om, PG_WRITEABLE); 2764 if (invlva) 2765 pmap_invalidate_page(pmap, va); 2766 } else{ 2767 PT_SET_VA(pte, newpte | PG_A, FALSE); 2768 } 2769 2770 } 2771 PT_UPDATES_FLUSH(); 2772 critical_exit(); 2773 if (*PMAP1) 2774 PT_SET_VA_MA(PMAP1, 0, TRUE); 2775 sched_unpin(); 2776 vm_page_unlock_queues(); 2777 PMAP_UNLOCK(pmap); 2778} 2779 2780/* 2781 * Maps a sequence of resident pages belonging to the same object. 2782 * The sequence begins with the given page m_start. This page is 2783 * mapped at the given virtual address start. Each subsequent page is 2784 * mapped at a virtual address that is offset from start by the same 2785 * amount as the page is offset from m_start within the object. The 2786 * last page in the sequence is the page with the largest offset from 2787 * m_start that can be mapped at a virtual address less than the given 2788 * virtual address end. Not every virtual page between start and end 2789 * is mapped; only those for which a resident page exists with the 2790 * corresponding offset from m_start are mapped. 2791 */ 2792void 2793pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2794 vm_page_t m_start, vm_prot_t prot) 2795{ 2796 vm_page_t m, mpte; 2797 vm_pindex_t diff, psize; 2798 multicall_entry_t mcl[16]; 2799 multicall_entry_t *mclp = mcl; 2800 int error, count = 0; 2801 2802 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2803 psize = atop(end - start); 2804 2805 mpte = NULL; 2806 m = m_start; 2807 vm_page_lock_queues(); 2808 PMAP_LOCK(pmap); 2809 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2810 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2811 prot, mpte); 2812 m = TAILQ_NEXT(m, listq); 2813 if (count == 16) { 2814 error = HYPERVISOR_multicall(mcl, count); 2815 KASSERT(error == 0, ("bad multicall %d", error)); 2816 mclp = mcl; 2817 count = 0; 2818 } 2819 } 2820 if (count) { 2821 error = HYPERVISOR_multicall(mcl, count); 2822 KASSERT(error == 0, ("bad multicall %d", error)); 2823 } 2824 vm_page_unlock_queues(); 2825 PMAP_UNLOCK(pmap); 2826} 2827 2828/* 2829 * this code makes some *MAJOR* assumptions: 2830 * 1. Current pmap & pmap exists. 2831 * 2. Not wired. 2832 * 3. Read access. 2833 * 4. No page table pages. 2834 * but is *MUCH* faster than pmap_enter... 2835 */ 2836 2837void 2838pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2839{ 2840 multicall_entry_t mcl, *mclp; 2841 int count = 0; 2842 mclp = &mcl; 2843 2844 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2845 pmap, va, m, prot); 2846 2847 vm_page_lock_queues(); 2848 PMAP_LOCK(pmap); 2849 (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2850 if (count) 2851 HYPERVISOR_multicall(&mcl, count); 2852 vm_page_unlock_queues(); 2853 PMAP_UNLOCK(pmap); 2854} 2855 2856#ifdef notyet 2857void 2858pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2859{ 2860 int i, error, index = 0; 2861 multicall_entry_t mcl[16]; 2862 multicall_entry_t *mclp = mcl; 2863 2864 PMAP_LOCK(pmap); 2865 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2866 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2867 continue; 2868 2869 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2870 if (index == 16) { 2871 error = HYPERVISOR_multicall(mcl, index); 2872 mclp = mcl; 2873 index = 0; 2874 KASSERT(error == 0, ("bad multicall %d", error)); 2875 } 2876 } 2877 if (index) { 2878 error = HYPERVISOR_multicall(mcl, index); 2879 KASSERT(error == 0, ("bad multicall %d", error)); 2880 } 2881 2882 PMAP_UNLOCK(pmap); 2883} 2884#endif 2885 2886static vm_page_t 2887pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2888 vm_prot_t prot, vm_page_t mpte) 2889{ 2890 pt_entry_t *pte; 2891 vm_paddr_t pa; 2892 vm_page_t free; 2893 multicall_entry_t *mcl = *mclpp; 2894 2895 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2896 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 2897 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2898 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2899 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2900 2901 /* 2902 * In the case that a page table page is not 2903 * resident, we are creating it here. 2904 */ 2905 if (va < VM_MAXUSER_ADDRESS) { 2906 unsigned ptepindex; 2907 pd_entry_t ptema; 2908 2909 /* 2910 * Calculate pagetable page index 2911 */ 2912 ptepindex = va >> PDRSHIFT; 2913 if (mpte && (mpte->pindex == ptepindex)) { 2914 mpte->wire_count++; 2915 } else { 2916 /* 2917 * Get the page directory entry 2918 */ 2919 ptema = pmap->pm_pdir[ptepindex]; 2920 2921 /* 2922 * If the page table page is mapped, we just increment 2923 * the hold count, and activate it. 2924 */ 2925 if (ptema & PG_V) { 2926 if (ptema & PG_PS) 2927 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2928 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2929 mpte->wire_count++; 2930 } else { 2931 mpte = _pmap_allocpte(pmap, ptepindex, 2932 M_NOWAIT); 2933 if (mpte == NULL) 2934 return (mpte); 2935 } 2936 } 2937 } else { 2938 mpte = NULL; 2939 } 2940 2941 /* 2942 * This call to vtopte makes the assumption that we are 2943 * entering the page into the current pmap. In order to support 2944 * quick entry into any pmap, one would likely use pmap_pte_quick. 2945 * But that isn't as quick as vtopte. 2946 */ 2947 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 2948 pte = vtopte(va); 2949 if (*pte & PG_V) { 2950 if (mpte != NULL) { 2951 mpte->wire_count--; 2952 mpte = NULL; 2953 } 2954 return (mpte); 2955 } 2956 2957 /* 2958 * Enter on the PV list if part of our managed memory. 2959 */ 2960 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 2961 !pmap_try_insert_pv_entry(pmap, va, m)) { 2962 if (mpte != NULL) { 2963 free = NULL; 2964 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 2965 pmap_invalidate_page(pmap, va); 2966 pmap_free_zero_pages(free); 2967 } 2968 2969 mpte = NULL; 2970 } 2971 return (mpte); 2972 } 2973 2974 /* 2975 * Increment counters 2976 */ 2977 pmap->pm_stats.resident_count++; 2978 2979 pa = VM_PAGE_TO_PHYS(m); 2980#ifdef PAE 2981 if ((prot & VM_PROT_EXECUTE) == 0) 2982 pa |= pg_nx; 2983#endif 2984 2985#if 0 2986 /* 2987 * Now validate mapping with RO protection 2988 */ 2989 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 2990 pte_store(pte, pa | PG_V | PG_U); 2991 else 2992 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 2993#else 2994 /* 2995 * Now validate mapping with RO protection 2996 */ 2997 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 2998 pa = xpmap_ptom(pa | PG_V | PG_U); 2999 else 3000 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3001 3002 mcl->op = __HYPERVISOR_update_va_mapping; 3003 mcl->args[0] = va; 3004 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3005 mcl->args[2] = (uint32_t)(pa >> 32); 3006 mcl->args[3] = 0; 3007 *mclpp = mcl + 1; 3008 *count = *count + 1; 3009#endif 3010 return mpte; 3011} 3012 3013/* 3014 * Make a temporary mapping for a physical address. This is only intended 3015 * to be used for panic dumps. 3016 */ 3017void * 3018pmap_kenter_temporary(vm_paddr_t pa, int i) 3019{ 3020 vm_offset_t va; 3021 vm_paddr_t ma = xpmap_ptom(pa); 3022 3023 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3024 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3025 invlpg(va); 3026 return ((void *)crashdumpmap); 3027} 3028 3029/* 3030 * This code maps large physical mmap regions into the 3031 * processor address space. Note that some shortcuts 3032 * are taken, but the code works. 3033 */ 3034void 3035pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 3036 vm_object_t object, vm_pindex_t pindex, 3037 vm_size_t size) 3038{ 3039 pd_entry_t *pde; 3040 vm_paddr_t pa, ptepa; 3041 vm_page_t p; 3042 int pat_mode; 3043 3044 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3045 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3046 ("pmap_object_init_pt: non-device object")); 3047 if (pseflag && 3048 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3049 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3050 return; 3051 p = vm_page_lookup(object, pindex); 3052 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3053 ("pmap_object_init_pt: invalid page %p", p)); 3054 pat_mode = p->md.pat_mode; 3055 /* 3056 * Abort the mapping if the first page is not physically 3057 * aligned to a 2/4MB page boundary. 3058 */ 3059 ptepa = VM_PAGE_TO_PHYS(p); 3060 if (ptepa & (NBPDR - 1)) 3061 return; 3062 /* 3063 * Skip the first page. Abort the mapping if the rest of 3064 * the pages are not physically contiguous or have differing 3065 * memory attributes. 3066 */ 3067 p = TAILQ_NEXT(p, listq); 3068 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3069 pa += PAGE_SIZE) { 3070 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3071 ("pmap_object_init_pt: invalid page %p", p)); 3072 if (pa != VM_PAGE_TO_PHYS(p) || 3073 pat_mode != p->md.pat_mode) 3074 return; 3075 p = TAILQ_NEXT(p, listq); 3076 } 3077 /* Map using 2/4MB pages. */ 3078 PMAP_LOCK(pmap); 3079 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3080 size; pa += NBPDR) { 3081 pde = pmap_pde(pmap, addr); 3082 if (*pde == 0) { 3083 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3084 PG_U | PG_RW | PG_V); 3085 pmap->pm_stats.resident_count += NBPDR / 3086 PAGE_SIZE; 3087 pmap_pde_mappings++; 3088 } 3089 /* Else continue on if the PDE is already valid. */ 3090 addr += NBPDR; 3091 } 3092 PMAP_UNLOCK(pmap); 3093 } 3094} 3095 3096/* 3097 * Routine: pmap_change_wiring 3098 * Function: Change the wiring attribute for a map/virtual-address 3099 * pair. 3100 * In/out conditions: 3101 * The mapping must already exist in the pmap. 3102 */ 3103void 3104pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3105{ 3106 pt_entry_t *pte; 3107 3108 vm_page_lock_queues(); 3109 PMAP_LOCK(pmap); 3110 pte = pmap_pte(pmap, va); 3111 3112 if (wired && !pmap_pte_w(pte)) { 3113 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3114 pmap->pm_stats.wired_count++; 3115 } else if (!wired && pmap_pte_w(pte)) { 3116 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3117 pmap->pm_stats.wired_count--; 3118 } 3119 3120 /* 3121 * Wiring is not a hardware characteristic so there is no need to 3122 * invalidate TLB. 3123 */ 3124 pmap_pte_release(pte); 3125 PMAP_UNLOCK(pmap); 3126 vm_page_unlock_queues(); 3127} 3128 3129 3130 3131/* 3132 * Copy the range specified by src_addr/len 3133 * from the source map to the range dst_addr/len 3134 * in the destination map. 3135 * 3136 * This routine is only advisory and need not do anything. 3137 */ 3138 3139void 3140pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3141 vm_offset_t src_addr) 3142{ 3143 vm_page_t free; 3144 vm_offset_t addr; 3145 vm_offset_t end_addr = src_addr + len; 3146 vm_offset_t pdnxt; 3147 3148 if (dst_addr != src_addr) 3149 return; 3150 3151 if (!pmap_is_current(src_pmap)) { 3152 CTR2(KTR_PMAP, 3153 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3154 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3155 3156 return; 3157 } 3158 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3159 dst_pmap, src_pmap, dst_addr, len, src_addr); 3160 3161 vm_page_lock_queues(); 3162 if (dst_pmap < src_pmap) { 3163 PMAP_LOCK(dst_pmap); 3164 PMAP_LOCK(src_pmap); 3165 } else { 3166 PMAP_LOCK(src_pmap); 3167 PMAP_LOCK(dst_pmap); 3168 } 3169 sched_pin(); 3170 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3171 pt_entry_t *src_pte, *dst_pte; 3172 vm_page_t dstmpte, srcmpte; 3173 pd_entry_t srcptepaddr; 3174 unsigned ptepindex; 3175 3176 KASSERT(addr < UPT_MIN_ADDRESS, 3177 ("pmap_copy: invalid to pmap_copy page tables")); 3178 3179 pdnxt = (addr + NBPDR) & ~PDRMASK; 3180 ptepindex = addr >> PDRSHIFT; 3181 3182 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3183 if (srcptepaddr == 0) 3184 continue; 3185 3186 if (srcptepaddr & PG_PS) { 3187 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3188 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3189 dst_pmap->pm_stats.resident_count += 3190 NBPDR / PAGE_SIZE; 3191 } 3192 continue; 3193 } 3194 3195 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3196 KASSERT(srcmpte->wire_count > 0, 3197 ("pmap_copy: source page table page is unused")); 3198 3199 if (pdnxt > end_addr) 3200 pdnxt = end_addr; 3201 3202 src_pte = vtopte(addr); 3203 while (addr < pdnxt) { 3204 pt_entry_t ptetemp; 3205 ptetemp = *src_pte; 3206 /* 3207 * we only virtual copy managed pages 3208 */ 3209 if ((ptetemp & PG_MANAGED) != 0) { 3210 dstmpte = pmap_allocpte(dst_pmap, addr, 3211 M_NOWAIT); 3212 if (dstmpte == NULL) 3213 break; 3214 dst_pte = pmap_pte_quick(dst_pmap, addr); 3215 if (*dst_pte == 0 && 3216 pmap_try_insert_pv_entry(dst_pmap, addr, 3217 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3218 /* 3219 * Clear the wired, modified, and 3220 * accessed (referenced) bits 3221 * during the copy. 3222 */ 3223 KASSERT(ptetemp != 0, ("src_pte not set")); 3224 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3225 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3226 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3227 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3228 dst_pmap->pm_stats.resident_count++; 3229 } else { 3230 free = NULL; 3231 if (pmap_unwire_pte_hold(dst_pmap, 3232 dstmpte, &free)) { 3233 pmap_invalidate_page(dst_pmap, 3234 addr); 3235 pmap_free_zero_pages(free); 3236 } 3237 } 3238 if (dstmpte->wire_count >= srcmpte->wire_count) 3239 break; 3240 } 3241 addr += PAGE_SIZE; 3242 src_pte++; 3243 } 3244 } 3245 PT_UPDATES_FLUSH(); 3246 sched_unpin(); 3247 vm_page_unlock_queues(); 3248 PMAP_UNLOCK(src_pmap); 3249 PMAP_UNLOCK(dst_pmap); 3250} 3251 3252static __inline void 3253pagezero(void *page) 3254{ 3255#if defined(I686_CPU) 3256 if (cpu_class == CPUCLASS_686) { 3257#if defined(CPU_ENABLE_SSE) 3258 if (cpu_feature & CPUID_SSE2) 3259 sse2_pagezero(page); 3260 else 3261#endif 3262 i686_pagezero(page); 3263 } else 3264#endif 3265 bzero(page, PAGE_SIZE); 3266} 3267 3268/* 3269 * pmap_zero_page zeros the specified hardware page by mapping 3270 * the page into KVM and using bzero to clear its contents. 3271 */ 3272void 3273pmap_zero_page(vm_page_t m) 3274{ 3275 struct sysmaps *sysmaps; 3276 3277 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3278 mtx_lock(&sysmaps->lock); 3279 if (*sysmaps->CMAP2) 3280 panic("pmap_zero_page: CMAP2 busy"); 3281 sched_pin(); 3282 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3283 pagezero(sysmaps->CADDR2); 3284 PT_SET_MA(sysmaps->CADDR2, 0); 3285 sched_unpin(); 3286 mtx_unlock(&sysmaps->lock); 3287} 3288 3289/* 3290 * pmap_zero_page_area zeros the specified hardware page by mapping 3291 * the page into KVM and using bzero to clear its contents. 3292 * 3293 * off and size may not cover an area beyond a single hardware page. 3294 */ 3295void 3296pmap_zero_page_area(vm_page_t m, int off, int size) 3297{ 3298 struct sysmaps *sysmaps; 3299 3300 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3301 mtx_lock(&sysmaps->lock); 3302 if (*sysmaps->CMAP2) 3303 panic("pmap_zero_page: CMAP2 busy"); 3304 sched_pin(); 3305 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3306 3307 if (off == 0 && size == PAGE_SIZE) 3308 pagezero(sysmaps->CADDR2); 3309 else 3310 bzero((char *)sysmaps->CADDR2 + off, size); 3311 PT_SET_MA(sysmaps->CADDR2, 0); 3312 sched_unpin(); 3313 mtx_unlock(&sysmaps->lock); 3314} 3315 3316/* 3317 * pmap_zero_page_idle zeros the specified hardware page by mapping 3318 * the page into KVM and using bzero to clear its contents. This 3319 * is intended to be called from the vm_pagezero process only and 3320 * outside of Giant. 3321 */ 3322void 3323pmap_zero_page_idle(vm_page_t m) 3324{ 3325 3326 if (*CMAP3) 3327 panic("pmap_zero_page: CMAP3 busy"); 3328 sched_pin(); 3329 PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3330 pagezero(CADDR3); 3331 PT_SET_MA(CADDR3, 0); 3332 sched_unpin(); 3333} 3334 3335/* 3336 * pmap_copy_page copies the specified (machine independent) 3337 * page by mapping the page into virtual memory and using 3338 * bcopy to copy the page, one machine dependent page at a 3339 * time. 3340 */ 3341void 3342pmap_copy_page(vm_page_t src, vm_page_t dst) 3343{ 3344 struct sysmaps *sysmaps; 3345 3346 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3347 mtx_lock(&sysmaps->lock); 3348 if (*sysmaps->CMAP1) 3349 panic("pmap_copy_page: CMAP1 busy"); 3350 if (*sysmaps->CMAP2) 3351 panic("pmap_copy_page: CMAP2 busy"); 3352 sched_pin(); 3353 PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3354 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3355 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3356 PT_SET_MA(sysmaps->CADDR1, 0); 3357 PT_SET_MA(sysmaps->CADDR2, 0); 3358 sched_unpin(); 3359 mtx_unlock(&sysmaps->lock); 3360} 3361 3362/* 3363 * Returns true if the pmap's pv is one of the first 3364 * 16 pvs linked to from this page. This count may 3365 * be changed upwards or downwards in the future; it 3366 * is only necessary that true be returned for a small 3367 * subset of pmaps for proper page aging. 3368 */ 3369boolean_t 3370pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3371{ 3372 pv_entry_t pv; 3373 int loops = 0; 3374 boolean_t rv; 3375 3376 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3377 ("pmap_page_exists_quick: page %p is not managed", m)); 3378 rv = FALSE; 3379 vm_page_lock_queues(); 3380 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3381 if (PV_PMAP(pv) == pmap) { 3382 rv = TRUE; 3383 break; 3384 } 3385 loops++; 3386 if (loops >= 16) 3387 break; 3388 } 3389 vm_page_unlock_queues(); 3390 return (rv); 3391} 3392 3393/* 3394 * pmap_page_wired_mappings: 3395 * 3396 * Return the number of managed mappings to the given physical page 3397 * that are wired. 3398 */ 3399int 3400pmap_page_wired_mappings(vm_page_t m) 3401{ 3402 pv_entry_t pv; 3403 pt_entry_t *pte; 3404 pmap_t pmap; 3405 int count; 3406 3407 count = 0; 3408 if ((m->flags & PG_FICTITIOUS) != 0) 3409 return (count); 3410 vm_page_lock_queues(); 3411 sched_pin(); 3412 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3413 pmap = PV_PMAP(pv); 3414 PMAP_LOCK(pmap); 3415 pte = pmap_pte_quick(pmap, pv->pv_va); 3416 if ((*pte & PG_W) != 0) 3417 count++; 3418 PMAP_UNLOCK(pmap); 3419 } 3420 sched_unpin(); 3421 vm_page_unlock_queues(); 3422 return (count); 3423} 3424 3425/* 3426 * Returns TRUE if the given page is mapped individually or as part of 3427 * a 4mpage. Otherwise, returns FALSE. 3428 */ 3429boolean_t 3430pmap_page_is_mapped(vm_page_t m) 3431{ 3432 boolean_t rv; 3433 3434 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 3435 return (FALSE); 3436 vm_page_lock_queues(); 3437 rv = !TAILQ_EMPTY(&m->md.pv_list) || 3438 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list); 3439 vm_page_unlock_queues(); 3440 return (rv); 3441} 3442 3443/* 3444 * Remove all pages from specified address space 3445 * this aids process exit speeds. Also, this code 3446 * is special cased for current process only, but 3447 * can have the more generic (and slightly slower) 3448 * mode enabled. This is much faster than pmap_remove 3449 * in the case of running down an entire address space. 3450 */ 3451void 3452pmap_remove_pages(pmap_t pmap) 3453{ 3454 pt_entry_t *pte, tpte; 3455 vm_page_t m, free = NULL; 3456 pv_entry_t pv; 3457 struct pv_chunk *pc, *npc; 3458 int field, idx; 3459 int32_t bit; 3460 uint32_t inuse, bitmask; 3461 int allfree; 3462 3463 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3464 3465 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3466 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3467 return; 3468 } 3469 vm_page_lock_queues(); 3470 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3471 PMAP_LOCK(pmap); 3472 sched_pin(); 3473 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3474 allfree = 1; 3475 for (field = 0; field < _NPCM; field++) { 3476 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 3477 while (inuse != 0) { 3478 bit = bsfl(inuse); 3479 bitmask = 1UL << bit; 3480 idx = field * 32 + bit; 3481 pv = &pc->pc_pventry[idx]; 3482 inuse &= ~bitmask; 3483 3484 pte = vtopte(pv->pv_va); 3485 tpte = *pte ? xpmap_mtop(*pte) : 0; 3486 3487 if (tpte == 0) { 3488 printf( 3489 "TPTE at %p IS ZERO @ VA %08x\n", 3490 pte, pv->pv_va); 3491 panic("bad pte"); 3492 } 3493 3494/* 3495 * We cannot remove wired pages from a process' mapping at this time 3496 */ 3497 if (tpte & PG_W) { 3498 allfree = 0; 3499 continue; 3500 } 3501 3502 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3503 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3504 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3505 m, (uintmax_t)m->phys_addr, 3506 (uintmax_t)tpte)); 3507 3508 KASSERT(m < &vm_page_array[vm_page_array_size], 3509 ("pmap_remove_pages: bad tpte %#jx", 3510 (uintmax_t)tpte)); 3511 3512 3513 PT_CLEAR_VA(pte, FALSE); 3514 3515 /* 3516 * Update the vm_page_t clean/reference bits. 3517 */ 3518 if (tpte & PG_M) 3519 vm_page_dirty(m); 3520 3521 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3522 if (TAILQ_EMPTY(&m->md.pv_list)) 3523 vm_page_flag_clear(m, PG_WRITEABLE); 3524 3525 pmap_unuse_pt(pmap, pv->pv_va, &free); 3526 3527 /* Mark free */ 3528 PV_STAT(pv_entry_frees++); 3529 PV_STAT(pv_entry_spare++); 3530 pv_entry_count--; 3531 pc->pc_map[field] |= bitmask; 3532 pmap->pm_stats.resident_count--; 3533 } 3534 } 3535 PT_UPDATES_FLUSH(); 3536 if (allfree) { 3537 PV_STAT(pv_entry_spare -= _NPCPV); 3538 PV_STAT(pc_chunk_count--); 3539 PV_STAT(pc_chunk_frees++); 3540 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3541 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 3542 pmap_qremove((vm_offset_t)pc, 1); 3543 vm_page_unwire(m, 0); 3544 vm_page_free(m); 3545 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 3546 } 3547 } 3548 PT_UPDATES_FLUSH(); 3549 if (*PMAP1) 3550 PT_SET_MA(PADDR1, 0); 3551 3552 sched_unpin(); 3553 pmap_invalidate_all(pmap); 3554 vm_page_unlock_queues(); 3555 PMAP_UNLOCK(pmap); 3556 pmap_free_zero_pages(free); 3557} 3558 3559/* 3560 * pmap_is_modified: 3561 * 3562 * Return whether or not the specified physical page was modified 3563 * in any physical maps. 3564 */ 3565boolean_t 3566pmap_is_modified(vm_page_t m) 3567{ 3568 pv_entry_t pv; 3569 pt_entry_t *pte; 3570 pmap_t pmap; 3571 boolean_t rv; 3572 3573 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3574 ("pmap_is_modified: page %p is not managed", m)); 3575 rv = FALSE; 3576 3577 /* 3578 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 3579 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 3580 * is clear, no PTEs can have PG_M set. 3581 */ 3582 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3583 if ((m->oflags & VPO_BUSY) == 0 && 3584 (m->flags & PG_WRITEABLE) == 0) 3585 return (rv); 3586 vm_page_lock_queues(); 3587 sched_pin(); 3588 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3589 pmap = PV_PMAP(pv); 3590 PMAP_LOCK(pmap); 3591 pte = pmap_pte_quick(pmap, pv->pv_va); 3592 rv = (*pte & PG_M) != 0; 3593 PMAP_UNLOCK(pmap); 3594 if (rv) 3595 break; 3596 } 3597 if (*PMAP1) 3598 PT_SET_MA(PADDR1, 0); 3599 sched_unpin(); 3600 vm_page_unlock_queues(); 3601 return (rv); 3602} 3603 3604/* 3605 * pmap_is_prefaultable: 3606 * 3607 * Return whether or not the specified virtual address is elgible 3608 * for prefault. 3609 */ 3610static boolean_t 3611pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3612{ 3613 pt_entry_t *pte; 3614 boolean_t rv = FALSE; 3615 3616 return (rv); 3617 3618 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3619 pte = vtopte(addr); 3620 rv = (*pte == 0); 3621 } 3622 return (rv); 3623} 3624 3625boolean_t 3626pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3627{ 3628 boolean_t rv; 3629 3630 PMAP_LOCK(pmap); 3631 rv = pmap_is_prefaultable_locked(pmap, addr); 3632 PMAP_UNLOCK(pmap); 3633 return (rv); 3634} 3635 3636boolean_t 3637pmap_is_referenced(vm_page_t m) 3638{ 3639 pv_entry_t pv; 3640 pt_entry_t *pte; 3641 pmap_t pmap; 3642 boolean_t rv; 3643 3644 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3645 ("pmap_is_referenced: page %p is not managed", m)); 3646 rv = FALSE; 3647 vm_page_lock_queues(); 3648 sched_pin(); 3649 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3650 pmap = PV_PMAP(pv); 3651 PMAP_LOCK(pmap); 3652 pte = pmap_pte_quick(pmap, pv->pv_va); 3653 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3654 PMAP_UNLOCK(pmap); 3655 if (rv) 3656 break; 3657 } 3658 if (*PMAP1) 3659 PT_SET_MA(PADDR1, 0); 3660 sched_unpin(); 3661 vm_page_unlock_queues(); 3662 return (rv); 3663} 3664 3665void 3666pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3667{ 3668 int i, npages = round_page(len) >> PAGE_SHIFT; 3669 for (i = 0; i < npages; i++) { 3670 pt_entry_t *pte; 3671 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3672 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3673 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3674 pmap_pte_release(pte); 3675 } 3676} 3677 3678void 3679pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3680{ 3681 int i, npages = round_page(len) >> PAGE_SHIFT; 3682 for (i = 0; i < npages; i++) { 3683 pt_entry_t *pte; 3684 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3685 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3686 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3687 pmap_pte_release(pte); 3688 } 3689} 3690 3691/* 3692 * Clear the write and modified bits in each of the given page's mappings. 3693 */ 3694void 3695pmap_remove_write(vm_page_t m) 3696{ 3697 pv_entry_t pv; 3698 pmap_t pmap; 3699 pt_entry_t oldpte, *pte; 3700 3701 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3702 ("pmap_remove_write: page %p is not managed", m)); 3703 3704 /* 3705 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 3706 * another thread while the object is locked. Thus, if PG_WRITEABLE 3707 * is clear, no page table entries need updating. 3708 */ 3709 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3710 if ((m->oflags & VPO_BUSY) == 0 && 3711 (m->flags & PG_WRITEABLE) == 0) 3712 return; 3713 vm_page_lock_queues(); 3714 sched_pin(); 3715 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3716 pmap = PV_PMAP(pv); 3717 PMAP_LOCK(pmap); 3718 pte = pmap_pte_quick(pmap, pv->pv_va); 3719retry: 3720 oldpte = *pte; 3721 if ((oldpte & PG_RW) != 0) { 3722 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3723 3724 /* 3725 * Regardless of whether a pte is 32 or 64 bits 3726 * in size, PG_RW and PG_M are among the least 3727 * significant 32 bits. 3728 */ 3729 PT_SET_VA_MA(pte, newpte, TRUE); 3730 if (*pte != newpte) 3731 goto retry; 3732 3733 if ((oldpte & PG_M) != 0) 3734 vm_page_dirty(m); 3735 pmap_invalidate_page(pmap, pv->pv_va); 3736 } 3737 PMAP_UNLOCK(pmap); 3738 } 3739 vm_page_flag_clear(m, PG_WRITEABLE); 3740 PT_UPDATES_FLUSH(); 3741 if (*PMAP1) 3742 PT_SET_MA(PADDR1, 0); 3743 sched_unpin(); 3744 vm_page_unlock_queues(); 3745} 3746 3747/* 3748 * pmap_ts_referenced: 3749 * 3750 * Return a count of reference bits for a page, clearing those bits. 3751 * It is not necessary for every reference bit to be cleared, but it 3752 * is necessary that 0 only be returned when there are truly no 3753 * reference bits set. 3754 * 3755 * XXX: The exact number of bits to check and clear is a matter that 3756 * should be tested and standardized at some point in the future for 3757 * optimal aging of shared pages. 3758 */ 3759int 3760pmap_ts_referenced(vm_page_t m) 3761{ 3762 pv_entry_t pv, pvf, pvn; 3763 pmap_t pmap; 3764 pt_entry_t *pte; 3765 int rtval = 0; 3766 3767 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3768 ("pmap_ts_referenced: page %p is not managed", m)); 3769 vm_page_lock_queues(); 3770 sched_pin(); 3771 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3772 pvf = pv; 3773 do { 3774 pvn = TAILQ_NEXT(pv, pv_list); 3775 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3776 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3777 pmap = PV_PMAP(pv); 3778 PMAP_LOCK(pmap); 3779 pte = pmap_pte_quick(pmap, pv->pv_va); 3780 if ((*pte & PG_A) != 0) { 3781 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3782 pmap_invalidate_page(pmap, pv->pv_va); 3783 rtval++; 3784 if (rtval > 4) 3785 pvn = NULL; 3786 } 3787 PMAP_UNLOCK(pmap); 3788 } while ((pv = pvn) != NULL && pv != pvf); 3789 } 3790 PT_UPDATES_FLUSH(); 3791 if (*PMAP1) 3792 PT_SET_MA(PADDR1, 0); 3793 3794 sched_unpin(); 3795 vm_page_unlock_queues(); 3796 return (rtval); 3797} 3798 3799/* 3800 * Clear the modify bits on the specified physical page. 3801 */ 3802void 3803pmap_clear_modify(vm_page_t m) 3804{ 3805 pv_entry_t pv; 3806 pmap_t pmap; 3807 pt_entry_t *pte; 3808 3809 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3810 ("pmap_clear_modify: page %p is not managed", m)); 3811 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3812 KASSERT((m->oflags & VPO_BUSY) == 0, 3813 ("pmap_clear_modify: page %p is busy", m)); 3814 3815 /* 3816 * If the page is not PG_WRITEABLE, then no PTEs can have PG_M set. 3817 * If the object containing the page is locked and the page is not 3818 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 3819 */ 3820 if ((m->flags & PG_WRITEABLE) == 0) 3821 return; 3822 vm_page_lock_queues(); 3823 sched_pin(); 3824 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3825 pmap = PV_PMAP(pv); 3826 PMAP_LOCK(pmap); 3827 pte = pmap_pte_quick(pmap, pv->pv_va); 3828 if ((*pte & PG_M) != 0) { 3829 /* 3830 * Regardless of whether a pte is 32 or 64 bits 3831 * in size, PG_M is among the least significant 3832 * 32 bits. 3833 */ 3834 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3835 pmap_invalidate_page(pmap, pv->pv_va); 3836 } 3837 PMAP_UNLOCK(pmap); 3838 } 3839 sched_unpin(); 3840 vm_page_unlock_queues(); 3841} 3842 3843/* 3844 * pmap_clear_reference: 3845 * 3846 * Clear the reference bit on the specified physical page. 3847 */ 3848void 3849pmap_clear_reference(vm_page_t m) 3850{ 3851 pv_entry_t pv; 3852 pmap_t pmap; 3853 pt_entry_t *pte; 3854 3855 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 3856 ("pmap_clear_reference: page %p is not managed", m)); 3857 vm_page_lock_queues(); 3858 sched_pin(); 3859 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3860 pmap = PV_PMAP(pv); 3861 PMAP_LOCK(pmap); 3862 pte = pmap_pte_quick(pmap, pv->pv_va); 3863 if ((*pte & PG_A) != 0) { 3864 /* 3865 * Regardless of whether a pte is 32 or 64 bits 3866 * in size, PG_A is among the least significant 3867 * 32 bits. 3868 */ 3869 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3870 pmap_invalidate_page(pmap, pv->pv_va); 3871 } 3872 PMAP_UNLOCK(pmap); 3873 } 3874 sched_unpin(); 3875 vm_page_unlock_queues(); 3876} 3877 3878/* 3879 * Miscellaneous support routines follow 3880 */ 3881 3882/* 3883 * Map a set of physical memory pages into the kernel virtual 3884 * address space. Return a pointer to where it is mapped. This 3885 * routine is intended to be used for mapping device memory, 3886 * NOT real memory. 3887 */ 3888void * 3889pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 3890{ 3891 vm_offset_t va, offset; 3892 vm_size_t tmpsize; 3893 3894 offset = pa & PAGE_MASK; 3895 size = roundup(offset + size, PAGE_SIZE); 3896 pa = pa & PG_FRAME; 3897 3898 if (pa < KERNLOAD && pa + size <= KERNLOAD) 3899 va = KERNBASE + pa; 3900 else 3901 va = kmem_alloc_nofault(kernel_map, size); 3902 if (!va) 3903 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3904 3905 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 3906 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 3907 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 3908 pmap_invalidate_cache_range(va, va + size); 3909 return ((void *)(va + offset)); 3910} 3911 3912void * 3913pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3914{ 3915 3916 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 3917} 3918 3919void * 3920pmap_mapbios(vm_paddr_t pa, vm_size_t size) 3921{ 3922 3923 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 3924} 3925 3926void 3927pmap_unmapdev(vm_offset_t va, vm_size_t size) 3928{ 3929 vm_offset_t base, offset, tmpva; 3930 3931 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 3932 return; 3933 base = trunc_page(va); 3934 offset = va & PAGE_MASK; 3935 size = roundup(offset + size, PAGE_SIZE); 3936 critical_enter(); 3937 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 3938 pmap_kremove(tmpva); 3939 pmap_invalidate_range(kernel_pmap, va, tmpva); 3940 critical_exit(); 3941 kmem_free(kernel_map, base, size); 3942} 3943 3944/* 3945 * Sets the memory attribute for the specified page. 3946 */ 3947void 3948pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 3949{ 3950 struct sysmaps *sysmaps; 3951 vm_offset_t sva, eva; 3952 3953 m->md.pat_mode = ma; 3954 if ((m->flags & PG_FICTITIOUS) != 0) 3955 return; 3956 3957 /* 3958 * If "m" is a normal page, flush it from the cache. 3959 * See pmap_invalidate_cache_range(). 3960 * 3961 * First, try to find an existing mapping of the page by sf 3962 * buffer. sf_buf_invalidate_cache() modifies mapping and 3963 * flushes the cache. 3964 */ 3965 if (sf_buf_invalidate_cache(m)) 3966 return; 3967 3968 /* 3969 * If page is not mapped by sf buffer, but CPU does not 3970 * support self snoop, map the page transient and do 3971 * invalidation. In the worst case, whole cache is flushed by 3972 * pmap_invalidate_cache_range(). 3973 */ 3974 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 3975 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3976 mtx_lock(&sysmaps->lock); 3977 if (*sysmaps->CMAP2) 3978 panic("pmap_page_set_memattr: CMAP2 busy"); 3979 sched_pin(); 3980 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 3981 VM_PAGE_TO_MACH(m) | PG_A | PG_M | 3982 pmap_cache_bits(m->md.pat_mode, 0)); 3983 invlcaddr(sysmaps->CADDR2); 3984 sva = (vm_offset_t)sysmaps->CADDR2; 3985 eva = sva + PAGE_SIZE; 3986 } else 3987 sva = eva = 0; /* gcc */ 3988 pmap_invalidate_cache_range(sva, eva); 3989 if (sva != 0) { 3990 PT_SET_MA(sysmaps->CADDR2, 0); 3991 sched_unpin(); 3992 mtx_unlock(&sysmaps->lock); 3993 } 3994} 3995 3996int 3997pmap_change_attr(va, size, mode) 3998 vm_offset_t va; 3999 vm_size_t size; 4000 int mode; 4001{ 4002 vm_offset_t base, offset, tmpva; 4003 pt_entry_t *pte; 4004 u_int opte, npte; 4005 pd_entry_t *pde; 4006 boolean_t changed; 4007 4008 base = trunc_page(va); 4009 offset = va & PAGE_MASK; 4010 size = roundup(offset + size, PAGE_SIZE); 4011 4012 /* Only supported on kernel virtual addresses. */ 4013 if (base <= VM_MAXUSER_ADDRESS) 4014 return (EINVAL); 4015 4016 /* 4MB pages and pages that aren't mapped aren't supported. */ 4017 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4018 pde = pmap_pde(kernel_pmap, tmpva); 4019 if (*pde & PG_PS) 4020 return (EINVAL); 4021 if ((*pde & PG_V) == 0) 4022 return (EINVAL); 4023 pte = vtopte(va); 4024 if ((*pte & PG_V) == 0) 4025 return (EINVAL); 4026 } 4027 4028 changed = FALSE; 4029 4030 /* 4031 * Ok, all the pages exist and are 4k, so run through them updating 4032 * their cache mode. 4033 */ 4034 for (tmpva = base; size > 0; ) { 4035 pte = vtopte(tmpva); 4036 4037 /* 4038 * The cache mode bits are all in the low 32-bits of the 4039 * PTE, so we can just spin on updating the low 32-bits. 4040 */ 4041 do { 4042 opte = *(u_int *)pte; 4043 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4044 npte |= pmap_cache_bits(mode, 0); 4045 PT_SET_VA_MA(pte, npte, TRUE); 4046 } while (npte != opte && (*pte != npte)); 4047 if (npte != opte) 4048 changed = TRUE; 4049 tmpva += PAGE_SIZE; 4050 size -= PAGE_SIZE; 4051 } 4052 4053 /* 4054 * Flush CPU caches to make sure any data isn't cached that shouldn't 4055 * be, etc. 4056 */ 4057 if (changed) { 4058 pmap_invalidate_range(kernel_pmap, base, tmpva); 4059 pmap_invalidate_cache_range(base, tmpva); 4060 } 4061 return (0); 4062} 4063 4064/* 4065 * perform the pmap work for mincore 4066 */ 4067int 4068pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4069{ 4070 pt_entry_t *ptep, pte; 4071 vm_paddr_t pa; 4072 int val; 4073 4074 PMAP_LOCK(pmap); 4075retry: 4076 ptep = pmap_pte(pmap, addr); 4077 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4078 pmap_pte_release(ptep); 4079 val = 0; 4080 if ((pte & PG_V) != 0) { 4081 val |= MINCORE_INCORE; 4082 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4083 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4084 if ((pte & PG_A) != 0) 4085 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4086 } 4087 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4088 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4089 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4090 pa = pte & PG_FRAME; 4091 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4092 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4093 goto retry; 4094 } else 4095 PA_UNLOCK_COND(*locked_pa); 4096 PMAP_UNLOCK(pmap); 4097 return (val); 4098} 4099 4100void 4101pmap_activate(struct thread *td) 4102{ 4103 pmap_t pmap, oldpmap; 4104 u_int32_t cr3; 4105 4106 critical_enter(); 4107 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4108 oldpmap = PCPU_GET(curpmap); 4109#if defined(SMP) 4110 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 4111 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 4112#else 4113 oldpmap->pm_active &= ~1; 4114 pmap->pm_active |= 1; 4115#endif 4116#ifdef PAE 4117 cr3 = vtophys(pmap->pm_pdpt); 4118#else 4119 cr3 = vtophys(pmap->pm_pdir); 4120#endif 4121 /* 4122 * pmap_activate is for the current thread on the current cpu 4123 */ 4124 td->td_pcb->pcb_cr3 = cr3; 4125 PT_UPDATES_FLUSH(); 4126 load_cr3(cr3); 4127 PCPU_SET(curpmap, pmap); 4128 critical_exit(); 4129} 4130 4131void 4132pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4133{ 4134} 4135 4136/* 4137 * Increase the starting virtual address of the given mapping if a 4138 * different alignment might result in more superpage mappings. 4139 */ 4140void 4141pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4142 vm_offset_t *addr, vm_size_t size) 4143{ 4144 vm_offset_t superpage_offset; 4145 4146 if (size < NBPDR) 4147 return; 4148 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4149 offset += ptoa(object->pg_color); 4150 superpage_offset = offset & PDRMASK; 4151 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4152 (*addr & PDRMASK) == superpage_offset) 4153 return; 4154 if ((*addr & PDRMASK) < superpage_offset) 4155 *addr = (*addr & ~PDRMASK) + superpage_offset; 4156 else 4157 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4158} 4159 4160void 4161pmap_suspend() 4162{ 4163 pmap_t pmap; 4164 int i, pdir, offset; 4165 vm_paddr_t pdirma; 4166 mmu_update_t mu[4]; 4167 4168 /* 4169 * We need to remove the recursive mapping structure from all 4170 * our pmaps so that Xen doesn't get confused when it restores 4171 * the page tables. The recursive map lives at page directory 4172 * index PTDPTDI. We assume that the suspend code has stopped 4173 * the other vcpus (if any). 4174 */ 4175 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4176 for (i = 0; i < 4; i++) { 4177 /* 4178 * Figure out which page directory (L2) page 4179 * contains this bit of the recursive map and 4180 * the offset within that page of the map 4181 * entry 4182 */ 4183 pdir = (PTDPTDI + i) / NPDEPG; 4184 offset = (PTDPTDI + i) % NPDEPG; 4185 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4186 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4187 mu[i].val = 0; 4188 } 4189 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4190 } 4191} 4192 4193void 4194pmap_resume() 4195{ 4196 pmap_t pmap; 4197 int i, pdir, offset; 4198 vm_paddr_t pdirma; 4199 mmu_update_t mu[4]; 4200 4201 /* 4202 * Restore the recursive map that we removed on suspend. 4203 */ 4204 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4205 for (i = 0; i < 4; i++) { 4206 /* 4207 * Figure out which page directory (L2) page 4208 * contains this bit of the recursive map and 4209 * the offset within that page of the map 4210 * entry 4211 */ 4212 pdir = (PTDPTDI + i) / NPDEPG; 4213 offset = (PTDPTDI + i) % NPDEPG; 4214 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4215 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4216 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4217 } 4218 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4219 } 4220} 4221 4222#if defined(PMAP_DEBUG) 4223pmap_pid_dump(int pid) 4224{ 4225 pmap_t pmap; 4226 struct proc *p; 4227 int npte = 0; 4228 int index; 4229 4230 sx_slock(&allproc_lock); 4231 FOREACH_PROC_IN_SYSTEM(p) { 4232 if (p->p_pid != pid) 4233 continue; 4234 4235 if (p->p_vmspace) { 4236 int i,j; 4237 index = 0; 4238 pmap = vmspace_pmap(p->p_vmspace); 4239 for (i = 0; i < NPDEPTD; i++) { 4240 pd_entry_t *pde; 4241 pt_entry_t *pte; 4242 vm_offset_t base = i << PDRSHIFT; 4243 4244 pde = &pmap->pm_pdir[i]; 4245 if (pde && pmap_pde_v(pde)) { 4246 for (j = 0; j < NPTEPG; j++) { 4247 vm_offset_t va = base + (j << PAGE_SHIFT); 4248 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4249 if (index) { 4250 index = 0; 4251 printf("\n"); 4252 } 4253 sx_sunlock(&allproc_lock); 4254 return npte; 4255 } 4256 pte = pmap_pte(pmap, va); 4257 if (pte && pmap_pte_v(pte)) { 4258 pt_entry_t pa; 4259 vm_page_t m; 4260 pa = PT_GET(pte); 4261 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4262 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4263 va, pa, m->hold_count, m->wire_count, m->flags); 4264 npte++; 4265 index++; 4266 if (index >= 2) { 4267 index = 0; 4268 printf("\n"); 4269 } else { 4270 printf(" "); 4271 } 4272 } 4273 } 4274 } 4275 } 4276 } 4277 } 4278 sx_sunlock(&allproc_lock); 4279 return npte; 4280} 4281#endif 4282 4283#if defined(DEBUG) 4284 4285static void pads(pmap_t pm); 4286void pmap_pvdump(vm_paddr_t pa); 4287 4288/* print address space of pmap*/ 4289static void 4290pads(pmap_t pm) 4291{ 4292 int i, j; 4293 vm_paddr_t va; 4294 pt_entry_t *ptep; 4295 4296 if (pm == kernel_pmap) 4297 return; 4298 for (i = 0; i < NPDEPTD; i++) 4299 if (pm->pm_pdir[i]) 4300 for (j = 0; j < NPTEPG; j++) { 4301 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4302 if (pm == kernel_pmap && va < KERNBASE) 4303 continue; 4304 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4305 continue; 4306 ptep = pmap_pte(pm, va); 4307 if (pmap_pte_v(ptep)) 4308 printf("%x:%x ", va, *ptep); 4309 }; 4310 4311} 4312 4313void 4314pmap_pvdump(vm_paddr_t pa) 4315{ 4316 pv_entry_t pv; 4317 pmap_t pmap; 4318 vm_page_t m; 4319 4320 printf("pa %x", pa); 4321 m = PHYS_TO_VM_PAGE(pa); 4322 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4323 pmap = PV_PMAP(pv); 4324 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4325 pads(pmap); 4326 } 4327 printf(" "); 4328} 4329#endif 4330