pmap.c revision 181808
1/*-
2 * Copyright (c) 1991 Regents of the University of California.
3 * All rights reserved.
4 * Copyright (c) 1994 John S. Dyson
5 * All rights reserved.
6 * Copyright (c) 1994 David Greenman
7 * All rights reserved.
8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu>
9 * All rights reserved.
10 *
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 *    must display the following acknowledgement:
25 *	This product includes software developed by the University of
26 *	California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 *    may be used to endorse or promote products derived from this software
29 *    without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * SUCH DAMAGE.
42 *
43 *	from:	@(#)pmap.c	7.7 (Berkeley)	5/12/91
44 */
45/*-
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
48 *
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
54 *
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
57 * are met:
58 * 1. Redistributions of source code must retain the above copyright
59 *    notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 *    notice, this list of conditions and the following disclaimer in the
62 *    documentation and/or other materials provided with the distribution.
63 *
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 * SUCH DAMAGE.
75 */
76
77#include <sys/cdefs.h>
78__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 181808 2008-08-17 23:36:52Z kmacy $");
79
80/*
81 *	Manages physical address maps.
82 *
83 *	In addition to hardware address maps, this
84 *	module is called upon to provide software-use-only
85 *	maps which may or may not be stored in the same
86 *	form as hardware maps.  These pseudo-maps are
87 *	used to store intermediate results from copy
88 *	operations to and from address spaces.
89 *
90 *	Since the information managed by this module is
91 *	also stored by the logical address mapping module,
92 *	this module may throw away valid virtual-to-physical
93 *	mappings at almost any time.  However, invalidations
94 *	of virtual-to-physical mappings must be done as
95 *	requested.
96 *
97 *	In order to cope with hardware architectures which
98 *	make virtual-to-physical map invalidates expensive,
99 *	this module may delay invalidate or reduced protection
100 *	operations until such time as they are actually
101 *	necessary.  This module is given full information as
102 *	to which processors are currently using which maps,
103 *	and to when physical maps must be made correct.
104 */
105
106#define PMAP_DIAGNOSTIC
107
108#include "opt_cpu.h"
109#include "opt_pmap.h"
110#include "opt_msgbuf.h"
111#include "opt_smp.h"
112#include "opt_xbox.h"
113
114#include <sys/param.h>
115#include <sys/systm.h>
116#include <sys/kernel.h>
117#include <sys/ktr.h>
118#include <sys/lock.h>
119#include <sys/malloc.h>
120#include <sys/mman.h>
121#include <sys/msgbuf.h>
122#include <sys/mutex.h>
123#include <sys/proc.h>
124#include <sys/sx.h>
125#include <sys/vmmeter.h>
126#include <sys/sched.h>
127#include <sys/sysctl.h>
128#ifdef SMP
129#include <sys/smp.h>
130#endif
131
132#include <vm/vm.h>
133#include <vm/vm_param.h>
134#include <vm/vm_kern.h>
135#include <vm/vm_page.h>
136#include <vm/vm_map.h>
137#include <vm/vm_object.h>
138#include <vm/vm_extern.h>
139#include <vm/vm_pageout.h>
140#include <vm/vm_pager.h>
141#include <vm/uma.h>
142
143#include <machine/cpu.h>
144#include <machine/cputypes.h>
145#include <machine/md_var.h>
146#include <machine/pcb.h>
147#include <machine/specialreg.h>
148#ifdef SMP
149#include <machine/smp.h>
150#endif
151
152#ifdef XBOX
153#include <machine/xbox.h>
154#endif
155
156#include <xen/interface/xen.h>
157#include <machine/xen/hypervisor.h>
158#include <machine/xen/hypercall.h>
159#include <machine/xen/xenvar.h>
160#include <machine/xen/xenfunc.h>
161
162#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
163#define CPU_ENABLE_SSE
164#endif
165
166#ifndef PMAP_SHPGPERPROC
167#define PMAP_SHPGPERPROC 200
168#endif
169
170#if defined(DIAGNOSTIC)
171#define PMAP_DIAGNOSTIC
172#endif
173
174#if !defined(PMAP_DIAGNOSTIC)
175#define PMAP_INLINE	__gnu89_inline
176#else
177#define PMAP_INLINE
178#endif
179
180#define PV_STATS
181#ifdef PV_STATS
182#define PV_STAT(x)	do { x ; } while (0)
183#else
184#define PV_STAT(x)	do { } while (0)
185#endif
186
187#define	pa_index(pa)	((pa) >> PDRSHIFT)
188#define	pa_to_pvh(pa)	(&pv_table[pa_index(pa)])
189
190/*
191 * Get PDEs and PTEs for user/kernel address space
192 */
193#define	pmap_pde(m, v)	(&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
194#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
195
196#define pmap_pde_v(pte)		((*(int *)pte & PG_V) != 0)
197#define pmap_pte_w(pte)		((*(int *)pte & PG_W) != 0)
198#define pmap_pte_m(pte)		((*(int *)pte & PG_M) != 0)
199#define pmap_pte_u(pte)		((*(int *)pte & PG_A) != 0)
200#define pmap_pte_v(pte)		((*(int *)pte & PG_V) != 0)
201
202#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
203
204struct pmap kernel_pmap_store;
205LIST_HEAD(pmaplist, pmap);
206static struct pmaplist allpmaps;
207static struct mtx allpmaps_lock;
208
209vm_offset_t virtual_avail;	/* VA of first avail page (after kernel bss) */
210vm_offset_t virtual_end;	/* VA of last avail page (end of kernel AS) */
211int pgeflag = 0;		/* PG_G or-in */
212int pseflag = 0;		/* PG_PS or-in */
213
214static int nkpt;
215vm_offset_t kernel_vm_end;
216extern u_int32_t KERNend;
217
218#ifdef PAE
219pt_entry_t pg_nx;
220#if !defined(XEN)
221static uma_zone_t pdptzone;
222#endif
223#endif
224
225/*
226 * Data for the pv entry allocation mechanism
227 */
228static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
229static struct md_page *pv_table;
230static int shpgperproc = PMAP_SHPGPERPROC;
231
232struct pv_chunk *pv_chunkbase;		/* KVA block for pv_chunks */
233int pv_maxchunks;			/* How many chunks we have KVA for */
234vm_offset_t pv_vafree;			/* freelist stored in the PTE */
235
236/*
237 * All those kernel PT submaps that BSD is so fond of
238 */
239struct sysmaps {
240	struct	mtx lock;
241	pt_entry_t *CMAP1;
242	pt_entry_t *CMAP2;
243	caddr_t	CADDR1;
244	caddr_t	CADDR2;
245};
246static struct sysmaps sysmaps_pcpu[MAXCPU];
247pt_entry_t *CMAP1 = 0;
248static pt_entry_t *CMAP3;
249caddr_t CADDR1 = 0, ptvmmap = 0;
250static caddr_t CADDR3;
251struct msgbuf *msgbufp = 0;
252
253/*
254 * Crashdump maps.
255 */
256static caddr_t crashdumpmap;
257
258static pt_entry_t *PMAP1 = 0, *PMAP2;
259static pt_entry_t *PADDR1 = 0, *PADDR2;
260#ifdef SMP
261static int PMAP1cpu;
262static int PMAP1changedcpu;
263SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
264	   &PMAP1changedcpu, 0,
265	   "Number of times pmap_pte_quick changed CPU with same PMAP1");
266#endif
267static int PMAP1changed;
268SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
269	   &PMAP1changed, 0,
270	   "Number of times pmap_pte_quick changed PMAP1");
271static int PMAP1unchanged;
272SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
273	   &PMAP1unchanged, 0,
274	   "Number of times pmap_pte_quick didn't change PMAP1");
275static struct mtx PMAP2mutex;
276
277SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
278static int pg_ps_enabled;
279SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RD, &pg_ps_enabled, 0,
280    "Are large page mappings enabled?");
281
282SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
283	"Max number of PV entries");
284SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
285	"Page share factor per proc");
286
287static void	free_pv_entry(pmap_t pmap, pv_entry_t pv);
288static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try);
289
290static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va,
291    vm_page_t m, vm_prot_t prot, vm_page_t mpte);
292static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
293    vm_page_t *free);
294static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
295    vm_page_t *free);
296static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
297					vm_offset_t va);
298static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
299static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
300    vm_page_t m);
301
302static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
303
304static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags);
305static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free);
306static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
307static void pmap_pte_release(pt_entry_t *pte);
308static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *);
309static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
310static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr);
311static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
312
313
314#if defined(PAE) && !defined(XEN)
315static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait);
316#endif
317
318CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
319CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
320
321/*
322 * If you get an error here, then you set KVA_PAGES wrong! See the
323 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
324 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
325 */
326CTASSERT(KERNBASE % (1 << 24) == 0);
327
328
329
330static __inline void
331pagezero(void *page)
332{
333#if defined(I686_CPU)
334	if (cpu_class == CPUCLASS_686) {
335#if defined(CPU_ENABLE_SSE)
336		if (cpu_feature & CPUID_SSE2)
337			sse2_pagezero(page);
338		else
339#endif
340			i686_pagezero(page);
341	} else
342#endif
343		bzero(page, PAGE_SIZE);
344}
345
346void
347pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type)
348{
349	vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]);
350
351	switch (type) {
352	case SH_PD_SET_VA:
353#if 0
354		xen_queue_pt_update(shadow_pdir_ma,
355				    xpmap_ptom(val & ~(PG_RW)));
356#endif
357		xen_queue_pt_update(pdir_ma,
358				    xpmap_ptom(val));
359		break;
360	case SH_PD_SET_VA_MA:
361#if 0
362		xen_queue_pt_update(shadow_pdir_ma,
363				    val & ~(PG_RW));
364#endif
365		xen_queue_pt_update(pdir_ma, val);
366		break;
367	case SH_PD_SET_VA_CLEAR:
368#if 0
369		xen_queue_pt_update(shadow_pdir_ma, 0);
370#endif
371		xen_queue_pt_update(pdir_ma, 0);
372		break;
373	}
374}
375
376/*
377 * Move the kernel virtual free pointer to the next
378 * 4MB.  This is used to help improve performance
379 * by using a large (4MB) page for much of the kernel
380 * (.text, .data, .bss)
381 */
382static vm_offset_t
383pmap_kmem_choose(vm_offset_t addr)
384{
385	vm_offset_t newaddr = addr;
386
387#ifndef DISABLE_PSE
388	if (cpu_feature & CPUID_PSE)
389		newaddr = (addr + PDRMASK) & ~PDRMASK;
390#endif
391	return newaddr;
392}
393
394/*
395 *	Bootstrap the system enough to run with virtual memory.
396 *
397 *	On the i386 this is called after mapping has already been enabled
398 *	and just syncs the pmap module with what has already been done.
399 *	[We can't call it easily with mapping off since the kernel is not
400 *	mapped with PA == VA, hence we would have to relocate every address
401 *	from the linked base (virtual) address "KERNBASE" to the actual
402 *	(physical) address starting relative to 0]
403 */
404void
405pmap_bootstrap(vm_paddr_t firstaddr)
406{
407	vm_offset_t va;
408	pt_entry_t *pte, *unused;
409	struct sysmaps *sysmaps;
410	int i;
411
412	/*
413	 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too
414	 * large. It should instead be correctly calculated in locore.s and
415	 * not based on 'first' (which is a physical address, not a virtual
416	 * address, for the start of unused physical memory). The kernel
417	 * page tables are NOT double mapped and thus should not be included
418	 * in this calculation.
419	 */
420	virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
421	virtual_avail = pmap_kmem_choose(virtual_avail);
422
423	virtual_end = VM_MAX_KERNEL_ADDRESS;
424
425	/*
426	 * Initialize the kernel pmap (which is statically allocated).
427	 */
428	PMAP_LOCK_INIT(kernel_pmap);
429	kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
430#ifdef PAE
431	kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
432#endif
433	kernel_pmap->pm_active = -1;	/* don't allow deactivation */
434	TAILQ_INIT(&kernel_pmap->pm_pvchunk);
435	LIST_INIT(&allpmaps);
436	mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
437	mtx_lock_spin(&allpmaps_lock);
438	LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
439	mtx_unlock_spin(&allpmaps_lock);
440	nkpt = NKPT;
441
442	/*
443	 * Reserve some special page table entries/VA space for temporary
444	 * mapping of pages.
445	 */
446#define	SYSMAP(c, p, v, n)	\
447	v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
448
449	va = virtual_avail;
450	pte = vtopte(va);
451
452	/*
453	 * CMAP1/CMAP2 are used for zeroing and copying pages.
454	 * CMAP3 is used for the idle process page zeroing.
455	 */
456	for (i = 0; i < MAXCPU; i++) {
457		sysmaps = &sysmaps_pcpu[i];
458		mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
459		SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
460		SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
461	}
462	SYSMAP(caddr_t, CMAP1, CADDR1, 1)
463	SYSMAP(caddr_t, CMAP3, CADDR3, 1)
464	PT_SET_MA(CADDR3, 0);
465
466	/*
467	 * Crashdump maps.
468	 */
469	SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
470
471	/*
472	 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
473	 */
474	SYSMAP(caddr_t, unused, ptvmmap, 1)
475
476	/*
477	 * msgbufp is used to map the system message buffer.
478	 */
479	SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE)))
480
481	/*
482	 * ptemap is used for pmap_pte_quick
483	 */
484	SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1);
485	SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1);
486
487	mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
488
489	virtual_avail = va;
490	PT_SET_MA(CADDR1, 0);
491
492	/*
493	 * Leave in place an identity mapping (virt == phys) for the low 1 MB
494	 * physical memory region that is used by the ACPI wakeup code.  This
495	 * mapping must not have PG_G set.
496	 */
497#ifndef XEN
498	/*
499	 * leave here deliberately to show that this is not supported
500	 */
501#ifdef XBOX
502	/* FIXME: This is gross, but needed for the XBOX. Since we are in such
503	 * an early stadium, we cannot yet neatly map video memory ... :-(
504	 * Better fixes are very welcome! */
505	if (!arch_i386_is_xbox)
506#endif
507	for (i = 1; i < NKPT; i++)
508		PTD[i] = 0;
509
510	/* Initialize the PAT MSR if present. */
511	pmap_init_pat();
512
513	/* Turn on PG_G on kernel page(s) */
514	pmap_set_pg();
515#endif
516}
517
518/*
519 * Setup the PAT MSR.
520 */
521void
522pmap_init_pat(void)
523{
524	uint64_t pat_msr;
525
526	/* Bail if this CPU doesn't implement PAT. */
527	if (!(cpu_feature & CPUID_PAT))
528		return;
529
530#ifdef PAT_WORKS
531	/*
532	 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-.
533	 * Program 4 and 5 as WP and WC.
534	 * Leave 6 and 7 as UC and UC-.
535	 */
536	pat_msr = rdmsr(MSR_PAT);
537	pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5));
538	pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) |
539	    PAT_VALUE(5, PAT_WRITE_COMBINING);
540#else
541	/*
542	 * Due to some Intel errata, we can only safely use the lower 4
543	 * PAT entries.  Thus, just replace PAT Index 2 with WC instead
544	 * of UC-.
545	 *
546	 *   Intel Pentium III Processor Specification Update
547	 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
548	 * or Mode C Paging)
549	 *
550	 *   Intel Pentium IV  Processor Specification Update
551	 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
552	 */
553	pat_msr = rdmsr(MSR_PAT);
554	pat_msr &= ~PAT_MASK(2);
555	pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
556#endif
557	wrmsr(MSR_PAT, pat_msr);
558}
559
560/*
561 * Set PG_G on kernel pages.  Only the BSP calls this when SMP is turned on.
562 */
563void
564pmap_set_pg(void)
565{
566	pd_entry_t pdir;
567	pt_entry_t *pte;
568	vm_offset_t va, endva;
569	int i;
570
571	if (pgeflag == 0)
572		return;
573
574	i = KERNLOAD/NBPDR;
575	endva = KERNBASE + KERNend;
576
577	if (pseflag) {
578		va = KERNBASE + KERNLOAD;
579		while (va  < endva) {
580			pdir = kernel_pmap->pm_pdir[KPTDI+i];
581			pdir |= pgeflag;
582			kernel_pmap->pm_pdir[KPTDI+i] = PTD[KPTDI+i] = pdir;
583			invltlb();	/* Play it safe, invltlb() every time */
584			i++;
585			va += NBPDR;
586		}
587	} else {
588		va = (vm_offset_t)btext;
589		while (va < endva) {
590			pte = vtopte(va);
591			if (*pte & PG_V)
592				*pte |= pgeflag;
593			invltlb();	/* Play it safe, invltlb() every time */
594			va += PAGE_SIZE;
595		}
596	}
597}
598
599/*
600 * Initialize a vm_page's machine-dependent fields.
601 */
602void
603pmap_page_init(vm_page_t m)
604{
605
606	TAILQ_INIT(&m->md.pv_list);
607}
608
609#if defined(PAE) && !defined(XEN)
610
611static MALLOC_DEFINE(M_PMAPPDPT, "pmap", "pmap pdpt");
612
613static void *
614pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
615{
616	*flags = UMA_SLAB_PRIV;
617	return (contigmalloc(PAGE_SIZE, M_PMAPPDPT, 0, 0x0ULL, 0xffffffffULL,
618	    1, 0));
619}
620#endif
621
622/*
623 * ABuse the pte nodes for unmapped kva to thread a kva freelist through.
624 * Requirements:
625 *  - Must deal with pages in order to ensure that none of the PG_* bits
626 *    are ever set, PG_V in particular.
627 *  - Assumes we can write to ptes without pte_store() atomic ops, even
628 *    on PAE systems.  This should be ok.
629 *  - Assumes nothing will ever test these addresses for 0 to indicate
630 *    no mapping instead of correctly checking PG_V.
631 *  - Assumes a vm_offset_t will fit in a pte (true for i386).
632 * Because PG_V is never set, there can be no mappings to invalidate.
633 */
634static int ptelist_count = 0;
635static vm_offset_t
636pmap_ptelist_alloc(vm_offset_t *head)
637{
638	vm_offset_t va;
639	vm_offset_t *phead = (vm_offset_t *)*head;
640
641	if (ptelist_count == 0) {
642		printf("out of memory!!!!!!\n");
643		return (0);	/* Out of memory */
644	}
645	ptelist_count--;
646	va = phead[ptelist_count];
647	return (va);
648}
649
650static void
651pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
652{
653	vm_offset_t *phead = (vm_offset_t *)*head;
654
655	phead[ptelist_count++] = va;
656}
657
658static void
659pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
660{
661	int i, nstackpages;
662	vm_offset_t va;
663	vm_page_t m;
664
665	nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t));
666	for (i = 0; i < nstackpages; i++) {
667		va = (vm_offset_t)base + i * PAGE_SIZE;
668		m = vm_page_alloc(NULL, i,
669		    VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
670		    VM_ALLOC_ZERO);
671		pmap_qenter(va, &m, 1);
672	}
673
674	*head = (vm_offset_t)base;
675	for (i = npages - 1; i >= nstackpages; i--) {
676		va = (vm_offset_t)base + i * PAGE_SIZE;
677		pmap_ptelist_free(head, va);
678	}
679}
680
681
682/*
683 *	Initialize the pmap module.
684 *	Called by vm_init, to initialize any structures that the pmap
685 *	system needs to map virtual memory.
686 */
687void
688pmap_init(void)
689{
690	vm_page_t mpte;
691	vm_size_t s;
692	int i, pv_npg;
693
694	/*
695	 * Initialize the vm page array entries for the kernel pmap's
696	 * page table pages.
697	 */
698	for (i = 0; i < nkpt; i++) {
699		mpte = PHYS_TO_VM_PAGE(xpmap_mtop(PTD[i + KPTDI] & PG_FRAME));
700		KASSERT(mpte >= vm_page_array &&
701		    mpte < &vm_page_array[vm_page_array_size],
702		    ("pmap_init: page table page is out of range"));
703		mpte->pindex = i + KPTDI;
704		mpte->phys_addr = xpmap_mtop(PTD[i + KPTDI] & PG_FRAME);
705	}
706
707        /*
708	 * Initialize the address space (zone) for the pv entries.  Set a
709	 * high water mark so that the system can recover from excessive
710	 * numbers of pv entries.
711	 */
712	TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
713	pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
714	TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
715	pv_entry_max = roundup(pv_entry_max, _NPCPV);
716	pv_entry_high_water = 9 * (pv_entry_max / 10);
717
718	/*
719	 * Are large page mappings enabled?
720	 */
721	TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
722
723	/*
724	 * Calculate the size of the pv head table for superpages.
725	 */
726	for (i = 0; phys_avail[i + 1]; i += 2);
727	pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR;
728
729	/*
730	 * Allocate memory for the pv head table for superpages.
731	 */
732	s = (vm_size_t)(pv_npg * sizeof(struct md_page));
733	s = round_page(s);
734	pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
735	for (i = 0; i < pv_npg; i++)
736		TAILQ_INIT(&pv_table[i].pv_list);
737
738	pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
739	pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map,
740	    PAGE_SIZE * pv_maxchunks);
741	if (pv_chunkbase == NULL)
742		panic("pmap_init: not enough kvm for pv chunks");
743	pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
744#if defined(PAE) && !defined(XEN)
745	pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
746	    NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
747	    UMA_ZONE_VM | UMA_ZONE_NOFREE);
748	uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
749#endif
750}
751
752
753/***************************************************
754 * Low level helper routines.....
755 ***************************************************/
756
757/*
758 * Determine the appropriate bits to set in a PTE or PDE for a specified
759 * caching mode.
760 */
761static int
762pmap_cache_bits(int mode, boolean_t is_pde)
763{
764	int pat_flag, pat_index, cache_bits;
765
766	/* The PAT bit is different for PTE's and PDE's. */
767	pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
768
769	/* If we don't support PAT, map extended modes to older ones. */
770	if (!(cpu_feature & CPUID_PAT)) {
771		switch (mode) {
772		case PAT_UNCACHEABLE:
773		case PAT_WRITE_THROUGH:
774		case PAT_WRITE_BACK:
775			break;
776		case PAT_UNCACHED:
777		case PAT_WRITE_COMBINING:
778		case PAT_WRITE_PROTECTED:
779			mode = PAT_UNCACHEABLE;
780			break;
781		}
782	}
783
784	/* Map the caching mode to a PAT index. */
785	switch (mode) {
786#ifdef PAT_WORKS
787	case PAT_UNCACHEABLE:
788		pat_index = 3;
789		break;
790	case PAT_WRITE_THROUGH:
791		pat_index = 1;
792		break;
793	case PAT_WRITE_BACK:
794		pat_index = 0;
795		break;
796	case PAT_UNCACHED:
797		pat_index = 2;
798		break;
799	case PAT_WRITE_COMBINING:
800		pat_index = 5;
801		break;
802	case PAT_WRITE_PROTECTED:
803		pat_index = 4;
804		break;
805#else
806	case PAT_UNCACHED:
807	case PAT_UNCACHEABLE:
808	case PAT_WRITE_PROTECTED:
809		pat_index = 3;
810		break;
811	case PAT_WRITE_THROUGH:
812		pat_index = 1;
813		break;
814	case PAT_WRITE_BACK:
815		pat_index = 0;
816		break;
817	case PAT_WRITE_COMBINING:
818		pat_index = 2;
819		break;
820#endif
821	default:
822		panic("Unknown caching mode %d\n", mode);
823	}
824
825	/* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
826	cache_bits = 0;
827	if (pat_index & 0x4)
828		cache_bits |= pat_flag;
829	if (pat_index & 0x2)
830		cache_bits |= PG_NC_PCD;
831	if (pat_index & 0x1)
832		cache_bits |= PG_NC_PWT;
833	return (cache_bits);
834}
835#ifdef SMP
836/*
837 * For SMP, these functions have to use the IPI mechanism for coherence.
838 *
839 * N.B.: Before calling any of the following TLB invalidation functions,
840 * the calling processor must ensure that all stores updating a non-
841 * kernel page table are globally performed.  Otherwise, another
842 * processor could cache an old, pre-update entry without being
843 * invalidated.  This can happen one of two ways: (1) The pmap becomes
844 * active on another processor after its pm_active field is checked by
845 * one of the following functions but before a store updating the page
846 * table is globally performed. (2) The pmap becomes active on another
847 * processor before its pm_active field is checked but due to
848 * speculative loads one of the following functions stills reads the
849 * pmap as inactive on the other processor.
850 *
851 * The kernel page table is exempt because its pm_active field is
852 * immutable.  The kernel page table is always active on every
853 * processor.
854 */
855void
856pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
857{
858	u_int cpumask;
859	u_int other_cpus;
860
861	CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x",
862	    pmap, va);
863
864	sched_pin();
865	if (pmap == kernel_pmap || pmap->pm_active == all_cpus) {
866		invlpg(va);
867		smp_invlpg(va);
868	} else {
869		cpumask = PCPU_GET(cpumask);
870		other_cpus = PCPU_GET(other_cpus);
871		if (pmap->pm_active & cpumask)
872			invlpg(va);
873		if (pmap->pm_active & other_cpus)
874			smp_masked_invlpg(pmap->pm_active & other_cpus, va);
875	}
876	sched_unpin();
877	PT_UPDATES_FLUSH();
878}
879
880void
881pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
882{
883	u_int cpumask;
884	u_int other_cpus;
885	vm_offset_t addr;
886
887	CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x",
888	    pmap, sva, eva);
889
890	sched_pin();
891	if (pmap == kernel_pmap || pmap->pm_active == all_cpus) {
892		for (addr = sva; addr < eva; addr += PAGE_SIZE)
893			invlpg(addr);
894		smp_invlpg_range(sva, eva);
895	} else {
896		cpumask = PCPU_GET(cpumask);
897		other_cpus = PCPU_GET(other_cpus);
898		if (pmap->pm_active & cpumask)
899			for (addr = sva; addr < eva; addr += PAGE_SIZE)
900				invlpg(addr);
901		if (pmap->pm_active & other_cpus)
902			smp_masked_invlpg_range(pmap->pm_active & other_cpus,
903			    sva, eva);
904	}
905	sched_unpin();
906	PT_UPDATES_FLUSH();
907}
908
909void
910pmap_invalidate_all(pmap_t pmap)
911{
912	u_int cpumask;
913	u_int other_cpus;
914
915	CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap);
916
917	sched_pin();
918	if (pmap == kernel_pmap || pmap->pm_active == all_cpus) {
919		invltlb();
920		smp_invltlb();
921	} else {
922		cpumask = PCPU_GET(cpumask);
923		other_cpus = PCPU_GET(other_cpus);
924		if (pmap->pm_active & cpumask)
925			invltlb();
926		if (pmap->pm_active & other_cpus)
927			smp_masked_invltlb(pmap->pm_active & other_cpus);
928	}
929	sched_unpin();
930}
931
932void
933pmap_invalidate_cache(void)
934{
935
936	sched_pin();
937	wbinvd();
938	smp_cache_flush();
939	sched_unpin();
940}
941#else /* !SMP */
942/*
943 * Normal, non-SMP, 486+ invalidation functions.
944 * We inline these within pmap.c for speed.
945 */
946PMAP_INLINE void
947pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
948{
949	CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x",
950	    pmap, va);
951
952	if (pmap == kernel_pmap || pmap->pm_active)
953		invlpg(va);
954	PT_UPDATES_FLUSH();
955}
956
957PMAP_INLINE void
958pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
959{
960	vm_offset_t addr;
961
962	if (eva - sva > PAGE_SIZE)
963		CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x",
964		    pmap, sva, eva);
965
966	if (pmap == kernel_pmap || pmap->pm_active)
967		for (addr = sva; addr < eva; addr += PAGE_SIZE)
968			invlpg(addr);
969	PT_UPDATES_FLUSH();
970}
971
972PMAP_INLINE void
973pmap_invalidate_all(pmap_t pmap)
974{
975
976	CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap);
977
978	if (pmap == kernel_pmap || pmap->pm_active)
979		invltlb();
980}
981
982PMAP_INLINE void
983pmap_invalidate_cache(void)
984{
985
986	wbinvd();
987}
988#endif /* !SMP */
989
990/*
991 * Are we current address space or kernel?  N.B. We return FALSE when
992 * a pmap's page table is in use because a kernel thread is borrowing
993 * it.  The borrowed page table can change spontaneously, making any
994 * dependence on its continued use subject to a race condition.
995 */
996static __inline int
997pmap_is_current(pmap_t pmap)
998{
999
1000	return (pmap == kernel_pmap ||
1001	    (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) &&
1002		(pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME)));
1003}
1004
1005/*
1006 * If the given pmap is not the current or kernel pmap, the returned pte must
1007 * be released by passing it to pmap_pte_release().
1008 */
1009pt_entry_t *
1010pmap_pte(pmap_t pmap, vm_offset_t va)
1011{
1012	pd_entry_t newpf;
1013	pd_entry_t *pde;
1014
1015	pde = pmap_pde(pmap, va);
1016	if (*pde & PG_PS)
1017		return (pde);
1018	if (*pde != 0) {
1019		/* are we current address space or kernel? */
1020		if (pmap_is_current(pmap))
1021			return (vtopte(va));
1022		mtx_lock(&PMAP2mutex);
1023		newpf = *pde & PG_FRAME;
1024		if ((*PMAP2 & PG_FRAME) != newpf) {
1025			PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M);
1026			CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x",
1027			    pmap, va, (*PMAP2 & 0xffffffff));
1028		}
1029
1030		return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1031	}
1032	return (0);
1033}
1034
1035/*
1036 * Releases a pte that was obtained from pmap_pte().  Be prepared for the pte
1037 * being NULL.
1038 */
1039static __inline void
1040pmap_pte_release(pt_entry_t *pte)
1041{
1042
1043	if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) {
1044		CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx",
1045		    *PMAP2);
1046		PT_SET_VA(PMAP2, 0, TRUE);
1047		mtx_unlock(&PMAP2mutex);
1048	}
1049}
1050
1051static __inline void
1052invlcaddr(void *caddr)
1053{
1054
1055	invlpg((u_int)caddr);
1056	PT_UPDATES_FLUSH();
1057}
1058
1059/*
1060 * Super fast pmap_pte routine best used when scanning
1061 * the pv lists.  This eliminates many coarse-grained
1062 * invltlb calls.  Note that many of the pv list
1063 * scans are across different pmaps.  It is very wasteful
1064 * to do an entire invltlb for checking a single mapping.
1065 *
1066 * If the given pmap is not the current pmap, vm_page_queue_mtx
1067 * must be held and curthread pinned to a CPU.
1068 */
1069static pt_entry_t *
1070pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1071{
1072	pd_entry_t newpf;
1073	pd_entry_t *pde;
1074
1075	pde = pmap_pde(pmap, va);
1076	if (*pde & PG_PS)
1077		return (pde);
1078	if (*pde != 0) {
1079		/* are we current address space or kernel? */
1080		if (pmap_is_current(pmap))
1081			return (vtopte(va));
1082		mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1083		KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1084		newpf = *pde & PG_FRAME;
1085		if ((*PMAP1 & PG_FRAME) != newpf) {
1086			PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M);
1087			CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x",
1088			    pmap, va, (u_long)*PMAP1);
1089
1090#ifdef SMP
1091			PMAP1cpu = PCPU_GET(cpuid);
1092#endif
1093			PMAP1changed++;
1094		} else
1095#ifdef SMP
1096		if (PMAP1cpu != PCPU_GET(cpuid)) {
1097			PMAP1cpu = PCPU_GET(cpuid);
1098			invlcaddr(PADDR1);
1099			PMAP1changedcpu++;
1100		} else
1101#endif
1102			PMAP1unchanged++;
1103		return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1104	}
1105	return (0);
1106}
1107
1108/*
1109 *	Routine:	pmap_extract
1110 *	Function:
1111 *		Extract the physical page address associated
1112 *		with the given map/virtual_address pair.
1113 */
1114vm_paddr_t
1115pmap_extract(pmap_t pmap, vm_offset_t va)
1116{
1117	vm_paddr_t rtval;
1118	pt_entry_t *pte;
1119	pd_entry_t pde;
1120	pt_entry_t pteval;
1121
1122	rtval = 0;
1123	PMAP_LOCK(pmap);
1124	pde = pmap->pm_pdir[va >> PDRSHIFT];
1125	if (pde != 0) {
1126		if ((pde & PG_PS) != 0) {
1127			rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK);
1128			PMAP_UNLOCK(pmap);
1129			return rtval;
1130		}
1131		pte = pmap_pte(pmap, va);
1132		pteval = *pte ? xpmap_mtop(*pte) : 0;
1133		rtval = (pteval & PG_FRAME) | (va & PAGE_MASK);
1134		pmap_pte_release(pte);
1135	}
1136	PMAP_UNLOCK(pmap);
1137	return (rtval);
1138}
1139
1140/*
1141 *	Routine:	pmap_extract_ma
1142 *	Function:
1143 *		Like pmap_extract, but returns machine address
1144 */
1145vm_paddr_t
1146pmap_extract_ma(pmap_t pmap, vm_offset_t va)
1147{
1148	vm_paddr_t rtval;
1149	pt_entry_t *pte;
1150	pd_entry_t pde;
1151
1152	rtval = 0;
1153	PMAP_LOCK(pmap);
1154	pde = pmap->pm_pdir[va >> PDRSHIFT];
1155	if (pde != 0) {
1156		if ((pde & PG_PS) != 0) {
1157			rtval = (pde & ~PDRMASK) | (va & PDRMASK);
1158			PMAP_UNLOCK(pmap);
1159			return rtval;
1160		}
1161		pte = pmap_pte(pmap, va);
1162		rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1163		pmap_pte_release(pte);
1164	}
1165	PMAP_UNLOCK(pmap);
1166	return (rtval);
1167}
1168
1169/*
1170 *	Routine:	pmap_extract_and_hold
1171 *	Function:
1172 *		Atomically extract and hold the physical page
1173 *		with the given pmap and virtual address pair
1174 *		if that mapping permits the given protection.
1175 */
1176vm_page_t
1177pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1178{
1179	pd_entry_t pde;
1180	pt_entry_t pte;
1181	vm_page_t m;
1182
1183	m = NULL;
1184	vm_page_lock_queues();
1185	PMAP_LOCK(pmap);
1186	pde = PT_GET(pmap_pde(pmap, va));
1187	if (pde != 0) {
1188		if (pde & PG_PS) {
1189			if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1190				m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1191				    (va & PDRMASK));
1192				vm_page_hold(m);
1193			}
1194		} else {
1195			sched_pin();
1196			pte = PT_GET(pmap_pte_quick(pmap, va));
1197			if (*PMAP1)
1198				PT_SET_MA(PADDR1, 0);
1199			if ((pte & PG_V) &&
1200			    ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1201				m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1202				vm_page_hold(m);
1203			}
1204			sched_unpin();
1205		}
1206	}
1207	vm_page_unlock_queues();
1208	PMAP_UNLOCK(pmap);
1209	return (m);
1210}
1211
1212/***************************************************
1213 * Low level mapping routines.....
1214 ***************************************************/
1215
1216/*
1217 * Add a wired page to the kva.
1218 * Note: not SMP coherent.
1219 */
1220void
1221pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1222{
1223	PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag);
1224}
1225
1226void
1227pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma)
1228{
1229	pt_entry_t *pte;
1230
1231	pte = vtopte(va);
1232	pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag);
1233}
1234
1235
1236static __inline void
1237pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1238{
1239	PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1240}
1241
1242/*
1243 * Remove a page from the kernel pagetables.
1244 * Note: not SMP coherent.
1245 */
1246PMAP_INLINE void
1247pmap_kremove(vm_offset_t va)
1248{
1249	pt_entry_t *pte;
1250
1251	pte = vtopte(va);
1252	PT_CLEAR_VA(pte, FALSE);
1253}
1254
1255/*
1256 *	Used to map a range of physical addresses into kernel
1257 *	virtual address space.
1258 *
1259 *	The value passed in '*virt' is a suggested virtual address for
1260 *	the mapping. Architectures which can support a direct-mapped
1261 *	physical to virtual region can return the appropriate address
1262 *	within that region, leaving '*virt' unchanged. Other
1263 *	architectures should map the pages starting at '*virt' and
1264 *	update '*virt' with the first usable address after the mapped
1265 *	region.
1266 */
1267vm_offset_t
1268pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1269{
1270	vm_offset_t va, sva;
1271
1272	va = sva = *virt;
1273	CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x",
1274	    va, start, end, prot);
1275	while (start < end) {
1276		pmap_kenter(va, start);
1277		va += PAGE_SIZE;
1278		start += PAGE_SIZE;
1279	}
1280	pmap_invalidate_range(kernel_pmap, sva, va);
1281	*virt = va;
1282	return (sva);
1283}
1284
1285
1286/*
1287 * Add a list of wired pages to the kva
1288 * this routine is only used for temporary
1289 * kernel mappings that do not need to have
1290 * page modification or references recorded.
1291 * Note that old mappings are simply written
1292 * over.  The page *must* be wired.
1293 * Note: SMP coherent.  Uses a ranged shootdown IPI.
1294 */
1295void
1296pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1297{
1298	pt_entry_t *endpte, *pte;
1299	vm_paddr_t pa;
1300	vm_offset_t va = sva;
1301	int mclcount = 0;
1302	multicall_entry_t mcl[16];
1303	multicall_entry_t *mclp = mcl;
1304	int error;
1305
1306	CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count);
1307	pte = vtopte(sva);
1308	endpte = pte + count;
1309	while (pte < endpte) {
1310		pa = xpmap_ptom(VM_PAGE_TO_PHYS(*ma)) | pgeflag | PG_RW | PG_V | PG_M | PG_A;
1311
1312		mclp->op = __HYPERVISOR_update_va_mapping;
1313		mclp->args[0] = va;
1314		mclp->args[1] = (uint32_t)(pa & 0xffffffff);
1315		mclp->args[2] = (uint32_t)(pa >> 32);
1316		mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0;
1317
1318		va += PAGE_SIZE;
1319		pte++;
1320		ma++;
1321		mclp++;
1322		mclcount++;
1323		if (mclcount == 16) {
1324			error = HYPERVISOR_multicall(mcl, mclcount);
1325			mclp = mcl;
1326			mclcount = 0;
1327			KASSERT(error == 0, ("bad multicall %d", error));
1328		}
1329	}
1330	if (mclcount) {
1331		error = HYPERVISOR_multicall(mcl, mclcount);
1332		KASSERT(error == 0, ("bad multicall %d", error));
1333	}
1334
1335#ifdef INVARIANTS
1336	for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++)
1337		KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE));
1338#endif
1339}
1340
1341
1342/*
1343 * This routine tears out page mappings from the
1344 * kernel -- it is meant only for temporary mappings.
1345 * Note: SMP coherent.  Uses a ranged shootdown IPI.
1346 */
1347void
1348pmap_qremove(vm_offset_t sva, int count)
1349{
1350	vm_offset_t va;
1351
1352	CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count);
1353	va = sva;
1354	vm_page_lock_queues();
1355	critical_enter();
1356	while (count-- > 0) {
1357		pmap_kremove(va);
1358		va += PAGE_SIZE;
1359	}
1360	pmap_invalidate_range(kernel_pmap, sva, va);
1361	critical_exit();
1362	vm_page_unlock_queues();
1363}
1364
1365/***************************************************
1366 * Page table page management routines.....
1367 ***************************************************/
1368static __inline void
1369pmap_free_zero_pages(vm_page_t free)
1370{
1371	vm_page_t m;
1372
1373	while (free != NULL) {
1374		m = free;
1375		free = m->right;
1376		vm_page_free_zero(m);
1377	}
1378}
1379
1380/*
1381 * This routine unholds page table pages, and if the hold count
1382 * drops to zero, then it decrements the wire count.
1383 */
1384static __inline int
1385pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1386{
1387
1388	--m->wire_count;
1389	if (m->wire_count == 0)
1390		return _pmap_unwire_pte_hold(pmap, m, free);
1391	else
1392		return 0;
1393}
1394
1395static int
1396_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1397{
1398	vm_offset_t pteva;
1399
1400	PT_UPDATES_FLUSH();
1401	/*
1402	 * unmap the page table page
1403	 */
1404	xen_pt_unpin(pmap->pm_pdir[m->pindex]);
1405	/*
1406	 * page *might* contain residual mapping :-/
1407	 */
1408	PD_CLEAR_VA(pmap, m->pindex, TRUE);
1409	pmap_zero_page(m);
1410	--pmap->pm_stats.resident_count;
1411
1412	/*
1413	 * This is a release store so that the ordinary store unmapping
1414	 * the page table page is globally performed before TLB shoot-
1415	 * down is begun.
1416	 */
1417	atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1418
1419	/*
1420	 * Do an invltlb to make the invalidated mapping
1421	 * take effect immediately.
1422	 */
1423	pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1424	pmap_invalidate_page(pmap, pteva);
1425
1426	/*
1427	 * Put page on a list so that it is released after
1428	 * *ALL* TLB shootdown is done
1429	 */
1430	m->right = *free;
1431	*free = m;
1432
1433	return 1;
1434}
1435
1436/*
1437 * After removing a page table entry, this routine is used to
1438 * conditionally free the page, and manage the hold/wire counts.
1439 */
1440static int
1441pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free)
1442{
1443	pd_entry_t ptepde;
1444	vm_page_t mpte;
1445
1446	if (va >= VM_MAXUSER_ADDRESS)
1447		return 0;
1448	ptepde = PT_GET(pmap_pde(pmap, va));
1449	mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1450	return pmap_unwire_pte_hold(pmap, mpte, free);
1451}
1452
1453void
1454pmap_pinit0(pmap_t pmap)
1455{
1456
1457	PMAP_LOCK_INIT(pmap);
1458	pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1459#ifdef PAE
1460	pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1461#endif
1462	pmap->pm_active = 0;
1463	PCPU_SET(curpmap, pmap);
1464	TAILQ_INIT(&pmap->pm_pvchunk);
1465	bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1466	mtx_lock_spin(&allpmaps_lock);
1467	LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1468	mtx_unlock_spin(&allpmaps_lock);
1469}
1470
1471/*
1472 * Initialize a preallocated and zeroed pmap structure,
1473 * such as one in a vmspace structure.
1474 */
1475int
1476pmap_pinit(pmap_t pmap)
1477{
1478	vm_page_t m, ptdpg[NPGPTD + 1];
1479	int npgptd = NPGPTD + 1;
1480	static int color;
1481	int i;
1482
1483	PMAP_LOCK_INIT(pmap);
1484
1485	/*
1486	 * No need to allocate page table space yet but we do need a valid
1487	 * page directory table.
1488	 */
1489	if (pmap->pm_pdir == NULL) {
1490		pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map,
1491		    NBPTD);
1492		if (pmap->pm_pdir == NULL) {
1493			PMAP_LOCK_DESTROY(pmap);
1494			return (0);
1495		}
1496#if defined(XEN) && defined(PAE)
1497		pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1);
1498#endif
1499
1500#if defined(PAE) && !defined(XEN)
1501		pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1502		KASSERT(((vm_offset_t)pmap->pm_pdpt &
1503		    ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1504		    ("pmap_pinit: pdpt misaligned"));
1505		KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1506		    ("pmap_pinit: pdpt above 4g"));
1507#endif
1508	}
1509
1510	/*
1511	 * allocate the page directory page(s)
1512	 */
1513	for (i = 0; i < npgptd;) {
1514		m = vm_page_alloc(NULL, color++,
1515		    VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1516		    VM_ALLOC_ZERO);
1517		if (m == NULL)
1518			VM_WAIT;
1519		else {
1520			ptdpg[i++] = m;
1521		}
1522	}
1523	pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1524	for (i = 0; i < NPGPTD; i++) {
1525		if ((ptdpg[i]->flags & PG_ZERO) == 0)
1526			pagezero(&pmap->pm_pdir[i*NPTEPG]);
1527	}
1528
1529	mtx_lock_spin(&allpmaps_lock);
1530	LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1531	mtx_unlock_spin(&allpmaps_lock);
1532	/* Wire in kernel global address entries. */
1533
1534	bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1535#ifdef PAE
1536#ifdef XEN
1537	pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1);
1538	if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0)
1539		bzero(pmap->pm_pdpt, PAGE_SIZE);
1540#endif
1541	for (i = 0; i < NPGPTD; i++) {
1542		vm_paddr_t ma;
1543
1544		ma = xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[i]));
1545		pmap->pm_pdpt[i] = ma | PG_V;
1546
1547	}
1548#endif
1549#ifdef XEN
1550	for (i = 0; i < NPGPTD; i++) {
1551		pt_entry_t *pd;
1552		vm_paddr_t ma;
1553
1554		ma = xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[i]));
1555		pd = pmap->pm_pdir + (i * NPDEPG);
1556		PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW));
1557#if 0
1558		xen_pgd_pin(ma);
1559#endif
1560	}
1561
1562#ifdef PAE
1563	PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW);
1564#endif
1565	vm_page_lock_queues();
1566	xen_flush_queue();
1567	xen_pgdpt_pin(xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[NPGPTD])));
1568	for (i = 0; i < NPGPTD; i++) {
1569		vm_paddr_t ma = xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[i]));
1570		PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE);
1571	}
1572	xen_flush_queue();
1573	vm_page_unlock_queues();
1574#endif
1575	pmap->pm_active = 0;
1576	TAILQ_INIT(&pmap->pm_pvchunk);
1577	bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1578
1579	return (1);
1580}
1581
1582/*
1583 * this routine is called if the page table page is not
1584 * mapped correctly.
1585 */
1586static vm_page_t
1587_pmap_allocpte(pmap_t pmap, unsigned int ptepindex, int flags)
1588{
1589	vm_paddr_t ptema;
1590	vm_page_t m;
1591
1592	KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1593	    (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1594	    ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1595
1596	/*
1597	 * Allocate a page table page.
1598	 */
1599	if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1600	    VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1601		if (flags & M_WAITOK) {
1602			PMAP_UNLOCK(pmap);
1603			vm_page_unlock_queues();
1604			VM_WAIT;
1605			vm_page_lock_queues();
1606			PMAP_LOCK(pmap);
1607		}
1608
1609		/*
1610		 * Indicate the need to retry.  While waiting, the page table
1611		 * page may have been allocated.
1612		 */
1613		return (NULL);
1614	}
1615	if ((m->flags & PG_ZERO) == 0)
1616		pmap_zero_page(m);
1617
1618	/*
1619	 * Map the pagetable page into the process address space, if
1620	 * it isn't already there.
1621	 */
1622	pmap->pm_stats.resident_count++;
1623
1624	ptema = xpmap_ptom(VM_PAGE_TO_PHYS(m));
1625	xen_pt_pin(ptema);
1626	PT_SET_VA_MA(&pmap->pm_pdir[ptepindex],
1627		(ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE);
1628
1629	KASSERT(pmap->pm_pdir[ptepindex],
1630	    ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex));
1631	return (m);
1632}
1633
1634static vm_page_t
1635pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
1636{
1637	unsigned ptepindex;
1638	pd_entry_t ptema;
1639	vm_page_t m;
1640
1641	KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1642	    (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1643	    ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1644
1645	/*
1646	 * Calculate pagetable page index
1647	 */
1648	ptepindex = va >> PDRSHIFT;
1649retry:
1650	/*
1651	 * Get the page directory entry
1652	 */
1653	ptema = pmap->pm_pdir[ptepindex];
1654
1655	/*
1656	 * This supports switching from a 4MB page to a
1657	 * normal 4K page.
1658	 */
1659	if (ptema & PG_PS) {
1660		/*
1661		 * XXX
1662		 */
1663		pmap->pm_pdir[ptepindex] = 0;
1664		ptema = 0;
1665		pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
1666		pmap_invalidate_all(kernel_pmap);
1667	}
1668
1669	/*
1670	 * If the page table page is mapped, we just increment the
1671	 * hold count, and activate it.
1672	 */
1673	if (ptema & PG_V) {
1674		m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME);
1675		m->wire_count++;
1676	} else {
1677		/*
1678		 * Here if the pte page isn't mapped, or if it has
1679		 * been deallocated.
1680		 */
1681		CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x",
1682		    pmap, va, flags);
1683		m = _pmap_allocpte(pmap, ptepindex, flags);
1684		if (m == NULL && (flags & M_WAITOK))
1685			goto retry;
1686
1687		KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex));
1688	}
1689	return (m);
1690}
1691
1692
1693/***************************************************
1694* Pmap allocation/deallocation routines.
1695 ***************************************************/
1696
1697#ifdef SMP
1698/*
1699 * Deal with a SMP shootdown of other users of the pmap that we are
1700 * trying to dispose of.  This can be a bit hairy.
1701 */
1702static u_int *lazymask;
1703static u_int lazyptd;
1704static volatile u_int lazywait;
1705
1706void pmap_lazyfix_action(void);
1707
1708void
1709pmap_lazyfix_action(void)
1710{
1711	u_int mymask = PCPU_GET(cpumask);
1712
1713#ifdef COUNT_IPIS
1714	(*ipi_lazypmap_counts[PCPU_GET(cpuid)])++;
1715#endif
1716	if (rcr3() == lazyptd)
1717		load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1718	atomic_clear_int(lazymask, mymask);
1719	atomic_store_rel_int(&lazywait, 1);
1720}
1721
1722static void
1723pmap_lazyfix_self(u_int mymask)
1724{
1725
1726	if (rcr3() == lazyptd)
1727		load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1728	atomic_clear_int(lazymask, mymask);
1729}
1730
1731
1732static void
1733pmap_lazyfix(pmap_t pmap)
1734{
1735	u_int mymask;
1736	u_int mask;
1737	u_int spins;
1738
1739	while ((mask = pmap->pm_active) != 0) {
1740		spins = 50000000;
1741		mask = mask & -mask;	/* Find least significant set bit */
1742		mtx_lock_spin(&smp_ipi_mtx);
1743#ifdef PAE
1744		lazyptd = vtophys(pmap->pm_pdpt);
1745#else
1746		lazyptd = vtophys(pmap->pm_pdir);
1747#endif
1748		mymask = PCPU_GET(cpumask);
1749		if (mask == mymask) {
1750			lazymask = &pmap->pm_active;
1751			pmap_lazyfix_self(mymask);
1752		} else {
1753			atomic_store_rel_int((u_int *)&lazymask,
1754			    (u_int)&pmap->pm_active);
1755			atomic_store_rel_int(&lazywait, 0);
1756			ipi_selected(mask, IPI_LAZYPMAP);
1757			while (lazywait == 0) {
1758				ia32_pause();
1759				if (--spins == 0)
1760					break;
1761			}
1762		}
1763		mtx_unlock_spin(&smp_ipi_mtx);
1764		if (spins == 0)
1765			printf("pmap_lazyfix: spun for 50000000\n");
1766	}
1767}
1768
1769#else	/* SMP */
1770
1771/*
1772 * Cleaning up on uniprocessor is easy.  For various reasons, we're
1773 * unlikely to have to even execute this code, including the fact
1774 * that the cleanup is deferred until the parent does a wait(2), which
1775 * means that another userland process has run.
1776 */
1777static void
1778pmap_lazyfix(pmap_t pmap)
1779{
1780	u_int cr3;
1781
1782	cr3 = vtophys(pmap->pm_pdir);
1783	if (cr3 == rcr3()) {
1784		load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1785		pmap->pm_active &= ~(PCPU_GET(cpumask));
1786	}
1787}
1788#endif	/* SMP */
1789
1790/*
1791 * Release any resources held by the given physical map.
1792 * Called when a pmap initialized by pmap_pinit is being released.
1793 * Should only be called if the map contains no valid mappings.
1794 */
1795void
1796pmap_release(pmap_t pmap)
1797{
1798	vm_page_t m, ptdpg[2*NPGPTD+1];
1799	vm_paddr_t ma;
1800	int i;
1801#ifdef XEN
1802#ifdef PAE
1803	int npgptd = NPGPTD + 1;
1804#else
1805	int npgptd = NPGPTD;
1806#endif
1807#else
1808	int npgptd = NPGPTD;
1809#endif
1810	KASSERT(pmap->pm_stats.resident_count == 0,
1811	    ("pmap_release: pmap resident count %ld != 0",
1812	    pmap->pm_stats.resident_count));
1813	PT_UPDATES_FLUSH();
1814
1815	pmap_lazyfix(pmap);
1816	mtx_lock_spin(&allpmaps_lock);
1817	LIST_REMOVE(pmap, pm_list);
1818	mtx_unlock_spin(&allpmaps_lock);
1819
1820	for (i = 0; i < NPGPTD; i++)
1821		ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME);
1822	pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
1823#if defined(PAE) && defined(XEN)
1824	ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt));
1825#endif
1826
1827	for (i = 0; i < npgptd; i++) {
1828		m = ptdpg[i];
1829		ma = xpmap_ptom(VM_PAGE_TO_PHYS(m));
1830		/* unpinning L1 and L2 treated the same */
1831                xen_pgd_unpin(ma);
1832#ifdef PAE
1833		KASSERT(xpmap_ptom(VM_PAGE_TO_PHYS(m)) == (pmap->pm_pdpt[i] & PG_FRAME),
1834		    ("pmap_release: got wrong ptd page"));
1835#endif
1836		m->wire_count--;
1837		atomic_subtract_int(&cnt.v_wire_count, 1);
1838		vm_page_free(m);
1839	}
1840	PMAP_LOCK_DESTROY(pmap);
1841}
1842
1843static int
1844kvm_size(SYSCTL_HANDLER_ARGS)
1845{
1846	unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
1847
1848	return sysctl_handle_long(oidp, &ksize, 0, req);
1849}
1850SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1851    0, 0, kvm_size, "IU", "Size of KVM");
1852
1853static int
1854kvm_free(SYSCTL_HANDLER_ARGS)
1855{
1856	unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1857
1858	return sysctl_handle_long(oidp, &kfree, 0, req);
1859}
1860SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1861    0, 0, kvm_free, "IU", "Amount of KVM free");
1862
1863/*
1864 * grow the number of kernel page table entries, if needed
1865 */
1866void
1867pmap_growkernel(vm_offset_t addr)
1868{
1869	struct pmap *pmap;
1870	vm_paddr_t ptppaddr;
1871	vm_page_t nkpg;
1872	pd_entry_t newpdir;
1873
1874	mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1875	if (kernel_vm_end == 0) {
1876		kernel_vm_end = KERNBASE;
1877		nkpt = 0;
1878		while (pdir_pde(PTD, kernel_vm_end)) {
1879			kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
1880			nkpt++;
1881			if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1882				kernel_vm_end = kernel_map->max_offset;
1883				break;
1884			}
1885		}
1886	}
1887	addr = roundup2(addr, PAGE_SIZE * NPTEPG);
1888	if (addr - 1 >= kernel_map->max_offset)
1889		addr = kernel_map->max_offset;
1890	while (kernel_vm_end < addr) {
1891		if (pdir_pde(PTD, kernel_vm_end)) {
1892			kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
1893			if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1894				kernel_vm_end = kernel_map->max_offset;
1895				break;
1896			}
1897			continue;
1898		}
1899
1900		/*
1901		 * This index is bogus, but out of the way
1902		 */
1903		nkpg = vm_page_alloc(NULL, nkpt,
1904		    VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED);
1905		if (!nkpg)
1906			panic("pmap_growkernel: no memory to grow kernel");
1907
1908		nkpt++;
1909
1910		pmap_zero_page(nkpg);
1911		ptppaddr = VM_PAGE_TO_PHYS(nkpg);
1912		newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
1913		PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE);
1914
1915		mtx_lock_spin(&allpmaps_lock);
1916		LIST_FOREACH(pmap, &allpmaps, pm_list)
1917			PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE);
1918
1919		mtx_unlock_spin(&allpmaps_lock);
1920		kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
1921		if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1922			kernel_vm_end = kernel_map->max_offset;
1923			break;
1924		}
1925	}
1926}
1927
1928
1929/***************************************************
1930 * page management routines.
1931 ***************************************************/
1932
1933CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1934CTASSERT(_NPCM == 11);
1935
1936static __inline struct pv_chunk *
1937pv_to_chunk(pv_entry_t pv)
1938{
1939
1940	return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK);
1941}
1942
1943#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1944
1945#define	PC_FREE0_9	0xfffffffful	/* Free values for index 0 through 9 */
1946#define	PC_FREE10	0x0000fffful	/* Free values for index 10 */
1947
1948static uint32_t pc_freemask[11] = {
1949	PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1950	PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1951	PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1952	PC_FREE0_9, PC_FREE10
1953};
1954
1955SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1956	"Current number of pv entries");
1957
1958#ifdef PV_STATS
1959static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1960
1961SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1962	"Current number of pv entry chunks");
1963SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1964	"Current number of pv entry chunks allocated");
1965SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1966	"Current number of pv entry chunks frees");
1967SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1968	"Number of times tried to get a chunk page but failed.");
1969
1970static long pv_entry_frees, pv_entry_allocs;
1971static int pv_entry_spare;
1972
1973SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1974	"Current number of pv entry frees");
1975SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1976	"Current number of pv entry allocs");
1977SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1978	"Current number of spare pv entries");
1979
1980static int pmap_collect_inactive, pmap_collect_active;
1981
1982SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0,
1983	"Current number times pmap_collect called on inactive queue");
1984SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0,
1985	"Current number times pmap_collect called on active queue");
1986#endif
1987
1988/*
1989 * We are in a serious low memory condition.  Resort to
1990 * drastic measures to free some pages so we can allocate
1991 * another pv entry chunk.  This is normally called to
1992 * unmap inactive pages, and if necessary, active pages.
1993 */
1994static void
1995pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq)
1996{
1997	pmap_t pmap;
1998	pt_entry_t *pte, tpte;
1999	pv_entry_t next_pv, pv;
2000	vm_offset_t va;
2001	vm_page_t m, free;
2002
2003	sched_pin();
2004	TAILQ_FOREACH(m, &vpq->pl, pageq) {
2005		if (m->hold_count || m->busy)
2006			continue;
2007		TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) {
2008			va = pv->pv_va;
2009			pmap = PV_PMAP(pv);
2010			/* Avoid deadlock and lock recursion. */
2011			if (pmap > locked_pmap)
2012				PMAP_LOCK(pmap);
2013			else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap))
2014				continue;
2015			pmap->pm_stats.resident_count--;
2016			pte = pmap_pte_quick(pmap, va);
2017			tpte = pte_load_clear(pte);
2018			KASSERT((tpte & PG_W) == 0,
2019			    ("pmap_collect: wired pte %#jx", (uintmax_t)tpte));
2020			if (tpte & PG_A)
2021				vm_page_flag_set(m, PG_REFERENCED);
2022			if (tpte & PG_M) {
2023				KASSERT((tpte & PG_RW),
2024	("pmap_collect: modified page not writable: va: %#x, pte: %#jx",
2025				    va, (uintmax_t)tpte));
2026				vm_page_dirty(m);
2027			}
2028			free = NULL;
2029			pmap_unuse_pt(pmap, va, &free);
2030			pmap_invalidate_page(pmap, va);
2031			pmap_free_zero_pages(free);
2032			TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2033			if (TAILQ_EMPTY(&m->md.pv_list))
2034				vm_page_flag_clear(m, PG_WRITEABLE);
2035			free_pv_entry(pmap, pv);
2036			if (pmap != locked_pmap)
2037				PMAP_UNLOCK(pmap);
2038		}
2039	}
2040	sched_unpin();
2041}
2042
2043
2044/*
2045 * free the pv_entry back to the free list
2046 */
2047static void
2048free_pv_entry(pmap_t pmap, pv_entry_t pv)
2049{
2050	vm_page_t m;
2051	struct pv_chunk *pc;
2052	int idx, field, bit;
2053
2054	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2055	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2056	PV_STAT(pv_entry_frees++);
2057	PV_STAT(pv_entry_spare++);
2058	pv_entry_count--;
2059	pc = pv_to_chunk(pv);
2060	idx = pv - &pc->pc_pventry[0];
2061	field = idx / 32;
2062	bit = idx % 32;
2063	pc->pc_map[field] |= 1ul << bit;
2064	/* move to head of list */
2065	TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2066	TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2067	for (idx = 0; idx < _NPCM; idx++)
2068		if (pc->pc_map[idx] != pc_freemask[idx])
2069			return;
2070	PV_STAT(pv_entry_spare -= _NPCPV);
2071	PV_STAT(pc_chunk_count--);
2072	PV_STAT(pc_chunk_frees++);
2073	/* entire chunk is free, return it */
2074	TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2075	m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2076	pmap_qremove((vm_offset_t)pc, 1);
2077	vm_page_unwire(m, 0);
2078	vm_page_free(m);
2079	pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2080}
2081
2082/*
2083 * get a new pv_entry, allocating a block from the system
2084 * when needed.
2085 */
2086static pv_entry_t
2087get_pv_entry(pmap_t pmap, int try)
2088{
2089	static const struct timeval printinterval = { 60, 0 };
2090	static struct timeval lastprint;
2091	static vm_pindex_t colour;
2092	struct vpgqueues *pq;
2093	int bit, field;
2094	pv_entry_t pv;
2095	struct pv_chunk *pc;
2096	vm_page_t m;
2097
2098	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2099	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2100	PV_STAT(pv_entry_allocs++);
2101	pv_entry_count++;
2102	if (pv_entry_count > pv_entry_high_water)
2103		if (ratecheck(&lastprint, &printinterval))
2104			printf("Approaching the limit on PV entries, consider "
2105			    "increasing either the vm.pmap.shpgperproc or the "
2106			    "vm.pmap.pv_entry_max tunable.\n");
2107	pq = NULL;
2108retry:
2109	pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2110	if (pc != NULL) {
2111		for (field = 0; field < _NPCM; field++) {
2112			if (pc->pc_map[field]) {
2113				bit = bsfl(pc->pc_map[field]);
2114				break;
2115			}
2116		}
2117		if (field < _NPCM) {
2118			pv = &pc->pc_pventry[field * 32 + bit];
2119			pc->pc_map[field] &= ~(1ul << bit);
2120			/* If this was the last item, move it to tail */
2121			for (field = 0; field < _NPCM; field++)
2122				if (pc->pc_map[field] != 0) {
2123					PV_STAT(pv_entry_spare--);
2124					return (pv);	/* not full, return */
2125				}
2126			TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2127			TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2128			PV_STAT(pv_entry_spare--);
2129			return (pv);
2130		}
2131	}
2132	/*
2133	 * Access to the ptelist "pv_vafree" is synchronized by the page
2134	 * queues lock.  If "pv_vafree" is currently non-empty, it will
2135	 * remain non-empty until pmap_ptelist_alloc() completes.
2136	 */
2137	if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq ==
2138	    &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) |
2139	    VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2140		if (try) {
2141			pv_entry_count--;
2142			PV_STAT(pc_chunk_tryfail++);
2143			return (NULL);
2144		}
2145		/*
2146		 * Reclaim pv entries: At first, destroy mappings to
2147		 * inactive pages.  After that, if a pv chunk entry
2148		 * is still needed, destroy mappings to active pages.
2149		 */
2150		if (pq == NULL) {
2151			PV_STAT(pmap_collect_inactive++);
2152			pq = &vm_page_queues[PQ_INACTIVE];
2153		} else if (pq == &vm_page_queues[PQ_INACTIVE]) {
2154			PV_STAT(pmap_collect_active++);
2155			pq = &vm_page_queues[PQ_ACTIVE];
2156		} else
2157			panic("get_pv_entry: increase vm.pmap.shpgperproc");
2158		pmap_collect(pmap, pq);
2159		goto retry;
2160	}
2161	PV_STAT(pc_chunk_count++);
2162	PV_STAT(pc_chunk_allocs++);
2163	colour++;
2164	pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2165	pmap_qenter((vm_offset_t)pc, &m, 1);
2166	if ((m->flags & PG_ZERO) == 0)
2167		pagezero(pc);
2168	pc->pc_pmap = pmap;
2169	pc->pc_map[0] = pc_freemask[0] & ~1ul;	/* preallocated bit 0 */
2170	for (field = 1; field < _NPCM; field++)
2171		pc->pc_map[field] = pc_freemask[field];
2172	pv = &pc->pc_pventry[0];
2173	TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2174	PV_STAT(pv_entry_spare += _NPCPV - 1);
2175	return (pv);
2176}
2177
2178static void
2179pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2180{
2181	pv_entry_t pv;
2182
2183	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2184	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2185	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2186		if (pmap == PV_PMAP(pv) && va == pv->pv_va)
2187			break;
2188	}
2189	KASSERT(pv != NULL, ("pmap_remove_entry: pv not found"));
2190	TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2191	if (TAILQ_EMPTY(&m->md.pv_list))
2192		vm_page_flag_clear(m, PG_WRITEABLE);
2193	free_pv_entry(pmap, pv);
2194}
2195
2196/*
2197 * Create a pv entry for page at pa for
2198 * (pmap, va).
2199 */
2200static void
2201pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2202{
2203	pv_entry_t pv;
2204
2205	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2206	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2207	pv = get_pv_entry(pmap, FALSE);
2208	pv->pv_va = va;
2209	TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2210}
2211
2212/*
2213 * Conditionally create a pv entry.
2214 */
2215static boolean_t
2216pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2217{
2218	pv_entry_t pv;
2219
2220	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2221	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2222	if (pv_entry_count < pv_entry_high_water &&
2223	    (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2224		pv->pv_va = va;
2225		TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2226		return (TRUE);
2227	} else
2228		return (FALSE);
2229}
2230
2231/*
2232 * pmap_remove_pte: do the things to unmap a page in a process
2233 */
2234static int
2235pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free)
2236{
2237	pt_entry_t oldpte;
2238	vm_page_t m;
2239
2240	CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x",
2241	    pmap, (u_long)*ptq, va);
2242
2243	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2244	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2245	oldpte = *ptq;
2246	PT_SET_VA_MA(ptq, 0, TRUE);
2247	if (oldpte & PG_W)
2248		pmap->pm_stats.wired_count -= 1;
2249	/*
2250	 * Machines that don't support invlpg, also don't support
2251	 * PG_G.
2252	 */
2253	if (oldpte & PG_G)
2254		pmap_invalidate_page(kernel_pmap, va);
2255	pmap->pm_stats.resident_count -= 1;
2256	/*
2257	 * XXX This is not strictly correctly, but somewhere along the line
2258	 * we are losing the managed bit on some pages. It is unclear to me
2259	 * why, but I think the most likely explanation is that xen's writable
2260	 * page table implementation doesn't respect the unused bits.
2261	 */
2262	if ((oldpte & PG_MANAGED) || ((oldpte & PG_V) && (va < VM_MAXUSER_ADDRESS))
2263		) {
2264		m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME);
2265
2266		if (!(oldpte & PG_MANAGED))
2267			printf("va=0x%x is unmanaged :-( pte=0x%llx\n", va, oldpte);
2268
2269		if (oldpte & PG_M) {
2270			KASSERT((oldpte & PG_RW),
2271	("pmap_remove_pte: modified page not writable: va: %#x, pte: %#jx",
2272			    va, (uintmax_t)oldpte));
2273			vm_page_dirty(m);
2274		}
2275		if (oldpte & PG_A)
2276			vm_page_flag_set(m, PG_REFERENCED);
2277		pmap_remove_entry(pmap, m, va);
2278	} else if ((va < VM_MAXUSER_ADDRESS) && (oldpte & PG_V))
2279		printf("va=0x%x is unmanaged :-( pte=0x%llx\n", va, oldpte);
2280
2281	return (pmap_unuse_pt(pmap, va, free));
2282}
2283
2284/*
2285 * Remove a single page from a process address space
2286 */
2287static void
2288pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free)
2289{
2290	pt_entry_t *pte;
2291
2292	CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x",
2293	    pmap, va);
2294
2295	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2296	KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2297	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2298	if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0)
2299		return;
2300	pmap_remove_pte(pmap, pte, va, free);
2301	pmap_invalidate_page(pmap, va);
2302	if (*PMAP1)
2303		PT_SET_MA(PADDR1, 0);
2304
2305}
2306
2307/*
2308 *	Remove the given range of addresses from the specified map.
2309 *
2310 *	It is assumed that the start and end are properly
2311 *	rounded to the page size.
2312 */
2313void
2314pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2315{
2316	vm_offset_t pdnxt;
2317	pd_entry_t ptpaddr;
2318	pt_entry_t *pte;
2319	vm_page_t free = NULL;
2320	int anyvalid;
2321
2322	CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x",
2323	    pmap, sva, eva);
2324
2325	/*
2326	 * Perform an unsynchronized read.  This is, however, safe.
2327	 */
2328	if (pmap->pm_stats.resident_count == 0)
2329		return;
2330
2331	anyvalid = 0;
2332
2333	vm_page_lock_queues();
2334	sched_pin();
2335	PMAP_LOCK(pmap);
2336
2337	/*
2338	 * special handling of removing one page.  a very
2339	 * common operation and easy to short circuit some
2340	 * code.
2341	 */
2342	if ((sva + PAGE_SIZE == eva) &&
2343	    ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2344		pmap_remove_page(pmap, sva, &free);
2345		goto out;
2346	}
2347
2348	for (; sva < eva; sva = pdnxt) {
2349		unsigned pdirindex;
2350
2351		/*
2352		 * Calculate index for next page table.
2353		 */
2354		pdnxt = (sva + NBPDR) & ~PDRMASK;
2355		if (pmap->pm_stats.resident_count == 0)
2356			break;
2357
2358		pdirindex = sva >> PDRSHIFT;
2359		ptpaddr = pmap->pm_pdir[pdirindex];
2360
2361		/*
2362		 * Weed out invalid mappings. Note: we assume that the page
2363		 * directory table is always allocated, and in kernel virtual.
2364		 */
2365		if (ptpaddr == 0)
2366			continue;
2367
2368		/*
2369		 * Check for large page.
2370		 */
2371		if ((ptpaddr & PG_PS) != 0) {
2372			PD_CLEAR_VA(pmap, pdirindex, TRUE);
2373			pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2374			anyvalid = 1;
2375			continue;
2376		}
2377
2378		/*
2379		 * Limit our scan to either the end of the va represented
2380		 * by the current page table page, or to the end of the
2381		 * range being removed.
2382		 */
2383		if (pdnxt > eva)
2384			pdnxt = eva;
2385
2386		for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2387		    sva += PAGE_SIZE) {
2388			if ((*pte & PG_V) == 0)
2389				continue;
2390
2391			/*
2392			 * The TLB entry for a PG_G mapping is invalidated
2393			 * by pmap_remove_pte().
2394			 */
2395			if ((*pte & PG_G) == 0)
2396				anyvalid = 1;
2397			if (pmap_remove_pte(pmap, pte, sva, &free))
2398				break;
2399		}
2400	}
2401	PT_UPDATES_FLUSH();
2402	if (*PMAP1)
2403		PT_SET_VA_MA(PMAP1, 0, TRUE);
2404out:
2405	if (anyvalid)
2406		pmap_invalidate_all(pmap);
2407	sched_unpin();
2408	vm_page_unlock_queues();
2409	PMAP_UNLOCK(pmap);
2410	pmap_free_zero_pages(free);
2411}
2412
2413/*
2414 *	Routine:	pmap_remove_all
2415 *	Function:
2416 *		Removes this physical page from
2417 *		all physical maps in which it resides.
2418 *		Reflects back modify bits to the pager.
2419 *
2420 *	Notes:
2421 *		Original versions of this routine were very
2422 *		inefficient because they iteratively called
2423 *		pmap_remove (slow...)
2424 */
2425
2426void
2427pmap_remove_all(vm_page_t m)
2428{
2429	pv_entry_t pv;
2430	pmap_t pmap;
2431	pt_entry_t *pte, tpte;
2432	vm_page_t free;
2433
2434#if defined(PMAP_DIAGNOSTIC)
2435	/*
2436	 * XXX This makes pmap_remove_all() illegal for non-managed pages!
2437	 */
2438	if (m->flags & PG_FICTITIOUS) {
2439		panic("pmap_remove_all: illegal for unmanaged page, va: 0x%jx",
2440		    VM_PAGE_TO_PHYS(m) & 0xffffffff);
2441	}
2442#endif
2443	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2444	sched_pin();
2445	while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2446		pmap = PV_PMAP(pv);
2447		PMAP_LOCK(pmap);
2448		pmap->pm_stats.resident_count--;
2449		pte = pmap_pte_quick(pmap, pv->pv_va);
2450
2451		tpte = *pte;
2452		PT_SET_VA_MA(pte, 0, TRUE);
2453		if (tpte & PG_W)
2454			pmap->pm_stats.wired_count--;
2455		if (tpte & PG_A)
2456			vm_page_flag_set(m, PG_REFERENCED);
2457
2458		/*
2459		 * Update the vm_page_t clean and reference bits.
2460		 */
2461		if (tpte & PG_M) {
2462			KASSERT((tpte & PG_RW),
2463	("pmap_remove_all: modified page not writable: va: %#x, pte: %#jx",
2464			    pv->pv_va, (uintmax_t)tpte));
2465			vm_page_dirty(m);
2466		}
2467		free = NULL;
2468		pmap_unuse_pt(pmap, pv->pv_va, &free);
2469		pmap_invalidate_page(pmap, pv->pv_va);
2470		pmap_free_zero_pages(free);
2471		TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2472		free_pv_entry(pmap, pv);
2473		PMAP_UNLOCK(pmap);
2474	}
2475	vm_page_flag_clear(m, PG_WRITEABLE);
2476	PT_UPDATES_FLUSH();
2477	if (*PMAP1)
2478		PT_SET_MA(PADDR1, 0);
2479	sched_unpin();
2480}
2481
2482/*
2483 *	Set the physical protection on the
2484 *	specified range of this map as requested.
2485 */
2486void
2487pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2488{
2489	vm_offset_t pdnxt;
2490	pd_entry_t ptpaddr;
2491	pt_entry_t *pte;
2492	int anychanged;
2493
2494	CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x",
2495	    pmap, sva, eva, prot);
2496
2497	if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2498		pmap_remove(pmap, sva, eva);
2499		return;
2500	}
2501
2502#ifdef PAE
2503	if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
2504	    (VM_PROT_WRITE|VM_PROT_EXECUTE))
2505		return;
2506#else
2507	if (prot & VM_PROT_WRITE)
2508		return;
2509#endif
2510
2511	anychanged = 0;
2512
2513	vm_page_lock_queues();
2514	sched_pin();
2515	PMAP_LOCK(pmap);
2516	for (; sva < eva; sva = pdnxt) {
2517		pt_entry_t obits, pbits;
2518		unsigned pdirindex;
2519
2520		pdnxt = (sva + NBPDR) & ~PDRMASK;
2521
2522		pdirindex = sva >> PDRSHIFT;
2523		ptpaddr = pmap->pm_pdir[pdirindex];
2524
2525		/*
2526		 * Weed out invalid mappings. Note: we assume that the page
2527		 * directory table is always allocated, and in kernel virtual.
2528		 */
2529		if (ptpaddr == 0)
2530			continue;
2531
2532		/*
2533		 * Check for large page.
2534		 */
2535		if ((ptpaddr & PG_PS) != 0) {
2536			if ((prot & VM_PROT_WRITE) == 0)
2537				pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW);
2538#ifdef PAE
2539			if ((prot & VM_PROT_EXECUTE) == 0)
2540				pmap->pm_pdir[pdirindex] |= pg_nx;
2541#endif
2542			anychanged = 1;
2543			continue;
2544		}
2545
2546		if (pdnxt > eva)
2547			pdnxt = eva;
2548
2549		for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2550		    sva += PAGE_SIZE) {
2551			vm_page_t m;
2552
2553retry:
2554			/*
2555			 * Regardless of whether a pte is 32 or 64 bits in
2556			 * size, PG_RW, PG_A, and PG_M are among the least
2557			 * significant 32 bits.
2558			 */
2559			obits = pbits = *pte;
2560			if ((pbits & PG_V) == 0)
2561				continue;
2562			if (pbits & PG_MANAGED) {
2563				m = NULL;
2564				if (pbits & PG_A) {
2565					m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & PG_FRAME);
2566					vm_page_flag_set(m, PG_REFERENCED);
2567					pbits &= ~PG_A;
2568				}
2569				if ((pbits & PG_M) != 0) {
2570					if (m == NULL)
2571						m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & PG_FRAME);
2572					vm_page_dirty(m);
2573				}
2574			}
2575
2576			if ((prot & VM_PROT_WRITE) == 0)
2577				pbits &= ~(PG_RW | PG_M);
2578#ifdef PAE
2579			if ((prot & VM_PROT_EXECUTE) == 0)
2580				pbits |= pg_nx;
2581#endif
2582
2583			if (pbits != obits) {
2584#ifdef XEN
2585				obits = *pte;
2586				PT_SET_VA_MA(pte, pbits, TRUE);
2587				if (*pte != pbits)
2588					goto retry;
2589#else
2590#ifdef PAE
2591				if (!atomic_cmpset_64(pte, obits, pbits))
2592					goto retry;
2593#else
2594				if (!atomic_cmpset_int((u_int *)pte, obits,
2595				    pbits))
2596					goto retry;
2597#endif
2598#endif
2599				if (obits & PG_G)
2600					pmap_invalidate_page(pmap, sva);
2601				else
2602					anychanged = 1;
2603			}
2604		}
2605	}
2606	PT_UPDATES_FLUSH();
2607	if (*PMAP1)
2608		PT_SET_VA_MA(PMAP1, 0, TRUE);
2609	if (anychanged)
2610		pmap_invalidate_all(pmap);
2611	sched_unpin();
2612	vm_page_unlock_queues();
2613	PMAP_UNLOCK(pmap);
2614}
2615
2616/*
2617 *	Insert the given physical page (p) at
2618 *	the specified virtual address (v) in the
2619 *	target physical map with the protection requested.
2620 *
2621 *	If specified, the page will be wired down, meaning
2622 *	that the related pte can not be reclaimed.
2623 *
2624 *	NB:  This is the only routine which MAY NOT lazy-evaluate
2625 *	or lose information.  That is, this routine must actually
2626 *	insert this page into the given map NOW.
2627 */
2628void
2629pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
2630    vm_prot_t prot, boolean_t wired)
2631{
2632	vm_paddr_t pa;
2633	pd_entry_t *pde;
2634	pt_entry_t *pte;
2635	vm_paddr_t opa;
2636	pt_entry_t origpte, newpte;
2637	vm_page_t mpte, om;
2638	boolean_t invlva;
2639
2640	CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d",
2641	    pmap, va, access, xpmap_ptom(VM_PAGE_TO_PHYS(m)), prot, wired);
2642	va = trunc_page(va);
2643#ifdef PMAP_DIAGNOSTIC
2644	if (va > VM_MAX_KERNEL_ADDRESS)
2645		panic("pmap_enter: toobig");
2646	if ((va >= UPT_MIN_ADDRESS) && (va < UPT_MAX_ADDRESS))
2647		panic("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", va);
2648#endif
2649
2650	mpte = NULL;
2651
2652	vm_page_lock_queues();
2653	PMAP_LOCK(pmap);
2654	sched_pin();
2655
2656	/*
2657	 * In the case that a page table page is not
2658	 * resident, we are creating it here.
2659	 */
2660	if (va < VM_MAXUSER_ADDRESS) {
2661		mpte = pmap_allocpte(pmap, va, M_WAITOK);
2662	}
2663#if 0 && defined(PMAP_DIAGNOSTIC)
2664	else {
2665		pd_entry_t *pdeaddr = pmap_pde(pmap, va);
2666		origpte = *pdeaddr;
2667		if ((origpte & PG_V) == 0) {
2668			panic("pmap_enter: invalid kernel page table page, pdir=%p, pde=%p, va=%p\n",
2669				pmap->pm_pdir[PTDPTDI], origpte, va);
2670		}
2671	}
2672#endif
2673
2674	pde = pmap_pde(pmap, va);
2675	if ((*pde & PG_PS) != 0)
2676		panic("pmap_enter: attempted pmap_enter on 4MB page");
2677	pte = pmap_pte_quick(pmap, va);
2678
2679	/*
2680	 * Page Directory table entry not valid, we need a new PT page
2681	 */
2682	if (pte == NULL) {
2683		panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x\n",
2684			(uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va);
2685	}
2686
2687	pa = VM_PAGE_TO_PHYS(m);
2688	om = NULL;
2689	opa = origpte = 0;
2690
2691#if 0
2692	KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx",
2693		pte, *pte));
2694#endif
2695	origpte = *pte;
2696	if (origpte)
2697		origpte = xpmap_mtop(origpte);
2698	opa = origpte & PG_FRAME;
2699
2700	/*
2701	 * Mapping has not changed, must be protection or wiring change.
2702	 */
2703	if (origpte && (opa == pa)) {
2704		/*
2705		 * Wiring change, just update stats. We don't worry about
2706		 * wiring PT pages as they remain resident as long as there
2707		 * are valid mappings in them. Hence, if a user page is wired,
2708		 * the PT page will be also.
2709		 */
2710		if (wired && ((origpte & PG_W) == 0))
2711			pmap->pm_stats.wired_count++;
2712		else if (!wired && (origpte & PG_W))
2713			pmap->pm_stats.wired_count--;
2714
2715		/*
2716		 * Remove extra pte reference
2717		 */
2718		if (mpte)
2719			mpte->wire_count--;
2720
2721		/*
2722		 * We might be turning off write access to the page,
2723		 * so we go ahead and sense modify status.
2724		 */
2725		if (origpte & PG_MANAGED) {
2726			om = m;
2727			pa |= PG_MANAGED;
2728		}
2729		goto validate;
2730	}
2731	/*
2732	 * Mapping has changed, invalidate old range and fall through to
2733	 * handle validating new mapping.
2734	 */
2735	if (opa) {
2736		if (origpte & PG_W)
2737			pmap->pm_stats.wired_count--;
2738		if (origpte & PG_MANAGED) {
2739			om = PHYS_TO_VM_PAGE(opa);
2740			pmap_remove_entry(pmap, om, va);
2741		} else if (va < VM_MAXUSER_ADDRESS)
2742			printf("va=0x%x is unmanaged :-( \n", va);
2743
2744		if (mpte != NULL) {
2745			mpte->wire_count--;
2746			KASSERT(mpte->wire_count > 0,
2747			    ("pmap_enter: missing reference to page table page,"
2748			     " va: 0x%x", va));
2749		}
2750	} else
2751		pmap->pm_stats.resident_count++;
2752
2753	/*
2754	 * Enter on the PV list if part of our managed memory.
2755	 */
2756	if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) {
2757		KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
2758		    ("pmap_enter: managed mapping within the clean submap"));
2759		pmap_insert_entry(pmap, va, m);
2760		pa |= PG_MANAGED;
2761	}
2762
2763	/*
2764	 * Increment counters
2765	 */
2766	if (wired)
2767		pmap->pm_stats.wired_count++;
2768
2769validate:
2770	/*
2771	 * Now validate mapping with desired protection/wiring.
2772	 */
2773	newpte = (pt_entry_t)(pa | PG_V);
2774	if ((prot & VM_PROT_WRITE) != 0) {
2775		newpte |= PG_RW;
2776		vm_page_flag_set(m, PG_WRITEABLE);
2777	}
2778#ifdef PAE
2779	if ((prot & VM_PROT_EXECUTE) == 0)
2780		newpte |= pg_nx;
2781#endif
2782	if (wired)
2783		newpte |= PG_W;
2784	if (va < VM_MAXUSER_ADDRESS)
2785		newpte |= PG_U;
2786	if (pmap == kernel_pmap)
2787		newpte |= pgeflag;
2788
2789	critical_enter();
2790	/*
2791	 * if the mapping or permission bits are different, we need
2792	 * to update the pte.
2793	 */
2794	if ((origpte & ~(PG_M|PG_A)) != newpte) {
2795		if (origpte) {
2796			invlva = FALSE;
2797			origpte = *pte;
2798			PT_SET_VA(pte, newpte | PG_A, FALSE);
2799			if (origpte & PG_A) {
2800				if (origpte & PG_MANAGED)
2801					vm_page_flag_set(om, PG_REFERENCED);
2802				if (opa != VM_PAGE_TO_PHYS(m))
2803					invlva = TRUE;
2804#ifdef PAE
2805				if ((origpte & PG_NX) == 0 &&
2806				    (newpte & PG_NX) != 0)
2807					invlva = TRUE;
2808#endif
2809			}
2810			if (origpte & PG_M) {
2811				KASSERT((origpte & PG_RW),
2812	("pmap_enter: modified page not writable: va: %#x, pte: %#jx",
2813				    va, (uintmax_t)origpte));
2814				if ((origpte & PG_MANAGED) != 0)
2815					vm_page_dirty(om);
2816				if ((prot & VM_PROT_WRITE) == 0)
2817					invlva = TRUE;
2818			}
2819			if (invlva)
2820				pmap_invalidate_page(pmap, va);
2821		} else{
2822			PT_SET_VA(pte, newpte | PG_A, FALSE);
2823		}
2824
2825	}
2826	PT_UPDATES_FLUSH();
2827	critical_exit();
2828	if (*PMAP1)
2829		PT_SET_VA_MA(PMAP1, 0, TRUE);
2830	sched_unpin();
2831	vm_page_unlock_queues();
2832	PMAP_UNLOCK(pmap);
2833}
2834
2835/*
2836 * Maps a sequence of resident pages belonging to the same object.
2837 * The sequence begins with the given page m_start.  This page is
2838 * mapped at the given virtual address start.  Each subsequent page is
2839 * mapped at a virtual address that is offset from start by the same
2840 * amount as the page is offset from m_start within the object.  The
2841 * last page in the sequence is the page with the largest offset from
2842 * m_start that can be mapped at a virtual address less than the given
2843 * virtual address end.  Not every virtual page between start and end
2844 * is mapped; only those for which a resident page exists with the
2845 * corresponding offset from m_start are mapped.
2846 */
2847void
2848pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2849    vm_page_t m_start, vm_prot_t prot)
2850{
2851	vm_page_t m, mpte;
2852	vm_pindex_t diff, psize;
2853	multicall_entry_t mcl[16];
2854	multicall_entry_t *mclp = mcl;
2855	int error, count = 0;
2856
2857	VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED);
2858	psize = atop(end - start);
2859
2860	mpte = NULL;
2861	m = m_start;
2862	PMAP_LOCK(pmap);
2863	while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2864		mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m,
2865		    prot, mpte);
2866		m = TAILQ_NEXT(m, listq);
2867		if (count == 16) {
2868			error = HYPERVISOR_multicall(mcl, count);
2869			KASSERT(error == 0, ("bad multicall %d", error));
2870			mclp = mcl;
2871			count = 0;
2872		}
2873	}
2874	if (count) {
2875		error = HYPERVISOR_multicall(mcl, count);
2876		KASSERT(error == 0, ("bad multicall %d", error));
2877	}
2878
2879	PMAP_UNLOCK(pmap);
2880}
2881
2882/*
2883 * this code makes some *MAJOR* assumptions:
2884 * 1. Current pmap & pmap exists.
2885 * 2. Not wired.
2886 * 3. Read access.
2887 * 4. No page table pages.
2888 * but is *MUCH* faster than pmap_enter...
2889 */
2890
2891void
2892pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2893{
2894	multicall_entry_t mcl, *mclp;
2895	int count = 0;
2896	mclp = &mcl;
2897
2898	CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x",
2899	    pmap, va, m, prot);
2900
2901	PMAP_LOCK(pmap);
2902	(void) pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL);
2903	if (count)
2904		HYPERVISOR_multicall(&mcl, count);
2905	PMAP_UNLOCK(pmap);
2906}
2907
2908#ifdef notyet
2909void
2910pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count)
2911{
2912	int i, error, index = 0;
2913	multicall_entry_t mcl[16];
2914	multicall_entry_t *mclp = mcl;
2915
2916	PMAP_LOCK(pmap);
2917	for (i = 0; i < count; i++, addrs++, pages++, prots++) {
2918		if (!pmap_is_prefaultable_locked(pmap, *addrs))
2919			continue;
2920
2921		(void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL);
2922		if (index == 16) {
2923			error = HYPERVISOR_multicall(mcl, index);
2924			mclp = mcl;
2925			index = 0;
2926			KASSERT(error == 0, ("bad multicall %d", error));
2927		}
2928	}
2929	if (index) {
2930		error = HYPERVISOR_multicall(mcl, index);
2931		KASSERT(error == 0, ("bad multicall %d", error));
2932	}
2933
2934	PMAP_UNLOCK(pmap);
2935}
2936#endif
2937
2938static vm_page_t
2939pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m,
2940    vm_prot_t prot, vm_page_t mpte)
2941{
2942	pt_entry_t *pte;
2943	vm_paddr_t pa;
2944	vm_page_t free;
2945	multicall_entry_t *mcl = *mclpp;
2946
2947	KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2948	    (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0,
2949	    ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2950	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2951	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2952
2953	/*
2954	 * In the case that a page table page is not
2955	 * resident, we are creating it here.
2956	 */
2957	if (va < VM_MAXUSER_ADDRESS) {
2958		unsigned ptepindex;
2959		pd_entry_t ptema;
2960
2961		/*
2962		 * Calculate pagetable page index
2963		 */
2964		ptepindex = va >> PDRSHIFT;
2965		if (mpte && (mpte->pindex == ptepindex)) {
2966			mpte->wire_count++;
2967		} else {
2968			/*
2969			 * Get the page directory entry
2970			 */
2971			ptema = pmap->pm_pdir[ptepindex];
2972
2973			/*
2974			 * If the page table page is mapped, we just increment
2975			 * the hold count, and activate it.
2976			 */
2977			if (ptema & PG_V) {
2978				if (ptema & PG_PS)
2979					panic("pmap_enter_quick: unexpected mapping into 4MB page");
2980				mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME);
2981				mpte->wire_count++;
2982			} else {
2983				mpte = _pmap_allocpte(pmap, ptepindex,
2984				    M_NOWAIT);
2985				if (mpte == NULL)
2986					return (mpte);
2987			}
2988		}
2989	} else {
2990		mpte = NULL;
2991	}
2992
2993	/*
2994	 * This call to vtopte makes the assumption that we are
2995	 * entering the page into the current pmap.  In order to support
2996	 * quick entry into any pmap, one would likely use pmap_pte_quick.
2997	 * But that isn't as quick as vtopte.
2998	 */
2999	KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap"));
3000	pte = vtopte(va);
3001	if (*pte & PG_V) {
3002		if (mpte != NULL) {
3003			mpte->wire_count--;
3004			mpte = NULL;
3005		}
3006		return (mpte);
3007	}
3008
3009	/*
3010	 * Enter on the PV list if part of our managed memory.
3011	 */
3012	if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 &&
3013	    !pmap_try_insert_pv_entry(pmap, va, m)) {
3014		if (mpte != NULL) {
3015			free = NULL;
3016			if (pmap_unwire_pte_hold(pmap, mpte, &free)) {
3017				pmap_invalidate_page(pmap, va);
3018				pmap_free_zero_pages(free);
3019			}
3020
3021			mpte = NULL;
3022		}
3023		return (mpte);
3024	}
3025
3026	/*
3027	 * Increment counters
3028	 */
3029	pmap->pm_stats.resident_count++;
3030
3031	pa = VM_PAGE_TO_PHYS(m);
3032#ifdef PAE
3033	if ((prot & VM_PROT_EXECUTE) == 0)
3034		pa |= pg_nx;
3035#endif
3036
3037#if 0
3038	/*
3039	 * Now validate mapping with RO protection
3040	 */
3041	if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED))
3042		pte_store(pte, pa | PG_V | PG_U);
3043	else
3044		pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3045#else
3046	/*
3047	 * Now validate mapping with RO protection
3048	 */
3049	if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED))
3050		pa = 	xpmap_ptom(pa | PG_V | PG_U);
3051	else
3052		pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED);
3053
3054	mcl->op = __HYPERVISOR_update_va_mapping;
3055	mcl->args[0] = va;
3056	mcl->args[1] = (uint32_t)(pa & 0xffffffff);
3057	mcl->args[2] = (uint32_t)(pa >> 32);
3058	mcl->args[3] = 0;
3059	*mclpp = mcl + 1;
3060	*count = *count + 1;
3061#endif
3062	return mpte;
3063}
3064
3065/*
3066 * Make a temporary mapping for a physical address.  This is only intended
3067 * to be used for panic dumps.
3068 */
3069void *
3070pmap_kenter_temporary(vm_paddr_t pa, int i)
3071{
3072	vm_offset_t va;
3073
3074	va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3075	pmap_kenter(va, pa);
3076	invlpg(va);
3077	return ((void *)crashdumpmap);
3078}
3079
3080/*
3081 * This code maps large physical mmap regions into the
3082 * processor address space.  Note that some shortcuts
3083 * are taken, but the code works.
3084 */
3085void
3086pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
3087		    vm_object_t object, vm_pindex_t pindex,
3088		    vm_size_t size)
3089{
3090	vm_page_t p;
3091
3092	VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3093	KASSERT(object->type == OBJT_DEVICE,
3094	    ("pmap_object_init_pt: non-device object"));
3095	if (pseflag &&
3096	    ((addr & (NBPDR - 1)) == 0) && ((size & (NBPDR - 1)) == 0)) {
3097		int i;
3098		vm_page_t m[1];
3099		unsigned int ptepindex;
3100		int npdes;
3101		pd_entry_t ptepa;
3102
3103		PMAP_LOCK(pmap);
3104		if (pmap->pm_pdir[ptepindex = (addr >> PDRSHIFT)])
3105			goto out;
3106		PMAP_UNLOCK(pmap);
3107retry:
3108		p = vm_page_lookup(object, pindex);
3109		if (p != NULL) {
3110			if (vm_page_sleep_if_busy(p, FALSE, "init4p"))
3111				goto retry;
3112		} else {
3113			p = vm_page_alloc(object, pindex, VM_ALLOC_NORMAL);
3114			if (p == NULL)
3115				return;
3116			m[0] = p;
3117
3118			if (vm_pager_get_pages(object, m, 1, 0) != VM_PAGER_OK) {
3119				vm_page_lock_queues();
3120				vm_page_free(p);
3121				vm_page_unlock_queues();
3122				return;
3123			}
3124
3125			p = vm_page_lookup(object, pindex);
3126			vm_page_lock_queues();
3127			vm_page_wakeup(p);
3128			vm_page_unlock_queues();
3129		}
3130
3131		ptepa = VM_PAGE_TO_PHYS(p);
3132		if (ptepa & (NBPDR - 1))
3133			return;
3134
3135		p->valid = VM_PAGE_BITS_ALL;
3136
3137		PMAP_LOCK(pmap);
3138		pmap->pm_stats.resident_count += size >> PAGE_SHIFT;
3139		npdes = size >> PDRSHIFT;
3140		critical_enter();
3141		for(i = 0; i < npdes; i++) {
3142			PD_SET_VA(pmap, ptepindex,
3143			    ptepa | PG_U | PG_M | PG_RW | PG_V | PG_PS, FALSE);
3144			ptepa += NBPDR;
3145			ptepindex += 1;
3146		}
3147		pmap_invalidate_all(pmap);
3148		critical_exit();
3149out:
3150		PMAP_UNLOCK(pmap);
3151	}
3152}
3153
3154/*
3155 *	Routine:	pmap_change_wiring
3156 *	Function:	Change the wiring attribute for a map/virtual-address
3157 *			pair.
3158 *	In/out conditions:
3159 *			The mapping must already exist in the pmap.
3160 */
3161void
3162pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3163{
3164	pt_entry_t *pte;
3165
3166	vm_page_lock_queues();
3167	PMAP_LOCK(pmap);
3168	pte = pmap_pte(pmap, va);
3169
3170	if (wired && !pmap_pte_w(pte)) {
3171		PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE);
3172		pmap->pm_stats.wired_count++;
3173	} else if (!wired && pmap_pte_w(pte)) {
3174		PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE);
3175		pmap->pm_stats.wired_count--;
3176	}
3177
3178	/*
3179	 * Wiring is not a hardware characteristic so there is no need to
3180	 * invalidate TLB.
3181	 */
3182	pmap_pte_release(pte);
3183	PMAP_UNLOCK(pmap);
3184	vm_page_unlock_queues();
3185}
3186
3187
3188
3189/*
3190 *	Copy the range specified by src_addr/len
3191 *	from the source map to the range dst_addr/len
3192 *	in the destination map.
3193 *
3194 *	This routine is only advisory and need not do anything.
3195 */
3196
3197void
3198pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3199	  vm_offset_t src_addr)
3200{
3201	vm_page_t   free;
3202	vm_offset_t addr;
3203	vm_offset_t end_addr = src_addr + len;
3204	vm_offset_t pdnxt;
3205
3206	if (dst_addr != src_addr)
3207		return;
3208
3209	if (!pmap_is_current(src_pmap)) {
3210		CTR2(KTR_PMAP,
3211		    "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx",
3212		    (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME));
3213
3214		return;
3215	}
3216	CTR5(KTR_PMAP, "pmap_copy:  dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x",
3217	    dst_pmap, src_pmap, dst_addr, len, src_addr);
3218
3219	vm_page_lock_queues();
3220	if (dst_pmap < src_pmap) {
3221		PMAP_LOCK(dst_pmap);
3222		PMAP_LOCK(src_pmap);
3223	} else {
3224		PMAP_LOCK(src_pmap);
3225		PMAP_LOCK(dst_pmap);
3226	}
3227	sched_pin();
3228	for (addr = src_addr; addr < end_addr; addr = pdnxt) {
3229		pt_entry_t *src_pte, *dst_pte;
3230		vm_page_t dstmpte, srcmpte;
3231		pd_entry_t srcptepaddr;
3232		unsigned ptepindex;
3233
3234		if (addr >= UPT_MIN_ADDRESS)
3235			panic("pmap_copy: invalid to pmap_copy page tables");
3236
3237		pdnxt = (addr + NBPDR) & ~PDRMASK;
3238		ptepindex = addr >> PDRSHIFT;
3239
3240		srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]);
3241		if (srcptepaddr == 0)
3242			continue;
3243
3244		if (srcptepaddr & PG_PS) {
3245			if (dst_pmap->pm_pdir[ptepindex] == 0) {
3246				PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE);
3247				dst_pmap->pm_stats.resident_count +=
3248				    NBPDR / PAGE_SIZE;
3249			}
3250			continue;
3251		}
3252
3253		srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
3254		if (srcmpte->wire_count == 0)
3255			panic("pmap_copy: source page table page is unused");
3256
3257		if (pdnxt > end_addr)
3258			pdnxt = end_addr;
3259
3260		src_pte = vtopte(addr);
3261		while (addr < pdnxt) {
3262			pt_entry_t ptetemp;
3263			ptetemp = *src_pte;
3264			/*
3265			 * we only virtual copy managed pages
3266			 */
3267			if ((ptetemp & PG_MANAGED) != 0) {
3268				dstmpte = pmap_allocpte(dst_pmap, addr,
3269				    M_NOWAIT);
3270				if (dstmpte == NULL)
3271					break;
3272				dst_pte = pmap_pte_quick(dst_pmap, addr);
3273				if (*dst_pte == 0 &&
3274				    pmap_try_insert_pv_entry(dst_pmap, addr,
3275				    PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) {
3276					/*
3277					 * Clear the wired, modified, and
3278					 * accessed (referenced) bits
3279					 * during the copy.
3280					 */
3281					KASSERT(ptetemp != 0, ("src_pte not set"));
3282					PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */);
3283					KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)),
3284					    ("no pmap copy expected: 0x%jx saw: 0x%jx",
3285						ptetemp &  ~(PG_W | PG_M | PG_A), *dst_pte));
3286					dst_pmap->pm_stats.resident_count++;
3287	 			} else {
3288					free = NULL;
3289					if (pmap_unwire_pte_hold(dst_pmap,
3290					    dstmpte, &free)) {
3291						pmap_invalidate_page(dst_pmap,
3292						    addr);
3293						pmap_free_zero_pages(free);
3294					}
3295				}
3296				if (dstmpte->wire_count >= srcmpte->wire_count)
3297					break;
3298			}
3299			addr += PAGE_SIZE;
3300			src_pte++;
3301		}
3302	}
3303	PT_UPDATES_FLUSH();
3304	sched_unpin();
3305	vm_page_unlock_queues();
3306	PMAP_UNLOCK(src_pmap);
3307	PMAP_UNLOCK(dst_pmap);
3308}
3309
3310/*
3311 *	pmap_zero_page zeros the specified hardware page by mapping
3312 *	the page into KVM and using bzero to clear its contents.
3313 */
3314void
3315pmap_zero_page(vm_page_t m)
3316{
3317	struct sysmaps *sysmaps;
3318
3319	sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
3320	mtx_lock(&sysmaps->lock);
3321	if (*sysmaps->CMAP2)
3322		panic("pmap_zero_page: CMAP2 busy");
3323	sched_pin();
3324	PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(m)) | PG_A | PG_M);
3325	pagezero(sysmaps->CADDR2);
3326	PT_SET_MA(sysmaps->CADDR2, 0);
3327	sched_unpin();
3328	mtx_unlock(&sysmaps->lock);
3329}
3330
3331/*
3332 *	pmap_zero_page_area zeros the specified hardware page by mapping
3333 *	the page into KVM and using bzero to clear its contents.
3334 *
3335 *	off and size may not cover an area beyond a single hardware page.
3336 */
3337void
3338pmap_zero_page_area(vm_page_t m, int off, int size)
3339{
3340	struct sysmaps *sysmaps;
3341
3342	sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
3343	mtx_lock(&sysmaps->lock);
3344	if (*sysmaps->CMAP2)
3345		panic("pmap_zero_page: CMAP2 busy");
3346	sched_pin();
3347	PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(m)) | PG_A | PG_M);
3348
3349	if (off == 0 && size == PAGE_SIZE)
3350		pagezero(sysmaps->CADDR2);
3351	else
3352		bzero((char *)sysmaps->CADDR2 + off, size);
3353	PT_SET_MA(sysmaps->CADDR2, 0);
3354	sched_unpin();
3355	mtx_unlock(&sysmaps->lock);
3356}
3357
3358/*
3359 *	pmap_zero_page_idle zeros the specified hardware page by mapping
3360 *	the page into KVM and using bzero to clear its contents.  This
3361 *	is intended to be called from the vm_pagezero process only and
3362 *	outside of Giant.
3363 */
3364void
3365pmap_zero_page_idle(vm_page_t m)
3366{
3367
3368	if (*CMAP3)
3369		panic("pmap_zero_page: CMAP3 busy");
3370	sched_pin();
3371	PT_SET_MA(CADDR3, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(m)) | PG_A | PG_M);
3372	pagezero(CADDR3);
3373	PT_SET_MA(CADDR3, 0);
3374	sched_unpin();
3375}
3376
3377/*
3378 *	pmap_copy_page copies the specified (machine independent)
3379 *	page by mapping the page into virtual memory and using
3380 *	bcopy to copy the page, one machine dependent page at a
3381 *	time.
3382 */
3383void
3384pmap_copy_page(vm_page_t src, vm_page_t dst)
3385{
3386	struct sysmaps *sysmaps;
3387
3388	sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
3389	mtx_lock(&sysmaps->lock);
3390	if (*sysmaps->CMAP1)
3391		panic("pmap_copy_page: CMAP1 busy");
3392	if (*sysmaps->CMAP2)
3393		panic("pmap_copy_page: CMAP2 busy");
3394	sched_pin();
3395	PT_SET_MA(sysmaps->CADDR1, PG_V | xpmap_ptom(VM_PAGE_TO_PHYS(src)) | PG_A);
3396	PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(dst)) | PG_A | PG_M);
3397	bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
3398	PT_SET_MA(sysmaps->CADDR1, 0);
3399	PT_SET_MA(sysmaps->CADDR2, 0);
3400	sched_unpin();
3401	mtx_unlock(&sysmaps->lock);
3402}
3403
3404/*
3405 * Returns true if the pmap's pv is one of the first
3406 * 16 pvs linked to from this page.  This count may
3407 * be changed upwards or downwards in the future; it
3408 * is only necessary that true be returned for a small
3409 * subset of pmaps for proper page aging.
3410 */
3411boolean_t
3412pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3413{
3414	pv_entry_t pv;
3415	int loops = 0;
3416
3417	if (m->flags & PG_FICTITIOUS)
3418		return (FALSE);
3419
3420	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3421	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3422		if (PV_PMAP(pv) == pmap) {
3423			return TRUE;
3424		}
3425		loops++;
3426		if (loops >= 16)
3427			break;
3428	}
3429	return (FALSE);
3430}
3431
3432/*
3433 *	pmap_page_wired_mappings:
3434 *
3435 *	Return the number of managed mappings to the given physical page
3436 *	that are wired.
3437 */
3438int
3439pmap_page_wired_mappings(vm_page_t m)
3440{
3441	pv_entry_t pv;
3442	pt_entry_t *pte;
3443	pmap_t pmap;
3444	int count;
3445
3446	count = 0;
3447	if ((m->flags & PG_FICTITIOUS) != 0)
3448		return (count);
3449	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3450	sched_pin();
3451	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3452		pmap = PV_PMAP(pv);
3453		PMAP_LOCK(pmap);
3454		pte = pmap_pte_quick(pmap, pv->pv_va);
3455		if ((*pte & PG_W) != 0)
3456			count++;
3457		PMAP_UNLOCK(pmap);
3458	}
3459	sched_unpin();
3460	return (count);
3461}
3462
3463/*
3464 * Returns TRUE if the given page is mapped individually or as part of
3465 * a 4mpage.  Otherwise, returns FALSE.
3466 */
3467boolean_t
3468pmap_page_is_mapped(vm_page_t m)
3469{
3470	struct md_page *pvh;
3471
3472	if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
3473		return (FALSE);
3474	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3475	if (TAILQ_EMPTY(&m->md.pv_list)) {
3476		pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3477		return (!TAILQ_EMPTY(&pvh->pv_list));
3478	} else
3479		return (TRUE);
3480}
3481
3482/*
3483 * Remove all pages from specified address space
3484 * this aids process exit speeds.  Also, this code
3485 * is special cased for current process only, but
3486 * can have the more generic (and slightly slower)
3487 * mode enabled.  This is much faster than pmap_remove
3488 * in the case of running down an entire address space.
3489 */
3490void
3491pmap_remove_pages(pmap_t pmap)
3492{
3493	pt_entry_t *pte, tpte;
3494	vm_page_t m, free = NULL;
3495	pv_entry_t pv;
3496	struct pv_chunk *pc, *npc;
3497	int field, idx;
3498	int32_t bit;
3499	uint32_t inuse, bitmask;
3500	int allfree;
3501
3502	CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap);
3503
3504	if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) {
3505		printf("warning: pmap_remove_pages called with non-current pmap\n");
3506		return;
3507	}
3508	vm_page_lock_queues();
3509	KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap"));
3510	PMAP_LOCK(pmap);
3511	sched_pin();
3512	TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3513		allfree = 1;
3514		for (field = 0; field < _NPCM; field++) {
3515			inuse = (~(pc->pc_map[field])) & pc_freemask[field];
3516			while (inuse != 0) {
3517				bit = bsfl(inuse);
3518				bitmask = 1UL << bit;
3519				idx = field * 32 + bit;
3520				pv = &pc->pc_pventry[idx];
3521				inuse &= ~bitmask;
3522
3523				pte = vtopte(pv->pv_va);
3524				tpte = *pte ? xpmap_mtop(*pte) : 0;
3525
3526				if (tpte == 0) {
3527					printf(
3528					    "TPTE at %p  IS ZERO @ VA %08x\n",
3529					    pte, pv->pv_va);
3530					panic("bad pte");
3531				}
3532
3533/*
3534 * We cannot remove wired pages from a process' mapping at this time
3535 */
3536				if (tpte & PG_W) {
3537					allfree = 0;
3538					continue;
3539				}
3540
3541				m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
3542				KASSERT(m->phys_addr == (tpte & PG_FRAME),
3543				    ("vm_page_t %p phys_addr mismatch %016jx %016jx",
3544				    m, (uintmax_t)m->phys_addr,
3545				    (uintmax_t)tpte));
3546
3547				KASSERT(m < &vm_page_array[vm_page_array_size],
3548					("pmap_remove_pages: bad tpte %#jx",
3549					(uintmax_t)tpte));
3550
3551
3552				PT_CLEAR_VA(pte, FALSE);
3553
3554				/*
3555				 * Update the vm_page_t clean/reference bits.
3556				 */
3557				if (tpte & PG_M)
3558					vm_page_dirty(m);
3559
3560				TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
3561				if (TAILQ_EMPTY(&m->md.pv_list))
3562					vm_page_flag_clear(m, PG_WRITEABLE);
3563
3564				pmap_unuse_pt(pmap, pv->pv_va, &free);
3565
3566				/* Mark free */
3567				PV_STAT(pv_entry_frees++);
3568				PV_STAT(pv_entry_spare++);
3569				pv_entry_count--;
3570				pc->pc_map[field] |= bitmask;
3571				pmap->pm_stats.resident_count--;
3572			}
3573		}
3574		PT_UPDATES_FLUSH();
3575		if (allfree) {
3576			PV_STAT(pv_entry_spare -= _NPCPV);
3577			PV_STAT(pc_chunk_count--);
3578			PV_STAT(pc_chunk_frees++);
3579			TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3580			m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
3581			pmap_qremove((vm_offset_t)pc, 1);
3582			vm_page_unwire(m, 0);
3583			vm_page_free(m);
3584			pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
3585		}
3586	}
3587	PT_UPDATES_FLUSH();
3588	if (*PMAP1)
3589		PT_SET_MA(PADDR1, 0);
3590
3591	sched_unpin();
3592	pmap_invalidate_all(pmap);
3593	vm_page_unlock_queues();
3594	PMAP_UNLOCK(pmap);
3595	pmap_free_zero_pages(free);
3596}
3597
3598/*
3599 *	pmap_is_modified:
3600 *
3601 *	Return whether or not the specified physical page was modified
3602 *	in any physical maps.
3603 */
3604boolean_t
3605pmap_is_modified(vm_page_t m)
3606{
3607	pv_entry_t pv;
3608	pt_entry_t *pte;
3609	pmap_t pmap;
3610	boolean_t rv;
3611
3612	rv = FALSE;
3613	if (m->flags & PG_FICTITIOUS)
3614		return (rv);
3615
3616	sched_pin();
3617	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3618	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3619		pmap = PV_PMAP(pv);
3620		PMAP_LOCK(pmap);
3621		pte = pmap_pte_quick(pmap, pv->pv_va);
3622		rv = (*pte & PG_M) != 0;
3623		PMAP_UNLOCK(pmap);
3624		if (rv)
3625			break;
3626	}
3627	if (*PMAP1)
3628		PT_SET_MA(PADDR1, 0);
3629	sched_unpin();
3630	return (rv);
3631}
3632
3633/*
3634 *	pmap_is_prefaultable:
3635 *
3636 *	Return whether or not the specified virtual address is elgible
3637 *	for prefault.
3638 */
3639static boolean_t
3640pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr)
3641{
3642	pt_entry_t *pte;
3643	boolean_t rv = FALSE;
3644
3645	return (rv);
3646
3647	if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) {
3648		pte = vtopte(addr);
3649		rv = (*pte == 0);
3650	}
3651	return (rv);
3652}
3653
3654boolean_t
3655pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3656{
3657	boolean_t rv;
3658
3659	PMAP_LOCK(pmap);
3660	rv = pmap_is_prefaultable_locked(pmap, addr);
3661	PMAP_UNLOCK(pmap);
3662	return (rv);
3663}
3664
3665void
3666pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len)
3667{
3668	int i, npages = round_page(len) >> PAGE_SHIFT;
3669	for (i = 0; i < npages; i++) {
3670		pt_entry_t *pte;
3671		pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE));
3672		pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M)));
3673		PMAP_MARK_PRIV(xpmap_mtop(*pte));
3674		pmap_pte_release(pte);
3675	}
3676}
3677
3678void
3679pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len)
3680{
3681	int i, npages = round_page(len) >> PAGE_SHIFT;
3682	for (i = 0; i < npages; i++) {
3683		pt_entry_t *pte;
3684		pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE));
3685		PMAP_MARK_UNPRIV(xpmap_mtop(*pte));
3686		pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M));
3687		pmap_pte_release(pte);
3688	}
3689}
3690
3691/*
3692 * Clear the write and modified bits in each of the given page's mappings.
3693 */
3694void
3695pmap_remove_write(vm_page_t m)
3696{
3697	pv_entry_t pv;
3698	pmap_t pmap;
3699	pt_entry_t oldpte, *pte;
3700
3701	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3702	if ((m->flags & PG_FICTITIOUS) != 0 ||
3703	    (m->flags & PG_WRITEABLE) == 0)
3704		return;
3705	sched_pin();
3706	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3707		pmap = PV_PMAP(pv);
3708		PMAP_LOCK(pmap);
3709		pte = pmap_pte_quick(pmap, pv->pv_va);
3710retry:
3711		oldpte = *pte;
3712		if ((oldpte & PG_RW) != 0) {
3713			/*
3714			 * Regardless of whether a pte is 32 or 64 bits
3715			 * in size, PG_RW and PG_M are among the least
3716			 * significant 32 bits.
3717			 */
3718			if (!atomic_cmpset_int((u_int *)pte, oldpte,
3719			    oldpte & ~(PG_RW | PG_M)))
3720				goto retry;
3721			if ((oldpte & PG_M) != 0)
3722				vm_page_dirty(m);
3723			pmap_invalidate_page(pmap, pv->pv_va);
3724		}
3725		PMAP_UNLOCK(pmap);
3726	}
3727	vm_page_flag_clear(m, PG_WRITEABLE);
3728	PT_UPDATES_FLUSH();
3729	if (*PMAP1)
3730		PT_SET_MA(PADDR1, 0);
3731	sched_unpin();
3732}
3733
3734/*
3735 *	pmap_ts_referenced:
3736 *
3737 *	Return a count of reference bits for a page, clearing those bits.
3738 *	It is not necessary for every reference bit to be cleared, but it
3739 *	is necessary that 0 only be returned when there are truly no
3740 *	reference bits set.
3741 *
3742 *	XXX: The exact number of bits to check and clear is a matter that
3743 *	should be tested and standardized at some point in the future for
3744 *	optimal aging of shared pages.
3745 */
3746int
3747pmap_ts_referenced(vm_page_t m)
3748{
3749	pv_entry_t pv, pvf, pvn;
3750	pmap_t pmap;
3751	pt_entry_t *pte;
3752	int rtval = 0;
3753
3754	if (m->flags & PG_FICTITIOUS)
3755		return (rtval);
3756	sched_pin();
3757	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3758	if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3759		pvf = pv;
3760		do {
3761			pvn = TAILQ_NEXT(pv, pv_list);
3762			TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
3763			TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
3764			pmap = PV_PMAP(pv);
3765			PMAP_LOCK(pmap);
3766			pte = pmap_pte_quick(pmap, pv->pv_va);
3767			if ((*pte & PG_A) != 0) {
3768				PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE);
3769				pmap_invalidate_page(pmap, pv->pv_va);
3770				rtval++;
3771				if (rtval > 4)
3772					pvn = NULL;
3773			}
3774			PMAP_UNLOCK(pmap);
3775		} while ((pv = pvn) != NULL && pv != pvf);
3776	}
3777	PT_UPDATES_FLUSH();
3778	if (*PMAP1)
3779		PT_SET_MA(PADDR1, 0);
3780
3781	sched_unpin();
3782	return (rtval);
3783}
3784
3785/*
3786 *	Clear the modify bits on the specified physical page.
3787 */
3788void
3789pmap_clear_modify(vm_page_t m)
3790{
3791	pv_entry_t pv;
3792	pmap_t pmap;
3793	pt_entry_t *pte;
3794
3795	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3796	if ((m->flags & PG_FICTITIOUS) != 0)
3797		return;
3798	sched_pin();
3799	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3800		pmap = PV_PMAP(pv);
3801		PMAP_LOCK(pmap);
3802		pte = pmap_pte_quick(pmap, pv->pv_va);
3803		if ((*pte & PG_M) != 0) {
3804			/*
3805			 * Regardless of whether a pte is 32 or 64 bits
3806			 * in size, PG_M is among the least significant
3807			 * 32 bits.
3808			 */
3809			PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE);
3810			pmap_invalidate_page(pmap, pv->pv_va);
3811		}
3812		PMAP_UNLOCK(pmap);
3813	}
3814	sched_unpin();
3815}
3816
3817/*
3818 *	pmap_clear_reference:
3819 *
3820 *	Clear the reference bit on the specified physical page.
3821 */
3822void
3823pmap_clear_reference(vm_page_t m)
3824{
3825	pv_entry_t pv;
3826	pmap_t pmap;
3827	pt_entry_t *pte;
3828
3829	mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3830	if ((m->flags & PG_FICTITIOUS) != 0)
3831		return;
3832	sched_pin();
3833	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3834		pmap = PV_PMAP(pv);
3835		PMAP_LOCK(pmap);
3836		pte = pmap_pte_quick(pmap, pv->pv_va);
3837		if ((*pte & PG_A) != 0) {
3838			/*
3839			 * Regardless of whether a pte is 32 or 64 bits
3840			 * in size, PG_A is among the least significant
3841			 * 32 bits.
3842			 */
3843			PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE);
3844			pmap_invalidate_page(pmap, pv->pv_va);
3845		}
3846		PMAP_UNLOCK(pmap);
3847	}
3848	sched_unpin();
3849}
3850
3851/*
3852 * Miscellaneous support routines follow
3853 */
3854
3855/*
3856 * Map a set of physical memory pages into the kernel virtual
3857 * address space. Return a pointer to where it is mapped. This
3858 * routine is intended to be used for mapping device memory,
3859 * NOT real memory.
3860 */
3861void *
3862pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
3863{
3864	vm_offset_t va, tmpva, offset;
3865
3866	offset = pa & PAGE_MASK;
3867	size = roundup(offset + size, PAGE_SIZE);
3868	pa = pa & PG_FRAME;
3869
3870	if (pa < KERNLOAD && pa + size <= KERNLOAD)
3871		va = KERNBASE + pa;
3872	else
3873		va = kmem_alloc_nofault(kernel_map, size);
3874	if (!va)
3875		panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3876
3877	for (tmpva = va; size > 0; ) {
3878		pmap_kenter_attr(tmpva, pa, mode);
3879		size -= PAGE_SIZE;
3880		tmpva += PAGE_SIZE;
3881		pa += PAGE_SIZE;
3882	}
3883	pmap_invalidate_range(kernel_pmap, va, tmpva);
3884	pmap_invalidate_cache();
3885	return ((void *)(va + offset));
3886}
3887
3888void *
3889pmap_mapdev(vm_paddr_t pa, vm_size_t size)
3890{
3891
3892	return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
3893}
3894
3895void *
3896pmap_mapbios(vm_paddr_t pa, vm_size_t size)
3897{
3898
3899	return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
3900}
3901
3902void
3903pmap_unmapdev(vm_offset_t va, vm_size_t size)
3904{
3905	vm_offset_t base, offset, tmpva;
3906
3907	if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
3908		return;
3909	base = trunc_page(va);
3910	offset = va & PAGE_MASK;
3911	size = roundup(offset + size, PAGE_SIZE);
3912	critical_enter();
3913	for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE)
3914		pmap_kremove(tmpva);
3915	pmap_invalidate_range(kernel_pmap, va, tmpva);
3916	critical_exit();
3917	kmem_free(kernel_map, base, size);
3918}
3919
3920int
3921pmap_change_attr(va, size, mode)
3922	vm_offset_t va;
3923	vm_size_t size;
3924	int mode;
3925{
3926	vm_offset_t base, offset, tmpva;
3927	pt_entry_t *pte;
3928	u_int opte, npte;
3929	pd_entry_t *pde;
3930
3931	base = trunc_page(va);
3932	offset = va & PAGE_MASK;
3933	size = roundup(offset + size, PAGE_SIZE);
3934
3935	/* Only supported on kernel virtual addresses. */
3936	if (base <= VM_MAXUSER_ADDRESS)
3937		return (EINVAL);
3938
3939	/* 4MB pages and pages that aren't mapped aren't supported. */
3940	for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) {
3941		pde = pmap_pde(kernel_pmap, tmpva);
3942		if (*pde & PG_PS)
3943			return (EINVAL);
3944		if ((*pde & PG_V) == 0)
3945			return (EINVAL);
3946		pte = vtopte(va);
3947		if ((*pte & PG_V) == 0)
3948			return (EINVAL);
3949	}
3950
3951	/*
3952	 * Ok, all the pages exist and are 4k, so run through them updating
3953	 * their cache mode.
3954	 */
3955	for (tmpva = base; size > 0; ) {
3956		pte = vtopte(tmpva);
3957
3958		/*
3959		 * The cache mode bits are all in the low 32-bits of the
3960		 * PTE, so we can just spin on updating the low 32-bits.
3961		 */
3962		do {
3963			opte = *(u_int *)pte;
3964			npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT);
3965			npte |= pmap_cache_bits(mode, 0);
3966			PT_SET_VA_MA(pte, npte, TRUE);
3967		} while (npte != opte && (*pte != npte));
3968		tmpva += PAGE_SIZE;
3969		size -= PAGE_SIZE;
3970	}
3971
3972	/*
3973	 * Flush CPU caches to make sure any data isn't cached that shouldn't
3974	 * be, etc.
3975	 */
3976	pmap_invalidate_range(kernel_pmap, base, tmpva);
3977	pmap_invalidate_cache();
3978	return (0);
3979}
3980
3981/*
3982 * perform the pmap work for mincore
3983 */
3984int
3985pmap_mincore(pmap_t pmap, vm_offset_t addr)
3986{
3987	pt_entry_t *ptep, pte;
3988	vm_page_t m;
3989	int val = 0;
3990
3991	PMAP_LOCK(pmap);
3992	ptep = pmap_pte(pmap, addr);
3993	pte = (ptep != NULL) ? PT_GET(ptep) : 0;
3994	pmap_pte_release(ptep);
3995	PMAP_UNLOCK(pmap);
3996
3997	if (pte != 0) {
3998		vm_paddr_t pa;
3999
4000		val = MINCORE_INCORE;
4001		if ((pte & PG_MANAGED) == 0)
4002			return val;
4003
4004		pa = pte & PG_FRAME;
4005
4006		m = PHYS_TO_VM_PAGE(pa);
4007
4008		/*
4009		 * Modified by us
4010		 */
4011		if (pte & PG_M)
4012			val |= MINCORE_MODIFIED|MINCORE_MODIFIED_OTHER;
4013		else {
4014			/*
4015			 * Modified by someone else
4016			 */
4017			vm_page_lock_queues();
4018			if (m->dirty || pmap_is_modified(m))
4019				val |= MINCORE_MODIFIED_OTHER;
4020			vm_page_unlock_queues();
4021		}
4022		/*
4023		 * Referenced by us
4024		 */
4025		if (pte & PG_A)
4026			val |= MINCORE_REFERENCED|MINCORE_REFERENCED_OTHER;
4027		else {
4028			/*
4029			 * Referenced by someone else
4030			 */
4031			vm_page_lock_queues();
4032			if ((m->flags & PG_REFERENCED) ||
4033			    pmap_ts_referenced(m)) {
4034				val |= MINCORE_REFERENCED_OTHER;
4035				vm_page_flag_set(m, PG_REFERENCED);
4036			}
4037			vm_page_unlock_queues();
4038		}
4039	}
4040	return val;
4041}
4042
4043void
4044pmap_activate(struct thread *td)
4045{
4046	pmap_t	pmap, oldpmap;
4047	u_int32_t  cr3;
4048
4049	critical_enter();
4050	pmap = vmspace_pmap(td->td_proc->p_vmspace);
4051	oldpmap = PCPU_GET(curpmap);
4052#if defined(SMP)
4053	atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask));
4054	atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask));
4055#else
4056	oldpmap->pm_active &= ~1;
4057	pmap->pm_active |= 1;
4058#endif
4059#ifdef PAE
4060	cr3 = vtophys(pmap->pm_pdpt);
4061#else
4062	cr3 = vtophys(pmap->pm_pdir);
4063#endif
4064	/*
4065	 * pmap_activate is for the current thread on the current cpu
4066	 */
4067	td->td_pcb->pcb_cr3 = cr3;
4068	PT_UPDATES_FLUSH();
4069	load_cr3(cr3);
4070
4071	PCPU_SET(curpmap, pmap);
4072	critical_exit();
4073}
4074
4075/*
4076 *	Increase the starting virtual address of the given mapping if a
4077 *	different alignment might result in more superpage mappings.
4078 */
4079void
4080pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4081    vm_offset_t *addr, vm_size_t size)
4082{
4083	vm_offset_t superpage_offset;
4084
4085	if (size < NBPDR)
4086		return;
4087	if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4088		offset += ptoa(object->pg_color);
4089	superpage_offset = offset & PDRMASK;
4090	if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
4091	    (*addr & PDRMASK) == superpage_offset)
4092		return;
4093	if ((*addr & PDRMASK) < superpage_offset)
4094		*addr = (*addr & ~PDRMASK) + superpage_offset;
4095	else
4096		*addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
4097}
4098
4099#if defined(PMAP_DEBUG)
4100pmap_pid_dump(int pid)
4101{
4102	pmap_t pmap;
4103	struct proc *p;
4104	int npte = 0;
4105	int index;
4106
4107	sx_slock(&allproc_lock);
4108	FOREACH_PROC_IN_SYSTEM(p) {
4109		if (p->p_pid != pid)
4110			continue;
4111
4112		if (p->p_vmspace) {
4113			int i,j;
4114			index = 0;
4115			pmap = vmspace_pmap(p->p_vmspace);
4116			for (i = 0; i < NPDEPTD; i++) {
4117				pd_entry_t *pde;
4118				pt_entry_t *pte;
4119				vm_offset_t base = i << PDRSHIFT;
4120
4121				pde = &pmap->pm_pdir[i];
4122				if (pde && pmap_pde_v(pde)) {
4123					for (j = 0; j < NPTEPG; j++) {
4124						vm_offset_t va = base + (j << PAGE_SHIFT);
4125						if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
4126							if (index) {
4127								index = 0;
4128								printf("\n");
4129							}
4130							sx_sunlock(&allproc_lock);
4131							return npte;
4132						}
4133						pte = pmap_pte(pmap, va);
4134						if (pte && pmap_pte_v(pte)) {
4135							pt_entry_t pa;
4136							vm_page_t m;
4137							pa = PT_GET(pte);
4138							m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
4139							printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
4140								va, pa, m->hold_count, m->wire_count, m->flags);
4141							npte++;
4142							index++;
4143							if (index >= 2) {
4144								index = 0;
4145								printf("\n");
4146							} else {
4147								printf(" ");
4148							}
4149						}
4150					}
4151				}
4152			}
4153		}
4154	}
4155	sx_sunlock(&allproc_lock);
4156	return npte;
4157}
4158#endif
4159
4160#if defined(DEBUG)
4161
4162static void	pads(pmap_t pm);
4163void		pmap_pvdump(vm_paddr_t pa);
4164
4165/* print address space of pmap*/
4166static void
4167pads(pmap_t pm)
4168{
4169	int i, j;
4170	vm_paddr_t va;
4171	pt_entry_t *ptep;
4172
4173	if (pm == kernel_pmap)
4174		return;
4175	for (i = 0; i < NPDEPTD; i++)
4176		if (pm->pm_pdir[i])
4177			for (j = 0; j < NPTEPG; j++) {
4178				va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
4179				if (pm == kernel_pmap && va < KERNBASE)
4180					continue;
4181				if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
4182					continue;
4183				ptep = pmap_pte(pm, va);
4184				if (pmap_pte_v(ptep))
4185					printf("%x:%x ", va, *ptep);
4186			};
4187
4188}
4189
4190void
4191pmap_pvdump(vm_paddr_t pa)
4192{
4193	pv_entry_t pv;
4194	pmap_t pmap;
4195	vm_page_t m;
4196
4197	printf("pa %x", pa);
4198	m = PHYS_TO_VM_PAGE(pa);
4199	TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4200		pmap = PV_PMAP(pv);
4201		printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);
4202		pads(pmap);
4203	}
4204	printf(" ");
4205}
4206#endif
4207