perfmon.h revision 18444
114825Swollman/* 214825Swollman * Copyright 1996 Massachusetts Institute of Technology 314825Swollman * 414825Swollman * Permission to use, copy, modify, and distribute this software and 514825Swollman * its documentation for any purpose and without fee is hereby 614825Swollman * granted, provided that both the above copyright notice and this 714825Swollman * permission notice appear in all copies, that both the above 814825Swollman * copyright notice and this permission notice appear in all 914825Swollman * supporting documentation, and that the name of M.I.T. not be used 1014825Swollman * in advertising or publicity pertaining to distribution of the 1114825Swollman * software without specific, written prior permission. M.I.T. makes 1214825Swollman * no representations about the suitability of this software for any 1314825Swollman * purpose. It is provided "as is" without express or implied 1414825Swollman * warranty. 1514825Swollman * 1614825Swollman * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS 1714825Swollman * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE, 1814825Swollman * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 1914825Swollman * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT 2014825Swollman * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2114825Swollman * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2214825Swollman * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 2314825Swollman * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 2414825Swollman * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2514825Swollman * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 2614825Swollman * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2714825Swollman * SUCH DAMAGE. 2814825Swollman * 2918444Sbde * $Id: perfmon.h,v 1.1 1996/03/26 19:57:56 wollman Exp $ 3014825Swollman */ 3114825Swollman 3214825Swollman/* 3314825Swollman * Interface to performance-monitoring counters for Intel Pentium and 3414825Swollman * Pentium Pro CPUs. 3514825Swollman */ 3614825Swollman 3718444Sbde#ifndef _MACHINE_PERFMON_H_ 3818444Sbde#define _MACHINE_PERFMON_H_ 3914825Swollman 4014825Swollman#ifndef KERNEL 4118444Sbde#include <sys/types.h> 4218444Sbde#endif 4314825Swollman#include <sys/ioccom.h> 4414825Swollman 4514825Swollman#define NPMC 2 4614825Swollman 4714825Swollman#define PMIOSETUP _IOW('5', 1, struct pmc) 4814825Swollman#define PMIOGET _IOWR('5', 7, struct pmc) 4914825Swollman#define PMIOSTART _IOW('5', 2, int) 5014825Swollman#define PMIOSTOP _IOW('5', 3, int) 5114825Swollman#define PMIOREAD _IOWR('5', 4, struct pmc_data) 5214825Swollman#define PMIORESET _IOW('5', 5, int) 5314825Swollman#define PMIOTSTAMP _IOR('5', 6, struct pmc_tstamp) 5414825Swollman 5514825Swollmanstruct pmc { 5614825Swollman int pmc_num; 5714825Swollman union { 5814825Swollman struct { 5914825Swollman unsigned char pmcus_event; 6014825Swollman unsigned char pmcus_unit; 6114825Swollman unsigned char pmcus_flags; 6214825Swollman unsigned char pmcus_mask; 6314825Swollman } pmcu_s; 6414825Swollman unsigned int pmcu_val; 6514825Swollman } pmc_pmcu; 6614825Swollman}; 6714825Swollman 6814825Swollman#define PMC_ALL (-1) 6914825Swollman 7014825Swollman#define pmc_event pmc_pmcu.pmcu_s.pmcus_event 7114825Swollman#define pmc_unit pmc_pmcu.pmcu_s.pmcus_unit 7214825Swollman#define pmc_flags pmc_pmcu.pmcu_s.pmcus_flags 7314825Swollman#define pmc_mask pmc_pmcu.pmcu_s.pmcus_mask 7414825Swollman#define pmc_val pmc_pmcu.pmcu_val 7514825Swollman 7614825Swollman#define PMCF_USR 0x01 /* count events in user mode */ 7714825Swollman#define PMCF_OS 0x02 /* count events in kernel mode */ 7814825Swollman#define PMCF_E 0x04 /* use edge-detection mode */ 7914825Swollman#define PMCF_PC 0x08 /* PMx output pin control */ 8014825Swollman#define PMCF_INT 0x10 /* APIC interrupt enable (do not use) */ 8114825Swollman#define PMCF_EN 0x40 /* enable counters */ 8214825Swollman#define PMCF_INV 0x80 /* invert counter mask comparison */ 8314825Swollman 8414825Swollman#define PMCF_SYS_FLAGS (PMCF_INT | PMCF_EN) /* user cannot set */ 8514825Swollman 8614825Swollmanstruct pmc_data { 8714825Swollman int pmcd_num; 8814825Swollman quad_t pmcd_value; 8914825Swollman}; 9014825Swollman 9114825Swollmanstruct pmc_tstamp { 9214825Swollman int pmct_rate; 9314825Swollman quad_t pmct_value; 9414825Swollman}; 9514825Swollman 9614825Swollman#ifndef KERNEL 9714825Swollman 9814825Swollman#define _PATH_PERFMON "/dev/perfmon" 9914825Swollman 10014825Swollman#else 10114825Swollman 10214825Swollman/* 10314825Swollman * Intra-kernel interface to performance monitoring counters 10414825Swollman */ 10514825Swollmanvoid perfmon_init __P((void)); 10614825Swollmanint perfmon_avail __P((void)); 10714825Swollmanint perfmon_setup __P((int, unsigned int)); 10814825Swollmanint perfmon_get __P((int, unsigned int *)); 10914825Swollmanint perfmon_fini __P((int)); 11014825Swollmanint perfmon_start __P((int)); 11114825Swollmanint perfmon_stop __P((int)); 11214825Swollmanint perfmon_read __P((int, quad_t *)); 11314825Swollmanint perfmon_reset __P((int)); 11414825Swollman 11514825Swollman/* 11614825Swollman * We pass the device down this interface because in the future 11714825Swollman * the different counters might be accessed through separate devices. 11814825Swollman */ 11914825Swollmanint perfmon_close __P((dev_t, int, int, struct proc *)); 12014825Swollmanint perfmon_open __P((dev_t, int, int, struct proc *)); 12114825Swollmanint perfmon_ioctl __P((dev_t, int, caddr_t, int, struct proc *)); 12214825Swollman#endif /* KERNEL */ 12314825Swollman 12414825Swollman/* 12514825Swollman * Pentium Pro performance counters, from Appendix B. 12614825Swollman */ 12714825Swollman/* Data Cache Unit */ 12814825Swollman#define PMC6_DATA_MEM_REFS 0x43 12914825Swollman#define PMC6_DCU_LINES_IN 0x45 13014825Swollman#define PMC6_DCU_M_LINES_IN 0x46 13114825Swollman#define PMC6_DCU_M_LINES_OUT 0x47 13214825Swollman#define PMC6_DCU_MISS_OUTSTANDING 0x48 13314825Swollman 13414825Swollman/* Instruction Fetch Unit */ 13514825Swollman#define PMC6_IFU_IFETCH 0x80 13614825Swollman#define PMC6_IFU_IFETCH_MISS 0x81 13714825Swollman#define PMC6_ITLB_MISS 0x85 13814825Swollman#define PMC6_IFU_MEM_STALL 0x86 13914825Swollman#define PMC6_ILD_STALL 0x87 14014825Swollman 14114825Swollman/* L2 Cache */ 14214825Swollman#define PMC6_L2_IFETCH 0x28 /* MESI */ 14314825Swollman#define PMC6_L2_LD 0x29 /* MESI */ 14414825Swollman#define PMC6_L2_ST 0x2a /* MESI */ 14514825Swollman#define PMC6_L2_LINES_IN 0x24 14614825Swollman#define PMC6_L2_LINES_OUT 0x26 14714825Swollman#define PMC6_L2_M_LINES_INM 0x25 14814825Swollman#define PMC6_L2_M_LINES_OUTM 0x27 14914825Swollman#define PMC6_L2_RQSTS 0x2e /* MESI */ 15014825Swollman#define PMC6_L2_ADS 0x21 15114825Swollman#define PMC6_L2_DBUS_BUSY 0x22 15214825Swollman#define PMC6_L2_DBUS_BUSY_RD 0x23 15314825Swollman 15414825Swollman/* External Bus Logic */ 15514825Swollman#define PMC6_BUS_DRDY_CLOCKS 0x62 15614825Swollman#define PMC6_BUS_LOCK_CLOCKS 0x63 15714825Swollman#define PMC6_BUS_REQ_OUTSTANDING 0x60 15814825Swollman#define PMC6_BUS_TRAN_BRD 0x65 15914825Swollman#define PMC6_BUS_TRAN_RFO 0x66 16014825Swollman#define PMC6_BUS_TRAN_WB 0x67 16114825Swollman#define PMC6_BUS_TRAN_IFETCH 0x68 16214825Swollman#define PMC6_BUS_TRAN_INVAL 0x69 16314825Swollman#define PMC6_BUS_TRAN_PWR 0x6a 16414825Swollman#define PMC6_BUS_TRAN_P 0x6b 16514825Swollman#define PMC6_BUS_TRAN_IO 0x6c 16614825Swollman#define PMC6_BUS_TRAN_DEF 0x6d 16714825Swollman#define PMC6_BUS_TRAN_BURST 0x6e 16814825Swollman#define PMC6_BUS_TRAN_ANY 0x70 16914825Swollman#define PMC6_BUS_TRAN_MEM 0x6f 17014825Swollman#define PMC6_BUS_DATA_RCV 0x64 17114825Swollman#define PMC6_BUS_BNR_DRV 0x61 17214825Swollman#define PMC6_BUS_HIT_DRV 0x7a 17314825Swollman#define PMC6_BUS_HITM_DRV 0x7b 17414825Swollman#define PMC6_BUS_SNOOP_STALL 0x7e 17514825Swollman 17614825Swollman/* Floating Point Unit */ 17714825Swollman#define PMC6_FLOPS 0xc1 /* counter 0 only */ 17814825Swollman#define PMC6_FP_COMP_OPS_EXE 0x10 /* counter 0 only */ 17914825Swollman#define PMC6_FP_ASSIST 0x11 /* counter 1 only */ 18014825Swollman#define PMC6_MUL 0x12 /* counter 1 only */ 18114825Swollman#define PMC6_DIV 0x13 /* counter 1 only */ 18214825Swollman#define PMC6_CYCLES_DIV_BUSY 0x14 /* counter 0 only */ 18314825Swollman 18414825Swollman/* Memory Ordering */ 18514825Swollman#define PMC6_LD_BLOCKS 0x03 18614825Swollman#define PMC6_SB_DRAINS 0x04 18714825Swollman#define PMC6_MISALIGN_MEM_REF 0x05 18814825Swollman 18914825Swollman/* Instruction Decoding and Retirement */ 19014825Swollman#define PMC6_INST_RETIRED 0xc0 19114825Swollman#define PMC6_UOPS_RETIRED 0xc2 19214825Swollman#define PMC6_INST_DECODER 0xd0 /* (sic) */ 19314825Swollman 19414825Swollman/* Interrupts */ 19514825Swollman#define PMC6_HW_INT_RX 0xc8 19614825Swollman#define PMC6_CYCLES_INT_MASKED 0xc6 19714825Swollman#define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 19814825Swollman 19914825Swollman/* Branches */ 20014825Swollman#define PMC6_BR_INST_RETIRED 0xc4 20114825Swollman#define PMC6_BR_MISS_PRED_RETIRED 0xc5 20214825Swollman#define PMC6_BR_TAKEN_RETIRED 0xc9 20314825Swollman#define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 20414825Swollman#define PMC6_BR_INST_DECODED 0xe0 20514825Swollman#define PMC6_BTB_MISSES 0xe2 20614825Swollman#define PMC6_BR_BOGUS 0xe4 20714825Swollman#define PMC6_BACLEARS 0xe6 20814825Swollman 20914825Swollman/* Stalls */ 21014825Swollman#define PMC6_RESOURCE_STALLS 0xa2 21114825Swollman#define PMC6_PARTIAL_RAT_STALLS 0xd2 21214825Swollman 21314825Swollman/* Segment Register Loads */ 21414825Swollman#define PMC6_SEGMENT_REG_LOADS 0x06 21514825Swollman 21614825Swollman/* Clocks */ 21714825Swollman#define PMC6_CPU_CLK_UNHALTED 0x79 21814825Swollman 21914825Swollman/* 22014825Swollman * Pentium Performance Counters 22114825Swollman * This list comes from the Harvard people, not Intel. 22214825Swollman */ 22314825Swollman#define PMC5_DATA_READ 0 22414825Swollman#define PMC5_DATA_WRITE 1 22514825Swollman#define PMC5_DATA_TLB_MISS 2 22614825Swollman#define PMC5_DATA_READ_MISS 3 22714825Swollman#define PMC5_DATA_WRITE_MISS 4 22814825Swollman#define PMC5_WRITE_M_E 5 22914825Swollman#define PMC5_DATA_LINES_WBACK 6 23014825Swollman#define PMC5_DATA_CACHE_SNOOP 7 23114825Swollman#define PMC5_DATA_CACHE_SNOOP_HIT 8 23214825Swollman#define PMC5_MEM_ACCESS_BOTH 9 23314825Swollman#define PMC5_BANK_CONFLICTS 10 23414825Swollman#define PMC5_MISALIGNED_DATA 11 23514825Swollman#define PMC5_INST_READ 12 23614825Swollman#define PMC5_INST_TLB_MISS 13 23714825Swollman#define PMC5_INST_CACHE_MISS 14 23814825Swollman#define PMC5_SEGMENT_REG_LOAD 15 23914825Swollman#define PMC5_BRANCHES 18 24014825Swollman#define PMC5_BTB_HITS 19 24114825Swollman#define PMC5_BRANCH_TAKEN 20 24214825Swollman#define PMC5_PIPELINE_FLUSH 21 24314825Swollman#define PMC5_INST_EXECUTED 22 24414825Swollman#define PMC5_INST_EXECUTED_V 23 24514825Swollman#define PMC5_BUS_UTILIZATION 24 24614825Swollman#define PMC5_WRITE_BACKUP_STALL 25 24714825Swollman#define PMC5_DATA_READ_STALL 26 24814825Swollman#define PMC5_WRITE_E_M_STALL 27 24914825Swollman#define PMC5_LOCKED_BUS 28 25014825Swollman#define PMC5_IO_CYCLE 29 25114825Swollman#define PMC5_NONCACHE_MEMORY 30 25214825Swollman#define PMC5_ADDR_GEN_INTERLOCK 31 25314825Swollman#define PMC5_FLOPS 34 25414825Swollman#define PMC5_BP0_MATCH 35 25514825Swollman#define PMC5_BP1_MATCH 36 25614825Swollman#define PMC5_BP2_MATCH 37 25714825Swollman#define PMC5_BP3_MATCH 38 25814825Swollman#define PMC5_HW_INTR 39 25914825Swollman#define PMC5_DATA_RW 40 26014825Swollman#define PMC5_DATA_RW_MISS 41 26114825Swollman 26218444Sbde#endif /* !_MACHINE_PERFMON_H_ */ 263