intr_machdep.h revision 255040
113546Sjulian/*- 213546Sjulian * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 313546Sjulian * All rights reserved. 413546Sjulian * 513546Sjulian * Redistribution and use in source and binary forms, with or without 613546Sjulian * modification, are permitted provided that the following conditions 713546Sjulian * are met: 813546Sjulian * 1. Redistributions of source code must retain the above copyright 913546Sjulian * notice, this list of conditions and the following disclaimer. 1013546Sjulian * 2. Redistributions in binary form must reproduce the above copyright 1113546Sjulian * notice, this list of conditions and the following disclaimer in the 1213546Sjulian * documentation and/or other materials provided with the distribution. 1313546Sjulian * 1413546Sjulian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1513546Sjulian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1613546Sjulian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1713546Sjulian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1813546Sjulian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1913546Sjulian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2013546Sjulian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2113546Sjulian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2213546Sjulian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2313546Sjulian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2413546Sjulian * SUCH DAMAGE. 2513546Sjulian * 2613546Sjulian * $FreeBSD: head/sys/i386/include/intr_machdep.h 255040 2013-08-29 19:52:18Z gibbs $ 2713546Sjulian */ 2813546Sjulian 2913546Sjulian#ifndef __MACHINE_INTR_MACHDEP_H__ 3013546Sjulian#define __MACHINE_INTR_MACHDEP_H__ 3113546Sjulian 3213546Sjulian#ifdef _KERNEL 3313546Sjulian 3413546Sjulian/* 3513546Sjulian * The maximum number of I/O interrupts we allow. This number is rather 3613546Sjulian * arbitrary as it is just the maximum IRQ resource value. The interrupt 3713546Sjulian * source for a given IRQ maps that I/O interrupt to device interrupt 3813546Sjulian * source whether it be a pin on an interrupt controller or an MSI interrupt. 3913546Sjulian * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 4013546Sjulian * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 4113546Sjulian * vectors available for device interrupts. On many systems with I/O APICs, 4213546Sjulian * a lot of the IRQs are not used, so this number can be much larger than 4313546Sjulian * 191 and still be safe since only interrupt sources in actual use will 4413546Sjulian * allocate IDT vectors. 4513546Sjulian * 4613546Sjulian * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs. 4713546Sjulian * IRQ values from 256 to 767 are used by MSI. When running under the Xen 4813546Sjulian * Hypervisor, IRQ values from 768 to 4863 are available for binding to 49 * event channel events. We leave 255 unused to avoid confusion since 255 is 50 * used in PCI to indicate an invalid IRQ. 51 */ 52#define NUM_MSI_INTS 512 53#define FIRST_MSI_INT 256 54#ifdef XENHVM 55#include <xen/xen-os.h> 56#define NUM_EVTCHN_INTS NR_EVENT_CHANNELS 57#define FIRST_EVTCHN_INT \ 58 (FIRST_MSI_INT + NUM_MSI_INTS) 59#define LAST_EVTCHN_INT \ 60 (FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1) 61#elif defined(XEN) 62#include <xen/xen-os.h> 63#define NUM_EVTCHN_INTS NR_EVENT_CHANNELS 64#define FIRST_EVTCHN_INT 0 65#define LAST_EVTCHN_INT \ 66 (FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1) 67#else /* !XEN && !XENHVM */ 68#define NUM_EVTCHN_INTS 0 69#endif 70#define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS + NUM_EVTCHN_INTS) 71 72/* 73 * Default base address for MSI messages on x86 platforms. 74 */ 75#define MSI_INTEL_ADDR_BASE 0xfee00000 76 77/* 78 * - 1 ??? dummy counter. 79 * - 2 counters for each I/O interrupt. 80 * - 1 counter for each CPU for lapic timer. 81 * - 9 counters for each CPU for IPI counters for SMP. 82 */ 83#ifdef SMP 84#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 9) * MAXCPU) 85#else 86#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1) 87#endif 88 89#ifndef LOCORE 90 91typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss); 92 93#define IDTVEC(name) __CONCAT(X,name) 94 95struct intsrc; 96 97/* 98 * Methods that a PIC provides to mask/unmask a given interrupt source, 99 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and 100 * return the vector associated with this source. 101 */ 102struct pic { 103 void (*pic_enable_source)(struct intsrc *); 104 void (*pic_disable_source)(struct intsrc *, int); 105 void (*pic_eoi_source)(struct intsrc *); 106 void (*pic_enable_intr)(struct intsrc *); 107 void (*pic_disable_intr)(struct intsrc *); 108 int (*pic_vector)(struct intsrc *); 109 int (*pic_source_pending)(struct intsrc *); 110 void (*pic_suspend)(struct pic *); 111 void (*pic_resume)(struct pic *); 112 int (*pic_config_intr)(struct intsrc *, enum intr_trigger, 113 enum intr_polarity); 114 int (*pic_assign_cpu)(struct intsrc *, u_int apic_id); 115 TAILQ_ENTRY(pic) pics; 116}; 117 118/* Flags for pic_disable_source() */ 119enum { 120 PIC_EOI, 121 PIC_NO_EOI, 122}; 123 124/* 125 * An interrupt source. The upper-layer code uses the PIC methods to 126 * control a given source. The lower-layer PIC drivers can store additional 127 * private data in a given interrupt source such as an interrupt pin number 128 * or an I/O APIC pointer. 129 */ 130struct intsrc { 131 struct pic *is_pic; 132 struct intr_event *is_event; 133 u_long *is_count; 134 u_long *is_straycount; 135 u_int is_index; 136 u_int is_handlers; 137}; 138 139struct trapframe; 140 141extern struct mtx icu_lock; 142extern int elcr_found; 143 144#ifndef DEV_ATPIC 145void atpic_reset(void); 146#endif 147/* XXX: The elcr_* prototypes probably belong somewhere else. */ 148int elcr_probe(void); 149enum intr_trigger elcr_read_trigger(u_int irq); 150void elcr_resume(void); 151void elcr_write_trigger(u_int irq, enum intr_trigger trigger); 152#ifdef SMP 153void intr_add_cpu(u_int cpu); 154#endif 155int intr_add_handler(const char *name, int vector, driver_filter_t filter, 156 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep); 157#ifdef SMP 158int intr_bind(u_int vector, u_char cpu); 159#endif 160int intr_config_intr(int vector, enum intr_trigger trig, 161 enum intr_polarity pol); 162int intr_describe(u_int vector, void *ih, const char *descr); 163void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 164u_int intr_next_cpu(void); 165struct intsrc *intr_lookup_source(int vector); 166int intr_register_pic(struct pic *pic); 167int intr_register_source(struct intsrc *isrc); 168int intr_remove_handler(void *cookie); 169void intr_resume(void); 170void intr_suspend(void); 171void intrcnt_add(const char *name, u_long **countp); 172void nexus_add_irq(u_long irq); 173int msi_alloc(device_t dev, int count, int maxcount, int *irqs); 174void msi_init(void); 175int msi_map(int irq, uint64_t *addr, uint32_t *data); 176int msi_release(int* irqs, int count); 177int msix_alloc(device_t dev, int *irq); 178int msix_release(int irq); 179 180#endif /* !LOCORE */ 181#endif /* _KERNEL */ 182#endif /* !__MACHINE_INTR_MACHDEP_H__ */ 183