1124144Sphk/*- 2124144Sphk * Copyright (c) 2004 John Birrell 3124144Sphk * All rights reserved. 4124144Sphk * 5139788Simp * Redistribution and use in source and binary forms, with or without 6139788Simp * modification, are permitted provided that the following conditions 7139788Simp * are met: 8139788Simp * 1. Redistributions of source code must retain the above copyright 9139788Simp * notice, this list of conditions and the following disclaimer. 10139788Simp * 2. Redistributions in binary form must reproduce the above copyright 11139788Simp * notice, this list of conditions and the following disclaimer in the 12139788Simp * documentation and/or other materials provided with the distribution. 13124144Sphk * 14139788Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15139788Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16139788Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17139788Simp * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18139788Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19139788Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20139788Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21139788Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22139788Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23139788Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24139788Simp * SUCH DAMAGE. 25139788Simp */ 26139788Simp 27139788Simp/* AMD Elan SC520 Memory Mapped Configuration Region (MMCR). 28124144Sphk * 29124144Sphk * The layout of this structure is documented by AMD in the Elan SC520 30124144Sphk * Microcontroller Register Set Manual. The field names match those 31124144Sphk * described in that document. The overall structure size must be 4096 32124144Sphk * bytes. Ignore fields with the 'pad' prefix - they are only present for 33124144Sphk * alignment purposes. 34124144Sphk * 35124144Sphk * $FreeBSD: releng/10.2/sys/i386/include/elan_mmcr.h 139788 2005-01-06 22:05:28Z imp $ 36124144Sphk */ 37124144Sphk 38124144Sphk#ifndef _MACHINE_ELAN_MMCR_H_ 39124144Sphk#define _MACHINE_ELAN_MMCR_H_ 1 40124144Sphk 41124144Sphkstruct elan_mmcr { 42124144Sphk /* CPU */ 43124144Sphk u_int16_t REVID; 44124144Sphk u_int8_t CPUCTL; 45124144Sphk u_int8_t pad_0x003[0xd]; 46124144Sphk 47124144Sphk /* SDRAM Controller */ 48124144Sphk u_int16_t DRCCTL; 49124144Sphk u_int16_t DRCTMCTL; 50124144Sphk u_int16_t DRCCFG; 51124144Sphk u_int16_t DRCBENDADR; 52124144Sphk u_int8_t pad_0x01a[0x6]; 53124144Sphk u_int8_t ECCCTL; 54124144Sphk u_int8_t ECCSTA; 55124144Sphk u_int8_t ECCCKBPOS; 56124144Sphk u_int8_t ECCCKTEST; 57124144Sphk u_int32_t ECCSBADD; 58124144Sphk u_int32_t ECCMBADD; 59124144Sphk u_int8_t pad_0x02c[0x14]; 60124144Sphk 61124144Sphk /* SDRAM Buffer */ 62124144Sphk u_int8_t DBCTL; 63124144Sphk u_int8_t pad_0x041[0xf]; 64124144Sphk 65124144Sphk /* ROM/Flash Controller */ 66124144Sphk u_int16_t BOOTCSCTL; 67124144Sphk u_int8_t pad_0x052[0x2]; 68124144Sphk u_int16_t ROMCS1CTL; 69124144Sphk u_int16_t ROMCS2CTL; 70124144Sphk u_int8_t pad_0x058[0x8]; 71124144Sphk 72124144Sphk /* PCI Bus Host Bridge */ 73124144Sphk u_int16_t HBCTL; 74124144Sphk u_int16_t HBTGTIRQCTL; 75124144Sphk u_int16_t HBTGTIRQSTA; 76124144Sphk u_int16_t HBMSTIRQCTL; 77124144Sphk u_int16_t HBMSTIRQSTA; 78124144Sphk u_int8_t pad_0x06a[0x2]; 79124144Sphk u_int32_t MSTINTADD; 80124144Sphk 81124144Sphk /* System Arbitration */ 82124144Sphk u_int8_t SYSARBCTL; 83124144Sphk u_int8_t PCIARBSTA; 84124144Sphk u_int16_t SYSARBMENB; 85124144Sphk u_int32_t ARBPRICTL; 86124144Sphk u_int8_t pad_0x078[0x8]; 87124144Sphk 88124144Sphk /* System Address Mapping */ 89124144Sphk u_int32_t ADDDECCTL; 90124144Sphk u_int32_t WPVSTA; 91124144Sphk u_int32_t PAR0; 92124144Sphk u_int32_t PAR1; 93124144Sphk u_int32_t PAR2; 94124144Sphk u_int32_t PAR3; 95124144Sphk u_int32_t PAR4; 96124144Sphk u_int32_t PAR5; 97124144Sphk u_int32_t PAR6; 98124144Sphk u_int32_t PAR7; 99124144Sphk u_int32_t PAR8; 100124144Sphk u_int32_t PAR9; 101124144Sphk u_int32_t PAR10; 102124144Sphk u_int32_t PAR11; 103124144Sphk u_int32_t PAR12; 104124144Sphk u_int32_t PAR13; 105124144Sphk u_int32_t PAR14; 106124144Sphk u_int32_t PAR15; 107124144Sphk u_int8_t pad_0x0c8[0xb38]; 108124144Sphk 109124144Sphk /* GP Bus Controller */ 110124144Sphk u_int8_t GPECHO; 111124144Sphk u_int8_t GPCSDW; 112124144Sphk u_int16_t GPCSQUAL; 113124144Sphk u_int8_t pad_0xc04[0x4]; 114124144Sphk u_int8_t GPCSRT; 115124144Sphk u_int8_t GPCSPW; 116124144Sphk u_int8_t GPCSOFF; 117124144Sphk u_int8_t GPRDW; 118124144Sphk u_int8_t GPRDOFF; 119124144Sphk u_int8_t GPWRW; 120124144Sphk u_int8_t GPWROFF; 121124144Sphk u_int8_t GPALEW; 122124144Sphk u_int8_t GPALEOFF; 123124144Sphk u_int8_t pad_0xc11[0xf]; 124124144Sphk 125124144Sphk /* Programmable Input/Output */ 126124144Sphk u_int16_t PIOPFS15_0; 127124144Sphk u_int16_t PIOPFS31_16; 128124144Sphk u_int8_t CSPFS; 129124144Sphk u_int8_t pad_0xc25; 130124144Sphk u_int8_t CLKSEL; 131124144Sphk u_int8_t pad_0xc27; 132124144Sphk u_int16_t DSCTL; 133124144Sphk u_int16_t PIODIR15_0; 134124144Sphk u_int16_t PIODIR31_16; 135124144Sphk u_int8_t pad_0xc2e[0x2]; 136124144Sphk u_int16_t PIODATA15_0; 137124144Sphk u_int16_t PIODATA31_16; 138124144Sphk u_int16_t PIOSET15_0; 139124144Sphk u_int16_t PIOSET31_16; 140124144Sphk u_int16_t PIOCLR15_0; 141124144Sphk u_int16_t PIOCLR31_16; 142124144Sphk u_int8_t pad_0xc3c[0x24]; 143124144Sphk 144124144Sphk /* Software Timer */ 145124144Sphk u_int16_t SWTMRMILLI; 146124144Sphk u_int16_t SWTMRMICRO; 147124144Sphk u_int8_t SWTMRCFG; 148124144Sphk u_int8_t pad_0xc65[0xb]; 149124144Sphk 150124144Sphk /* General-Purpose Timers */ 151124144Sphk u_int8_t GPTMRSTA; 152124144Sphk u_int8_t pad_0xc71; 153124144Sphk u_int16_t GPTMR0CTL; 154124144Sphk u_int16_t GPTMR0CNT; 155124144Sphk u_int16_t GPTMR0MAXCMPA; 156124144Sphk u_int16_t GPTMR0MAXCMPB; 157124144Sphk u_int16_t GPTMR1CTL; 158124144Sphk u_int16_t GPTMR1CNT; 159124144Sphk u_int16_t GPTMR1MAXCMPA; 160124144Sphk u_int16_t GPTMR1MAXCMPB; 161124144Sphk u_int16_t GPTMR2CTL; 162124144Sphk u_int16_t GPTMR2CNT; 163124144Sphk u_int8_t pad_0xc86[0x8]; 164124144Sphk u_int16_t GPTMR2MAXCMPA; 165124144Sphk u_int8_t pad_0xc90[0x20]; 166124144Sphk 167124144Sphk /* Watchdog Timer */ 168124144Sphk u_int16_t WDTMRCTL; 169124144Sphk u_int16_t WDTMRCNTL; 170124144Sphk u_int16_t WDTMRCNTH; 171124144Sphk u_int8_t pad_0xcb6[0xa]; 172124144Sphk 173124144Sphk /* UART Serial Ports */ 174124144Sphk u_int8_t UART1CTL; 175124144Sphk u_int8_t UART1STA; 176124144Sphk u_int8_t UART1FCRSHAD; 177124144Sphk u_int8_t pad_0xcc3; 178124144Sphk u_int8_t UART2CTL; 179124144Sphk u_int8_t UART2STA; 180124144Sphk u_int8_t UART2FCRSHAD; 181124144Sphk u_int8_t pad_0xcc7[0x9]; 182124144Sphk 183124144Sphk /* Synchronous Serial Interface */ 184124144Sphk u_int8_t SSICTL; 185124144Sphk u_int8_t SSIXMIT; 186124144Sphk u_int8_t SSICMD; 187124144Sphk u_int8_t SSISTA; 188124144Sphk u_int8_t SSIRCV; 189124144Sphk u_int8_t pad_0xcd5[0x2b]; 190124144Sphk 191124144Sphk /* Programmable Interrupt Controller */ 192124144Sphk u_int8_t PICICR; 193124144Sphk u_int8_t pad_0xd01; 194124144Sphk u_int8_t MPICMODE; 195124144Sphk u_int8_t SL1PICMODE; 196124144Sphk u_int8_t SL2PICMODE; 197124144Sphk u_int8_t pad_0xd05[0x3]; 198124144Sphk u_int16_t SWINT16_1; 199124144Sphk u_int8_t SWINT22_17; 200124144Sphk u_int8_t pad_0xd0b[0x5]; 201124144Sphk u_int16_t INTPINPOL; 202124144Sphk u_int8_t pad_0xd12[0x2]; 203124144Sphk u_int16_t PCIHOSTMAP; 204124144Sphk u_int8_t pad_0xd16[0x2]; 205124144Sphk u_int16_t ECCMAP; 206124144Sphk u_int8_t GPTMR0MAP; 207124144Sphk u_int8_t GPTMR1MAP; 208124144Sphk u_int8_t GPTMR2MAP; 209124144Sphk u_int8_t pad_0xd1d[0x3]; 210124144Sphk u_int8_t PIT0MAP; 211124144Sphk u_int8_t PIT1MAP; 212124144Sphk u_int8_t PIT2MAP; 213124144Sphk u_int8_t pad_0xd23[0x5]; 214124144Sphk u_int8_t UART1MAP; 215124144Sphk u_int8_t UART2MAP; 216124144Sphk u_int8_t pad_0xd2a[0x6]; 217124144Sphk u_int8_t PCIINTAMAP; 218124144Sphk u_int8_t PCIINTBMAP; 219124144Sphk u_int8_t PCIINTCMAP; 220124144Sphk u_int8_t PCIINTDMAP; 221124144Sphk u_int8_t pad_0xd34[0xc]; 222124144Sphk u_int8_t DMABCINTMAP; 223124144Sphk u_int8_t SSIMAP; 224124144Sphk u_int8_t WDTMAP; 225124144Sphk u_int8_t RTCMAP; 226124144Sphk u_int8_t WPVMAP; 227124144Sphk u_int8_t ICEMAP; 228124144Sphk u_int8_t FERRMAP; 229124144Sphk u_int8_t pad_0xd47[0x9]; 230124144Sphk u_int8_t GP0IMAP; 231124144Sphk u_int8_t GP1IMAP; 232124144Sphk u_int8_t GP2IMAP; 233124144Sphk u_int8_t GP3IMAP; 234124144Sphk u_int8_t GP4IMAP; 235124144Sphk u_int8_t GP5IMAP; 236124144Sphk u_int8_t GP6IMAP; 237124144Sphk u_int8_t GP7IMAP; 238124144Sphk u_int8_t GP8IMAP; 239124144Sphk u_int8_t GP9IMAP; 240124144Sphk u_int8_t GP10IMAP; 241124144Sphk u_int8_t pad_0xd5b[0x15]; 242124144Sphk 243124144Sphk /* Reset Generation */ 244124144Sphk u_int8_t SYSINFO; 245124144Sphk u_int8_t pad_0xd71; 246124144Sphk u_int8_t RESCFG; 247124144Sphk u_int8_t pad_0xd73; 248124144Sphk u_int8_t RESSTA; 249124144Sphk u_int8_t pad_0xd75[0xb]; 250124144Sphk 251124144Sphk /* GP DMA Controller */ 252124144Sphk u_int8_t GPDMACTL; 253124144Sphk u_int8_t GPDMAMMIO; 254124144Sphk u_int16_t GPDMAEXTCHMAPA; 255124144Sphk u_int16_t GPDMAEXTCHMAPB; 256124144Sphk u_int8_t GPDMAEXTPG0; 257124144Sphk u_int8_t GPDMAEXTPG1; 258124144Sphk u_int8_t GPDMAEXTPG2; 259124144Sphk u_int8_t GPDMAEXTPG3; 260124144Sphk u_int8_t GPDMAEXTPG5; 261124144Sphk u_int8_t GPDMAEXTPG6; 262124144Sphk u_int8_t GPDMAEXTPG7; 263124144Sphk u_int8_t pad_0xd8d[0x3]; 264124144Sphk u_int8_t GPDMAEXTTC3; 265124144Sphk u_int8_t GPDMAEXTTC5; 266124144Sphk u_int8_t GPDMAEXTTC6; 267124144Sphk u_int8_t GPDMAEXTTC7; 268124144Sphk u_int8_t pad_0xd94[0x4]; 269124144Sphk u_int8_t GPDMABCCTL; 270124144Sphk u_int8_t GPDMABCSTA; 271124144Sphk u_int8_t GPDMABSINTENB; 272124144Sphk u_int8_t GPDMABCVAL; 273124144Sphk u_int8_t pad_0xd9c[0x4]; 274124144Sphk u_int16_t GPDMANXTADDL3; 275124144Sphk u_int16_t GPDMANXTADDH3; 276124144Sphk u_int16_t GPDMANXTADDL5; 277124144Sphk u_int16_t GPDMANXTADDH5; 278124144Sphk u_int16_t GPDMANXTADDL6; 279124144Sphk u_int16_t GPDMANXTADDH6; 280124144Sphk u_int16_t GPDMANXTADDL7; 281124144Sphk u_int16_t GPDMANXTADDH7; 282124144Sphk u_int16_t GPDMANXTTCL3; 283124144Sphk u_int8_t GPDMANXTTCH3; 284124144Sphk u_int8_t pad_0xdb3; 285124144Sphk u_int16_t GPDMANXTTCL5; 286124144Sphk u_int8_t GPDMANXTTCH5; 287124144Sphk u_int8_t pad_0xdb7; 288124144Sphk u_int16_t GPDMANXTTCL6; 289124144Sphk u_int8_t GPDMANXTTCH6; 290124144Sphk u_int8_t pad_0xdbb; 291124144Sphk u_int16_t GPDMANXTTCL7; 292124144Sphk u_int8_t GPDMANXTTCH7; 293124144Sphk u_int8_t pad_0xdc0[0x240]; 294124144Sphk }; 295124144Sphk 296124144SphkCTASSERT(sizeof(struct elan_mmcr) == 4096); 297124144Sphk 298124144Sphkextern volatile struct elan_mmcr * elan_mmcr; 299124144Sphk 300124144Sphk#endif /* _MACHINE_ELAN_MMCR_H_ */ 301