1270866Simp/* 2270866Simp * This header provides constants for binding nvidia,tegra30-car. 3270866Simp * 4270866Simp * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 5270866Simp * registers. These IDs often match those in the CAR's RST_DEVICES registers, 6270866Simp * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 7270866Simp * this case, those clocks are assigned IDs above 160 in order to highlight 8270866Simp * this issue. Implementations that interpret these clock IDs as bit values 9270866Simp * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 10270866Simp * explicitly handle these special cases. 11270866Simp * 12270866Simp * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 13270866Simp * above. 14270866Simp */ 15270866Simp 16270866Simp#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 17270866Simp#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 18270866Simp 19270866Simp#define TEGRA30_CLK_CPU 0 20270866Simp/* 1 */ 21270866Simp/* 2 */ 22270866Simp/* 3 */ 23270866Simp#define TEGRA30_CLK_RTC 4 24270866Simp#define TEGRA30_CLK_TIMER 5 25270866Simp#define TEGRA30_CLK_UARTA 6 26270866Simp/* 7 (register bit affects uartb and vfir) */ 27270866Simp#define TEGRA30_CLK_GPIO 8 28270866Simp#define TEGRA30_CLK_SDMMC2 9 29270866Simp/* 10 (register bit affects spdif_in and spdif_out) */ 30270866Simp#define TEGRA30_CLK_I2S1 11 31270866Simp#define TEGRA30_CLK_I2C1 12 32270866Simp#define TEGRA30_CLK_NDFLASH 13 33270866Simp#define TEGRA30_CLK_SDMMC1 14 34270866Simp#define TEGRA30_CLK_SDMMC4 15 35270866Simp/* 16 */ 36270866Simp#define TEGRA30_CLK_PWM 17 37270866Simp#define TEGRA30_CLK_I2S2 18 38270866Simp#define TEGRA30_CLK_EPP 19 39270866Simp/* 20 (register bit affects vi and vi_sensor) */ 40270866Simp#define TEGRA30_CLK_GR2D 21 41270866Simp#define TEGRA30_CLK_USBD 22 42270866Simp#define TEGRA30_CLK_ISP 23 43270866Simp#define TEGRA30_CLK_GR3D 24 44270866Simp/* 25 */ 45270866Simp#define TEGRA30_CLK_DISP2 26 46270866Simp#define TEGRA30_CLK_DISP1 27 47270866Simp#define TEGRA30_CLK_HOST1X 28 48270866Simp#define TEGRA30_CLK_VCP 29 49270866Simp#define TEGRA30_CLK_I2S0 30 50270866Simp#define TEGRA30_CLK_COP_CACHE 31 51270866Simp 52270866Simp#define TEGRA30_CLK_MC 32 53270866Simp#define TEGRA30_CLK_AHBDMA 33 54270866Simp#define TEGRA30_CLK_APBDMA 34 55270866Simp/* 35 */ 56270866Simp#define TEGRA30_CLK_KBC 36 57270866Simp#define TEGRA30_CLK_STATMON 37 58270866Simp#define TEGRA30_CLK_PMC 38 59270866Simp/* 39 (register bit affects fuse and fuse_burn) */ 60270866Simp#define TEGRA30_CLK_KFUSE 40 61270866Simp#define TEGRA30_CLK_SBC1 41 62270866Simp#define TEGRA30_CLK_NOR 42 63270866Simp/* 43 */ 64270866Simp#define TEGRA30_CLK_SBC2 44 65270866Simp/* 45 */ 66270866Simp#define TEGRA30_CLK_SBC3 46 67270866Simp#define TEGRA30_CLK_I2C5 47 68270866Simp#define TEGRA30_CLK_DSIA 48 69270866Simp/* 49 (register bit affects cve and tvo) */ 70270866Simp#define TEGRA30_CLK_MIPI 50 71270866Simp#define TEGRA30_CLK_HDMI 51 72270866Simp#define TEGRA30_CLK_CSI 52 73270866Simp#define TEGRA30_CLK_TVDAC 53 74270866Simp#define TEGRA30_CLK_I2C2 54 75270866Simp#define TEGRA30_CLK_UARTC 55 76270866Simp/* 56 */ 77270866Simp#define TEGRA30_CLK_EMC 57 78270866Simp#define TEGRA30_CLK_USB2 58 79270866Simp#define TEGRA30_CLK_USB3 59 80270866Simp#define TEGRA30_CLK_MPE 60 81270866Simp#define TEGRA30_CLK_VDE 61 82270866Simp#define TEGRA30_CLK_BSEA 62 83270866Simp#define TEGRA30_CLK_BSEV 63 84270866Simp 85270866Simp#define TEGRA30_CLK_SPEEDO 64 86270866Simp#define TEGRA30_CLK_UARTD 65 87270866Simp#define TEGRA30_CLK_UARTE 66 88270866Simp#define TEGRA30_CLK_I2C3 67 89270866Simp#define TEGRA30_CLK_SBC4 68 90270866Simp#define TEGRA30_CLK_SDMMC3 69 91270866Simp#define TEGRA30_CLK_PCIE 70 92270866Simp#define TEGRA30_CLK_OWR 71 93270866Simp#define TEGRA30_CLK_AFI 72 94270866Simp#define TEGRA30_CLK_CSITE 73 95270866Simp/* 74 */ 96270866Simp#define TEGRA30_CLK_AVPUCQ 75 97270866Simp#define TEGRA30_CLK_LA 76 98270866Simp/* 77 */ 99270866Simp/* 78 */ 100270866Simp#define TEGRA30_CLK_DTV 79 101270866Simp#define TEGRA30_CLK_NDSPEED 80 102270866Simp#define TEGRA30_CLK_I2CSLOW 81 103270866Simp#define TEGRA30_CLK_DSIB 82 104270866Simp/* 83 */ 105270866Simp#define TEGRA30_CLK_IRAMA 84 106270866Simp#define TEGRA30_CLK_IRAMB 85 107270866Simp#define TEGRA30_CLK_IRAMC 86 108270866Simp#define TEGRA30_CLK_IRAMD 87 109270866Simp#define TEGRA30_CLK_CRAM2 88 110270866Simp/* 89 */ 111270866Simp#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ 112270866Simp/* 91 */ 113270866Simp#define TEGRA30_CLK_CSUS 92 114270866Simp#define TEGRA30_CLK_CDEV2 93 115270866Simp#define TEGRA30_CLK_CDEV1 94 116270866Simp/* 95 */ 117270866Simp 118270866Simp#define TEGRA30_CLK_CPU_G 96 119270866Simp#define TEGRA30_CLK_CPU_LP 97 120270866Simp#define TEGRA30_CLK_GR3D2 98 121270866Simp#define TEGRA30_CLK_MSELECT 99 122270866Simp#define TEGRA30_CLK_TSENSOR 100 123270866Simp#define TEGRA30_CLK_I2S3 101 124270866Simp#define TEGRA30_CLK_I2S4 102 125270866Simp#define TEGRA30_CLK_I2C4 103 126270866Simp#define TEGRA30_CLK_SBC5 104 127270866Simp#define TEGRA30_CLK_SBC6 105 128270866Simp#define TEGRA30_CLK_D_AUDIO 106 129270866Simp#define TEGRA30_CLK_APBIF 107 130270866Simp#define TEGRA30_CLK_DAM0 108 131270866Simp#define TEGRA30_CLK_DAM1 109 132270866Simp#define TEGRA30_CLK_DAM2 110 133270866Simp#define TEGRA30_CLK_HDA2CODEC_2X 111 134270866Simp#define TEGRA30_CLK_ATOMICS 112 135270866Simp#define TEGRA30_CLK_AUDIO0_2X 113 136270866Simp#define TEGRA30_CLK_AUDIO1_2X 114 137270866Simp#define TEGRA30_CLK_AUDIO2_2X 115 138270866Simp#define TEGRA30_CLK_AUDIO3_2X 116 139270866Simp#define TEGRA30_CLK_AUDIO4_2X 117 140270866Simp#define TEGRA30_CLK_SPDIF_2X 118 141270866Simp#define TEGRA30_CLK_ACTMON 119 142270866Simp#define TEGRA30_CLK_EXTERN1 120 143270866Simp#define TEGRA30_CLK_EXTERN2 121 144270866Simp#define TEGRA30_CLK_EXTERN3 122 145270866Simp#define TEGRA30_CLK_SATA_OOB 123 146270866Simp#define TEGRA30_CLK_SATA 124 147270866Simp#define TEGRA30_CLK_HDA 125 148270866Simp/* 126 */ 149270866Simp#define TEGRA30_CLK_SE 127 150270866Simp 151270866Simp#define TEGRA30_CLK_HDA2HDMI 128 152270866Simp#define TEGRA30_CLK_SATA_COLD 129 153270866Simp/* 130 */ 154270866Simp/* 131 */ 155270866Simp/* 132 */ 156270866Simp/* 133 */ 157270866Simp/* 134 */ 158270866Simp/* 135 */ 159270866Simp/* 136 */ 160270866Simp/* 137 */ 161270866Simp/* 138 */ 162270866Simp/* 139 */ 163270866Simp/* 140 */ 164270866Simp/* 141 */ 165270866Simp/* 142 */ 166270866Simp/* 143 */ 167270866Simp/* 144 */ 168270866Simp/* 145 */ 169270866Simp/* 146 */ 170270866Simp/* 147 */ 171270866Simp/* 148 */ 172270866Simp/* 149 */ 173270866Simp/* 150 */ 174270866Simp/* 151 */ 175270866Simp/* 152 */ 176270866Simp/* 153 */ 177270866Simp/* 154 */ 178270866Simp/* 155 */ 179270866Simp/* 156 */ 180270866Simp/* 157 */ 181270866Simp/* 158 */ 182270866Simp/* 159 */ 183270866Simp 184270866Simp#define TEGRA30_CLK_UARTB 160 185270866Simp#define TEGRA30_CLK_VFIR 161 186270866Simp#define TEGRA30_CLK_SPDIF_IN 162 187270866Simp#define TEGRA30_CLK_SPDIF_OUT 163 188270866Simp#define TEGRA30_CLK_VI 164 189270866Simp#define TEGRA30_CLK_VI_SENSOR 165 190270866Simp#define TEGRA30_CLK_FUSE 166 191270866Simp#define TEGRA30_CLK_FUSE_BURN 167 192270866Simp#define TEGRA30_CLK_CVE 168 193270866Simp#define TEGRA30_CLK_TVO 169 194270866Simp#define TEGRA30_CLK_CLK_32K 170 195270866Simp#define TEGRA30_CLK_CLK_M 171 196270866Simp#define TEGRA30_CLK_CLK_M_DIV2 172 197270866Simp#define TEGRA30_CLK_CLK_M_DIV4 173 198270866Simp#define TEGRA30_CLK_PLL_REF 174 199270866Simp#define TEGRA30_CLK_PLL_C 175 200270866Simp#define TEGRA30_CLK_PLL_C_OUT1 176 201270866Simp#define TEGRA30_CLK_PLL_M 177 202270866Simp#define TEGRA30_CLK_PLL_M_OUT1 178 203270866Simp#define TEGRA30_CLK_PLL_P 179 204270866Simp#define TEGRA30_CLK_PLL_P_OUT1 180 205270866Simp#define TEGRA30_CLK_PLL_P_OUT2 181 206270866Simp#define TEGRA30_CLK_PLL_P_OUT3 182 207270866Simp#define TEGRA30_CLK_PLL_P_OUT4 183 208270866Simp#define TEGRA30_CLK_PLL_A 184 209270866Simp#define TEGRA30_CLK_PLL_A_OUT0 185 210270866Simp#define TEGRA30_CLK_PLL_D 186 211270866Simp#define TEGRA30_CLK_PLL_D_OUT0 187 212270866Simp#define TEGRA30_CLK_PLL_D2 188 213270866Simp#define TEGRA30_CLK_PLL_D2_OUT0 189 214270866Simp#define TEGRA30_CLK_PLL_U 190 215270866Simp#define TEGRA30_CLK_PLL_X 191 216270866Simp 217270866Simp#define TEGRA30_CLK_PLL_X_OUT0 192 218270866Simp#define TEGRA30_CLK_PLL_E 193 219270866Simp#define TEGRA30_CLK_SPDIF_IN_SYNC 194 220270866Simp#define TEGRA30_CLK_I2S0_SYNC 195 221270866Simp#define TEGRA30_CLK_I2S1_SYNC 196 222270866Simp#define TEGRA30_CLK_I2S2_SYNC 197 223270866Simp#define TEGRA30_CLK_I2S3_SYNC 198 224270866Simp#define TEGRA30_CLK_I2S4_SYNC 199 225270866Simp#define TEGRA30_CLK_VIMCLK_SYNC 200 226270866Simp#define TEGRA30_CLK_AUDIO0 201 227270866Simp#define TEGRA30_CLK_AUDIO1 202 228270866Simp#define TEGRA30_CLK_AUDIO2 203 229270866Simp#define TEGRA30_CLK_AUDIO3 204 230270866Simp#define TEGRA30_CLK_AUDIO4 205 231270866Simp#define TEGRA30_CLK_SPDIF 206 232270866Simp#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ 233270866Simp#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ 234270866Simp#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ 235270866Simp#define TEGRA30_CLK_SCLK 210 236270866Simp#define TEGRA30_CLK_BLINK 211 237270866Simp#define TEGRA30_CLK_CCLK_G 212 238270866Simp#define TEGRA30_CLK_CCLK_LP 213 239270866Simp#define TEGRA30_CLK_TWD 214 240270866Simp#define TEGRA30_CLK_CML0 215 241270866Simp#define TEGRA30_CLK_CML1 216 242270866Simp#define TEGRA30_CLK_HCLK 217 243270866Simp#define TEGRA30_CLK_PCLK 218 244270866Simp/* 219 */ 245270866Simp/* 220 */ 246270866Simp/* 221 */ 247270866Simp/* 222 */ 248270866Simp/* 223 */ 249270866Simp 250270866Simp/* 288 */ 251270866Simp/* 289 */ 252270866Simp/* 290 */ 253270866Simp/* 291 */ 254270866Simp/* 292 */ 255270866Simp/* 293 */ 256270866Simp/* 294 */ 257270866Simp/* 295 */ 258270866Simp/* 296 */ 259270866Simp/* 297 */ 260270866Simp/* 298 */ 261270866Simp/* 299 */ 262270866Simp#define TEGRA30_CLK_CLK_OUT_1_MUX 300 263270866Simp#define TEGRA30_CLK_CLK_OUT_2_MUX 301 264270866Simp#define TEGRA30_CLK_CLK_OUT_3_MUX 302 265270866Simp#define TEGRA30_CLK_AUDIO0_MUX 303 266270866Simp#define TEGRA30_CLK_AUDIO1_MUX 304 267270866Simp#define TEGRA30_CLK_AUDIO2_MUX 305 268270866Simp#define TEGRA30_CLK_AUDIO3_MUX 306 269270866Simp#define TEGRA30_CLK_AUDIO4_MUX 307 270270866Simp#define TEGRA30_CLK_SPDIF_MUX 308 271270866Simp#define TEGRA30_CLK_CLK_MAX 309 272270866Simp 273270866Simp#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ 274270866Simp