1262569Simp/* 2262569Simp * This header provides constants for binding nvidia,tegra114-car. 3262569Simp * 4262569Simp * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 5262569Simp * registers. These IDs often match those in the CAR's RST_DEVICES registers, 6262569Simp * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 7262569Simp * this case, those clocks are assigned IDs above 160 in order to highlight 8262569Simp * this issue. Implementations that interpret these clock IDs as bit values 9262569Simp * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 10262569Simp * explicitly handle these special cases. 11262569Simp * 12262569Simp * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 13262569Simp * above. 14262569Simp */ 15262569Simp 16262569Simp#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H 17262569Simp#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H 18262569Simp 19262569Simp/* 0 */ 20262569Simp/* 1 */ 21262569Simp/* 2 */ 22262569Simp/* 3 */ 23262569Simp#define TEGRA114_CLK_RTC 4 24262569Simp#define TEGRA114_CLK_TIMER 5 25262569Simp#define TEGRA114_CLK_UARTA 6 26262569Simp/* 7 (register bit affects uartb and vfir) */ 27262569Simp/* 8 */ 28262569Simp#define TEGRA114_CLK_SDMMC2 9 29262569Simp/* 10 (register bit affects spdif_in and spdif_out) */ 30262569Simp#define TEGRA114_CLK_I2S1 11 31262569Simp#define TEGRA114_CLK_I2C1 12 32262569Simp#define TEGRA114_CLK_NDFLASH 13 33262569Simp#define TEGRA114_CLK_SDMMC1 14 34262569Simp#define TEGRA114_CLK_SDMMC4 15 35262569Simp/* 16 */ 36262569Simp#define TEGRA114_CLK_PWM 17 37262569Simp#define TEGRA114_CLK_I2S2 18 38262569Simp#define TEGRA114_CLK_EPP 19 39262569Simp/* 20 (register bit affects vi and vi_sensor) */ 40262569Simp#define TEGRA114_CLK_GR2D 21 41262569Simp#define TEGRA114_CLK_USBD 22 42262569Simp#define TEGRA114_CLK_ISP 23 43262569Simp#define TEGRA114_CLK_GR3D 24 44262569Simp/* 25 */ 45262569Simp#define TEGRA114_CLK_DISP2 26 46262569Simp#define TEGRA114_CLK_DISP1 27 47262569Simp#define TEGRA114_CLK_HOST1X 28 48262569Simp#define TEGRA114_CLK_VCP 29 49262569Simp#define TEGRA114_CLK_I2S0 30 50262569Simp/* 31 */ 51262569Simp 52284090Sian#define TEGRA114_CLK_MC 32 53262569Simp/* 33 */ 54262569Simp#define TEGRA114_CLK_APBDMA 34 55262569Simp/* 35 */ 56262569Simp#define TEGRA114_CLK_KBC 36 57262569Simp/* 37 */ 58262569Simp/* 38 */ 59262569Simp/* 39 (register bit affects fuse and fuse_burn) */ 60262569Simp#define TEGRA114_CLK_KFUSE 40 61262569Simp#define TEGRA114_CLK_SBC1 41 62262569Simp#define TEGRA114_CLK_NOR 42 63262569Simp/* 43 */ 64262569Simp#define TEGRA114_CLK_SBC2 44 65262569Simp/* 45 */ 66262569Simp#define TEGRA114_CLK_SBC3 46 67262569Simp#define TEGRA114_CLK_I2C5 47 68262569Simp#define TEGRA114_CLK_DSIA 48 69262569Simp/* 49 */ 70262569Simp#define TEGRA114_CLK_MIPI 50 71262569Simp#define TEGRA114_CLK_HDMI 51 72262569Simp#define TEGRA114_CLK_CSI 52 73262569Simp/* 53 */ 74262569Simp#define TEGRA114_CLK_I2C2 54 75262569Simp#define TEGRA114_CLK_UARTC 55 76262569Simp#define TEGRA114_CLK_MIPI_CAL 56 77262569Simp#define TEGRA114_CLK_EMC 57 78262569Simp#define TEGRA114_CLK_USB2 58 79262569Simp#define TEGRA114_CLK_USB3 59 80262569Simp/* 60 */ 81262569Simp#define TEGRA114_CLK_VDE 61 82262569Simp#define TEGRA114_CLK_BSEA 62 83262569Simp#define TEGRA114_CLK_BSEV 63 84262569Simp 85262569Simp/* 64 */ 86262569Simp#define TEGRA114_CLK_UARTD 65 87262569Simp/* 66 */ 88262569Simp#define TEGRA114_CLK_I2C3 67 89262569Simp#define TEGRA114_CLK_SBC4 68 90262569Simp#define TEGRA114_CLK_SDMMC3 69 91262569Simp/* 70 */ 92262569Simp#define TEGRA114_CLK_OWR 71 93262569Simp/* 72 */ 94262569Simp#define TEGRA114_CLK_CSITE 73 95262569Simp/* 74 */ 96262569Simp/* 75 */ 97262569Simp#define TEGRA114_CLK_LA 76 98262569Simp#define TEGRA114_CLK_TRACE 77 99262569Simp#define TEGRA114_CLK_SOC_THERM 78 100262569Simp#define TEGRA114_CLK_DTV 79 101262569Simp#define TEGRA114_CLK_NDSPEED 80 102262569Simp#define TEGRA114_CLK_I2CSLOW 81 103262569Simp#define TEGRA114_CLK_DSIB 82 104262569Simp#define TEGRA114_CLK_TSEC 83 105262569Simp/* 84 */ 106262569Simp/* 85 */ 107262569Simp/* 86 */ 108262569Simp/* 87 */ 109262569Simp/* 88 */ 110262569Simp#define TEGRA114_CLK_XUSB_HOST 89 111262569Simp/* 90 */ 112262569Simp#define TEGRA114_CLK_MSENC 91 113262569Simp#define TEGRA114_CLK_CSUS 92 114262569Simp/* 93 */ 115262569Simp/* 94 */ 116262569Simp/* 95 (bit affects xusb_dev and xusb_dev_src) */ 117262569Simp 118262569Simp/* 96 */ 119262569Simp/* 97 */ 120262569Simp/* 98 */ 121262569Simp#define TEGRA114_CLK_MSELECT 99 122262569Simp#define TEGRA114_CLK_TSENSOR 100 123262569Simp#define TEGRA114_CLK_I2S3 101 124262569Simp#define TEGRA114_CLK_I2S4 102 125262569Simp#define TEGRA114_CLK_I2C4 103 126262569Simp#define TEGRA114_CLK_SBC5 104 127262569Simp#define TEGRA114_CLK_SBC6 105 128262569Simp#define TEGRA114_CLK_D_AUDIO 106 129262569Simp#define TEGRA114_CLK_APBIF 107 130262569Simp#define TEGRA114_CLK_DAM0 108 131262569Simp#define TEGRA114_CLK_DAM1 109 132262569Simp#define TEGRA114_CLK_DAM2 110 133262569Simp#define TEGRA114_CLK_HDA2CODEC_2X 111 134262569Simp/* 112 */ 135262569Simp#define TEGRA114_CLK_AUDIO0_2X 113 136262569Simp#define TEGRA114_CLK_AUDIO1_2X 114 137262569Simp#define TEGRA114_CLK_AUDIO2_2X 115 138262569Simp#define TEGRA114_CLK_AUDIO3_2X 116 139262569Simp#define TEGRA114_CLK_AUDIO4_2X 117 140262569Simp#define TEGRA114_CLK_SPDIF_2X 118 141262569Simp#define TEGRA114_CLK_ACTMON 119 142262569Simp#define TEGRA114_CLK_EXTERN1 120 143262569Simp#define TEGRA114_CLK_EXTERN2 121 144262569Simp#define TEGRA114_CLK_EXTERN3 122 145262569Simp/* 123 */ 146262569Simp/* 124 */ 147262569Simp#define TEGRA114_CLK_HDA 125 148262569Simp/* 126 */ 149262569Simp#define TEGRA114_CLK_SE 127 150262569Simp 151262569Simp#define TEGRA114_CLK_HDA2HDMI 128 152262569Simp/* 129 */ 153262569Simp/* 130 */ 154262569Simp/* 131 */ 155262569Simp/* 132 */ 156262569Simp/* 133 */ 157262569Simp/* 134 */ 158262569Simp/* 135 */ 159262569Simp/* 136 */ 160262569Simp/* 137 */ 161262569Simp/* 138 */ 162262569Simp/* 139 */ 163262569Simp/* 140 */ 164262569Simp/* 141 */ 165262569Simp/* 142 */ 166262569Simp/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ 167262569Simp/* xusb_host_src and xusb_ss_src) */ 168262569Simp#define TEGRA114_CLK_CILAB 144 169262569Simp#define TEGRA114_CLK_CILCD 145 170262569Simp#define TEGRA114_CLK_CILE 146 171262569Simp#define TEGRA114_CLK_DSIALP 147 172262569Simp#define TEGRA114_CLK_DSIBLP 148 173262569Simp/* 149 */ 174262569Simp#define TEGRA114_CLK_DDS 150 175262569Simp/* 151 */ 176262569Simp#define TEGRA114_CLK_DP2 152 177262569Simp#define TEGRA114_CLK_AMX 153 178262569Simp#define TEGRA114_CLK_ADX 154 179262569Simp/* 155 (bit affects dfll_ref and dfll_soc) */ 180262569Simp#define TEGRA114_CLK_XUSB_SS 156 181262569Simp/* 157 */ 182262569Simp/* 158 */ 183262569Simp/* 159 */ 184262569Simp 185262569Simp/* 160 */ 186262569Simp/* 161 */ 187262569Simp/* 162 */ 188262569Simp/* 163 */ 189262569Simp/* 164 */ 190262569Simp/* 165 */ 191262569Simp/* 166 */ 192262569Simp/* 167 */ 193262569Simp/* 168 */ 194262569Simp/* 169 */ 195262569Simp/* 170 */ 196262569Simp/* 171 */ 197262569Simp/* 172 */ 198262569Simp/* 173 */ 199262569Simp/* 174 */ 200262569Simp/* 175 */ 201262569Simp/* 176 */ 202262569Simp/* 177 */ 203262569Simp/* 178 */ 204262569Simp/* 179 */ 205262569Simp/* 180 */ 206262569Simp/* 181 */ 207262569Simp/* 182 */ 208262569Simp/* 183 */ 209262569Simp/* 184 */ 210262569Simp/* 185 */ 211262569Simp/* 186 */ 212262569Simp/* 187 */ 213262569Simp/* 188 */ 214262569Simp/* 189 */ 215262569Simp/* 190 */ 216262569Simp/* 191 */ 217262569Simp 218262569Simp#define TEGRA114_CLK_UARTB 192 219262569Simp#define TEGRA114_CLK_VFIR 193 220262569Simp#define TEGRA114_CLK_SPDIF_IN 194 221262569Simp#define TEGRA114_CLK_SPDIF_OUT 195 222262569Simp#define TEGRA114_CLK_VI 196 223262569Simp#define TEGRA114_CLK_VI_SENSOR 197 224262569Simp#define TEGRA114_CLK_FUSE 198 225262569Simp#define TEGRA114_CLK_FUSE_BURN 199 226262569Simp#define TEGRA114_CLK_CLK_32K 200 227262569Simp#define TEGRA114_CLK_CLK_M 201 228262569Simp#define TEGRA114_CLK_CLK_M_DIV2 202 229262569Simp#define TEGRA114_CLK_CLK_M_DIV4 203 230262569Simp#define TEGRA114_CLK_PLL_REF 204 231262569Simp#define TEGRA114_CLK_PLL_C 205 232262569Simp#define TEGRA114_CLK_PLL_C_OUT1 206 233262569Simp#define TEGRA114_CLK_PLL_C2 207 234262569Simp#define TEGRA114_CLK_PLL_C3 208 235262569Simp#define TEGRA114_CLK_PLL_M 209 236262569Simp#define TEGRA114_CLK_PLL_M_OUT1 210 237262569Simp#define TEGRA114_CLK_PLL_P 211 238262569Simp#define TEGRA114_CLK_PLL_P_OUT1 212 239262569Simp#define TEGRA114_CLK_PLL_P_OUT2 213 240262569Simp#define TEGRA114_CLK_PLL_P_OUT3 214 241262569Simp#define TEGRA114_CLK_PLL_P_OUT4 215 242262569Simp#define TEGRA114_CLK_PLL_A 216 243262569Simp#define TEGRA114_CLK_PLL_A_OUT0 217 244262569Simp#define TEGRA114_CLK_PLL_D 218 245262569Simp#define TEGRA114_CLK_PLL_D_OUT0 219 246262569Simp#define TEGRA114_CLK_PLL_D2 220 247262569Simp#define TEGRA114_CLK_PLL_D2_OUT0 221 248262569Simp#define TEGRA114_CLK_PLL_U 222 249262569Simp#define TEGRA114_CLK_PLL_U_480M 223 250262569Simp 251262569Simp#define TEGRA114_CLK_PLL_U_60M 224 252262569Simp#define TEGRA114_CLK_PLL_U_48M 225 253262569Simp#define TEGRA114_CLK_PLL_U_12M 226 254262569Simp#define TEGRA114_CLK_PLL_X 227 255262569Simp#define TEGRA114_CLK_PLL_X_OUT0 228 256262569Simp#define TEGRA114_CLK_PLL_RE_VCO 229 257262569Simp#define TEGRA114_CLK_PLL_RE_OUT 230 258262569Simp#define TEGRA114_CLK_PLL_E_OUT0 231 259262569Simp#define TEGRA114_CLK_SPDIF_IN_SYNC 232 260262569Simp#define TEGRA114_CLK_I2S0_SYNC 233 261262569Simp#define TEGRA114_CLK_I2S1_SYNC 234 262262569Simp#define TEGRA114_CLK_I2S2_SYNC 235 263262569Simp#define TEGRA114_CLK_I2S3_SYNC 236 264262569Simp#define TEGRA114_CLK_I2S4_SYNC 237 265262569Simp#define TEGRA114_CLK_VIMCLK_SYNC 238 266262569Simp#define TEGRA114_CLK_AUDIO0 239 267262569Simp#define TEGRA114_CLK_AUDIO1 240 268262569Simp#define TEGRA114_CLK_AUDIO2 241 269262569Simp#define TEGRA114_CLK_AUDIO3 242 270262569Simp#define TEGRA114_CLK_AUDIO4 243 271262569Simp#define TEGRA114_CLK_SPDIF 244 272262569Simp#define TEGRA114_CLK_CLK_OUT_1 245 273262569Simp#define TEGRA114_CLK_CLK_OUT_2 246 274262569Simp#define TEGRA114_CLK_CLK_OUT_3 247 275262569Simp#define TEGRA114_CLK_BLINK 248 276262569Simp/* 249 */ 277262569Simp/* 250 */ 278262569Simp/* 251 */ 279262569Simp#define TEGRA114_CLK_XUSB_HOST_SRC 252 280262569Simp#define TEGRA114_CLK_XUSB_FALCON_SRC 253 281262569Simp#define TEGRA114_CLK_XUSB_FS_SRC 254 282262569Simp#define TEGRA114_CLK_XUSB_SS_SRC 255 283262569Simp 284262569Simp#define TEGRA114_CLK_XUSB_DEV_SRC 256 285262569Simp#define TEGRA114_CLK_XUSB_DEV 257 286262569Simp#define TEGRA114_CLK_XUSB_HS_SRC 258 287262569Simp#define TEGRA114_CLK_SCLK 259 288262569Simp#define TEGRA114_CLK_HCLK 260 289262569Simp#define TEGRA114_CLK_PCLK 261 290262569Simp#define TEGRA114_CLK_CCLK_G 262 291262569Simp#define TEGRA114_CLK_CCLK_LP 263 292262569Simp#define TEGRA114_CLK_DFLL_REF 264 293262569Simp#define TEGRA114_CLK_DFLL_SOC 265 294262569Simp/* 266 */ 295262569Simp/* 267 */ 296262569Simp/* 268 */ 297262569Simp/* 269 */ 298262569Simp/* 270 */ 299262569Simp/* 271 */ 300262569Simp/* 272 */ 301262569Simp/* 273 */ 302262569Simp/* 274 */ 303262569Simp/* 275 */ 304262569Simp/* 276 */ 305262569Simp/* 277 */ 306262569Simp/* 278 */ 307262569Simp/* 279 */ 308262569Simp/* 280 */ 309262569Simp/* 281 */ 310262569Simp/* 282 */ 311262569Simp/* 283 */ 312262569Simp/* 284 */ 313262569Simp/* 285 */ 314262569Simp/* 286 */ 315262569Simp/* 287 */ 316262569Simp 317262569Simp/* 288 */ 318262569Simp/* 289 */ 319262569Simp/* 290 */ 320262569Simp/* 291 */ 321262569Simp/* 292 */ 322262569Simp/* 293 */ 323262569Simp/* 294 */ 324262569Simp/* 295 */ 325262569Simp/* 296 */ 326262569Simp/* 297 */ 327262569Simp/* 298 */ 328262569Simp/* 299 */ 329262569Simp#define TEGRA114_CLK_AUDIO0_MUX 300 330262569Simp#define TEGRA114_CLK_AUDIO1_MUX 301 331262569Simp#define TEGRA114_CLK_AUDIO2_MUX 302 332262569Simp#define TEGRA114_CLK_AUDIO3_MUX 303 333262569Simp#define TEGRA114_CLK_AUDIO4_MUX 304 334262569Simp#define TEGRA114_CLK_SPDIF_MUX 305 335262569Simp#define TEGRA114_CLK_CLK_OUT_1_MUX 306 336262569Simp#define TEGRA114_CLK_CLK_OUT_2_MUX 307 337262569Simp#define TEGRA114_CLK_CLK_OUT_3_MUX 308 338262569Simp#define TEGRA114_CLK_DSIA_MUX 309 339262569Simp#define TEGRA114_CLK_DSIB_MUX 310 340273712Sian#define TEGRA114_CLK_XUSB_SS_DIV2 311 341273712Sian#define TEGRA114_CLK_CLK_MAX 312 342262569Simp 343262569Simp#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ 344