stih407-clks.h revision 279377
1279377Simp/* 2279377Simp * This header provides constants clk index STMicroelectronics 3279377Simp * STiH407 SoC. 4279377Simp */ 5279377Simp#ifndef _DT_BINDINGS_CLK_STIH407 6279377Simp#define _DT_BINDINGS_CLK_STIH407 7279377Simp 8279377Simp/* CLOCKGEN C0 */ 9279377Simp#define CLK_ICN_GPU 0 10279377Simp#define CLK_FDMA 1 11279377Simp#define CLK_NAND 2 12279377Simp#define CLK_HVA 3 13279377Simp#define CLK_PROC_STFE 4 14279377Simp#define CLK_PROC_TP 5 15279377Simp#define CLK_RX_ICN_DMU 6 16279377Simp#define CLK_RX_ICN_DISP_0 6 17279377Simp#define CLK_RX_ICN_DISP_1 6 18279377Simp#define CLK_RX_ICN_HVA 7 19279377Simp#define CLK_RX_ICN_TS 7 20279377Simp#define CLK_ICN_CPU 8 21279377Simp#define CLK_TX_ICN_DMU 9 22279377Simp#define CLK_TX_ICN_HVA 9 23279377Simp#define CLK_TX_ICN_TS 9 24279377Simp#define CLK_ICN_COMPO 9 25279377Simp#define CLK_MMC_0 10 26279377Simp#define CLK_MMC_1 11 27279377Simp#define CLK_JPEGDEC 12 28279377Simp#define CLK_ICN_REG 13 29279377Simp#define CLK_TRACE_A9 13 30279377Simp#define CLK_PTI_STM 13 31279377Simp#define CLK_EXT2F_A9 13 32279377Simp#define CLK_IC_BDISP_0 14 33279377Simp#define CLK_IC_BDISP_1 15 34279377Simp#define CLK_PP_DMU 16 35279377Simp#define CLK_VID_DMU 17 36279377Simp#define CLK_DSS_LPC 18 37279377Simp#define CLK_ST231_AUD_0 19 38279377Simp#define CLK_ST231_GP_0 19 39279377Simp#define CLK_ST231_GP_1 20 40279377Simp#define CLK_ST231_DMU 21 41279377Simp#define CLK_ICN_LMI 22 42279377Simp#define CLK_TX_ICN_DISP_0 23 43279377Simp#define CLK_TX_ICN_DISP_1 23 44279377Simp#define CLK_ICN_SBC 24 45279377Simp#define CLK_STFE_FRC2 25 46279377Simp#define CLK_ETH_PHY 26 47279377Simp#define CLK_ETH_REF_PHYCLK 27 48279377Simp#define CLK_FLASH_PROMIP 28 49279377Simp#define CLK_MAIN_DISP 29 50279377Simp#define CLK_AUX_DISP 30 51279377Simp#define CLK_COMPO_DVP 31 52279377Simp 53279377Simp/* CLOCKGEN D0 */ 54279377Simp#define CLK_PCM_0 0 55279377Simp#define CLK_PCM_1 1 56279377Simp#define CLK_PCM_2 2 57279377Simp#define CLK_SPDIFF 3 58279377Simp 59279377Simp/* CLOCKGEN D2 */ 60279377Simp#define CLK_PIX_MAIN_DISP 0 61279377Simp#define CLK_PIX_PIP 1 62279377Simp#define CLK_PIX_GDP1 2 63279377Simp#define CLK_PIX_GDP2 3 64279377Simp#define CLK_PIX_GDP3 4 65279377Simp#define CLK_PIX_GDP4 5 66279377Simp#define CLK_PIX_AUX_DISP 6 67279377Simp#define CLK_DENC 7 68279377Simp#define CLK_PIX_HDDAC 8 69279377Simp#define CLK_HDDAC 9 70279377Simp#define CLK_SDDAC 10 71279377Simp#define CLK_PIX_DVO 11 72279377Simp#define CLK_DVO 12 73279377Simp#define CLK_PIX_HDMI 13 74279377Simp#define CLK_TMDS_HDMI 14 75279377Simp#define CLK_REF_HDMIPHY 15 76279377Simp 77279377Simp/* CLOCKGEN D3 */ 78279377Simp#define CLK_STFE_FRC1 0 79279377Simp#define CLK_TSOUT_0 1 80279377Simp#define CLK_TSOUT_1 2 81279377Simp#define CLK_MCHI 3 82279377Simp#define CLK_VSENS_COMPO 4 83279377Simp#define CLK_FRC1_REMOTE 5 84279377Simp#define CLK_LPC_0 6 85279377Simp#define CLK_LPC_1 7 86279377Simp#endif 87