1270866Simp/* 2270866Simp * Copyright (c) 2014 MundoReader S.L. 3270866Simp * Author: Heiko Stuebner <heiko@sntech.de> 4270866Simp * 5270866Simp * This program is free software; you can redistribute it and/or modify 6270866Simp * it under the terms of the GNU General Public License as published by 7270866Simp * the Free Software Foundation; either version 2 of the License, or 8270866Simp * (at your option) any later version. 9270866Simp * 10270866Simp * This program is distributed in the hope that it will be useful, 11270866Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 12270866Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13270866Simp * GNU General Public License for more details. 14270866Simp */ 15270866Simp 16270866Simp/* core clocks */ 17270866Simp#define PLL_APLL 1 18270866Simp#define PLL_DPLL 2 19270866Simp#define PLL_CPLL 3 20270866Simp#define PLL_GPLL 4 21270866Simp#define PLL_NPLL 5 22284090Sian#define ARMCLK 6 23270866Simp 24270866Simp/* sclk gates (special clocks) */ 25270866Simp#define SCLK_GPU 64 26270866Simp#define SCLK_SPI0 65 27270866Simp#define SCLK_SPI1 66 28270866Simp#define SCLK_SPI2 67 29270866Simp#define SCLK_SDMMC 68 30270866Simp#define SCLK_SDIO0 69 31270866Simp#define SCLK_SDIO1 70 32270866Simp#define SCLK_EMMC 71 33270866Simp#define SCLK_TSADC 72 34270866Simp#define SCLK_SARADC 73 35270866Simp#define SCLK_PS2C 74 36270866Simp#define SCLK_NANDC0 75 37270866Simp#define SCLK_NANDC1 76 38270866Simp#define SCLK_UART0 77 39270866Simp#define SCLK_UART1 78 40270866Simp#define SCLK_UART2 79 41270866Simp#define SCLK_UART3 80 42270866Simp#define SCLK_UART4 81 43270866Simp#define SCLK_I2S0 82 44270866Simp#define SCLK_SPDIF 83 45270866Simp#define SCLK_SPDIF8CH 84 46270866Simp#define SCLK_TIMER0 85 47270866Simp#define SCLK_TIMER1 86 48270866Simp#define SCLK_TIMER2 87 49270866Simp#define SCLK_TIMER3 88 50270866Simp#define SCLK_TIMER4 89 51270866Simp#define SCLK_TIMER5 90 52270866Simp#define SCLK_TIMER6 91 53270866Simp#define SCLK_HSADC 92 54270866Simp#define SCLK_OTGPHY0 93 55270866Simp#define SCLK_OTGPHY1 94 56270866Simp#define SCLK_OTGPHY2 95 57270866Simp#define SCLK_OTG_ADP 96 58270866Simp#define SCLK_HSICPHY480M 97 59270866Simp#define SCLK_HSICPHY12M 98 60270866Simp#define SCLK_MACREF 99 61270866Simp#define SCLK_LCDC_PWM0 100 62270866Simp#define SCLK_LCDC_PWM1 101 63270866Simp#define SCLK_MAC_RX 102 64270866Simp#define SCLK_MAC_TX 103 65284090Sian#define SCLK_EDP_24M 104 66284090Sian#define SCLK_EDP 105 67284090Sian#define SCLK_RGA 106 68284090Sian#define SCLK_ISP 107 69284090Sian#define SCLK_ISP_JPE 108 70284090Sian#define SCLK_HDMI_HDCP 109 71284090Sian#define SCLK_HDMI_CEC 110 72284090Sian#define SCLK_HEVC_CABAC 111 73284090Sian#define SCLK_HEVC_CORE 112 74284090Sian#define SCLK_I2S0_OUT 113 75284090Sian#define SCLK_SDMMC_DRV 114 76284090Sian#define SCLK_SDIO0_DRV 115 77284090Sian#define SCLK_SDIO1_DRV 116 78284090Sian#define SCLK_EMMC_DRV 117 79284090Sian#define SCLK_SDMMC_SAMPLE 118 80284090Sian#define SCLK_SDIO0_SAMPLE 119 81284090Sian#define SCLK_SDIO1_SAMPLE 120 82284090Sian#define SCLK_EMMC_SAMPLE 121 83284090Sian#define SCLK_USBPHY480M_SRC 122 84284090Sian#define SCLK_PVTM_CORE 123 85284090Sian#define SCLK_PVTM_GPU 124 86270866Simp 87284090Sian#define SCLK_MAC 151 88284090Sian#define SCLK_MACREF_OUT 152 89284090Sian 90270866Simp#define DCLK_VOP0 190 91270866Simp#define DCLK_VOP1 191 92270866Simp 93270866Simp/* aclk gates */ 94270866Simp#define ACLK_GPU 192 95270866Simp#define ACLK_DMAC1 193 96270866Simp#define ACLK_DMAC2 194 97270866Simp#define ACLK_MMU 195 98270866Simp#define ACLK_GMAC 196 99270866Simp#define ACLK_VOP0 197 100270866Simp#define ACLK_VOP1 198 101270866Simp#define ACLK_CRYPTO 199 102270866Simp#define ACLK_RGA 200 103284090Sian#define ACLK_RGA_NIU 201 104284090Sian#define ACLK_IEP 202 105284090Sian#define ACLK_VIO0_NIU 203 106284090Sian#define ACLK_VIP 204 107284090Sian#define ACLK_ISP 205 108284090Sian#define ACLK_VIO1_NIU 206 109284090Sian#define ACLK_HEVC 207 110284090Sian#define ACLK_VCODEC 208 111284090Sian#define ACLK_CPU 209 112284090Sian#define ACLK_PERI 210 113270866Simp 114270866Simp/* pclk gates */ 115270866Simp#define PCLK_GPIO0 320 116270866Simp#define PCLK_GPIO1 321 117270866Simp#define PCLK_GPIO2 322 118270866Simp#define PCLK_GPIO3 323 119270866Simp#define PCLK_GPIO4 324 120270866Simp#define PCLK_GPIO5 325 121270866Simp#define PCLK_GPIO6 326 122270866Simp#define PCLK_GPIO7 327 123270866Simp#define PCLK_GPIO8 328 124270866Simp#define PCLK_GRF 329 125270866Simp#define PCLK_SGRF 330 126270866Simp#define PCLK_PMU 331 127270866Simp#define PCLK_I2C0 332 128270866Simp#define PCLK_I2C1 333 129270866Simp#define PCLK_I2C2 334 130270866Simp#define PCLK_I2C3 335 131270866Simp#define PCLK_I2C4 336 132270866Simp#define PCLK_I2C5 337 133270866Simp#define PCLK_SPI0 338 134270866Simp#define PCLK_SPI1 339 135270866Simp#define PCLK_SPI2 340 136270866Simp#define PCLK_UART0 341 137270866Simp#define PCLK_UART1 342 138270866Simp#define PCLK_UART2 343 139270866Simp#define PCLK_UART3 344 140270866Simp#define PCLK_UART4 345 141270866Simp#define PCLK_TSADC 346 142270866Simp#define PCLK_SARADC 347 143270866Simp#define PCLK_SIM 348 144270866Simp#define PCLK_GMAC 349 145270866Simp#define PCLK_PWM 350 146270866Simp#define PCLK_RKPWM 351 147270866Simp#define PCLK_PS2C 352 148270866Simp#define PCLK_TIMER 353 149270866Simp#define PCLK_TZPC 354 150284090Sian#define PCLK_EDP_CTRL 355 151284090Sian#define PCLK_MIPI_DSI0 356 152284090Sian#define PCLK_MIPI_DSI1 357 153284090Sian#define PCLK_MIPI_CSI 358 154284090Sian#define PCLK_LVDS_PHY 359 155284090Sian#define PCLK_HDMI_CTRL 360 156284090Sian#define PCLK_VIO2_H2P 361 157284090Sian#define PCLK_CPU 362 158284090Sian#define PCLK_PERI 363 159284090Sian#define PCLK_DDRUPCTL0 364 160284090Sian#define PCLK_PUBL0 365 161284090Sian#define PCLK_DDRUPCTL1 366 162284090Sian#define PCLK_PUBL1 367 163284090Sian#define PCLK_WDT 368 164270866Simp 165270866Simp/* hclk gates */ 166270866Simp#define HCLK_GPS 448 167270866Simp#define HCLK_OTG0 449 168270866Simp#define HCLK_USBHOST0 450 169270866Simp#define HCLK_USBHOST1 451 170270866Simp#define HCLK_HSIC 452 171270866Simp#define HCLK_NANDC0 453 172270866Simp#define HCLK_NANDC1 454 173270866Simp#define HCLK_TSP 455 174270866Simp#define HCLK_SDMMC 456 175270866Simp#define HCLK_SDIO0 457 176270866Simp#define HCLK_SDIO1 458 177270866Simp#define HCLK_EMMC 459 178270866Simp#define HCLK_HSADC 460 179270866Simp#define HCLK_CRYPTO 461 180270866Simp#define HCLK_I2S0 462 181270866Simp#define HCLK_SPDIF 463 182270866Simp#define HCLK_SPDIF8CH 464 183270866Simp#define HCLK_VOP0 465 184270866Simp#define HCLK_VOP1 466 185270866Simp#define HCLK_ROM 467 186270866Simp#define HCLK_IEP 468 187270866Simp#define HCLK_ISP 469 188270866Simp#define HCLK_RGA 470 189284090Sian#define HCLK_VIO_AHB_ARBI 471 190284090Sian#define HCLK_VIO_NIU 472 191284090Sian#define HCLK_VIP 473 192284090Sian#define HCLK_VIO2_H2P 474 193284090Sian#define HCLK_HEVC 475 194284090Sian#define HCLK_VCODEC 476 195284090Sian#define HCLK_CPU 477 196284090Sian#define HCLK_PERI 478 197270866Simp 198284090Sian#define CLK_NR_CLKS (HCLK_PERI + 1) 199270866Simp 200270866Simp/* soft-reset indices */ 201270866Simp#define SRST_CORE0 0 202270866Simp#define SRST_CORE1 1 203270866Simp#define SRST_CORE2 2 204270866Simp#define SRST_CORE3 3 205270866Simp#define SRST_CORE0_PO 4 206270866Simp#define SRST_CORE1_PO 5 207270866Simp#define SRST_CORE2_PO 6 208270866Simp#define SRST_CORE3_PO 7 209270866Simp#define SRST_PDCORE_STRSYS 8 210270866Simp#define SRST_PDBUS_STRSYS 9 211270866Simp#define SRST_L2C 10 212270866Simp#define SRST_TOPDBG 11 213270866Simp#define SRST_CORE0_DBG 12 214270866Simp#define SRST_CORE1_DBG 13 215270866Simp#define SRST_CORE2_DBG 14 216270866Simp#define SRST_CORE3_DBG 15 217270866Simp 218270866Simp#define SRST_PDBUG_AHB_ARBITOR 16 219270866Simp#define SRST_EFUSE256 17 220270866Simp#define SRST_DMAC1 18 221270866Simp#define SRST_INTMEM 19 222270866Simp#define SRST_ROM 20 223270866Simp#define SRST_SPDIF8CH 21 224270866Simp#define SRST_TIMER 22 225270866Simp#define SRST_I2S0 23 226270866Simp#define SRST_SPDIF 24 227270866Simp#define SRST_TIMER0 25 228270866Simp#define SRST_TIMER1 26 229270866Simp#define SRST_TIMER2 27 230270866Simp#define SRST_TIMER3 28 231270866Simp#define SRST_TIMER4 29 232270866Simp#define SRST_TIMER5 30 233270866Simp#define SRST_EFUSE 31 234270866Simp 235270866Simp#define SRST_GPIO0 32 236270866Simp#define SRST_GPIO1 33 237270866Simp#define SRST_GPIO2 34 238270866Simp#define SRST_GPIO3 35 239270866Simp#define SRST_GPIO4 36 240270866Simp#define SRST_GPIO5 37 241270866Simp#define SRST_GPIO6 38 242270866Simp#define SRST_GPIO7 39 243270866Simp#define SRST_GPIO8 40 244270866Simp#define SRST_I2C0 42 245270866Simp#define SRST_I2C1 43 246270866Simp#define SRST_I2C2 44 247270866Simp#define SRST_I2C3 45 248270866Simp#define SRST_I2C4 46 249270866Simp#define SRST_I2C5 47 250270866Simp 251270866Simp#define SRST_DWPWM 48 252270866Simp#define SRST_MMC_PERI 49 253270866Simp#define SRST_PERIPH_MMU 50 254270866Simp#define SRST_DAP 51 255270866Simp#define SRST_DAP_SYS 52 256270866Simp#define SRST_TPIU 53 257270866Simp#define SRST_PMU_APB 54 258270866Simp#define SRST_GRF 55 259270866Simp#define SRST_PMU 56 260270866Simp#define SRST_PERIPH_AXI 57 261270866Simp#define SRST_PERIPH_AHB 58 262270866Simp#define SRST_PERIPH_APB 59 263270866Simp#define SRST_PERIPH_NIU 60 264270866Simp#define SRST_PDPERI_AHB_ARBI 61 265270866Simp#define SRST_EMEM 62 266270866Simp#define SRST_USB_PERI 63 267270866Simp 268270866Simp#define SRST_DMAC2 64 269270866Simp#define SRST_MAC 66 270270866Simp#define SRST_GPS 67 271270866Simp#define SRST_RKPWM 69 272270866Simp#define SRST_CCP 71 273270866Simp#define SRST_USBHOST0 72 274270866Simp#define SRST_HSIC 73 275270866Simp#define SRST_HSIC_AUX 74 276270866Simp#define SRST_HSIC_PHY 75 277270866Simp#define SRST_HSADC 76 278270866Simp#define SRST_NANDC0 77 279270866Simp#define SRST_NANDC1 78 280270866Simp 281270866Simp#define SRST_TZPC 80 282270866Simp#define SRST_SPI0 83 283270866Simp#define SRST_SPI1 84 284270866Simp#define SRST_SPI2 85 285270866Simp#define SRST_SARADC 87 286270866Simp#define SRST_PDALIVE_NIU 88 287270866Simp#define SRST_PDPMU_INTMEM 89 288270866Simp#define SRST_PDPMU_NIU 90 289270866Simp#define SRST_SGRF 91 290270866Simp 291270866Simp#define SRST_VIO_ARBI 96 292270866Simp#define SRST_RGA_NIU 97 293270866Simp#define SRST_VIO0_NIU_AXI 98 294270866Simp#define SRST_VIO_NIU_AHB 99 295270866Simp#define SRST_LCDC0_AXI 100 296270866Simp#define SRST_LCDC0_AHB 101 297270866Simp#define SRST_LCDC0_DCLK 102 298270866Simp#define SRST_VIO1_NIU_AXI 103 299270866Simp#define SRST_VIP 104 300270866Simp#define SRST_RGA_CORE 105 301270866Simp#define SRST_IEP_AXI 106 302270866Simp#define SRST_IEP_AHB 107 303270866Simp#define SRST_RGA_AXI 108 304270866Simp#define SRST_RGA_AHB 109 305270866Simp#define SRST_ISP 110 306270866Simp#define SRST_EDP 111 307270866Simp 308270866Simp#define SRST_VCODEC_AXI 112 309270866Simp#define SRST_VCODEC_AHB 113 310270866Simp#define SRST_VIO_H2P 114 311270866Simp#define SRST_MIPIDSI0 115 312270866Simp#define SRST_MIPIDSI1 116 313270866Simp#define SRST_MIPICSI 117 314270866Simp#define SRST_LVDS_PHY 118 315270866Simp#define SRST_LVDS_CON 119 316270866Simp#define SRST_GPU 120 317270866Simp#define SRST_HDMI 121 318270866Simp#define SRST_CORE_PVTM 124 319270866Simp#define SRST_GPU_PVTM 125 320270866Simp 321270866Simp#define SRST_MMC0 128 322270866Simp#define SRST_SDIO0 129 323270866Simp#define SRST_SDIO1 130 324270866Simp#define SRST_EMMC 131 325270866Simp#define SRST_USBOTG_AHB 132 326270866Simp#define SRST_USBOTG_PHY 133 327270866Simp#define SRST_USBOTG_CON 134 328270866Simp#define SRST_USBHOST0_AHB 135 329270866Simp#define SRST_USBHOST0_PHY 136 330270866Simp#define SRST_USBHOST0_CON 137 331270866Simp#define SRST_USBHOST1_AHB 138 332270866Simp#define SRST_USBHOST1_PHY 139 333270866Simp#define SRST_USBHOST1_CON 140 334270866Simp#define SRST_USB_ADP 141 335270866Simp#define SRST_ACC_EFUSE 142 336284090Sian 337284090Sian#define SRST_CORESIGHT 144 338284090Sian#define SRST_PD_CORE_AHB_NOC 145 339284090Sian#define SRST_PD_CORE_APB_NOC 146 340284090Sian#define SRST_PD_CORE_MP_AXI 147 341284090Sian#define SRST_GIC 148 342284090Sian#define SRST_LCDC_PWM0 149 343284090Sian#define SRST_LCDC_PWM1 150 344284090Sian#define SRST_VIO0_H2P_BRG 151 345284090Sian#define SRST_VIO1_H2P_BRG 152 346284090Sian#define SRST_RGA_H2P_BRG 153 347284090Sian#define SRST_HEVC 154 348284090Sian#define SRST_TSADC 159 349284090Sian 350284090Sian#define SRST_DDRPHY0 160 351284090Sian#define SRST_DDRPHY0_APB 161 352284090Sian#define SRST_DDRCTRL0 162 353284090Sian#define SRST_DDRCTRL0_APB 163 354284090Sian#define SRST_DDRPHY0_CTRL 164 355284090Sian#define SRST_DDRPHY1 165 356284090Sian#define SRST_DDRPHY1_APB 166 357284090Sian#define SRST_DDRCTRL1 167 358284090Sian#define SRST_DDRCTRL1_APB 168 359284090Sian#define SRST_DDRPHY1_CTRL 169 360284090Sian#define SRST_DDRMSCH0 170 361284090Sian#define SRST_DDRMSCH1 171 362284090Sian#define SRST_CRYPTO 174 363284090Sian#define SRST_C2C_HOST 175 364284090Sian 365284090Sian#define SRST_LCDC1_AXI 176 366284090Sian#define SRST_LCDC1_AHB 177 367284090Sian#define SRST_LCDC1_DCLK 178 368284090Sian#define SRST_UART0 179 369284090Sian#define SRST_UART1 180 370284090Sian#define SRST_UART2 181 371284090Sian#define SRST_UART3 182 372284090Sian#define SRST_UART4 183 373284090Sian#define SRST_SIMC 186 374284090Sian#define SRST_PS2C 187 375284090Sian#define SRST_TSP 188 376284090Sian#define SRST_TSP_CLKIN0 189 377284090Sian#define SRST_TSP_CLKIN1 190 378284090Sian#define SRST_TSP_27M 191 379