imx5-clock.h revision 284090
1262569Simp/* 2262569Simp * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de> 3262569Simp * 4262569Simp * This program is free software; you can redistribute it and/or modify 5262569Simp * it under the terms of the GNU General Public License version 2 as 6262569Simp * published by the Free Software Foundation. 7262569Simp * 8262569Simp */ 9262569Simp 10262569Simp#ifndef __DT_BINDINGS_CLOCK_IMX5_H 11262569Simp#define __DT_BINDINGS_CLOCK_IMX5_H 12262569Simp 13262569Simp#define IMX5_CLK_DUMMY 0 14262569Simp#define IMX5_CLK_CKIL 1 15262569Simp#define IMX5_CLK_OSC 2 16262569Simp#define IMX5_CLK_CKIH1 3 17262569Simp#define IMX5_CLK_CKIH2 4 18262569Simp#define IMX5_CLK_AHB 5 19262569Simp#define IMX5_CLK_IPG 6 20262569Simp#define IMX5_CLK_AXI_A 7 21262569Simp#define IMX5_CLK_AXI_B 8 22262569Simp#define IMX5_CLK_UART_PRED 9 23262569Simp#define IMX5_CLK_UART_ROOT 10 24262569Simp#define IMX5_CLK_ESDHC_A_PRED 11 25262569Simp#define IMX5_CLK_ESDHC_B_PRED 12 26262569Simp#define IMX5_CLK_ESDHC_C_SEL 13 27262569Simp#define IMX5_CLK_ESDHC_D_SEL 14 28262569Simp#define IMX5_CLK_EMI_SEL 15 29262569Simp#define IMX5_CLK_EMI_SLOW_PODF 16 30262569Simp#define IMX5_CLK_NFC_PODF 17 31262569Simp#define IMX5_CLK_ECSPI_PRED 18 32262569Simp#define IMX5_CLK_ECSPI_PODF 19 33262569Simp#define IMX5_CLK_USBOH3_PRED 20 34262569Simp#define IMX5_CLK_USBOH3_PODF 21 35262569Simp#define IMX5_CLK_USB_PHY_PRED 22 36262569Simp#define IMX5_CLK_USB_PHY_PODF 23 37262569Simp#define IMX5_CLK_CPU_PODF 24 38262569Simp#define IMX5_CLK_DI_PRED 25 39262569Simp#define IMX5_CLK_TVE_SEL 27 40262569Simp#define IMX5_CLK_UART1_IPG_GATE 28 41262569Simp#define IMX5_CLK_UART1_PER_GATE 29 42262569Simp#define IMX5_CLK_UART2_IPG_GATE 30 43262569Simp#define IMX5_CLK_UART2_PER_GATE 31 44262569Simp#define IMX5_CLK_UART3_IPG_GATE 32 45262569Simp#define IMX5_CLK_UART3_PER_GATE 33 46262569Simp#define IMX5_CLK_I2C1_GATE 34 47262569Simp#define IMX5_CLK_I2C2_GATE 35 48262569Simp#define IMX5_CLK_GPT_IPG_GATE 36 49262569Simp#define IMX5_CLK_PWM1_IPG_GATE 37 50262569Simp#define IMX5_CLK_PWM1_HF_GATE 38 51262569Simp#define IMX5_CLK_PWM2_IPG_GATE 39 52262569Simp#define IMX5_CLK_PWM2_HF_GATE 40 53262569Simp#define IMX5_CLK_GPT_HF_GATE 41 54262569Simp#define IMX5_CLK_FEC_GATE 42 55262569Simp#define IMX5_CLK_USBOH3_PER_GATE 43 56262569Simp#define IMX5_CLK_ESDHC1_IPG_GATE 44 57262569Simp#define IMX5_CLK_ESDHC2_IPG_GATE 45 58262569Simp#define IMX5_CLK_ESDHC3_IPG_GATE 46 59262569Simp#define IMX5_CLK_ESDHC4_IPG_GATE 47 60262569Simp#define IMX5_CLK_SSI1_IPG_GATE 48 61262569Simp#define IMX5_CLK_SSI2_IPG_GATE 49 62262569Simp#define IMX5_CLK_SSI3_IPG_GATE 50 63262569Simp#define IMX5_CLK_ECSPI1_IPG_GATE 51 64262569Simp#define IMX5_CLK_ECSPI1_PER_GATE 52 65262569Simp#define IMX5_CLK_ECSPI2_IPG_GATE 53 66262569Simp#define IMX5_CLK_ECSPI2_PER_GATE 54 67262569Simp#define IMX5_CLK_CSPI_IPG_GATE 55 68262569Simp#define IMX5_CLK_SDMA_GATE 56 69262569Simp#define IMX5_CLK_EMI_SLOW_GATE 57 70262569Simp#define IMX5_CLK_IPU_SEL 58 71262569Simp#define IMX5_CLK_IPU_GATE 59 72262569Simp#define IMX5_CLK_NFC_GATE 60 73262569Simp#define IMX5_CLK_IPU_DI1_GATE 61 74262569Simp#define IMX5_CLK_VPU_SEL 62 75262569Simp#define IMX5_CLK_VPU_GATE 63 76262569Simp#define IMX5_CLK_VPU_REFERENCE_GATE 64 77262569Simp#define IMX5_CLK_UART4_IPG_GATE 65 78262569Simp#define IMX5_CLK_UART4_PER_GATE 66 79262569Simp#define IMX5_CLK_UART5_IPG_GATE 67 80262569Simp#define IMX5_CLK_UART5_PER_GATE 68 81262569Simp#define IMX5_CLK_TVE_GATE 69 82262569Simp#define IMX5_CLK_TVE_PRED 70 83262569Simp#define IMX5_CLK_ESDHC1_PER_GATE 71 84262569Simp#define IMX5_CLK_ESDHC2_PER_GATE 72 85262569Simp#define IMX5_CLK_ESDHC3_PER_GATE 73 86262569Simp#define IMX5_CLK_ESDHC4_PER_GATE 74 87262569Simp#define IMX5_CLK_USB_PHY_GATE 75 88262569Simp#define IMX5_CLK_HSI2C_GATE 76 89262569Simp#define IMX5_CLK_MIPI_HSC1_GATE 77 90262569Simp#define IMX5_CLK_MIPI_HSC2_GATE 78 91262569Simp#define IMX5_CLK_MIPI_ESC_GATE 79 92262569Simp#define IMX5_CLK_MIPI_HSP_GATE 80 93262569Simp#define IMX5_CLK_LDB_DI1_DIV_3_5 81 94262569Simp#define IMX5_CLK_LDB_DI1_DIV 82 95262569Simp#define IMX5_CLK_LDB_DI0_DIV_3_5 83 96262569Simp#define IMX5_CLK_LDB_DI0_DIV 84 97262569Simp#define IMX5_CLK_LDB_DI1_GATE 85 98262569Simp#define IMX5_CLK_CAN2_SERIAL_GATE 86 99262569Simp#define IMX5_CLK_CAN2_IPG_GATE 87 100262569Simp#define IMX5_CLK_I2C3_GATE 88 101262569Simp#define IMX5_CLK_LP_APM 89 102262569Simp#define IMX5_CLK_PERIPH_APM 90 103262569Simp#define IMX5_CLK_MAIN_BUS 91 104262569Simp#define IMX5_CLK_AHB_MAX 92 105262569Simp#define IMX5_CLK_AIPS_TZ1 93 106262569Simp#define IMX5_CLK_AIPS_TZ2 94 107262569Simp#define IMX5_CLK_TMAX1 95 108262569Simp#define IMX5_CLK_TMAX2 96 109262569Simp#define IMX5_CLK_TMAX3 97 110262569Simp#define IMX5_CLK_SPBA 98 111262569Simp#define IMX5_CLK_UART_SEL 99 112262569Simp#define IMX5_CLK_ESDHC_A_SEL 100 113262569Simp#define IMX5_CLK_ESDHC_B_SEL 101 114262569Simp#define IMX5_CLK_ESDHC_A_PODF 102 115262569Simp#define IMX5_CLK_ESDHC_B_PODF 103 116262569Simp#define IMX5_CLK_ECSPI_SEL 104 117262569Simp#define IMX5_CLK_USBOH3_SEL 105 118262569Simp#define IMX5_CLK_USB_PHY_SEL 106 119262569Simp#define IMX5_CLK_IIM_GATE 107 120262569Simp#define IMX5_CLK_USBOH3_GATE 108 121262569Simp#define IMX5_CLK_EMI_FAST_GATE 109 122262569Simp#define IMX5_CLK_IPU_DI0_GATE 110 123262569Simp#define IMX5_CLK_GPC_DVFS 111 124262569Simp#define IMX5_CLK_PLL1_SW 112 125262569Simp#define IMX5_CLK_PLL2_SW 113 126262569Simp#define IMX5_CLK_PLL3_SW 114 127262569Simp#define IMX5_CLK_IPU_DI0_SEL 115 128262569Simp#define IMX5_CLK_IPU_DI1_SEL 116 129262569Simp#define IMX5_CLK_TVE_EXT_SEL 117 130262569Simp#define IMX5_CLK_MX51_MIPI 118 131262569Simp#define IMX5_CLK_PLL4_SW 119 132262569Simp#define IMX5_CLK_LDB_DI1_SEL 120 133262569Simp#define IMX5_CLK_DI_PLL4_PODF 121 134262569Simp#define IMX5_CLK_LDB_DI0_SEL 122 135262569Simp#define IMX5_CLK_LDB_DI0_GATE 123 136262569Simp#define IMX5_CLK_USB_PHY1_GATE 124 137262569Simp#define IMX5_CLK_USB_PHY2_GATE 125 138262569Simp#define IMX5_CLK_PER_LP_APM 126 139262569Simp#define IMX5_CLK_PER_PRED1 127 140262569Simp#define IMX5_CLK_PER_PRED2 128 141262569Simp#define IMX5_CLK_PER_PODF 129 142262569Simp#define IMX5_CLK_PER_ROOT 130 143262569Simp#define IMX5_CLK_SSI_APM 131 144262569Simp#define IMX5_CLK_SSI1_ROOT_SEL 132 145262569Simp#define IMX5_CLK_SSI2_ROOT_SEL 133 146262569Simp#define IMX5_CLK_SSI3_ROOT_SEL 134 147262569Simp#define IMX5_CLK_SSI_EXT1_SEL 135 148262569Simp#define IMX5_CLK_SSI_EXT2_SEL 136 149262569Simp#define IMX5_CLK_SSI_EXT1_COM_SEL 137 150262569Simp#define IMX5_CLK_SSI_EXT2_COM_SEL 138 151262569Simp#define IMX5_CLK_SSI1_ROOT_PRED 139 152262569Simp#define IMX5_CLK_SSI1_ROOT_PODF 140 153262569Simp#define IMX5_CLK_SSI2_ROOT_PRED 141 154262569Simp#define IMX5_CLK_SSI2_ROOT_PODF 142 155262569Simp#define IMX5_CLK_SSI_EXT1_PRED 143 156262569Simp#define IMX5_CLK_SSI_EXT1_PODF 144 157262569Simp#define IMX5_CLK_SSI_EXT2_PRED 145 158262569Simp#define IMX5_CLK_SSI_EXT2_PODF 146 159262569Simp#define IMX5_CLK_SSI1_ROOT_GATE 147 160262569Simp#define IMX5_CLK_SSI2_ROOT_GATE 148 161262569Simp#define IMX5_CLK_SSI3_ROOT_GATE 149 162262569Simp#define IMX5_CLK_SSI_EXT1_GATE 150 163262569Simp#define IMX5_CLK_SSI_EXT2_GATE 151 164262569Simp#define IMX5_CLK_EPIT1_IPG_GATE 152 165262569Simp#define IMX5_CLK_EPIT1_HF_GATE 153 166262569Simp#define IMX5_CLK_EPIT2_IPG_GATE 154 167262569Simp#define IMX5_CLK_EPIT2_HF_GATE 155 168262569Simp#define IMX5_CLK_CAN_SEL 156 169262569Simp#define IMX5_CLK_CAN1_SERIAL_GATE 157 170262569Simp#define IMX5_CLK_CAN1_IPG_GATE 158 171262569Simp#define IMX5_CLK_OWIRE_GATE 159 172262569Simp#define IMX5_CLK_GPU3D_SEL 160 173262569Simp#define IMX5_CLK_GPU2D_SEL 161 174262569Simp#define IMX5_CLK_GPU3D_GATE 162 175262569Simp#define IMX5_CLK_GPU2D_GATE 163 176262569Simp#define IMX5_CLK_GARB_GATE 164 177262569Simp#define IMX5_CLK_CKO1_SEL 165 178262569Simp#define IMX5_CLK_CKO1_PODF 166 179262569Simp#define IMX5_CLK_CKO1 167 180262569Simp#define IMX5_CLK_CKO2_SEL 168 181262569Simp#define IMX5_CLK_CKO2_PODF 169 182262569Simp#define IMX5_CLK_CKO2 170 183262569Simp#define IMX5_CLK_SRTC_GATE 171 184262569Simp#define IMX5_CLK_PATA_GATE 172 185262569Simp#define IMX5_CLK_SATA_GATE 173 186262569Simp#define IMX5_CLK_SPDIF_XTAL_SEL 174 187262569Simp#define IMX5_CLK_SPDIF0_SEL 175 188262569Simp#define IMX5_CLK_SPDIF1_SEL 176 189262569Simp#define IMX5_CLK_SPDIF0_PRED 177 190262569Simp#define IMX5_CLK_SPDIF0_PODF 178 191262569Simp#define IMX5_CLK_SPDIF1_PRED 179 192262569Simp#define IMX5_CLK_SPDIF1_PODF 180 193262569Simp#define IMX5_CLK_SPDIF0_COM_SEL 181 194262569Simp#define IMX5_CLK_SPDIF1_COM_SEL 182 195262569Simp#define IMX5_CLK_SPDIF0_GATE 183 196262569Simp#define IMX5_CLK_SPDIF1_GATE 184 197262569Simp#define IMX5_CLK_SPDIF_IPG_GATE 185 198262569Simp#define IMX5_CLK_OCRAM 186 199262569Simp#define IMX5_CLK_SAHARA_IPG_GATE 187 200262569Simp#define IMX5_CLK_SATA_REF 188 201284090Sian#define IMX5_CLK_STEP_SEL 189 202284090Sian#define IMX5_CLK_CPU_PODF_SEL 190 203284090Sian#define IMX5_CLK_ARM 191 204284090Sian#define IMX5_CLK_END 192 205262569Simp 206262569Simp#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ 207