imx27-clock.h revision 271133
1270866Simp/* 2270866Simp * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 3270866Simp * 4270866Simp * This program is free software; you can redistribute it and/or modify 5270866Simp * it under the terms of the GNU General Public License version 2 as 6270866Simp * published by the Free Software Foundation. 7270866Simp * 8270866Simp */ 9270866Simp 10270866Simp#ifndef __DT_BINDINGS_CLOCK_IMX27_H 11270866Simp#define __DT_BINDINGS_CLOCK_IMX27_H 12270866Simp 13270866Simp#define IMX27_CLK_DUMMY 0 14270866Simp#define IMX27_CLK_CKIH 1 15270866Simp#define IMX27_CLK_CKIL 2 16270866Simp#define IMX27_CLK_MPLL 3 17270866Simp#define IMX27_CLK_SPLL 4 18270866Simp#define IMX27_CLK_MPLL_MAIN2 5 19270866Simp#define IMX27_CLK_AHB 6 20270866Simp#define IMX27_CLK_IPG 7 21270866Simp#define IMX27_CLK_NFC_DIV 8 22270866Simp#define IMX27_CLK_PER1_DIV 9 23270866Simp#define IMX27_CLK_PER2_DIV 10 24270866Simp#define IMX27_CLK_PER3_DIV 11 25270866Simp#define IMX27_CLK_PER4_DIV 12 26270866Simp#define IMX27_CLK_VPU_SEL 13 27270866Simp#define IMX27_CLK_VPU_DIV 14 28270866Simp#define IMX27_CLK_USB_DIV 15 29270866Simp#define IMX27_CLK_CPU_SEL 16 30270866Simp#define IMX27_CLK_CLKO_SEL 17 31270866Simp#define IMX27_CLK_CPU_DIV 18 32270866Simp#define IMX27_CLK_CLKO_DIV 19 33270866Simp#define IMX27_CLK_SSI1_SEL 20 34270866Simp#define IMX27_CLK_SSI2_SEL 21 35270866Simp#define IMX27_CLK_SSI1_DIV 22 36270866Simp#define IMX27_CLK_SSI2_DIV 23 37270866Simp#define IMX27_CLK_CLKO_EN 24 38270866Simp#define IMX27_CLK_SSI2_IPG_GATE 25 39270866Simp#define IMX27_CLK_SSI1_IPG_GATE 26 40270866Simp#define IMX27_CLK_SLCDC_IPG_GATE 27 41270866Simp#define IMX27_CLK_SDHC3_IPG_GATE 28 42270866Simp#define IMX27_CLK_SDHC2_IPG_GATE 29 43270866Simp#define IMX27_CLK_SDHC1_IPG_GATE 30 44270866Simp#define IMX27_CLK_SCC_IPG_GATE 31 45270866Simp#define IMX27_CLK_SAHARA_IPG_GATE 32 46270866Simp#define IMX27_CLK_RTC_IPG_GATE 33 47270866Simp#define IMX27_CLK_PWM_IPG_GATE 34 48270866Simp#define IMX27_CLK_OWIRE_IPG_GATE 35 49270866Simp#define IMX27_CLK_LCDC_IPG_GATE 36 50270866Simp#define IMX27_CLK_KPP_IPG_GATE 37 51270866Simp#define IMX27_CLK_IIM_IPG_GATE 38 52270866Simp#define IMX27_CLK_I2C2_IPG_GATE 39 53270866Simp#define IMX27_CLK_I2C1_IPG_GATE 40 54270866Simp#define IMX27_CLK_GPT6_IPG_GATE 41 55270866Simp#define IMX27_CLK_GPT5_IPG_GATE 42 56270866Simp#define IMX27_CLK_GPT4_IPG_GATE 43 57270866Simp#define IMX27_CLK_GPT3_IPG_GATE 44 58270866Simp#define IMX27_CLK_GPT2_IPG_GATE 45 59270866Simp#define IMX27_CLK_GPT1_IPG_GATE 46 60270866Simp#define IMX27_CLK_GPIO_IPG_GATE 47 61270866Simp#define IMX27_CLK_FEC_IPG_GATE 48 62270866Simp#define IMX27_CLK_EMMA_IPG_GATE 49 63270866Simp#define IMX27_CLK_DMA_IPG_GATE 50 64270866Simp#define IMX27_CLK_CSPI3_IPG_GATE 51 65270866Simp#define IMX27_CLK_CSPI2_IPG_GATE 52 66270866Simp#define IMX27_CLK_CSPI1_IPG_GATE 53 67270866Simp#define IMX27_CLK_NFC_BAUD_GATE 54 68270866Simp#define IMX27_CLK_SSI2_BAUD_GATE 55 69270866Simp#define IMX27_CLK_SSI1_BAUD_GATE 56 70270866Simp#define IMX27_CLK_VPU_BAUD_GATE 57 71270866Simp#define IMX27_CLK_PER4_GATE 58 72270866Simp#define IMX27_CLK_PER3_GATE 59 73270866Simp#define IMX27_CLK_PER2_GATE 60 74270866Simp#define IMX27_CLK_PER1_GATE 61 75270866Simp#define IMX27_CLK_USB_AHB_GATE 62 76270866Simp#define IMX27_CLK_SLCDC_AHB_GATE 63 77270866Simp#define IMX27_CLK_SAHARA_AHB_GATE 64 78#define IMX27_CLK_LCDC_AHB_GATE 65 79#define IMX27_CLK_VPU_AHB_GATE 66 80#define IMX27_CLK_FEC_AHB_GATE 67 81#define IMX27_CLK_EMMA_AHB_GATE 68 82#define IMX27_CLK_EMI_AHB_GATE 69 83#define IMX27_CLK_DMA_AHB_GATE 70 84#define IMX27_CLK_CSI_AHB_GATE 71 85#define IMX27_CLK_BROM_AHB_GATE 72 86#define IMX27_CLK_ATA_AHB_GATE 73 87#define IMX27_CLK_WDOG_IPG_GATE 74 88#define IMX27_CLK_USB_IPG_GATE 75 89#define IMX27_CLK_UART6_IPG_GATE 76 90#define IMX27_CLK_UART5_IPG_GATE 77 91#define IMX27_CLK_UART4_IPG_GATE 78 92#define IMX27_CLK_UART3_IPG_GATE 79 93#define IMX27_CLK_UART2_IPG_GATE 80 94#define IMX27_CLK_UART1_IPG_GATE 81 95#define IMX27_CLK_CKIH_DIV1P5 82 96#define IMX27_CLK_FPM 83 97#define IMX27_CLK_MPLL_OSC_SEL 84 98#define IMX27_CLK_MPLL_SEL 85 99#define IMX27_CLK_SPLL_GATE 86 100#define IMX27_CLK_MSHC_DIV 87 101#define IMX27_CLK_RTIC_IPG_GATE 88 102#define IMX27_CLK_MSHC_IPG_GATE 89 103#define IMX27_CLK_RTIC_AHB_GATE 90 104#define IMX27_CLK_MSHC_BAUD_GATE 91 105#define IMX27_CLK_CKIH_GATE 92 106#define IMX27_CLK_MAX 93 107 108#endif 109