hix5hd2-clock.h revision 270866
1270866Simp/* 2270866Simp * Copyright (c) 2014 Linaro Ltd. 3270866Simp * Copyright (c) 2014 Hisilicon Limited. 4270866Simp * 5270866Simp * This program is free software; you can redistribute it and/or modify it 6270866Simp * under the terms and conditions of the GNU General Public License, 7270866Simp * version 2, as published by the Free Software Foundation. 8270866Simp */ 9270866Simp 10270866Simp#ifndef __DTS_HIX5HD2_CLOCK_H 11270866Simp#define __DTS_HIX5HD2_CLOCK_H 12270866Simp 13270866Simp/* fixed rate */ 14270866Simp#define HIX5HD2_FIXED_1200M 1 15270866Simp#define HIX5HD2_FIXED_400M 2 16270866Simp#define HIX5HD2_FIXED_48M 3 17270866Simp#define HIX5HD2_FIXED_24M 4 18270866Simp#define HIX5HD2_FIXED_600M 5 19270866Simp#define HIX5HD2_FIXED_300M 6 20270866Simp#define HIX5HD2_FIXED_75M 7 21270866Simp#define HIX5HD2_FIXED_200M 8 22270866Simp#define HIX5HD2_FIXED_100M 9 23270866Simp#define HIX5HD2_FIXED_40M 10 24270866Simp#define HIX5HD2_FIXED_150M 11 25270866Simp#define HIX5HD2_FIXED_1728M 12 26270866Simp#define HIX5HD2_FIXED_28P8M 13 27270866Simp#define HIX5HD2_FIXED_432M 14 28270866Simp#define HIX5HD2_FIXED_345P6M 15 29270866Simp#define HIX5HD2_FIXED_288M 16 30270866Simp#define HIX5HD2_FIXED_60M 17 31270866Simp#define HIX5HD2_FIXED_750M 18 32270866Simp#define HIX5HD2_FIXED_500M 19 33270866Simp#define HIX5HD2_FIXED_54M 20 34270866Simp#define HIX5HD2_FIXED_27M 21 35270866Simp#define HIX5HD2_FIXED_1500M 22 36270866Simp#define HIX5HD2_FIXED_375M 23 37270866Simp#define HIX5HD2_FIXED_187M 24 38270866Simp#define HIX5HD2_FIXED_250M 25 39270866Simp#define HIX5HD2_FIXED_125M 26 40270866Simp#define HIX5HD2_FIXED_2P02M 27 41270866Simp#define HIX5HD2_FIXED_50M 28 42270866Simp#define HIX5HD2_FIXED_25M 29 43270866Simp#define HIX5HD2_FIXED_83M 30 44270866Simp 45270866Simp/* mux clocks */ 46270866Simp#define HIX5HD2_SFC_MUX 64 47270866Simp#define HIX5HD2_MMC_MUX 65 48270866Simp#define HIX5HD2_FEPHY_MUX 66 49270866Simp 50270866Simp/* gate clocks */ 51270866Simp#define HIX5HD2_SFC_RST 128 52270866Simp#define HIX5HD2_SFC_CLK 129 53270866Simp#define HIX5HD2_MMC_CIU_CLK 130 54270866Simp#define HIX5HD2_MMC_BIU_CLK 131 55270866Simp#define HIX5HD2_MMC_CIU_RST 132 56270866Simp 57270866Simp#define HIX5HD2_NR_CLKS 256 58270866Simp#endif /* __DTS_HIX5HD2_CLOCK_H */ 59