exynos7-clk.h revision 279377
1279377Simp/* 2279377Simp * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3279377Simp * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4279377Simp * 5279377Simp * This program is free software; you can redistribute it and/or modify 6279377Simp * it under the terms of the GNU General Public License version 2 as 7279377Simp * published by the Free Software Foundation. 8279377Simp*/ 9279377Simp 10279377Simp#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H 11279377Simp#define _DT_BINDINGS_CLOCK_EXYNOS7_H 12279377Simp 13279377Simp/* TOPC */ 14279377Simp#define DOUT_ACLK_PERIS 1 15279377Simp#define DOUT_SCLK_BUS0_PLL 2 16279377Simp#define DOUT_SCLK_BUS1_PLL 3 17279377Simp#define DOUT_SCLK_CC_PLL 4 18279377Simp#define DOUT_SCLK_MFC_PLL 5 19279377Simp#define DOUT_ACLK_CCORE_133 6 20279377Simp#define DOUT_ACLK_MSCL_532 7 21279377Simp#define ACLK_MSCL_532 8 22279377Simp#define DOUT_SCLK_AUD_PLL 9 23279377Simp#define FOUT_AUD_PLL 10 24279377Simp#define TOPC_NR_CLK 11 25279377Simp 26279377Simp/* TOP0 */ 27279377Simp#define DOUT_ACLK_PERIC1 1 28279377Simp#define DOUT_ACLK_PERIC0 2 29279377Simp#define CLK_SCLK_UART0 3 30279377Simp#define CLK_SCLK_UART1 4 31279377Simp#define CLK_SCLK_UART2 5 32279377Simp#define CLK_SCLK_UART3 6 33279377Simp#define CLK_SCLK_SPI0 7 34279377Simp#define CLK_SCLK_SPI1 8 35279377Simp#define CLK_SCLK_SPI2 9 36279377Simp#define CLK_SCLK_SPI3 10 37279377Simp#define CLK_SCLK_SPI4 11 38279377Simp#define CLK_SCLK_SPDIF 12 39279377Simp#define CLK_SCLK_PCM1 13 40279377Simp#define CLK_SCLK_I2S1 14 41279377Simp#define TOP0_NR_CLK 15 42279377Simp 43279377Simp/* TOP1 */ 44279377Simp#define DOUT_ACLK_FSYS1_200 1 45279377Simp#define DOUT_ACLK_FSYS0_200 2 46279377Simp#define DOUT_SCLK_MMC2 3 47279377Simp#define DOUT_SCLK_MMC1 4 48279377Simp#define DOUT_SCLK_MMC0 5 49279377Simp#define CLK_SCLK_MMC2 6 50279377Simp#define CLK_SCLK_MMC1 7 51279377Simp#define CLK_SCLK_MMC0 8 52279377Simp#define TOP1_NR_CLK 9 53279377Simp 54279377Simp/* CCORE */ 55279377Simp#define PCLK_RTC 1 56279377Simp#define CCORE_NR_CLK 2 57279377Simp 58279377Simp/* PERIC0 */ 59279377Simp#define PCLK_UART0 1 60279377Simp#define SCLK_UART0 2 61279377Simp#define PCLK_HSI2C0 3 62279377Simp#define PCLK_HSI2C1 4 63279377Simp#define PCLK_HSI2C4 5 64279377Simp#define PCLK_HSI2C5 6 65279377Simp#define PCLK_HSI2C9 7 66279377Simp#define PCLK_HSI2C10 8 67279377Simp#define PCLK_HSI2C11 9 68279377Simp#define PCLK_PWM 10 69279377Simp#define SCLK_PWM 11 70279377Simp#define PCLK_ADCIF 12 71279377Simp#define PERIC0_NR_CLK 13 72279377Simp 73279377Simp/* PERIC1 */ 74279377Simp#define PCLK_UART1 1 75279377Simp#define PCLK_UART2 2 76279377Simp#define PCLK_UART3 3 77279377Simp#define SCLK_UART1 4 78279377Simp#define SCLK_UART2 5 79279377Simp#define SCLK_UART3 6 80279377Simp#define PCLK_HSI2C2 7 81279377Simp#define PCLK_HSI2C3 8 82279377Simp#define PCLK_HSI2C6 9 83279377Simp#define PCLK_HSI2C7 10 84279377Simp#define PCLK_HSI2C8 11 85279377Simp#define PCLK_SPI0 12 86279377Simp#define PCLK_SPI1 13 87279377Simp#define PCLK_SPI2 14 88279377Simp#define PCLK_SPI3 15 89279377Simp#define PCLK_SPI4 16 90279377Simp#define SCLK_SPI0 17 91279377Simp#define SCLK_SPI1 18 92279377Simp#define SCLK_SPI2 19 93279377Simp#define SCLK_SPI3 20 94279377Simp#define SCLK_SPI4 21 95279377Simp#define PCLK_I2S1 22 96279377Simp#define PCLK_PCM1 23 97279377Simp#define PCLK_SPDIF 24 98279377Simp#define SCLK_I2S1 25 99279377Simp#define SCLK_PCM1 26 100279377Simp#define SCLK_SPDIF 27 101279377Simp#define PERIC1_NR_CLK 28 102279377Simp 103279377Simp/* PERIS */ 104279377Simp#define PCLK_CHIPID 1 105279377Simp#define SCLK_CHIPID 2 106279377Simp#define PCLK_WDT 3 107279377Simp#define PCLK_TMU 4 108279377Simp#define SCLK_TMU 5 109279377Simp#define PERIS_NR_CLK 6 110279377Simp 111279377Simp/* FSYS0 */ 112279377Simp#define ACLK_MMC2 1 113279377Simp#define ACLK_AXIUS_USBDRD30X_FSYS0X 2 114279377Simp#define ACLK_USBDRD300 3 115279377Simp#define SCLK_USBDRD300_SUSPENDCLK 4 116279377Simp#define SCLK_USBDRD300_REFCLK 5 117279377Simp#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 118279377Simp#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 119279377Simp#define OSCCLK_PHY_CLKOUT_USB30_PHY 8 120279377Simp#define ACLK_PDMA0 9 121279377Simp#define ACLK_PDMA1 10 122279377Simp#define FSYS0_NR_CLK 11 123279377Simp 124279377Simp/* FSYS1 */ 125279377Simp#define ACLK_MMC1 1 126279377Simp#define ACLK_MMC0 2 127279377Simp#define FSYS1_NR_CLK 3 128279377Simp 129279377Simp/* MSCL */ 130279377Simp#define USERMUX_ACLK_MSCL_532 1 131279377Simp#define DOUT_PCLK_MSCL 2 132279377Simp#define ACLK_MSCL_0 3 133279377Simp#define ACLK_MSCL_1 4 134279377Simp#define ACLK_JPEG 5 135279377Simp#define ACLK_G2D 6 136279377Simp#define ACLK_LH_ASYNC_SI_MSCL_0 7 137279377Simp#define ACLK_LH_ASYNC_SI_MSCL_1 8 138279377Simp#define ACLK_AXI2ACEL_BRIDGE 9 139279377Simp#define ACLK_XIU_MSCLX_0 10 140279377Simp#define ACLK_XIU_MSCLX_1 11 141279377Simp#define ACLK_QE_MSCL_0 12 142279377Simp#define ACLK_QE_MSCL_1 13 143279377Simp#define ACLK_QE_JPEG 14 144279377Simp#define ACLK_QE_G2D 15 145279377Simp#define ACLK_PPMU_MSCL_0 16 146279377Simp#define ACLK_PPMU_MSCL_1 17 147279377Simp#define ACLK_MSCLNP_133 18 148279377Simp#define ACLK_AHB2APB_MSCL0P 19 149279377Simp#define ACLK_AHB2APB_MSCL1P 20 150279377Simp 151279377Simp#define PCLK_MSCL_0 21 152279377Simp#define PCLK_MSCL_1 22 153279377Simp#define PCLK_JPEG 23 154279377Simp#define PCLK_G2D 24 155279377Simp#define PCLK_QE_MSCL_0 25 156279377Simp#define PCLK_QE_MSCL_1 26 157279377Simp#define PCLK_QE_JPEG 27 158279377Simp#define PCLK_QE_G2D 28 159279377Simp#define PCLK_PPMU_MSCL_0 29 160279377Simp#define PCLK_PPMU_MSCL_1 30 161279377Simp#define PCLK_AXI2ACEL_BRIDGE 31 162279377Simp#define PCLK_PMU_MSCL 32 163279377Simp#define MSCL_NR_CLK 33 164279377Simp 165279377Simp/* AUD */ 166279377Simp#define SCLK_I2S 1 167279377Simp#define SCLK_PCM 2 168279377Simp#define PCLK_I2S 3 169279377Simp#define PCLK_PCM 4 170279377Simp#define ACLK_ADMA 5 171279377Simp#define AUD_NR_CLK 6 172279377Simp#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ 173