exynos5440.h revision 273712
10Sstevel@tonic-gate/*
20Sstevel@tonic-gate * Copyright (c) 2013 Samsung Electronics Co., Ltd.
30Sstevel@tonic-gate * Author: Andrzej Hajda <a.hajda@samsung.com>
40Sstevel@tonic-gate *
51772Sjl139090 * This program is free software; you can redistribute it and/or modify
61772Sjl139090 * it under the terms of the GNU General Public License version 2 as
70Sstevel@tonic-gate * published by the Free Software Foundation.
80Sstevel@tonic-gate *
90Sstevel@tonic-gate * Device Tree binding constants for Exynos5440 clock controller.
100Sstevel@tonic-gate*/
110Sstevel@tonic-gate
120Sstevel@tonic-gate#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H
130Sstevel@tonic-gate#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H
140Sstevel@tonic-gate
150Sstevel@tonic-gate#define CLK_XTAL		1
160Sstevel@tonic-gate#define CLK_ARM_CLK		2
170Sstevel@tonic-gate#define CLK_SPI_BAUD		16
180Sstevel@tonic-gate#define CLK_PB0_250		17
190Sstevel@tonic-gate#define CLK_PR0_250		18
200Sstevel@tonic-gate#define CLK_PR1_250		19
210Sstevel@tonic-gate#define CLK_B_250		20
2210841SAlan.Adamson@Sun.COM#define CLK_B_125		21
230Sstevel@tonic-gate#define CLK_B_200		22
240Sstevel@tonic-gate#define CLK_SATA		23
250Sstevel@tonic-gate#define CLK_USB			24
260Sstevel@tonic-gate#define CLK_GMAC0		25
270Sstevel@tonic-gate#define CLK_CS250		26
280Sstevel@tonic-gate#define CLK_PB0_250_O		27
290Sstevel@tonic-gate#define CLK_PR0_250_O		28
300Sstevel@tonic-gate#define CLK_PR1_250_O		29
310Sstevel@tonic-gate#define CLK_B_250_O		30
320Sstevel@tonic-gate#define CLK_B_125_O		31
330Sstevel@tonic-gate#define CLK_B_200_O		32
340Sstevel@tonic-gate#define CLK_SATA_O		33
353274Set142600#define CLK_USB_O		34
363274Set142600#define CLK_GMAC0_O		35
373274Set142600#define CLK_CS250_O		36
383274Set142600
393274Set142600/* must be greater than maximal clock id */
403274Set142600#define CLK_NR_CLKS		37
410Sstevel@tonic-gate
420Sstevel@tonic-gate#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */
430Sstevel@tonic-gate