exynos5420.h revision 273712
1262569Simp/* 2262569Simp * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3273712Sian * Author: Andrzej Hajda <a.hajda@samsung.com> 4262569Simp * 5262569Simp * This program is free software; you can redistribute it and/or modify 6262569Simp * it under the terms of the GNU General Public License version 2 as 7262569Simp * published by the Free Software Foundation. 8262569Simp * 9262569Simp * Device Tree binding constants for Exynos5420 clock controller. 10262569Simp*/ 11262569Simp 12262569Simp#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H 13262569Simp#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H 14262569Simp 15262569Simp/* core clocks */ 16262569Simp#define CLK_FIN_PLL 1 17262569Simp#define CLK_FOUT_APLL 2 18262569Simp#define CLK_FOUT_CPLL 3 19262569Simp#define CLK_FOUT_DPLL 4 20262569Simp#define CLK_FOUT_EPLL 5 21262569Simp#define CLK_FOUT_RPLL 6 22262569Simp#define CLK_FOUT_IPLL 7 23262569Simp#define CLK_FOUT_SPLL 8 24262569Simp#define CLK_FOUT_VPLL 9 25262569Simp#define CLK_FOUT_MPLL 10 26262569Simp#define CLK_FOUT_BPLL 11 27262569Simp#define CLK_FOUT_KPLL 12 28262569Simp 29262569Simp/* gate for special clocks (sclk) */ 30262569Simp#define CLK_SCLK_UART0 128 31262569Simp#define CLK_SCLK_UART1 129 32262569Simp#define CLK_SCLK_UART2 130 33262569Simp#define CLK_SCLK_UART3 131 34262569Simp#define CLK_SCLK_MMC0 132 35262569Simp#define CLK_SCLK_MMC1 133 36262569Simp#define CLK_SCLK_MMC2 134 37262569Simp#define CLK_SCLK_SPI0 135 38262569Simp#define CLK_SCLK_SPI1 136 39262569Simp#define CLK_SCLK_SPI2 137 40262569Simp#define CLK_SCLK_I2S1 138 41262569Simp#define CLK_SCLK_I2S2 139 42262569Simp#define CLK_SCLK_PCM1 140 43262569Simp#define CLK_SCLK_PCM2 141 44262569Simp#define CLK_SCLK_SPDIF 142 45262569Simp#define CLK_SCLK_HDMI 143 46262569Simp#define CLK_SCLK_PIXEL 144 47262569Simp#define CLK_SCLK_DP1 145 48262569Simp#define CLK_SCLK_MIPI1 146 49262569Simp#define CLK_SCLK_FIMD1 147 50262569Simp#define CLK_SCLK_MAUDIO0 148 51262569Simp#define CLK_SCLK_MAUPCM0 149 52262569Simp#define CLK_SCLK_USBD300 150 53262569Simp#define CLK_SCLK_USBD301 151 54262569Simp#define CLK_SCLK_USBPHY300 152 55262569Simp#define CLK_SCLK_USBPHY301 153 56262569Simp#define CLK_SCLK_UNIPRO 154 57262569Simp#define CLK_SCLK_PWM 155 58262569Simp#define CLK_SCLK_GSCL_WA 156 59262569Simp#define CLK_SCLK_GSCL_WB 157 60262569Simp#define CLK_SCLK_HDMIPHY 158 61273712Sian#define CLK_MAU_EPLL 159 62273712Sian#define CLK_SCLK_HSIC_12M 160 63273712Sian#define CLK_SCLK_MPHY_IXTAL24 161 64262569Simp 65262569Simp/* gate clocks */ 66262569Simp#define CLK_UART0 257 67262569Simp#define CLK_UART1 258 68262569Simp#define CLK_UART2 259 69262569Simp#define CLK_UART3 260 70262569Simp#define CLK_I2C0 261 71262569Simp#define CLK_I2C1 262 72262569Simp#define CLK_I2C2 263 73262569Simp#define CLK_I2C3 264 74273712Sian#define CLK_USI0 265 75273712Sian#define CLK_USI1 266 76273712Sian#define CLK_USI2 267 77273712Sian#define CLK_USI3 268 78262569Simp#define CLK_I2C_HDMI 269 79262569Simp#define CLK_TSADC 270 80262569Simp#define CLK_SPI0 271 81262569Simp#define CLK_SPI1 272 82262569Simp#define CLK_SPI2 273 83262569Simp#define CLK_KEYIF 274 84262569Simp#define CLK_I2S1 275 85262569Simp#define CLK_I2S2 276 86262569Simp#define CLK_PCM1 277 87262569Simp#define CLK_PCM2 278 88262569Simp#define CLK_PWM 279 89262569Simp#define CLK_SPDIF 280 90273712Sian#define CLK_USI4 281 91273712Sian#define CLK_USI5 282 92273712Sian#define CLK_USI6 283 93262569Simp#define CLK_ACLK66_PSGEN 300 94262569Simp#define CLK_CHIPID 301 95262569Simp#define CLK_SYSREG 302 96262569Simp#define CLK_TZPC0 303 97262569Simp#define CLK_TZPC1 304 98262569Simp#define CLK_TZPC2 305 99262569Simp#define CLK_TZPC3 306 100262569Simp#define CLK_TZPC4 307 101262569Simp#define CLK_TZPC5 308 102262569Simp#define CLK_TZPC6 309 103262569Simp#define CLK_TZPC7 310 104262569Simp#define CLK_TZPC8 311 105262569Simp#define CLK_TZPC9 312 106262569Simp#define CLK_HDMI_CEC 313 107262569Simp#define CLK_SECKEY 314 108262569Simp#define CLK_MCT 315 109262569Simp#define CLK_WDT 316 110262569Simp#define CLK_RTC 317 111262569Simp#define CLK_TMU 318 112262569Simp#define CLK_TMU_GPU 319 113262569Simp#define CLK_PCLK66_GPIO 330 114262569Simp#define CLK_ACLK200_FSYS2 350 115262569Simp#define CLK_MMC0 351 116262569Simp#define CLK_MMC1 352 117262569Simp#define CLK_MMC2 353 118262569Simp#define CLK_SROMC 354 119262569Simp#define CLK_UFS 355 120262569Simp#define CLK_ACLK200_FSYS 360 121262569Simp#define CLK_TSI 361 122262569Simp#define CLK_PDMA0 362 123262569Simp#define CLK_PDMA1 363 124262569Simp#define CLK_RTIC 364 125262569Simp#define CLK_USBH20 365 126262569Simp#define CLK_USBD300 366 127262569Simp#define CLK_USBD301 367 128262569Simp#define CLK_ACLK400_MSCL 380 129262569Simp#define CLK_MSCL0 381 130262569Simp#define CLK_MSCL1 382 131262569Simp#define CLK_MSCL2 383 132262569Simp#define CLK_SMMU_MSCL0 384 133262569Simp#define CLK_SMMU_MSCL1 385 134262569Simp#define CLK_SMMU_MSCL2 386 135262569Simp#define CLK_ACLK333 400 136262569Simp#define CLK_MFC 401 137262569Simp#define CLK_SMMU_MFCL 402 138262569Simp#define CLK_SMMU_MFCR 403 139262569Simp#define CLK_ACLK200_DISP1 410 140262569Simp#define CLK_DSIM1 411 141262569Simp#define CLK_DP1 412 142262569Simp#define CLK_HDMI 413 143262569Simp#define CLK_ACLK300_DISP1 420 144262569Simp#define CLK_FIMD1 421 145273712Sian#define CLK_SMMU_FIMD1M0 422 146273712Sian#define CLK_SMMU_FIMD1M1 423 147262569Simp#define CLK_ACLK166 430 148262569Simp#define CLK_MIXER 431 149262569Simp#define CLK_ACLK266 440 150262569Simp#define CLK_ROTATOR 441 151262569Simp#define CLK_MDMA1 442 152262569Simp#define CLK_SMMU_ROTATOR 443 153262569Simp#define CLK_SMMU_MDMA1 444 154262569Simp#define CLK_ACLK300_JPEG 450 155262569Simp#define CLK_JPEG 451 156262569Simp#define CLK_JPEG2 452 157262569Simp#define CLK_SMMU_JPEG 453 158273712Sian#define CLK_SMMU_JPEG2 454 159262569Simp#define CLK_ACLK300_GSCL 460 160262569Simp#define CLK_SMMU_GSCL0 461 161262569Simp#define CLK_SMMU_GSCL1 462 162262569Simp#define CLK_GSCL_WA 463 163262569Simp#define CLK_GSCL_WB 464 164262569Simp#define CLK_GSCL0 465 165262569Simp#define CLK_GSCL1 466 166273712Sian#define CLK_FIMC_3AA 467 167262569Simp#define CLK_ACLK266_G2D 470 168262569Simp#define CLK_SSS 471 169262569Simp#define CLK_SLIM_SSS 472 170262569Simp#define CLK_MDMA0 473 171262569Simp#define CLK_ACLK333_G2D 480 172262569Simp#define CLK_G2D 481 173262569Simp#define CLK_ACLK333_432_GSCL 490 174262569Simp#define CLK_SMMU_3AA 491 175262569Simp#define CLK_SMMU_FIMCL0 492 176262569Simp#define CLK_SMMU_FIMCL1 493 177262569Simp#define CLK_SMMU_FIMCL3 494 178262569Simp#define CLK_FIMC_LITE3 495 179273712Sian#define CLK_FIMC_LITE0 496 180273712Sian#define CLK_FIMC_LITE1 497 181262569Simp#define CLK_ACLK_G3D 500 182262569Simp#define CLK_G3D 501 183262569Simp#define CLK_SMMU_MIXER 502 184273712Sian#define CLK_SMMU_G2D 503 185273712Sian#define CLK_SMMU_MDMA0 504 186273712Sian#define CLK_MC 505 187273712Sian#define CLK_TOP_RTC 506 188273712Sian#define CLK_SCLK_UART_ISP 510 189273712Sian#define CLK_SCLK_SPI0_ISP 511 190273712Sian#define CLK_SCLK_SPI1_ISP 512 191273712Sian#define CLK_SCLK_PWM_ISP 513 192273712Sian#define CLK_SCLK_ISP_SENSOR0 514 193273712Sian#define CLK_SCLK_ISP_SENSOR1 515 194273712Sian#define CLK_SCLK_ISP_SENSOR2 516 195273712Sian#define CLK_ACLK432_SCALER 517 196273712Sian#define CLK_ACLK432_CAM 518 197273712Sian#define CLK_ACLK_FL1550_CAM 519 198273712Sian#define CLK_ACLK550_CAM 520 199262569Simp 200262569Simp/* mux clocks */ 201262569Simp#define CLK_MOUT_HDMI 640 202273712Sian#define CLK_MOUT_G3D 641 203273712Sian#define CLK_MOUT_VPLL 642 204273712Sian#define CLK_MOUT_MAUDIO0 643 205273712Sian#define CLK_MOUT_USER_ACLK333 644 206273712Sian#define CLK_MOUT_SW_ACLK333 645 207262569Simp 208262569Simp/* divider clocks */ 209262569Simp#define CLK_DOUT_PIXEL 768 210262569Simp 211262569Simp/* must be greater than maximal clock id */ 212262569Simp#define CLK_NR_CLKS 769 213262569Simp 214262569Simp#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ 215