exynos5420.h revision 262569
1262569Simp/* 2262569Simp * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3262569Simp * Author: Andrzej Haja <a.hajda@samsung.com> 4262569Simp * 5262569Simp * This program is free software; you can redistribute it and/or modify 6262569Simp * it under the terms of the GNU General Public License version 2 as 7262569Simp * published by the Free Software Foundation. 8262569Simp * 9262569Simp * Device Tree binding constants for Exynos5420 clock controller. 10262569Simp*/ 11262569Simp 12262569Simp#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H 13262569Simp#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H 14262569Simp 15262569Simp/* core clocks */ 16262569Simp#define CLK_FIN_PLL 1 17262569Simp#define CLK_FOUT_APLL 2 18262569Simp#define CLK_FOUT_CPLL 3 19262569Simp#define CLK_FOUT_DPLL 4 20262569Simp#define CLK_FOUT_EPLL 5 21262569Simp#define CLK_FOUT_RPLL 6 22262569Simp#define CLK_FOUT_IPLL 7 23262569Simp#define CLK_FOUT_SPLL 8 24262569Simp#define CLK_FOUT_VPLL 9 25262569Simp#define CLK_FOUT_MPLL 10 26262569Simp#define CLK_FOUT_BPLL 11 27262569Simp#define CLK_FOUT_KPLL 12 28262569Simp 29262569Simp/* gate for special clocks (sclk) */ 30262569Simp#define CLK_SCLK_UART0 128 31262569Simp#define CLK_SCLK_UART1 129 32262569Simp#define CLK_SCLK_UART2 130 33262569Simp#define CLK_SCLK_UART3 131 34262569Simp#define CLK_SCLK_MMC0 132 35262569Simp#define CLK_SCLK_MMC1 133 36262569Simp#define CLK_SCLK_MMC2 134 37262569Simp#define CLK_SCLK_SPI0 135 38262569Simp#define CLK_SCLK_SPI1 136 39262569Simp#define CLK_SCLK_SPI2 137 40262569Simp#define CLK_SCLK_I2S1 138 41262569Simp#define CLK_SCLK_I2S2 139 42262569Simp#define CLK_SCLK_PCM1 140 43262569Simp#define CLK_SCLK_PCM2 141 44262569Simp#define CLK_SCLK_SPDIF 142 45262569Simp#define CLK_SCLK_HDMI 143 46262569Simp#define CLK_SCLK_PIXEL 144 47262569Simp#define CLK_SCLK_DP1 145 48262569Simp#define CLK_SCLK_MIPI1 146 49262569Simp#define CLK_SCLK_FIMD1 147 50262569Simp#define CLK_SCLK_MAUDIO0 148 51262569Simp#define CLK_SCLK_MAUPCM0 149 52262569Simp#define CLK_SCLK_USBD300 150 53262569Simp#define CLK_SCLK_USBD301 151 54262569Simp#define CLK_SCLK_USBPHY300 152 55262569Simp#define CLK_SCLK_USBPHY301 153 56262569Simp#define CLK_SCLK_UNIPRO 154 57262569Simp#define CLK_SCLK_PWM 155 58262569Simp#define CLK_SCLK_GSCL_WA 156 59262569Simp#define CLK_SCLK_GSCL_WB 157 60262569Simp#define CLK_SCLK_HDMIPHY 158 61262569Simp 62262569Simp/* gate clocks */ 63262569Simp#define CLK_ACLK66_PERIC 256 64262569Simp#define CLK_UART0 257 65262569Simp#define CLK_UART1 258 66262569Simp#define CLK_UART2 259 67262569Simp#define CLK_UART3 260 68262569Simp#define CLK_I2C0 261 69262569Simp#define CLK_I2C1 262 70262569Simp#define CLK_I2C2 263 71262569Simp#define CLK_I2C3 264 72262569Simp#define CLK_I2C4 265 73262569Simp#define CLK_I2C5 266 74262569Simp#define CLK_I2C6 267 75262569Simp#define CLK_I2C7 268 76262569Simp#define CLK_I2C_HDMI 269 77262569Simp#define CLK_TSADC 270 78262569Simp#define CLK_SPI0 271 79262569Simp#define CLK_SPI1 272 80262569Simp#define CLK_SPI2 273 81262569Simp#define CLK_KEYIF 274 82262569Simp#define CLK_I2S1 275 83262569Simp#define CLK_I2S2 276 84262569Simp#define CLK_PCM1 277 85262569Simp#define CLK_PCM2 278 86262569Simp#define CLK_PWM 279 87262569Simp#define CLK_SPDIF 280 88262569Simp#define CLK_I2C8 281 89262569Simp#define CLK_I2C9 282 90262569Simp#define CLK_I2C10 283 91262569Simp#define CLK_ACLK66_PSGEN 300 92262569Simp#define CLK_CHIPID 301 93262569Simp#define CLK_SYSREG 302 94262569Simp#define CLK_TZPC0 303 95262569Simp#define CLK_TZPC1 304 96262569Simp#define CLK_TZPC2 305 97262569Simp#define CLK_TZPC3 306 98262569Simp#define CLK_TZPC4 307 99262569Simp#define CLK_TZPC5 308 100262569Simp#define CLK_TZPC6 309 101262569Simp#define CLK_TZPC7 310 102262569Simp#define CLK_TZPC8 311 103262569Simp#define CLK_TZPC9 312 104262569Simp#define CLK_HDMI_CEC 313 105262569Simp#define CLK_SECKEY 314 106262569Simp#define CLK_MCT 315 107262569Simp#define CLK_WDT 316 108262569Simp#define CLK_RTC 317 109262569Simp#define CLK_TMU 318 110262569Simp#define CLK_TMU_GPU 319 111262569Simp#define CLK_PCLK66_GPIO 330 112262569Simp#define CLK_ACLK200_FSYS2 350 113262569Simp#define CLK_MMC0 351 114262569Simp#define CLK_MMC1 352 115262569Simp#define CLK_MMC2 353 116262569Simp#define CLK_SROMC 354 117262569Simp#define CLK_UFS 355 118262569Simp#define CLK_ACLK200_FSYS 360 119262569Simp#define CLK_TSI 361 120262569Simp#define CLK_PDMA0 362 121262569Simp#define CLK_PDMA1 363 122262569Simp#define CLK_RTIC 364 123262569Simp#define CLK_USBH20 365 124262569Simp#define CLK_USBD300 366 125262569Simp#define CLK_USBD301 367 126262569Simp#define CLK_ACLK400_MSCL 380 127262569Simp#define CLK_MSCL0 381 128262569Simp#define CLK_MSCL1 382 129262569Simp#define CLK_MSCL2 383 130262569Simp#define CLK_SMMU_MSCL0 384 131262569Simp#define CLK_SMMU_MSCL1 385 132262569Simp#define CLK_SMMU_MSCL2 386 133262569Simp#define CLK_ACLK333 400 134262569Simp#define CLK_MFC 401 135262569Simp#define CLK_SMMU_MFCL 402 136262569Simp#define CLK_SMMU_MFCR 403 137262569Simp#define CLK_ACLK200_DISP1 410 138262569Simp#define CLK_DSIM1 411 139262569Simp#define CLK_DP1 412 140262569Simp#define CLK_HDMI 413 141262569Simp#define CLK_ACLK300_DISP1 420 142262569Simp#define CLK_FIMD1 421 143262569Simp#define CLK_SMMU_FIMD1 422 144262569Simp#define CLK_ACLK166 430 145262569Simp#define CLK_MIXER 431 146262569Simp#define CLK_ACLK266 440 147262569Simp#define CLK_ROTATOR 441 148262569Simp#define CLK_MDMA1 442 149262569Simp#define CLK_SMMU_ROTATOR 443 150262569Simp#define CLK_SMMU_MDMA1 444 151262569Simp#define CLK_ACLK300_JPEG 450 152262569Simp#define CLK_JPEG 451 153262569Simp#define CLK_JPEG2 452 154262569Simp#define CLK_SMMU_JPEG 453 155262569Simp#define CLK_ACLK300_GSCL 460 156262569Simp#define CLK_SMMU_GSCL0 461 157262569Simp#define CLK_SMMU_GSCL1 462 158262569Simp#define CLK_GSCL_WA 463 159262569Simp#define CLK_GSCL_WB 464 160262569Simp#define CLK_GSCL0 465 161262569Simp#define CLK_GSCL1 466 162262569Simp#define CLK_CLK_3AA 467 163262569Simp#define CLK_ACLK266_G2D 470 164262569Simp#define CLK_SSS 471 165262569Simp#define CLK_SLIM_SSS 472 166262569Simp#define CLK_MDMA0 473 167262569Simp#define CLK_ACLK333_G2D 480 168262569Simp#define CLK_G2D 481 169262569Simp#define CLK_ACLK333_432_GSCL 490 170262569Simp#define CLK_SMMU_3AA 491 171262569Simp#define CLK_SMMU_FIMCL0 492 172262569Simp#define CLK_SMMU_FIMCL1 493 173262569Simp#define CLK_SMMU_FIMCL3 494 174262569Simp#define CLK_FIMC_LITE3 495 175262569Simp#define CLK_ACLK_G3D 500 176262569Simp#define CLK_G3D 501 177262569Simp#define CLK_SMMU_MIXER 502 178262569Simp 179262569Simp/* mux clocks */ 180262569Simp#define CLK_MOUT_HDMI 640 181262569Simp 182262569Simp/* divider clocks */ 183262569Simp#define CLK_DOUT_PIXEL 768 184262569Simp 185262569Simp/* must be greater than maximal clock id */ 186262569Simp#define CLK_NR_CLKS 769 187262569Simp 188262569Simp#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ 189