exynos5260-clk.h revision 270866
1270866Simp/* 2270866Simp * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3270866Simp * Author: Rahul Sharma <rahul.sharma@samsung.com> 4270866Simp * 5270866Simp * This program is free software; you can redistribute it and/or modify 6270866Simp * it under the terms of the GNU General Public License version 2 as 7270866Simp * published by the Free Software Foundation. 8270866Simp * 9270866Simp * Provides Constants for Exynos5260 clocks. 10270866Simp*/ 11270866Simp 12270866Simp#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H 13270866Simp#define _DT_BINDINGS_CLK_EXYNOS5260_H 14270866Simp 15270866Simp/* Clock names: <cmu><type><IP> */ 16270866Simp 17270866Simp/* List Of Clocks For CMU_TOP */ 18270866Simp 19270866Simp#define TOP_FOUT_DISP_PLL 1 20270866Simp#define TOP_FOUT_AUD_PLL 2 21270866Simp#define TOP_MOUT_AUDTOP_PLL_USER 3 22270866Simp#define TOP_MOUT_AUD_PLL 4 23270866Simp#define TOP_MOUT_DISP_PLL 5 24270866Simp#define TOP_MOUT_BUSTOP_PLL_USER 6 25270866Simp#define TOP_MOUT_MEMTOP_PLL_USER 7 26270866Simp#define TOP_MOUT_MEDIATOP_PLL_USER 8 27270866Simp#define TOP_MOUT_DISP_DISP_333 9 28270866Simp#define TOP_MOUT_ACLK_DISP_333 10 29270866Simp#define TOP_MOUT_DISP_DISP_222 11 30270866Simp#define TOP_MOUT_ACLK_DISP_222 12 31270866Simp#define TOP_MOUT_DISP_MEDIA_PIXEL 13 32270866Simp#define TOP_MOUT_FIMD1 14 33270866Simp#define TOP_MOUT_SCLK_PERI_SPI0_CLK 15 34270866Simp#define TOP_MOUT_SCLK_PERI_SPI1_CLK 16 35270866Simp#define TOP_MOUT_SCLK_PERI_SPI2_CLK 17 36270866Simp#define TOP_MOUT_SCLK_PERI_UART0_UCLK 18 37270866Simp#define TOP_MOUT_SCLK_PERI_UART2_UCLK 19 38270866Simp#define TOP_MOUT_SCLK_PERI_UART1_UCLK 20 39270866Simp#define TOP_MOUT_BUS4_BUSTOP_100 21 40270866Simp#define TOP_MOUT_BUS4_BUSTOP_400 22 41270866Simp#define TOP_MOUT_BUS3_BUSTOP_100 23 42270866Simp#define TOP_MOUT_BUS3_BUSTOP_400 24 43270866Simp#define TOP_MOUT_BUS2_BUSTOP_400 25 44270866Simp#define TOP_MOUT_BUS2_BUSTOP_100 26 45270866Simp#define TOP_MOUT_BUS1_BUSTOP_100 27 46270866Simp#define TOP_MOUT_BUS1_BUSTOP_400 28 47270866Simp#define TOP_MOUT_SCLK_FSYS_USB 29 48270866Simp#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30 49270866Simp#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31 50270866Simp#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32 51270866Simp#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33 52270866Simp#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34 53270866Simp#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35 54270866Simp#define TOP_MOUT_ACLK_ISP1_266 36 55270866Simp#define TOP_MOUT_ISP1_MEDIA_266 37 56270866Simp#define TOP_MOUT_ACLK_ISP1_400 38 57270866Simp#define TOP_MOUT_ISP1_MEDIA_400 39 58270866Simp#define TOP_MOUT_SCLK_ISP1_SPI0 40 59270866Simp#define TOP_MOUT_SCLK_ISP1_SPI1 41 60270866Simp#define TOP_MOUT_SCLK_ISP1_UART 42 61270866Simp#define TOP_MOUT_SCLK_ISP1_SENSOR2 43 62270866Simp#define TOP_MOUT_SCLK_ISP1_SENSOR1 44 63270866Simp#define TOP_MOUT_SCLK_ISP1_SENSOR0 45 64270866Simp#define TOP_MOUT_ACLK_MFC_333 46 65270866Simp#define TOP_MOUT_MFC_BUSTOP_333 47 66270866Simp#define TOP_MOUT_ACLK_G2D_333 48 67270866Simp#define TOP_MOUT_G2D_BUSTOP_333 49 68270866Simp#define TOP_MOUT_ACLK_GSCL_FIMC 50 69270866Simp#define TOP_MOUT_GSCL_BUSTOP_FIMC 51 70270866Simp#define TOP_MOUT_ACLK_GSCL_333 52 71270866Simp#define TOP_MOUT_GSCL_BUSTOP_333 53 72270866Simp#define TOP_MOUT_ACLK_GSCL_400 54 73270866Simp#define TOP_MOUT_M2M_MEDIATOP_400 55 74270866Simp#define TOP_DOUT_ACLK_MFC_333 56 75270866Simp#define TOP_DOUT_ACLK_G2D_333 57 76270866Simp#define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58 77270866Simp#define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59 78270866Simp#define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60 79270866Simp#define TOP_DOUT_ACLK_GSCL_FIMC 61 80270866Simp#define TOP_DOUT_ACLK_GSCL_400 62 81270866Simp#define TOP_DOUT_ACLK_GSCL_333 63 82270866Simp#define TOP_DOUT_SCLK_ISP1_SPI0_B 64 83270866Simp#define TOP_DOUT_SCLK_ISP1_SPI0_A 65 84270866Simp#define TOP_DOUT_ACLK_ISP1_400 66 85270866Simp#define TOP_DOUT_ACLK_ISP1_266 67 86270866Simp#define TOP_DOUT_SCLK_ISP1_UART 68 87270866Simp#define TOP_DOUT_SCLK_ISP1_SPI1_B 69 88270866Simp#define TOP_DOUT_SCLK_ISP1_SPI1_A 70 89270866Simp#define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71 90270866Simp#define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72 91270866Simp#define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73 92270866Simp#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74 93270866Simp#define TOP_DOUT_SCLK_DISP_PIXEL 75 94270866Simp#define TOP_DOUT_ACLK_DISP_222 76 95270866Simp#define TOP_DOUT_ACLK_DISP_333 77 96270866Simp#define TOP_DOUT_ACLK_BUS4_100 78 97270866Simp#define TOP_DOUT_ACLK_BUS4_400 79 98270866Simp#define TOP_DOUT_ACLK_BUS3_100 80 99270866Simp#define TOP_DOUT_ACLK_BUS3_400 81 100270866Simp#define TOP_DOUT_ACLK_BUS2_100 82 101270866Simp#define TOP_DOUT_ACLK_BUS2_400 83 102270866Simp#define TOP_DOUT_ACLK_BUS1_100 84 103270866Simp#define TOP_DOUT_ACLK_BUS1_400 85 104270866Simp#define TOP_DOUT_SCLK_PERI_SPI1_B 86 105270866Simp#define TOP_DOUT_SCLK_PERI_SPI1_A 87 106270866Simp#define TOP_DOUT_SCLK_PERI_SPI0_B 88 107270866Simp#define TOP_DOUT_SCLK_PERI_SPI0_A 89 108270866Simp#define TOP_DOUT_SCLK_PERI_UART0 90 109270866Simp#define TOP_DOUT_SCLK_PERI_UART2 91 110270866Simp#define TOP_DOUT_SCLK_PERI_UART1 92 111270866Simp#define TOP_DOUT_SCLK_PERI_SPI2_B 93 112270866Simp#define TOP_DOUT_SCLK_PERI_SPI2_A 94 113270866Simp#define TOP_DOUT_ACLK_PERI_AUD 95 114270866Simp#define TOP_DOUT_ACLK_PERI_66 96 115270866Simp#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97 116270866Simp#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98 117270866Simp#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99 118270866Simp#define TOP_DOUT_ACLK_FSYS_200 100 119270866Simp#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101 120270866Simp#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102 121270866Simp#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103 122270866Simp#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104 123270866Simp#define TOP_SCLK_FIMD1 105 124270866Simp#define TOP_SCLK_MMC2 106 125270866Simp#define TOP_SCLK_MMC1 107 126270866Simp#define TOP_SCLK_MMC0 108 127270866Simp#define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109 128270866Simp#define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110 129270866Simp#define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111 130270866Simp#define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112 131270866Simp#define phyclk_hdmi_phy_tmds_clko 113 132270866Simp#define PHYCLK_HDMI_PHY_PIXEL_CLKO 114 133270866Simp#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115 134270866Simp#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116 135270866Simp#define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117 136270866Simp#define PHYCLK_DPTX_PHY_CLK_DIV2 118 137270866Simp#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119 138270866Simp#define PHYCLK_USBHOST20_PHY_PHYCLOCK 120 139270866Simp#define PHYCLK_USBHOST20_PHY_FREECLK 121 140270866Simp#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122 141270866Simp#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123 142270866Simp#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124 143270866Simp#define TOP_NR_CLK 125 144270866Simp 145270866Simp 146270866Simp/* List Of Clocks For CMU_EGL */ 147270866Simp 148270866Simp#define EGL_FOUT_EGL_PLL 1 149270866Simp#define EGL_FOUT_EGL_DPLL 2 150270866Simp#define EGL_MOUT_EGL_B 3 151270866Simp#define EGL_MOUT_EGL_PLL 4 152270866Simp#define EGL_DOUT_EGL_PLL 5 153270866Simp#define EGL_DOUT_EGL_PCLK_DBG 6 154270866Simp#define EGL_DOUT_EGL_ATCLK 7 155270866Simp#define EGL_DOUT_PCLK_EGL 8 156270866Simp#define EGL_DOUT_ACLK_EGL 9 157270866Simp#define EGL_DOUT_EGL2 10 158270866Simp#define EGL_DOUT_EGL1 11 159270866Simp#define EGL_NR_CLK 12 160270866Simp 161270866Simp 162270866Simp/* List Of Clocks For CMU_KFC */ 163270866Simp 164270866Simp#define KFC_FOUT_KFC_PLL 1 165270866Simp#define KFC_MOUT_KFC_PLL 2 166270866Simp#define KFC_MOUT_KFC 3 167270866Simp#define KFC_DOUT_KFC_PLL 4 168270866Simp#define KFC_DOUT_PCLK_KFC 5 169270866Simp#define KFC_DOUT_ACLK_KFC 6 170270866Simp#define KFC_DOUT_KFC_PCLK_DBG 7 171270866Simp#define KFC_DOUT_KFC_ATCLK 8 172270866Simp#define KFC_DOUT_KFC2 9 173270866Simp#define KFC_DOUT_KFC1 10 174270866Simp#define KFC_NR_CLK 11 175270866Simp 176270866Simp 177270866Simp/* List Of Clocks For CMU_MIF */ 178270866Simp 179270866Simp#define MIF_FOUT_MEM_PLL 1 180270866Simp#define MIF_FOUT_MEDIA_PLL 2 181270866Simp#define MIF_FOUT_BUS_PLL 3 182270866Simp#define MIF_MOUT_CLK2X_PHY 4 183270866Simp#define MIF_MOUT_MIF_DREX2X 5 184270866Simp#define MIF_MOUT_CLKM_PHY 6 185270866Simp#define MIF_MOUT_MIF_DREX 7 186270866Simp#define MIF_MOUT_MEDIA_PLL 8 187270866Simp#define MIF_MOUT_BUS_PLL 9 188270866Simp#define MIF_MOUT_MEM_PLL 10 189270866Simp#define MIF_DOUT_ACLK_BUS_100 11 190270866Simp#define MIF_DOUT_ACLK_BUS_200 12 191270866Simp#define MIF_DOUT_ACLK_MIF_466 13 192270866Simp#define MIF_DOUT_CLK2X_PHY 14 193270866Simp#define MIF_DOUT_CLKM_PHY 15 194270866Simp#define MIF_DOUT_BUS_PLL 16 195270866Simp#define MIF_DOUT_MEM_PLL 17 196270866Simp#define MIF_DOUT_MEDIA_PLL 18 197270866Simp#define MIF_CLK_LPDDR3PHY_WRAP1 19 198270866Simp#define MIF_CLK_LPDDR3PHY_WRAP0 20 199270866Simp#define MIF_CLK_MONOCNT 21 200270866Simp#define MIF_CLK_MIF_RTC 22 201270866Simp#define MIF_CLK_DREX1 23 202270866Simp#define MIF_CLK_DREX0 24 203270866Simp#define MIF_CLK_INTMEM 25 204270866Simp#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26 205270866Simp#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 206270866Simp#define MIF_NR_CLK 28 207270866Simp 208270866Simp 209270866Simp/* List Of Clocks For CMU_G3D */ 210270866Simp 211270866Simp#define G3D_FOUT_G3D_PLL 1 212270866Simp#define G3D_MOUT_G3D_PLL 2 213270866Simp#define G3D_DOUT_PCLK_G3D 3 214270866Simp#define G3D_DOUT_ACLK_G3D 4 215270866Simp#define G3D_CLK_G3D_HPM 5 216270866Simp#define G3D_CLK_G3D 6 217270866Simp#define G3D_NR_CLK 7 218270866Simp 219270866Simp 220270866Simp/* List Of Clocks For CMU_AUD */ 221270866Simp 222270866Simp#define AUD_MOUT_SCLK_AUD_PCM 1 223270866Simp#define AUD_MOUT_SCLK_AUD_I2S 2 224270866Simp#define AUD_MOUT_AUD_PLL_USER 3 225270866Simp#define AUD_DOUT_ACLK_AUD_131 4 226270866Simp#define AUD_DOUT_SCLK_AUD_UART 5 227270866Simp#define AUD_DOUT_SCLK_AUD_PCM 6 228270866Simp#define AUD_DOUT_SCLK_AUD_I2S 7 229270866Simp#define AUD_CLK_AUD_UART 8 230270866Simp#define AUD_CLK_PCM 9 231270866Simp#define AUD_CLK_I2S 10 232270866Simp#define AUD_CLK_DMAC 11 233270866Simp#define AUD_CLK_SRAMC 12 234270866Simp#define AUD_SCLK_AUD_UART 13 235270866Simp#define AUD_SCLK_PCM 14 236270866Simp#define AUD_SCLK_I2S 15 237270866Simp#define AUD_NR_CLK 16 238270866Simp 239270866Simp 240270866Simp/* List Of Clocks For CMU_MFC */ 241270866Simp 242270866Simp#define MFC_MOUT_ACLK_MFC_333_USER 1 243270866Simp#define MFC_DOUT_PCLK_MFC_83 2 244270866Simp#define MFC_CLK_MFC 3 245270866Simp#define MFC_CLK_SMMU2_MFCM1 4 246270866Simp#define MFC_CLK_SMMU2_MFCM0 5 247270866Simp#define MFC_NR_CLK 6 248270866Simp 249270866Simp 250270866Simp/* List Of Clocks For CMU_GSCL */ 251270866Simp 252270866Simp#define GSCL_MOUT_ACLK_CSIS 1 253270866Simp#define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2 254270866Simp#define GSCL_MOUT_ACLK_M2M_400_USER 3 255270866Simp#define GSCL_MOUT_ACLK_GSCL_333_USER 4 256270866Simp#define GSCL_DOUT_ACLK_CSIS_200 5 257270866Simp#define GSCL_DOUT_PCLK_M2M_100 6 258270866Simp#define GSCL_CLK_PIXEL_GSCL1 7 259270866Simp#define GSCL_CLK_PIXEL_GSCL0 8 260270866Simp#define GSCL_CLK_MSCL1 9 261270866Simp#define GSCL_CLK_MSCL0 10 262270866Simp#define GSCL_CLK_GSCL1 11 263270866Simp#define GSCL_CLK_GSCL0 12 264270866Simp#define GSCL_CLK_FIMC_LITE_D 13 265270866Simp#define GSCL_CLK_FIMC_LITE_B 14 266270866Simp#define GSCL_CLK_FIMC_LITE_A 15 267270866Simp#define GSCL_CLK_CSIS1 16 268270866Simp#define GSCL_CLK_CSIS0 17 269270866Simp#define GSCL_CLK_SMMU3_LITE_D 18 270270866Simp#define GSCL_CLK_SMMU3_LITE_B 19 271270866Simp#define GSCL_CLK_SMMU3_LITE_A 20 272270866Simp#define GSCL_CLK_SMMU3_GSCL0 21 273270866Simp#define GSCL_CLK_SMMU3_GSCL1 22 274270866Simp#define GSCL_CLK_SMMU3_MSCL0 23 275270866Simp#define GSCL_CLK_SMMU3_MSCL1 24 276270866Simp#define GSCL_SCLK_CSIS1_WRAP 25 277270866Simp#define GSCL_SCLK_CSIS0_WRAP 26 278270866Simp#define GSCL_NR_CLK 27 279270866Simp 280270866Simp 281270866Simp/* List Of Clocks For CMU_FSYS */ 282270866Simp 283270866Simp#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1 284270866Simp#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2 285270866Simp#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3 286270866Simp#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4 287270866Simp#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5 288270866Simp#define FSYS_CLK_TSI 6 289270866Simp#define FSYS_CLK_USBLINK 7 290270866Simp#define FSYS_CLK_USBHOST20 8 291270866Simp#define FSYS_CLK_USBDRD30 9 292270866Simp#define FSYS_CLK_SROMC 10 293270866Simp#define FSYS_CLK_PDMA 11 294270866Simp#define FSYS_CLK_MMC2 12 295270866Simp#define FSYS_CLK_MMC1 13 296270866Simp#define FSYS_CLK_MMC0 14 297270866Simp#define FSYS_CLK_RTIC 15 298270866Simp#define FSYS_CLK_SMMU_RTIC 16 299270866Simp#define FSYS_PHYCLK_USBDRD30 17 300270866Simp#define FSYS_PHYCLK_USBHOST20 18 301270866Simp#define FSYS_NR_CLK 19 302270866Simp 303270866Simp 304270866Simp/* List Of Clocks For CMU_PERI */ 305270866Simp 306270866Simp#define PERI_MOUT_SCLK_SPDIF 1 307270866Simp#define PERI_MOUT_SCLK_I2SCOD 2 308270866Simp#define PERI_MOUT_SCLK_PCM 3 309270866Simp#define PERI_DOUT_I2S 4 310270866Simp#define PERI_DOUT_PCM 5 311270866Simp#define PERI_CLK_WDT_KFC 6 312270866Simp#define PERI_CLK_WDT_EGL 7 313270866Simp#define PERI_CLK_HSIC3 8 314270866Simp#define PERI_CLK_HSIC2 9 315270866Simp#define PERI_CLK_HSIC1 10 316270866Simp#define PERI_CLK_HSIC0 11 317270866Simp#define PERI_CLK_PCM 12 318270866Simp#define PERI_CLK_MCT 13 319270866Simp#define PERI_CLK_I2S 14 320270866Simp#define PERI_CLK_I2CHDMI 15 321270866Simp#define PERI_CLK_I2C7 16 322270866Simp#define PERI_CLK_I2C6 17 323270866Simp#define PERI_CLK_I2C5 18 324270866Simp#define PERI_CLK_I2C4 19 325270866Simp#define PERI_CLK_I2C9 20 326270866Simp#define PERI_CLK_I2C8 21 327270866Simp#define PERI_CLK_I2C11 22 328270866Simp#define PERI_CLK_I2C10 23 329270866Simp#define PERI_CLK_HDMICEC 24 330270866Simp#define PERI_CLK_EFUSE_WRITER 25 331270866Simp#define PERI_CLK_ABB 26 332270866Simp#define PERI_CLK_UART2 27 333270866Simp#define PERI_CLK_UART1 28 334270866Simp#define PERI_CLK_UART0 29 335270866Simp#define PERI_CLK_ADC 30 336270866Simp#define PERI_CLK_TMU4 31 337270866Simp#define PERI_CLK_TMU3 32 338270866Simp#define PERI_CLK_TMU2 33 339270866Simp#define PERI_CLK_TMU1 34 340270866Simp#define PERI_CLK_TMU0 35 341270866Simp#define PERI_CLK_SPI2 36 342270866Simp#define PERI_CLK_SPI1 37 343270866Simp#define PERI_CLK_SPI0 38 344270866Simp#define PERI_CLK_SPDIF 39 345270866Simp#define PERI_CLK_PWM 40 346270866Simp#define PERI_CLK_UART4 41 347270866Simp#define PERI_CLK_CHIPID 42 348270866Simp#define PERI_CLK_PROVKEY0 43 349270866Simp#define PERI_CLK_PROVKEY1 44 350270866Simp#define PERI_CLK_SECKEY 45 351270866Simp#define PERI_CLK_TOP_RTC 46 352270866Simp#define PERI_CLK_TZPC10 47 353270866Simp#define PERI_CLK_TZPC9 48 354270866Simp#define PERI_CLK_TZPC8 49 355270866Simp#define PERI_CLK_TZPC7 50 356270866Simp#define PERI_CLK_TZPC6 51 357270866Simp#define PERI_CLK_TZPC5 52 358270866Simp#define PERI_CLK_TZPC4 53 359270866Simp#define PERI_CLK_TZPC3 54 360270866Simp#define PERI_CLK_TZPC2 55 361270866Simp#define PERI_CLK_TZPC1 56 362270866Simp#define PERI_CLK_TZPC0 57 363270866Simp#define PERI_SCLK_UART2 58 364270866Simp#define PERI_SCLK_UART1 59 365270866Simp#define PERI_SCLK_UART0 60 366270866Simp#define PERI_SCLK_SPI2 61 367270866Simp#define PERI_SCLK_SPI1 62 368270866Simp#define PERI_SCLK_SPI0 63 369270866Simp#define PERI_SCLK_SPDIF 64 370270866Simp#define PERI_SCLK_I2S 65 371270866Simp#define PERI_SCLK_PCM1 66 372270866Simp#define PERI_NR_CLK 67 373270866Simp 374270866Simp 375270866Simp/* List Of Clocks For CMU_DISP */ 376270866Simp 377270866Simp#define DISP_MOUT_SCLK_HDMI_SPDIF 1 378270866Simp#define DISP_MOUT_SCLK_HDMI_PIXEL 2 379270866Simp#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3 380270866Simp#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4 381270866Simp#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5 382270866Simp#define DISP_MOUT_HDMI_PHY_PIXEL 6 383270866Simp#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7 384270866Simp#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8 385270866Simp#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9 386270866Simp#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10 387270866Simp#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11 388270866Simp#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12 389270866Simp#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13 390270866Simp#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14 391270866Simp#define DISP_MOUT_ACLK_DISP_222_USER 15 392270866Simp#define DISP_MOUT_SCLK_DISP_PIXEL_USER 16 393270866Simp#define DISP_MOUT_ACLK_DISP_333_USER 17 394270866Simp#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18 395270866Simp#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19 396270866Simp#define DISP_DOUT_PCLK_DISP_111 20 397270866Simp#define DISP_CLK_SMMU_TV 21 398270866Simp#define DISP_CLK_SMMU_FIMD1M1 22 399270866Simp#define DISP_CLK_SMMU_FIMD1M0 23 400270866Simp#define DISP_CLK_PIXEL_MIXER 24 401270866Simp#define DISP_CLK_PIXEL_DISP 25 402270866Simp#define DISP_CLK_MIXER 26 403270866Simp#define DISP_CLK_MIPIPHY 27 404270866Simp#define DISP_CLK_HDMIPHY 28 405270866Simp#define DISP_CLK_HDMI 29 406270866Simp#define DISP_CLK_FIMD1 30 407270866Simp#define DISP_CLK_DSIM1 31 408270866Simp#define DISP_CLK_DPPHY 32 409270866Simp#define DISP_CLK_DP 33 410270866Simp#define DISP_SCLK_PIXEL 34 411270866Simp#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35 412270866Simp#define DISP_NR_CLK 36 413270866Simp 414270866Simp 415270866Simp/* List Of Clocks For CMU_G2D */ 416270866Simp 417270866Simp#define G2D_MOUT_ACLK_G2D_333_USER 1 418270866Simp#define G2D_DOUT_PCLK_G2D_83 2 419270866Simp#define G2D_CLK_SMMU3_JPEG 3 420270866Simp#define G2D_CLK_MDMA 4 421270866Simp#define G2D_CLK_JPEG 5 422270866Simp#define G2D_CLK_G2D 6 423270866Simp#define G2D_CLK_SSS 7 424270866Simp#define G2D_CLK_SLIM_SSS 8 425270866Simp#define G2D_CLK_SMMU_SLIM_SSS 9 426270866Simp#define G2D_CLK_SMMU_SSS 10 427270866Simp#define G2D_CLK_SMMU_MDMA 11 428270866Simp#define G2D_CLK_SMMU3_G2D 12 429270866Simp#define G2D_NR_CLK 13 430270866Simp 431270866Simp 432270866Simp/* List Of Clocks For CMU_ISP */ 433270866Simp 434270866Simp#define ISP_MOUT_ISP_400_USER 1 435270866Simp#define ISP_MOUT_ISP_266_USER 2 436270866Simp#define ISP_DOUT_SCLK_MPWM 3 437270866Simp#define ISP_DOUT_CA5_PCLKDBG 4 438270866Simp#define ISP_DOUT_CA5_ATCLKIN 5 439270866Simp#define ISP_DOUT_PCLK_ISP_133 6 440270866Simp#define ISP_DOUT_PCLK_ISP_66 7 441270866Simp#define ISP_CLK_GIC 8 442270866Simp#define ISP_CLK_WDT 9 443270866Simp#define ISP_CLK_UART 10 444270866Simp#define ISP_CLK_SPI1 11 445270866Simp#define ISP_CLK_SPI0 12 446270866Simp#define ISP_CLK_SMMU_SCALERP 13 447270866Simp#define ISP_CLK_SMMU_SCALERC 14 448270866Simp#define ISP_CLK_SMMU_ISPCX 15 449270866Simp#define ISP_CLK_SMMU_ISP 16 450270866Simp#define ISP_CLK_SMMU_FD 17 451270866Simp#define ISP_CLK_SMMU_DRC 18 452270866Simp#define ISP_CLK_PWM 19 453270866Simp#define ISP_CLK_MTCADC 20 454270866Simp#define ISP_CLK_MPWM 21 455270866Simp#define ISP_CLK_MCUCTL 22 456270866Simp#define ISP_CLK_I2C1 23 457270866Simp#define ISP_CLK_I2C0 24 458270866Simp#define ISP_CLK_FIMC_SCALERP 25 459270866Simp#define ISP_CLK_FIMC_SCALERC 26 460270866Simp#define ISP_CLK_FIMC 27 461270866Simp#define ISP_CLK_FIMC_FD 28 462270866Simp#define ISP_CLK_FIMC_DRC 29 463270866Simp#define ISP_CLK_CA5 30 464270866Simp#define ISP_SCLK_SPI0_EXT 31 465270866Simp#define ISP_SCLK_SPI1_EXT 32 466270866Simp#define ISP_SCLK_UART_EXT 33 467270866Simp#define ISP_NR_CLK 34 468270866Simp 469270866Simp#endif 470