exynos5250.h revision 273712
1262569Simp/* 2262569Simp * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3273712Sian * Author: Andrzej Hajda <a.hajda@samsung.com> 4262569Simp * 5262569Simp * This program is free software; you can redistribute it and/or modify 6262569Simp * it under the terms of the GNU General Public License version 2 as 7262569Simp * published by the Free Software Foundation. 8262569Simp * 9262569Simp * Device Tree binding constants for Exynos5250 clock controller. 10262569Simp*/ 11262569Simp 12262569Simp#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H 13262569Simp#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H 14262569Simp 15262569Simp/* core clocks */ 16262569Simp#define CLK_FIN_PLL 1 17262569Simp#define CLK_FOUT_APLL 2 18262569Simp#define CLK_FOUT_MPLL 3 19262569Simp#define CLK_FOUT_BPLL 4 20262569Simp#define CLK_FOUT_GPLL 5 21262569Simp#define CLK_FOUT_CPLL 6 22262569Simp#define CLK_FOUT_EPLL 7 23262569Simp#define CLK_FOUT_VPLL 8 24262569Simp 25262569Simp/* gate for special clocks (sclk) */ 26262569Simp#define CLK_SCLK_CAM_BAYER 128 27262569Simp#define CLK_SCLK_CAM0 129 28262569Simp#define CLK_SCLK_CAM1 130 29262569Simp#define CLK_SCLK_GSCL_WA 131 30262569Simp#define CLK_SCLK_GSCL_WB 132 31262569Simp#define CLK_SCLK_FIMD1 133 32262569Simp#define CLK_SCLK_MIPI1 134 33262569Simp#define CLK_SCLK_DP 135 34262569Simp#define CLK_SCLK_HDMI 136 35262569Simp#define CLK_SCLK_PIXEL 137 36262569Simp#define CLK_SCLK_AUDIO0 138 37262569Simp#define CLK_SCLK_MMC0 139 38262569Simp#define CLK_SCLK_MMC1 140 39262569Simp#define CLK_SCLK_MMC2 141 40262569Simp#define CLK_SCLK_MMC3 142 41262569Simp#define CLK_SCLK_SATA 143 42262569Simp#define CLK_SCLK_USB3 144 43262569Simp#define CLK_SCLK_JPEG 145 44262569Simp#define CLK_SCLK_UART0 146 45262569Simp#define CLK_SCLK_UART1 147 46262569Simp#define CLK_SCLK_UART2 148 47262569Simp#define CLK_SCLK_UART3 149 48262569Simp#define CLK_SCLK_PWM 150 49262569Simp#define CLK_SCLK_AUDIO1 151 50262569Simp#define CLK_SCLK_AUDIO2 152 51262569Simp#define CLK_SCLK_SPDIF 153 52262569Simp#define CLK_SCLK_SPI0 154 53262569Simp#define CLK_SCLK_SPI1 155 54262569Simp#define CLK_SCLK_SPI2 156 55262569Simp#define CLK_DIV_I2S1 157 56262569Simp#define CLK_DIV_I2S2 158 57262569Simp#define CLK_SCLK_HDMIPHY 159 58262569Simp#define CLK_DIV_PCM0 160 59262569Simp 60262569Simp/* gate clocks */ 61262569Simp#define CLK_GSCL0 256 62262569Simp#define CLK_GSCL1 257 63262569Simp#define CLK_GSCL2 258 64262569Simp#define CLK_GSCL3 259 65262569Simp#define CLK_GSCL_WA 260 66262569Simp#define CLK_GSCL_WB 261 67262569Simp#define CLK_SMMU_GSCL0 262 68262569Simp#define CLK_SMMU_GSCL1 263 69262569Simp#define CLK_SMMU_GSCL2 264 70262569Simp#define CLK_SMMU_GSCL3 265 71262569Simp#define CLK_MFC 266 72262569Simp#define CLK_SMMU_MFCL 267 73262569Simp#define CLK_SMMU_MFCR 268 74262569Simp#define CLK_ROTATOR 269 75262569Simp#define CLK_JPEG 270 76262569Simp#define CLK_MDMA1 271 77262569Simp#define CLK_SMMU_ROTATOR 272 78262569Simp#define CLK_SMMU_JPEG 273 79262569Simp#define CLK_SMMU_MDMA1 274 80262569Simp#define CLK_PDMA0 275 81262569Simp#define CLK_PDMA1 276 82262569Simp#define CLK_SATA 277 83262569Simp#define CLK_USBOTG 278 84262569Simp#define CLK_MIPI_HSI 279 85262569Simp#define CLK_SDMMC0 280 86262569Simp#define CLK_SDMMC1 281 87262569Simp#define CLK_SDMMC2 282 88262569Simp#define CLK_SDMMC3 283 89262569Simp#define CLK_SROMC 284 90262569Simp#define CLK_USB2 285 91262569Simp#define CLK_USB3 286 92262569Simp#define CLK_SATA_PHYCTRL 287 93262569Simp#define CLK_SATA_PHYI2C 288 94262569Simp#define CLK_UART0 289 95262569Simp#define CLK_UART1 290 96262569Simp#define CLK_UART2 291 97262569Simp#define CLK_UART3 292 98262569Simp#define CLK_UART4 293 99262569Simp#define CLK_I2C0 294 100262569Simp#define CLK_I2C1 295 101262569Simp#define CLK_I2C2 296 102262569Simp#define CLK_I2C3 297 103262569Simp#define CLK_I2C4 298 104262569Simp#define CLK_I2C5 299 105262569Simp#define CLK_I2C6 300 106262569Simp#define CLK_I2C7 301 107262569Simp#define CLK_I2C_HDMI 302 108262569Simp#define CLK_ADC 303 109262569Simp#define CLK_SPI0 304 110262569Simp#define CLK_SPI1 305 111262569Simp#define CLK_SPI2 306 112262569Simp#define CLK_I2S1 307 113262569Simp#define CLK_I2S2 308 114262569Simp#define CLK_PCM1 309 115262569Simp#define CLK_PCM2 310 116262569Simp#define CLK_PWM 311 117262569Simp#define CLK_SPDIF 312 118262569Simp#define CLK_AC97 313 119262569Simp#define CLK_HSI2C0 314 120262569Simp#define CLK_HSI2C1 315 121262569Simp#define CLK_HSI2C2 316 122262569Simp#define CLK_HSI2C3 317 123262569Simp#define CLK_CHIPID 318 124262569Simp#define CLK_SYSREG 319 125262569Simp#define CLK_PMU 320 126262569Simp#define CLK_CMU_TOP 321 127262569Simp#define CLK_CMU_CORE 322 128262569Simp#define CLK_CMU_MEM 323 129262569Simp#define CLK_TZPC0 324 130262569Simp#define CLK_TZPC1 325 131262569Simp#define CLK_TZPC2 326 132262569Simp#define CLK_TZPC3 327 133262569Simp#define CLK_TZPC4 328 134262569Simp#define CLK_TZPC5 329 135262569Simp#define CLK_TZPC6 330 136262569Simp#define CLK_TZPC7 331 137262569Simp#define CLK_TZPC8 332 138262569Simp#define CLK_TZPC9 333 139262569Simp#define CLK_HDMI_CEC 334 140262569Simp#define CLK_MCT 335 141262569Simp#define CLK_WDT 336 142262569Simp#define CLK_RTC 337 143262569Simp#define CLK_TMU 338 144262569Simp#define CLK_FIMD1 339 145262569Simp#define CLK_MIE1 340 146262569Simp#define CLK_DSIM0 341 147262569Simp#define CLK_DP 342 148262569Simp#define CLK_MIXER 343 149262569Simp#define CLK_HDMI 344 150262569Simp#define CLK_G2D 345 151262569Simp#define CLK_MDMA0 346 152262569Simp#define CLK_SMMU_MDMA0 347 153273712Sian#define CLK_SSS 348 154273712Sian#define CLK_G3D 349 155273712Sian#define CLK_SMMU_TV 350 156273712Sian#define CLK_SMMU_FIMD1 351 157273712Sian#define CLK_SMMU_2D 352 158273712Sian#define CLK_SMMU_FIMC_ISP 353 159273712Sian#define CLK_SMMU_FIMC_DRC 354 160273712Sian#define CLK_SMMU_FIMC_SCC 355 161273712Sian#define CLK_SMMU_FIMC_SCP 356 162273712Sian#define CLK_SMMU_FIMC_FD 357 163273712Sian#define CLK_SMMU_FIMC_MCU 358 164273712Sian#define CLK_SMMU_FIMC_ODC 359 165273712Sian#define CLK_SMMU_FIMC_DIS0 360 166273712Sian#define CLK_SMMU_FIMC_DIS1 361 167273712Sian#define CLK_SMMU_FIMC_3DNR 362 168273712Sian#define CLK_SMMU_FIMC_LITE0 363 169273712Sian#define CLK_SMMU_FIMC_LITE1 364 170273712Sian#define CLK_CAMIF_TOP 365 171262569Simp 172262569Simp/* mux clocks */ 173262569Simp#define CLK_MOUT_HDMI 1024 174273712Sian#define CLK_MOUT_GPLL 1025 175262569Simp 176262569Simp/* must be greater than maximal clock id */ 177273712Sian#define CLK_NR_CLKS 1026 178262569Simp 179262569Simp#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ 180