exynos4415.h revision 279385
1262569Simp/* 2262569Simp * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3262569Simp * Author: Chanwoo Choi <cw00.choi@samsung.com> 4262569Simp * 5262569Simp * This program is free software; you can redistribute it and/or modify 6262569Simp * it under the terms of the GNU General Public License version 2 as 7262569Simp * published by the Free Software Foundation. 8262569Simp * 9262569Simp * Device Tree binding constants for Samsung Exynos4415 clock controllers. 10262569Simp */ 11262569Simp 12262569Simp#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H 13262569Simp#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H 14262569Simp 15262569Simp/* 16262569Simp * Let each exported clock get a unique index, which is used on DT-enabled 17262569Simp * platforms to lookup the clock from a clock specifier. These indices are 18262569Simp * therefore considered an ABI and so must not be changed. This implies 19262569Simp * that new clocks should be added either in free spaces between clock groups 20262569Simp * or at the end. 21262569Simp */ 22262569Simp 23262569Simp/* 24262569Simp * Main CMU 25262569Simp */ 26262569Simp 27262569Simp#define CLK_OSCSEL 1 28262569Simp#define CLK_FIN_PLL 2 29262569Simp#define CLK_FOUT_APLL 3 30262569Simp#define CLK_FOUT_MPLL 4 31262569Simp#define CLK_FOUT_EPLL 5 32262569Simp#define CLK_FOUT_G3D_PLL 6 33262569Simp#define CLK_FOUT_ISP_PLL 7 34262569Simp#define CLK_FOUT_DISP_PLL 8 35262569Simp 36262569Simp/* Muxes */ 37262569Simp#define CLK_MOUT_MPLL_USER_L 16 38262569Simp#define CLK_MOUT_GDL 17 39262569Simp#define CLK_MOUT_MPLL_USER_R 18 40262569Simp#define CLK_MOUT_GDR 19 41262569Simp#define CLK_MOUT_EBI 20 42262569Simp#define CLK_MOUT_ACLK_200 21 43262569Simp#define CLK_MOUT_ACLK_160 22 44262569Simp#define CLK_MOUT_ACLK_100 23 45262569Simp#define CLK_MOUT_ACLK_266 24 46262569Simp#define CLK_MOUT_G3D_PLL 25 47262569Simp#define CLK_MOUT_EPLL 26 48262569Simp#define CLK_MOUT_EBI_1 27 49262569Simp#define CLK_MOUT_ISP_PLL 28 50262569Simp#define CLK_MOUT_DISP_PLL 29 51262569Simp#define CLK_MOUT_MPLL_USER_T 30 52284090Sian#define CLK_MOUT_ACLK_400_MCUISP 31 53262569Simp#define CLK_MOUT_G3D_PLLSRC 32 54262569Simp#define CLK_MOUT_CSIS1 33 55262569Simp#define CLK_MOUT_CSIS0 34 56262569Simp#define CLK_MOUT_CAM1 35 57262569Simp#define CLK_MOUT_FIMC3_LCLK 36 58262569Simp#define CLK_MOUT_FIMC2_LCLK 37 59262569Simp#define CLK_MOUT_FIMC1_LCLK 38 60262569Simp#define CLK_MOUT_FIMC0_LCLK 39 61262569Simp#define CLK_MOUT_MFC 40 62262569Simp#define CLK_MOUT_MFC_1 41 63262569Simp#define CLK_MOUT_MFC_0 42 64262569Simp#define CLK_MOUT_G3D 43 65262569Simp#define CLK_MOUT_G3D_1 44 66262569Simp#define CLK_MOUT_G3D_0 45 67262569Simp#define CLK_MOUT_MIPI0 46 68262569Simp#define CLK_MOUT_FIMD0 47 69262569Simp#define CLK_MOUT_TSADC_ISP 48 70262569Simp#define CLK_MOUT_UART_ISP 49 71262569Simp#define CLK_MOUT_SPI1_ISP 50 72262569Simp#define CLK_MOUT_SPI0_ISP 51 73262569Simp#define CLK_MOUT_PWM_ISP 52 74262569Simp#define CLK_MOUT_AUDIO0 53 75262569Simp#define CLK_MOUT_TSADC 54 76262569Simp#define CLK_MOUT_MMC2 55 77262569Simp#define CLK_MOUT_MMC1 56 78262569Simp#define CLK_MOUT_MMC0 57 79262569Simp#define CLK_MOUT_UART3 58 80262569Simp#define CLK_MOUT_UART2 59 81262569Simp#define CLK_MOUT_UART1 60 82262569Simp#define CLK_MOUT_UART0 61 83262569Simp#define CLK_MOUT_SPI2 62 84262569Simp#define CLK_MOUT_SPI1 63 85262569Simp#define CLK_MOUT_SPI0 64 86262569Simp#define CLK_MOUT_SPDIF 65 87262569Simp#define CLK_MOUT_AUDIO2 66 88262569Simp#define CLK_MOUT_AUDIO1 67 89262569Simp#define CLK_MOUT_MPLL_USER_C 68 90262569Simp#define CLK_MOUT_HPM 69 91262569Simp#define CLK_MOUT_CORE 70 92262569Simp#define CLK_MOUT_APLL 71 93262569Simp#define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72 94262569Simp#define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73 95262569Simp#define CLK_MOUT_JPEG 74 96262569Simp#define CLK_MOUT_JPEG1 75 97262569Simp#define CLK_MOUT_JPEG0 76 98262569Simp#define CLK_MOUT_ACLK_ISP0_300 77 99262569Simp#define CLK_MOUT_ACLK_ISP0_400 78 100262569Simp#define CLK_MOUT_ACLK_ISP0_300_USER 79 101262569Simp#define CLK_MOUT_ACLK_ISP1_300 80 102262569Simp#define CLK_MOUT_ACLK_ISP1_300_USER 81 103262569Simp#define CLK_MOUT_HDMI 82 104262569Simp 105262569Simp/* Dividers */ 106262569Simp#define CLK_DIV_GPL 90 107262569Simp#define CLK_DIV_GDL 91 108262569Simp#define CLK_DIV_GPR 92 109262569Simp#define CLK_DIV_GDR 93 110262569Simp#define CLK_DIV_ACLK_400_MCUISP 94 111262569Simp#define CLK_DIV_EBI 95 112262569Simp#define CLK_DIV_ACLK_200 96 113262569Simp#define CLK_DIV_ACLK_160 97 114262569Simp#define CLK_DIV_ACLK_100 98 115262569Simp#define CLK_DIV_ACLK_266 99 116262569Simp#define CLK_DIV_CSIS1 100 117262569Simp#define CLK_DIV_CSIS0 101 118262569Simp#define CLK_DIV_CAM1 102 119262569Simp#define CLK_DIV_FIMC3_LCLK 103 120262569Simp#define CLK_DIV_FIMC2_LCLK 104 121262569Simp#define CLK_DIV_FIMC1_LCLK 105 122262569Simp#define CLK_DIV_FIMC0_LCLK 106 123262569Simp#define CLK_DIV_TV_BLK 107 124262569Simp#define CLK_DIV_MFC 108 125262569Simp#define CLK_DIV_G3D 109 126262569Simp#define CLK_DIV_MIPI0_PRE 110 127262569Simp#define CLK_DIV_MIPI0 111 128262569Simp#define CLK_DIV_FIMD0 112 129262569Simp#define CLK_DIV_UART_ISP 113 130262569Simp#define CLK_DIV_SPI1_ISP_PRE 114 131262569Simp#define CLK_DIV_SPI1_ISP 115 132262569Simp#define CLK_DIV_SPI0_ISP_PRE 116 133262569Simp#define CLK_DIV_SPI0_ISP 117 134262569Simp#define CLK_DIV_PWM_ISP 118 135262569Simp#define CLK_DIV_PCM0 119 136262569Simp#define CLK_DIV_AUDIO0 120 137262569Simp#define CLK_DIV_TSADC_PRE 121 138262569Simp#define CLK_DIV_TSADC 122 139262569Simp#define CLK_DIV_MMC1_PRE 123 140262569Simp#define CLK_DIV_MMC1 124 141262569Simp#define CLK_DIV_MMC0_PRE 125 142262569Simp#define CLK_DIV_MMC0 126 143262569Simp#define CLK_DIV_MMC2_PRE 127 144262569Simp#define CLK_DIV_MMC2 128 145262569Simp#define CLK_DIV_UART3 129 146262569Simp#define CLK_DIV_UART2 130 147262569Simp#define CLK_DIV_UART1 131 148262569Simp#define CLK_DIV_UART0 132 149262569Simp#define CLK_DIV_SPI1_PRE 133 150262569Simp#define CLK_DIV_SPI1 134 151262569Simp#define CLK_DIV_SPI0_PRE 135 152262569Simp#define CLK_DIV_SPI0 136 153262569Simp#define CLK_DIV_SPI2_PRE 137 154262569Simp#define CLK_DIV_SPI2 138 155262569Simp#define CLK_DIV_PCM2 139 156262569Simp#define CLK_DIV_AUDIO2 140 157262569Simp#define CLK_DIV_PCM1 141 158262569Simp#define CLK_DIV_AUDIO1 142 159262569Simp#define CLK_DIV_I2S1 143 160262569Simp#define CLK_DIV_PXLASYNC_CSIS1_FIMC 144 161262569Simp#define CLK_DIV_PXLASYNC_CSIS0_FIMC 145 162262569Simp#define CLK_DIV_JPEG 146 163262569Simp#define CLK_DIV_CORE2 147 164262569Simp#define CLK_DIV_APLL 148 165262569Simp#define CLK_DIV_PCLK_DBG 149 166262569Simp#define CLK_DIV_ATB 150 167262569Simp#define CLK_DIV_PERIPH 151 168262569Simp#define CLK_DIV_COREM1 152 169262569Simp#define CLK_DIV_COREM0 153 170262569Simp#define CLK_DIV_CORE 154 171262569Simp#define CLK_DIV_HPM 155 172262569Simp#define CLK_DIV_COPY 156 173262569Simp 174262569Simp/* Gates */ 175262569Simp#define CLK_ASYNC_G3D 180 176262569Simp#define CLK_ASYNC_MFCL 181 177262569Simp#define CLK_ASYNC_TVX 182 178262569Simp#define CLK_PPMULEFT 183 179262569Simp#define CLK_GPIO_LEFT 184 180262569Simp#define CLK_PPMUIMAGE 185 181262569Simp#define CLK_QEMDMA2 186 182262569Simp#define CLK_QEROTATOR 187 183262569Simp#define CLK_SMMUMDMA2 188 184262569Simp#define CLK_SMMUROTATOR 189 185262569Simp#define CLK_MDMA2 190 186262569Simp#define CLK_ROTATOR 191 187262569Simp#define CLK_ASYNC_ISPMX 192 188262569Simp#define CLK_ASYNC_MAUDIOX 193 189262569Simp#define CLK_ASYNC_MFCR 194 190262569Simp#define CLK_ASYNC_FSYSD 195 191262569Simp#define CLK_ASYNC_LCD0X 196 192262569Simp#define CLK_ASYNC_CAMX 197 193262569Simp#define CLK_PPMURIGHT 198 194262569Simp#define CLK_GPIO_RIGHT 199 195262569Simp#define CLK_ANTIRBK_APBIF 200 196262569Simp#define CLK_EFUSE_WRITER_APBIF 201 197262569Simp#define CLK_MONOCNT 202 198262569Simp#define CLK_TZPC6 203 199262569Simp#define CLK_PROVISIONKEY1 204 200262569Simp#define CLK_PROVISIONKEY0 205 201262569Simp#define CLK_CMU_ISPPART 206 202262569Simp#define CLK_TMU_APBIF 207 203262569Simp#define CLK_KEYIF 208 204262569Simp#define CLK_RTC 209 205262569Simp#define CLK_WDT 210 206262569Simp#define CLK_MCT 211 207262569Simp#define CLK_SECKEY 212 208262569Simp#define CLK_HDMI_CEC 213 209262569Simp#define CLK_TZPC5 214 210262569Simp#define CLK_TZPC4 215 211262569Simp#define CLK_TZPC3 216 212262569Simp#define CLK_TZPC2 217 213262569Simp#define CLK_TZPC1 218 214262569Simp#define CLK_TZPC0 219 215262569Simp#define CLK_CMU_COREPART 220 216262569Simp#define CLK_CMU_TOPPART 221 217262569Simp#define CLK_PMU_APBIF 222 218262569Simp#define CLK_SYSREG 223 219262569Simp#define CLK_CHIP_ID 224 220262569Simp#define CLK_SMMUFIMC_LITE2 225 221262569Simp#define CLK_FIMC_LITE2 226 222262569Simp#define CLK_PIXELASYNCM1 227 223262569Simp#define CLK_PIXELASYNCM0 228 224262569Simp#define CLK_PPMUCAMIF 229 225262569Simp#define CLK_SMMUJPEG 230 226262569Simp#define CLK_SMMUFIMC3 231 227262569Simp#define CLK_SMMUFIMC2 232 228262569Simp#define CLK_SMMUFIMC1 233 229262569Simp#define CLK_SMMUFIMC0 234 230262569Simp#define CLK_JPEG 235 231262569Simp#define CLK_CSIS1 236 232262569Simp#define CLK_CSIS0 237 233262569Simp#define CLK_FIMC3 238 234262569Simp#define CLK_FIMC2 239 235262569Simp#define CLK_FIMC1 240 236262569Simp#define CLK_FIMC0 241 237262569Simp#define CLK_PPMUTV 242 238262569Simp#define CLK_SMMUTV 243 239262569Simp#define CLK_HDMI 244 240262569Simp#define CLK_MIXER 245 241262569Simp#define CLK_VP 246 242262569Simp#define CLK_PPMUMFC_R 247 243262569Simp#define CLK_PPMUMFC_L 248 244262569Simp#define CLK_SMMUMFC_R 249 245262569Simp#define CLK_SMMUMFC_L 250 246262569Simp#define CLK_MFC 251 247262569Simp#define CLK_PPMUG3D 252 248262569Simp#define CLK_G3D 253 249262569Simp#define CLK_PPMULCD0 254 250262569Simp#define CLK_SMMUFIMD0 255 251262569Simp#define CLK_DSIM0 256 252262569Simp#define CLK_SMIES 257 253262569Simp#define CLK_MIE0 258 254262569Simp#define CLK_FIMD0 259 255262569Simp#define CLK_TSADC 260 256262569Simp#define CLK_PPMUFILE 261 257262569Simp#define CLK_NFCON 262 258262569Simp#define CLK_USBDEVICE 263 259262569Simp#define CLK_USBHOST 264 260262569Simp#define CLK_SROMC 265 261262569Simp#define CLK_SDMMC2 266 262262569Simp#define CLK_SDMMC1 267 263262569Simp#define CLK_SDMMC0 268 264262569Simp#define CLK_PDMA1 269 265262569Simp#define CLK_PDMA0 270 266262569Simp#define CLK_SPDIF 271 267262569Simp#define CLK_PWM 272 268262569Simp#define CLK_PCM2 273 269262569Simp#define CLK_PCM1 274 270262569Simp#define CLK_I2S1 275 271262569Simp#define CLK_SPI2 276 272262569Simp#define CLK_SPI1 277 273262569Simp#define CLK_SPI0 278 274262569Simp#define CLK_I2CHDMI 279 275262569Simp#define CLK_I2C7 280 276262569Simp#define CLK_I2C6 281 277262569Simp#define CLK_I2C5 282 278262569Simp#define CLK_I2C4 283 279262569Simp#define CLK_I2C3 284 280262569Simp#define CLK_I2C2 285 281262569Simp#define CLK_I2C1 286 282262569Simp#define CLK_I2C0 287 283262569Simp#define CLK_UART3 288 284262569Simp#define CLK_UART2 289 285262569Simp#define CLK_UART1 290 286262569Simp#define CLK_UART0 291 287262569Simp 288262569Simp/* Special clocks */ 289262569Simp#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330 290262569Simp#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331 291262569Simp#define CLK_SCLK_JPEG 332 292262569Simp#define CLK_SCLK_CSIS1 333 293262569Simp#define CLK_SCLK_CSIS0 334 294262569Simp#define CLK_SCLK_CAM1 335 295262569Simp#define CLK_SCLK_FIMC3_LCLK 336 296262569Simp#define CLK_SCLK_FIMC2_LCLK 337 297262569Simp#define CLK_SCLK_FIMC1_LCLK 338 298262569Simp#define CLK_SCLK_FIMC0_LCLK 339 299262569Simp#define CLK_SCLK_PIXEL 340 300262569Simp#define CLK_SCLK_HDMI 341 301262569Simp#define CLK_SCLK_MIXER 342 302262569Simp#define CLK_SCLK_MFC 343 303262569Simp#define CLK_SCLK_G3D 344 304262569Simp#define CLK_SCLK_MIPIDPHY4L 345 305262569Simp#define CLK_SCLK_MIPI0 346 306262569Simp#define CLK_SCLK_MDNIE0 347 307262569Simp#define CLK_SCLK_FIMD0 348 308262569Simp#define CLK_SCLK_PCM0 349 309262569Simp#define CLK_SCLK_AUDIO0 350 310262569Simp#define CLK_SCLK_TSADC 351 311262569Simp#define CLK_SCLK_EBI 352 312262569Simp#define CLK_SCLK_MMC2 353 313262569Simp#define CLK_SCLK_MMC1 354 314262569Simp#define CLK_SCLK_MMC0 355 315262569Simp#define CLK_SCLK_I2S 356 316262569Simp#define CLK_SCLK_PCM2 357 317262569Simp#define CLK_SCLK_PCM1 358 318262569Simp#define CLK_SCLK_AUDIO2 359 319262569Simp#define CLK_SCLK_AUDIO1 360 320262569Simp#define CLK_SCLK_SPDIF 361 321262569Simp#define CLK_SCLK_SPI2 362 322262569Simp#define CLK_SCLK_SPI1 363 323262569Simp#define CLK_SCLK_SPI0 364 324262569Simp#define CLK_SCLK_UART3 365 325262569Simp#define CLK_SCLK_UART2 366 326262569Simp#define CLK_SCLK_UART1 367 327262569Simp#define CLK_SCLK_UART0 368 328262569Simp#define CLK_SCLK_HDMIPHY 369 329262569Simp 330262569Simp/* 331262569Simp * Total number of clocks of main CMU. 332262569Simp * NOTE: Must be equal to last clock ID increased by one. 333262569Simp */ 334262569Simp#define CLK_NR_CLKS 370 335262569Simp 336262569Simp/* 337262569Simp * CMU DMC 338262569Simp */ 339262569Simp#define CLK_DMC_FOUT_MPLL 1 340273712Sian#define CLK_DMC_FOUT_BPLL 2 341273712Sian 342262569Simp#define CLK_DMC_MOUT_MPLL 3 343262569Simp#define CLK_DMC_MOUT_BPLL 4 344#define CLK_DMC_MOUT_DPHY 5 345#define CLK_DMC_MOUT_DMC_BUS 6 346 347#define CLK_DMC_DIV_DMC 7 348#define CLK_DMC_DIV_DPHY 8 349#define CLK_DMC_DIV_DMC_PRE 9 350#define CLK_DMC_DIV_DMCP 10 351#define CLK_DMC_DIV_DMCD 11 352#define CLK_DMC_DIV_MPLL_PRE 12 353 354/* 355 * Total number of clocks of CMU_DMC. 356 * NOTE: Must be equal to highest clock ID increased by one. 357 */ 358#define NR_CLKS_DMC 13 359 360#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */ 361