exynos4415.h revision 279377
1279377Simp/* 2279377Simp * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3279377Simp * Author: Chanwoo Choi <cw00.choi@samsung.com> 4279377Simp * 5279377Simp * This program is free software; you can redistribute it and/or modify 6279377Simp * it under the terms of the GNU General Public License version 2 as 7279377Simp * published by the Free Software Foundation. 8279377Simp * 9279377Simp * Device Tree binding constants for Samsung Exynos4415 clock controllers. 10279377Simp */ 11279377Simp 12279377Simp#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H 13279377Simp#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H 14279377Simp 15279377Simp/* 16279377Simp * Let each exported clock get a unique index, which is used on DT-enabled 17279377Simp * platforms to lookup the clock from a clock specifier. These indices are 18279377Simp * therefore considered an ABI and so must not be changed. This implies 19279377Simp * that new clocks should be added either in free spaces between clock groups 20279377Simp * or at the end. 21279377Simp */ 22279377Simp 23279377Simp/* 24279377Simp * Main CMU 25279377Simp */ 26279377Simp 27279377Simp#define CLK_OSCSEL 1 28279377Simp#define CLK_FIN_PLL 2 29279377Simp#define CLK_FOUT_APLL 3 30279377Simp#define CLK_FOUT_MPLL 4 31279377Simp#define CLK_FOUT_EPLL 5 32279377Simp#define CLK_FOUT_G3D_PLL 6 33279377Simp#define CLK_FOUT_ISP_PLL 7 34279377Simp#define CLK_FOUT_DISP_PLL 8 35279377Simp 36279377Simp/* Muxes */ 37279377Simp#define CLK_MOUT_MPLL_USER_L 16 38279377Simp#define CLK_MOUT_GDL 17 39279377Simp#define CLK_MOUT_MPLL_USER_R 18 40279377Simp#define CLK_MOUT_GDR 19 41279377Simp#define CLK_MOUT_EBI 20 42279377Simp#define CLK_MOUT_ACLK_200 21 43279377Simp#define CLK_MOUT_ACLK_160 22 44279377Simp#define CLK_MOUT_ACLK_100 23 45279377Simp#define CLK_MOUT_ACLK_266 24 46279377Simp#define CLK_MOUT_G3D_PLL 25 47279377Simp#define CLK_MOUT_EPLL 26 48279377Simp#define CLK_MOUT_EBI_1 27 49279377Simp#define CLK_MOUT_ISP_PLL 28 50279377Simp#define CLK_MOUT_DISP_PLL 29 51279377Simp#define CLK_MOUT_MPLL_USER_T 30 52279377Simp#define CLK_MOUT_ACLK_400_MCUISP 31 53279377Simp#define CLK_MOUT_G3D_PLLSRC 32 54279377Simp#define CLK_MOUT_CSIS1 33 55279377Simp#define CLK_MOUT_CSIS0 34 56279377Simp#define CLK_MOUT_CAM1 35 57279377Simp#define CLK_MOUT_FIMC3_LCLK 36 58279377Simp#define CLK_MOUT_FIMC2_LCLK 37 59279377Simp#define CLK_MOUT_FIMC1_LCLK 38 60279377Simp#define CLK_MOUT_FIMC0_LCLK 39 61279377Simp#define CLK_MOUT_MFC 40 62279377Simp#define CLK_MOUT_MFC_1 41 63279377Simp#define CLK_MOUT_MFC_0 42 64279377Simp#define CLK_MOUT_G3D 43 65279377Simp#define CLK_MOUT_G3D_1 44 66279377Simp#define CLK_MOUT_G3D_0 45 67279377Simp#define CLK_MOUT_MIPI0 46 68279377Simp#define CLK_MOUT_FIMD0 47 69279377Simp#define CLK_MOUT_TSADC_ISP 48 70279377Simp#define CLK_MOUT_UART_ISP 49 71279377Simp#define CLK_MOUT_SPI1_ISP 50 72279377Simp#define CLK_MOUT_SPI0_ISP 51 73279377Simp#define CLK_MOUT_PWM_ISP 52 74279377Simp#define CLK_MOUT_AUDIO0 53 75279377Simp#define CLK_MOUT_TSADC 54 76279377Simp#define CLK_MOUT_MMC2 55 77279377Simp#define CLK_MOUT_MMC1 56 78279377Simp#define CLK_MOUT_MMC0 57 79279377Simp#define CLK_MOUT_UART3 58 80279377Simp#define CLK_MOUT_UART2 59 81279377Simp#define CLK_MOUT_UART1 60 82279377Simp#define CLK_MOUT_UART0 61 83279377Simp#define CLK_MOUT_SPI2 62 84279377Simp#define CLK_MOUT_SPI1 63 85279377Simp#define CLK_MOUT_SPI0 64 86279377Simp#define CLK_MOUT_SPDIF 65 87279377Simp#define CLK_MOUT_AUDIO2 66 88279377Simp#define CLK_MOUT_AUDIO1 67 89279377Simp#define CLK_MOUT_MPLL_USER_C 68 90279377Simp#define CLK_MOUT_HPM 69 91279377Simp#define CLK_MOUT_CORE 70 92279377Simp#define CLK_MOUT_APLL 71 93279377Simp#define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72 94279377Simp#define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73 95279377Simp#define CLK_MOUT_JPEG 74 96279377Simp#define CLK_MOUT_JPEG1 75 97279377Simp#define CLK_MOUT_JPEG0 76 98279377Simp#define CLK_MOUT_ACLK_ISP0_300 77 99279377Simp#define CLK_MOUT_ACLK_ISP0_400 78 100279377Simp#define CLK_MOUT_ACLK_ISP0_300_USER 79 101279377Simp#define CLK_MOUT_ACLK_ISP1_300 80 102279377Simp#define CLK_MOUT_ACLK_ISP1_300_USER 81 103279377Simp#define CLK_MOUT_HDMI 82 104279377Simp 105279377Simp/* Dividers */ 106279377Simp#define CLK_DIV_GPL 90 107279377Simp#define CLK_DIV_GDL 91 108279377Simp#define CLK_DIV_GPR 92 109279377Simp#define CLK_DIV_GDR 93 110279377Simp#define CLK_DIV_ACLK_400_MCUISP 94 111279377Simp#define CLK_DIV_EBI 95 112279377Simp#define CLK_DIV_ACLK_200 96 113279377Simp#define CLK_DIV_ACLK_160 97 114279377Simp#define CLK_DIV_ACLK_100 98 115279377Simp#define CLK_DIV_ACLK_266 99 116279377Simp#define CLK_DIV_CSIS1 100 117279377Simp#define CLK_DIV_CSIS0 101 118279377Simp#define CLK_DIV_CAM1 102 119279377Simp#define CLK_DIV_FIMC3_LCLK 103 120279377Simp#define CLK_DIV_FIMC2_LCLK 104 121279377Simp#define CLK_DIV_FIMC1_LCLK 105 122279377Simp#define CLK_DIV_FIMC0_LCLK 106 123279377Simp#define CLK_DIV_TV_BLK 107 124279377Simp#define CLK_DIV_MFC 108 125279377Simp#define CLK_DIV_G3D 109 126279377Simp#define CLK_DIV_MIPI0_PRE 110 127279377Simp#define CLK_DIV_MIPI0 111 128279377Simp#define CLK_DIV_FIMD0 112 129279377Simp#define CLK_DIV_UART_ISP 113 130279377Simp#define CLK_DIV_SPI1_ISP_PRE 114 131279377Simp#define CLK_DIV_SPI1_ISP 115 132279377Simp#define CLK_DIV_SPI0_ISP_PRE 116 133279377Simp#define CLK_DIV_SPI0_ISP 117 134279377Simp#define CLK_DIV_PWM_ISP 118 135279377Simp#define CLK_DIV_PCM0 119 136279377Simp#define CLK_DIV_AUDIO0 120 137279377Simp#define CLK_DIV_TSADC_PRE 121 138279377Simp#define CLK_DIV_TSADC 122 139279377Simp#define CLK_DIV_MMC1_PRE 123 140279377Simp#define CLK_DIV_MMC1 124 141279377Simp#define CLK_DIV_MMC0_PRE 125 142279377Simp#define CLK_DIV_MMC0 126 143279377Simp#define CLK_DIV_MMC2_PRE 127 144279377Simp#define CLK_DIV_MMC2 128 145279377Simp#define CLK_DIV_UART3 129 146279377Simp#define CLK_DIV_UART2 130 147279377Simp#define CLK_DIV_UART1 131 148279377Simp#define CLK_DIV_UART0 132 149279377Simp#define CLK_DIV_SPI1_PRE 133 150279377Simp#define CLK_DIV_SPI1 134 151279377Simp#define CLK_DIV_SPI0_PRE 135 152279377Simp#define CLK_DIV_SPI0 136 153279377Simp#define CLK_DIV_SPI2_PRE 137 154279377Simp#define CLK_DIV_SPI2 138 155279377Simp#define CLK_DIV_PCM2 139 156279377Simp#define CLK_DIV_AUDIO2 140 157279377Simp#define CLK_DIV_PCM1 141 158279377Simp#define CLK_DIV_AUDIO1 142 159279377Simp#define CLK_DIV_I2S1 143 160279377Simp#define CLK_DIV_PXLASYNC_CSIS1_FIMC 144 161279377Simp#define CLK_DIV_PXLASYNC_CSIS0_FIMC 145 162279377Simp#define CLK_DIV_JPEG 146 163279377Simp#define CLK_DIV_CORE2 147 164279377Simp#define CLK_DIV_APLL 148 165279377Simp#define CLK_DIV_PCLK_DBG 149 166279377Simp#define CLK_DIV_ATB 150 167279377Simp#define CLK_DIV_PERIPH 151 168279377Simp#define CLK_DIV_COREM1 152 169279377Simp#define CLK_DIV_COREM0 153 170279377Simp#define CLK_DIV_CORE 154 171279377Simp#define CLK_DIV_HPM 155 172279377Simp#define CLK_DIV_COPY 156 173279377Simp 174279377Simp/* Gates */ 175279377Simp#define CLK_ASYNC_G3D 180 176279377Simp#define CLK_ASYNC_MFCL 181 177279377Simp#define CLK_ASYNC_TVX 182 178279377Simp#define CLK_PPMULEFT 183 179279377Simp#define CLK_GPIO_LEFT 184 180279377Simp#define CLK_PPMUIMAGE 185 181279377Simp#define CLK_QEMDMA2 186 182279377Simp#define CLK_QEROTATOR 187 183279377Simp#define CLK_SMMUMDMA2 188 184279377Simp#define CLK_SMMUROTATOR 189 185279377Simp#define CLK_MDMA2 190 186279377Simp#define CLK_ROTATOR 191 187279377Simp#define CLK_ASYNC_ISPMX 192 188279377Simp#define CLK_ASYNC_MAUDIOX 193 189279377Simp#define CLK_ASYNC_MFCR 194 190279377Simp#define CLK_ASYNC_FSYSD 195 191279377Simp#define CLK_ASYNC_LCD0X 196 192279377Simp#define CLK_ASYNC_CAMX 197 193279377Simp#define CLK_PPMURIGHT 198 194279377Simp#define CLK_GPIO_RIGHT 199 195279377Simp#define CLK_ANTIRBK_APBIF 200 196279377Simp#define CLK_EFUSE_WRITER_APBIF 201 197279377Simp#define CLK_MONOCNT 202 198279377Simp#define CLK_TZPC6 203 199279377Simp#define CLK_PROVISIONKEY1 204 200279377Simp#define CLK_PROVISIONKEY0 205 201279377Simp#define CLK_CMU_ISPPART 206 202279377Simp#define CLK_TMU_APBIF 207 203279377Simp#define CLK_KEYIF 208 204279377Simp#define CLK_RTC 209 205279377Simp#define CLK_WDT 210 206279377Simp#define CLK_MCT 211 207279377Simp#define CLK_SECKEY 212 208279377Simp#define CLK_HDMI_CEC 213 209279377Simp#define CLK_TZPC5 214 210279377Simp#define CLK_TZPC4 215 211279377Simp#define CLK_TZPC3 216 212279377Simp#define CLK_TZPC2 217 213279377Simp#define CLK_TZPC1 218 214279377Simp#define CLK_TZPC0 219 215279377Simp#define CLK_CMU_COREPART 220 216279377Simp#define CLK_CMU_TOPPART 221 217279377Simp#define CLK_PMU_APBIF 222 218279377Simp#define CLK_SYSREG 223 219279377Simp#define CLK_CHIP_ID 224 220279377Simp#define CLK_SMMUFIMC_LITE2 225 221279377Simp#define CLK_FIMC_LITE2 226 222279377Simp#define CLK_PIXELASYNCM1 227 223279377Simp#define CLK_PIXELASYNCM0 228 224279377Simp#define CLK_PPMUCAMIF 229 225279377Simp#define CLK_SMMUJPEG 230 226279377Simp#define CLK_SMMUFIMC3 231 227279377Simp#define CLK_SMMUFIMC2 232 228279377Simp#define CLK_SMMUFIMC1 233 229279377Simp#define CLK_SMMUFIMC0 234 230279377Simp#define CLK_JPEG 235 231279377Simp#define CLK_CSIS1 236 232279377Simp#define CLK_CSIS0 237 233279377Simp#define CLK_FIMC3 238 234279377Simp#define CLK_FIMC2 239 235279377Simp#define CLK_FIMC1 240 236279377Simp#define CLK_FIMC0 241 237279377Simp#define CLK_PPMUTV 242 238279377Simp#define CLK_SMMUTV 243 239279377Simp#define CLK_HDMI 244 240279377Simp#define CLK_MIXER 245 241279377Simp#define CLK_VP 246 242279377Simp#define CLK_PPMUMFC_R 247 243279377Simp#define CLK_PPMUMFC_L 248 244279377Simp#define CLK_SMMUMFC_R 249 245279377Simp#define CLK_SMMUMFC_L 250 246279377Simp#define CLK_MFC 251 247279377Simp#define CLK_PPMUG3D 252 248279377Simp#define CLK_G3D 253 249279377Simp#define CLK_PPMULCD0 254 250279377Simp#define CLK_SMMUFIMD0 255 251279377Simp#define CLK_DSIM0 256 252279377Simp#define CLK_SMIES 257 253279377Simp#define CLK_MIE0 258 254279377Simp#define CLK_FIMD0 259 255279377Simp#define CLK_TSADC 260 256279377Simp#define CLK_PPMUFILE 261 257279377Simp#define CLK_NFCON 262 258279377Simp#define CLK_USBDEVICE 263 259279377Simp#define CLK_USBHOST 264 260279377Simp#define CLK_SROMC 265 261279377Simp#define CLK_SDMMC2 266 262279377Simp#define CLK_SDMMC1 267 263279377Simp#define CLK_SDMMC0 268 264279377Simp#define CLK_PDMA1 269 265279377Simp#define CLK_PDMA0 270 266279377Simp#define CLK_SPDIF 271 267279377Simp#define CLK_PWM 272 268279377Simp#define CLK_PCM2 273 269279377Simp#define CLK_PCM1 274 270279377Simp#define CLK_I2S1 275 271279377Simp#define CLK_SPI2 276 272279377Simp#define CLK_SPI1 277 273279377Simp#define CLK_SPI0 278 274279377Simp#define CLK_I2CHDMI 279 275279377Simp#define CLK_I2C7 280 276279377Simp#define CLK_I2C6 281 277279377Simp#define CLK_I2C5 282 278279377Simp#define CLK_I2C4 283 279279377Simp#define CLK_I2C3 284 280279377Simp#define CLK_I2C2 285 281279377Simp#define CLK_I2C1 286 282279377Simp#define CLK_I2C0 287 283279377Simp#define CLK_UART3 288 284279377Simp#define CLK_UART2 289 285279377Simp#define CLK_UART1 290 286279377Simp#define CLK_UART0 291 287279377Simp 288279377Simp/* Special clocks */ 289279377Simp#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330 290279377Simp#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331 291279377Simp#define CLK_SCLK_JPEG 332 292279377Simp#define CLK_SCLK_CSIS1 333 293279377Simp#define CLK_SCLK_CSIS0 334 294279377Simp#define CLK_SCLK_CAM1 335 295279377Simp#define CLK_SCLK_FIMC3_LCLK 336 296279377Simp#define CLK_SCLK_FIMC2_LCLK 337 297279377Simp#define CLK_SCLK_FIMC1_LCLK 338 298279377Simp#define CLK_SCLK_FIMC0_LCLK 339 299279377Simp#define CLK_SCLK_PIXEL 340 300279377Simp#define CLK_SCLK_HDMI 341 301279377Simp#define CLK_SCLK_MIXER 342 302279377Simp#define CLK_SCLK_MFC 343 303279377Simp#define CLK_SCLK_G3D 344 304279377Simp#define CLK_SCLK_MIPIDPHY4L 345 305279377Simp#define CLK_SCLK_MIPI0 346 306279377Simp#define CLK_SCLK_MDNIE0 347 307279377Simp#define CLK_SCLK_FIMD0 348 308279377Simp#define CLK_SCLK_PCM0 349 309279377Simp#define CLK_SCLK_AUDIO0 350 310279377Simp#define CLK_SCLK_TSADC 351 311279377Simp#define CLK_SCLK_EBI 352 312279377Simp#define CLK_SCLK_MMC2 353 313279377Simp#define CLK_SCLK_MMC1 354 314279377Simp#define CLK_SCLK_MMC0 355 315279377Simp#define CLK_SCLK_I2S 356 316279377Simp#define CLK_SCLK_PCM2 357 317279377Simp#define CLK_SCLK_PCM1 358 318279377Simp#define CLK_SCLK_AUDIO2 359 319279377Simp#define CLK_SCLK_AUDIO1 360 320279377Simp#define CLK_SCLK_SPDIF 361 321279377Simp#define CLK_SCLK_SPI2 362 322279377Simp#define CLK_SCLK_SPI1 363 323279377Simp#define CLK_SCLK_SPI0 364 324279377Simp#define CLK_SCLK_UART3 365 325279377Simp#define CLK_SCLK_UART2 366 326279377Simp#define CLK_SCLK_UART1 367 327279377Simp#define CLK_SCLK_UART0 368 328279377Simp#define CLK_SCLK_HDMIPHY 369 329279377Simp 330279377Simp/* 331279377Simp * Total number of clocks of main CMU. 332279377Simp * NOTE: Must be equal to last clock ID increased by one. 333279377Simp */ 334279377Simp#define CLK_NR_CLKS 370 335279377Simp 336279377Simp/* 337279377Simp * CMU DMC 338279377Simp */ 339279377Simp#define CLK_DMC_FOUT_MPLL 1 340279377Simp#define CLK_DMC_FOUT_BPLL 2 341279377Simp 342279377Simp#define CLK_DMC_MOUT_MPLL 3 343279377Simp#define CLK_DMC_MOUT_BPLL 4 344279377Simp#define CLK_DMC_MOUT_DPHY 5 345279377Simp#define CLK_DMC_MOUT_DMC_BUS 6 346279377Simp 347279377Simp#define CLK_DMC_DIV_DMC 7 348279377Simp#define CLK_DMC_DIV_DPHY 8 349279377Simp#define CLK_DMC_DIV_DMC_PRE 9 350279377Simp#define CLK_DMC_DIV_DMCP 10 351279377Simp#define CLK_DMC_DIV_DMCD 11 352279377Simp#define CLK_DMC_DIV_MPLL_PRE 12 353279377Simp 354279377Simp/* 355279377Simp * Total number of clocks of CMU_DMC. 356279377Simp * NOTE: Must be equal to highest clock ID increased by one. 357279377Simp */ 358279377Simp#define NR_CLKS_DMC 13 359279377Simp 360279377Simp#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */ 361