1279377Simp/* 2279377Simp * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3279377Simp * 4279377Simp * This program is free software; you can redistribute it and/or modify 5279377Simp * it under the terms of the GNU General Public License version 2 as 6279377Simp * published by the Free Software Foundation. 7279377Simp */ 8279377Simp 9279377Simp/* AM43x EPOS EVM */ 10279377Simp 11279377Simp/dts-v1/; 12279377Simp 13279377Simp#include "am4372.dtsi" 14279377Simp#include <dt-bindings/pinctrl/am43xx.h> 15279377Simp#include <dt-bindings/gpio/gpio.h> 16279377Simp#include <dt-bindings/pwm/pwm.h> 17279377Simp 18279377Simp/ { 19279377Simp model = "TI AM43x EPOS EVM"; 20279377Simp compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; 21279377Simp 22279377Simp aliases { 23279377Simp display0 = &lcd0; 24279377Simp }; 25279377Simp 26279377Simp vmmcsd_fixed: fixedregulator-sd { 27279377Simp compatible = "regulator-fixed"; 28279377Simp regulator-name = "vmmcsd_fixed"; 29279377Simp regulator-min-microvolt = <3300000>; 30279377Simp regulator-max-microvolt = <3300000>; 31279377Simp enable-active-high; 32279377Simp }; 33279377Simp 34279377Simp lcd0: display { 35279377Simp compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; 36279377Simp label = "lcd"; 37279377Simp 38279377Simp pinctrl-names = "default"; 39279377Simp pinctrl-0 = <&lcd_pins>; 40279377Simp 41279377Simp /* 42279377Simp * SelLCDorHDMI, LOW to select HDMI. This is not really the 43279377Simp * panel's enable GPIO, but we don't have HDMI driver support nor 44279377Simp * support to switch between two displays, so using this gpio as 45279377Simp * panel's enable should be safe. 46279377Simp */ 47279377Simp enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 48279377Simp 49279377Simp panel-timing { 50279377Simp clock-frequency = <33000000>; 51279377Simp hactive = <800>; 52279377Simp vactive = <480>; 53279377Simp hfront-porch = <210>; 54279377Simp hback-porch = <16>; 55279377Simp hsync-len = <30>; 56279377Simp vback-porch = <10>; 57279377Simp vfront-porch = <22>; 58279377Simp vsync-len = <13>; 59279377Simp hsync-active = <0>; 60279377Simp vsync-active = <0>; 61279377Simp de-active = <1>; 62279377Simp pixelclk-active = <1>; 63279377Simp }; 64279377Simp 65279377Simp port { 66279377Simp lcd_in: endpoint { 67279377Simp remote-endpoint = <&dpi_out>; 68279377Simp }; 69279377Simp }; 70279377Simp }; 71279377Simp 72279377Simp am43xx_pinmux: pinmux@44e10800 { 73279377Simp cpsw_default: cpsw_default { 74279377Simp pinctrl-single,pins = < 75279377Simp /* Slave 1 */ 76279377Simp 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ 77279377Simp 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ 78279377Simp 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ 79279377Simp 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ 80279377Simp 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 81279377Simp 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 82279377Simp 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 83279377Simp 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 84279377Simp 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ 85279377Simp >; 86279377Simp }; 87279377Simp 88279377Simp cpsw_sleep: cpsw_sleep { 89279377Simp pinctrl-single,pins = < 90279377Simp /* Slave 1 reset value */ 91279377Simp 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) 92279377Simp 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) 93279377Simp 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 94279377Simp 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 95279377Simp 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 96279377Simp 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 97279377Simp 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 98279377Simp 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 99279377Simp 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) 100279377Simp >; 101279377Simp }; 102279377Simp 103279377Simp davinci_mdio_default: davinci_mdio_default { 104279377Simp pinctrl-single,pins = < 105279377Simp /* MDIO */ 106279377Simp 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 107279377Simp 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 108279377Simp >; 109279377Simp }; 110279377Simp 111279377Simp davinci_mdio_sleep: davinci_mdio_sleep { 112279377Simp pinctrl-single,pins = < 113279377Simp /* MDIO reset value */ 114279377Simp 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 115279377Simp 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 116279377Simp >; 117279377Simp }; 118279377Simp 119279377Simp i2c0_pins: pinmux_i2c0_pins { 120279377Simp pinctrl-single,pins = < 121279377Simp 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 122279377Simp 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 123279377Simp >; 124279377Simp }; 125279377Simp 126279377Simp nand_flash_x8: nand_flash_x8 { 127279377Simp pinctrl-single,pins = < 128279377Simp 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ 129279377Simp 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 130279377Simp 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 131279377Simp 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 132279377Simp 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 133279377Simp 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 134279377Simp 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 135279377Simp 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 136279377Simp 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 137279377Simp 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 138279377Simp 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ 139279377Simp 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 140279377Simp 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 141279377Simp 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 142279377Simp 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 143279377Simp 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 144279377Simp >; 145279377Simp }; 146279377Simp 147279377Simp ecap0_pins: backlight_pins { 148279377Simp pinctrl-single,pins = < 149279377Simp 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 150279377Simp >; 151279377Simp }; 152279377Simp 153279377Simp i2c2_pins: pinmux_i2c2_pins { 154279377Simp pinctrl-single,pins = < 155279377Simp 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ 156279377Simp 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ 157279377Simp >; 158279377Simp }; 159279377Simp 160279377Simp spi0_pins: pinmux_spi0_pins { 161279377Simp pinctrl-single,pins = < 162279377Simp 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ 163279377Simp 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ 164279377Simp 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ 165279377Simp 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ 166279377Simp >; 167279377Simp }; 168279377Simp 169279377Simp spi1_pins: pinmux_spi1_pins { 170279377Simp pinctrl-single,pins = < 171279377Simp 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ 172279377Simp 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ 173279377Simp 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ 174279377Simp 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ 175279377Simp >; 176279377Simp }; 177279377Simp 178279377Simp mmc1_pins: pinmux_mmc1_pins { 179279377Simp pinctrl-single,pins = < 180279377Simp 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 181279377Simp >; 182279377Simp }; 183279377Simp 184279377Simp qspi1_default: qspi1_default { 185279377Simp pinctrl-single,pins = < 186279377Simp 0x7c (PIN_INPUT_PULLUP | MUX_MODE3) 187279377Simp 0x88 (PIN_INPUT_PULLUP | MUX_MODE2) 188279377Simp 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) 189279377Simp 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) 190279377Simp 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) 191279377Simp 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) 192279377Simp >; 193279377Simp }; 194279377Simp 195279377Simp pixcir_ts_pins: pixcir_ts_pins { 196279377Simp pinctrl-single,pins = < 197279377Simp 0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ 198279377Simp >; 199279377Simp }; 200279377Simp 201279377Simp hdq_pins: pinmux_hdq_pins { 202279377Simp pinctrl-single,pins = < 203279377Simp 0x234 (PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ 204279377Simp >; 205279377Simp }; 206279377Simp 207279377Simp dss_pins: dss_pins { 208279377Simp pinctrl-single,pins = < 209279377Simp 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ 210279377Simp 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) 211279377Simp 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) 212279377Simp 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1) 213279377Simp 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) 214279377Simp 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) 215279377Simp 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) 216279377Simp 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ 217279377Simp 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ 218279377Simp 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 219279377Simp 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 220279377Simp 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0) 221279377Simp 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 222279377Simp 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 223279377Simp 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 224279377Simp 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0) 225279377Simp 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 226279377Simp 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 227279377Simp 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 228279377Simp 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0) 229279377Simp 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 230279377Simp 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 231279377Simp 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 232279377Simp 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ 233279377Simp 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ 234279377Simp 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ 235279377Simp 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ 236279377Simp 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ 237279377Simp >; 238279377Simp }; 239279377Simp 240279377Simp lcd_pins: lcd_pins { 241279377Simp pinctrl-single,pins = < 242279377Simp /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ 243279377Simp 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7) 244279377Simp >; 245279377Simp }; 246279377Simp 247279377Simp vpfe1_pins_default: vpfe1_pins_default { 248279377Simp pinctrl-single,pins = < 249279377Simp 0x1cc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ 250279377Simp 0x1d0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ 251279377Simp 0x1d4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ 252279377Simp 0x1d8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ 253279377Simp 0x1dc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ 254279377Simp 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ 255279377Simp 0x1ec (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ 256279377Simp 0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ 257279377Simp 0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ 258279377Simp 0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ 259279377Simp 0x1fc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ 260279377Simp 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ 261279377Simp 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ 262279377Simp >; 263279377Simp }; 264279377Simp 265279377Simp vpfe1_pins_sleep: vpfe1_pins_sleep { 266279377Simp pinctrl-single,pins = < 267279377Simp 0x1cc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 268279377Simp 0x1d0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 269279377Simp 0x1d4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 270279377Simp 0x1d8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 271279377Simp 0x1dc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 272279377Simp 0x1e8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 273279377Simp 0x1ec (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 274279377Simp 0x1f0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 275279377Simp 0x1f4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 276279377Simp 0x1f8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 277279377Simp 0x1fc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 278279377Simp 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 279279377Simp 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 280279377Simp >; 281279377Simp }; 282279377Simp }; 283279377Simp 284279377Simp matrix_keypad: matrix_keypad@0 { 285279377Simp compatible = "gpio-matrix-keypad"; 286279377Simp debounce-delay-ms = <5>; 287279377Simp col-scan-delay-us = <2>; 288279377Simp 289279377Simp row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ 290279377Simp &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ 291279377Simp &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ 292279377Simp &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ 293279377Simp 294279377Simp col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ 295279377Simp &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ 296279377Simp &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ 297279377Simp &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ 298279377Simp 299279377Simp linux,keymap = <0x00000201 /* P1 */ 300279377Simp 0x01000204 /* P4 */ 301279377Simp 0x02000207 /* P7 */ 302279377Simp 0x0300020a /* NUMERIC_STAR */ 303279377Simp 0x00010202 /* P2 */ 304279377Simp 0x01010205 /* P5 */ 305279377Simp 0x02010208 /* P8 */ 306279377Simp 0x03010200 /* P0 */ 307279377Simp 0x00020203 /* P3 */ 308279377Simp 0x01020206 /* P6 */ 309279377Simp 0x02020209 /* P9 */ 310279377Simp 0x0302020b /* NUMERIC_POUND */ 311279377Simp 0x00030067 /* UP */ 312279377Simp 0x0103006a /* RIGHT */ 313279377Simp 0x0203006c /* DOWN */ 314279377Simp 0x03030069>; /* LEFT */ 315279377Simp }; 316279377Simp 317279377Simp backlight { 318279377Simp compatible = "pwm-backlight"; 319279377Simp pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; 320279377Simp brightness-levels = <0 51 53 56 62 75 101 152 255>; 321279377Simp default-brightness-level = <8>; 322279377Simp }; 323279377Simp}; 324279377Simp 325279377Simp&mmc1 { 326279377Simp status = "okay"; 327279377Simp vmmc-supply = <&vmmcsd_fixed>; 328279377Simp bus-width = <4>; 329279377Simp pinctrl-names = "default"; 330279377Simp pinctrl-0 = <&mmc1_pins>; 331279377Simp cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; 332279377Simp}; 333279377Simp 334279377Simp&mac { 335279377Simp pinctrl-names = "default", "sleep"; 336279377Simp pinctrl-0 = <&cpsw_default>; 337279377Simp pinctrl-1 = <&cpsw_sleep>; 338279377Simp status = "okay"; 339279377Simp}; 340279377Simp 341279377Simp&davinci_mdio { 342279377Simp pinctrl-names = "default", "sleep"; 343279377Simp pinctrl-0 = <&davinci_mdio_default>; 344279377Simp pinctrl-1 = <&davinci_mdio_sleep>; 345279377Simp status = "okay"; 346279377Simp}; 347279377Simp 348279377Simp&cpsw_emac0 { 349279377Simp phy_id = <&davinci_mdio>, <16>; 350279377Simp phy-mode = "rmii"; 351279377Simp}; 352279377Simp 353279377Simp&cpsw_emac1 { 354279377Simp phy_id = <&davinci_mdio>, <1>; 355279377Simp phy-mode = "rmii"; 356279377Simp}; 357279377Simp 358279377Simp&phy_sel { 359279377Simp rmii-clock-ext; 360279377Simp}; 361279377Simp 362279377Simp&i2c0 { 363279377Simp status = "okay"; 364279377Simp pinctrl-names = "default"; 365279377Simp pinctrl-0 = <&i2c0_pins>; 366279377Simp clock-frequency = <400000>; 367279377Simp 368279377Simp tps65218: tps65218@24 { 369279377Simp reg = <0x24>; 370279377Simp compatible = "ti,tps65218"; 371279377Simp interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ 372279377Simp interrupt-parent = <&gic>; 373279377Simp interrupt-controller; 374279377Simp #interrupt-cells = <2>; 375279377Simp 376279377Simp dcdc1: regulator-dcdc1 { 377279377Simp compatible = "ti,tps65218-dcdc1"; 378279377Simp regulator-name = "vdd_core"; 379279377Simp regulator-min-microvolt = <912000>; 380279377Simp regulator-max-microvolt = <1144000>; 381279377Simp regulator-boot-on; 382279377Simp regulator-always-on; 383279377Simp }; 384279377Simp 385279377Simp dcdc2: regulator-dcdc2 { 386279377Simp compatible = "ti,tps65218-dcdc2"; 387279377Simp regulator-name = "vdd_mpu"; 388279377Simp regulator-min-microvolt = <912000>; 389279377Simp regulator-max-microvolt = <1378000>; 390279377Simp regulator-boot-on; 391279377Simp regulator-always-on; 392279377Simp }; 393279377Simp 394279377Simp dcdc3: regulator-dcdc3 { 395279377Simp compatible = "ti,tps65218-dcdc3"; 396279377Simp regulator-name = "vdcdc3"; 397279377Simp regulator-min-microvolt = <1500000>; 398279377Simp regulator-max-microvolt = <1500000>; 399279377Simp regulator-boot-on; 400279377Simp regulator-always-on; 401279377Simp }; 402279377Simp 403279377Simp dcdc5: regulator-dcdc5 { 404279377Simp compatible = "ti,tps65218-dcdc5"; 405279377Simp regulator-name = "v1_0bat"; 406279377Simp regulator-min-microvolt = <1000000>; 407279377Simp regulator-max-microvolt = <1000000>; 408279377Simp }; 409279377Simp 410279377Simp dcdc6: regulator-dcdc6 { 411279377Simp compatible = "ti,tps65218-dcdc6"; 412279377Simp regulator-name = "v1_8bat"; 413279377Simp regulator-min-microvolt = <1800000>; 414279377Simp regulator-max-microvolt = <1800000>; 415279377Simp }; 416279377Simp 417279377Simp ldo1: regulator-ldo1 { 418279377Simp compatible = "ti,tps65218-ldo1"; 419279377Simp regulator-min-microvolt = <1800000>; 420279377Simp regulator-max-microvolt = <1800000>; 421279377Simp regulator-boot-on; 422279377Simp regulator-always-on; 423279377Simp }; 424279377Simp }; 425279377Simp 426279377Simp at24@50 { 427279377Simp compatible = "at24,24c256"; 428279377Simp pagesize = <64>; 429279377Simp reg = <0x50>; 430279377Simp }; 431279377Simp 432279377Simp pixcir_ts@5c { 433279377Simp compatible = "pixcir,pixcir_tangoc"; 434279377Simp pinctrl-names = "default"; 435279377Simp pinctrl-0 = <&pixcir_ts_pins>; 436279377Simp reg = <0x5c>; 437279377Simp interrupt-parent = <&gpio1>; 438279377Simp interrupts = <17 0>; 439279377Simp 440279377Simp attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; 441279377Simp 442279377Simp touchscreen-size-x = <1024>; 443279377Simp touchscreen-size-y = <600>; 444279377Simp }; 445279377Simp}; 446279377Simp 447279377Simp&i2c2 { 448279377Simp pinctrl-names = "default"; 449279377Simp pinctrl-0 = <&i2c2_pins>; 450279377Simp status = "okay"; 451279377Simp}; 452279377Simp 453279377Simp&gpio0 { 454279377Simp status = "okay"; 455279377Simp}; 456279377Simp 457279377Simp&gpio1 { 458279377Simp status = "okay"; 459279377Simp}; 460279377Simp 461279377Simp&gpio2 { 462279377Simp status = "okay"; 463279377Simp}; 464279377Simp 465279377Simp&gpio3 { 466279377Simp status = "okay"; 467279377Simp}; 468279377Simp 469279377Simp&elm { 470279377Simp status = "okay"; 471279377Simp}; 472279377Simp 473279377Simp&gpmc { 474279377Simp status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ 475279377Simp pinctrl-names = "default"; 476279377Simp pinctrl-0 = <&nand_flash_x8>; 477279377Simp ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 478279377Simp nand@0,0 { 479279377Simp reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 480279377Simp ti,nand-ecc-opt = "bch16"; 481279377Simp ti,elm-id = <&elm>; 482279377Simp nand-bus-width = <8>; 483279377Simp gpmc,device-width = <1>; 484279377Simp gpmc,sync-clk-ps = <0>; 485279377Simp gpmc,cs-on-ns = <0>; 486279377Simp gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ 487279377Simp gpmc,cs-wr-off-ns = <40>; 488279377Simp gpmc,adv-on-ns = <0>; /* cs-on-ns */ 489279377Simp gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ 490279377Simp gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ 491279377Simp gpmc,we-on-ns = <0>; /* cs-on-ns */ 492279377Simp gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ 493279377Simp gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ 494279377Simp gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ 495279377Simp gpmc,access-ns = <30>; /* tCEA + 4*/ 496279377Simp gpmc,rd-cycle-ns = <40>; 497279377Simp gpmc,wr-cycle-ns = <40>; 498279377Simp gpmc,wait-pin = <0>; 499279377Simp gpmc,bus-turnaround-ns = <0>; 500279377Simp gpmc,cycle2cycle-delay-ns = <0>; 501279377Simp gpmc,clk-activation-ns = <0>; 502279377Simp gpmc,wait-monitoring-ns = <0>; 503279377Simp gpmc,wr-access-ns = <40>; 504279377Simp gpmc,wr-data-mux-bus-ns = <0>; 505279377Simp /* MTD partition table */ 506279377Simp /* All SPL-* partitions are sized to minimal length 507279377Simp * which can be independently programmable. For 508279377Simp * NAND flash this is equal to size of erase-block */ 509279377Simp #address-cells = <1>; 510279377Simp #size-cells = <1>; 511279377Simp partition@0 { 512279377Simp label = "NAND.SPL"; 513279377Simp reg = <0x00000000 0x00040000>; 514279377Simp }; 515279377Simp partition@1 { 516279377Simp label = "NAND.SPL.backup1"; 517279377Simp reg = <0x00040000 0x00040000>; 518279377Simp }; 519279377Simp partition@2 { 520279377Simp label = "NAND.SPL.backup2"; 521279377Simp reg = <0x00080000 0x00040000>; 522279377Simp }; 523279377Simp partition@3 { 524279377Simp label = "NAND.SPL.backup3"; 525279377Simp reg = <0x000C0000 0x00040000>; 526279377Simp }; 527279377Simp partition@4 { 528279377Simp label = "NAND.u-boot-spl-os"; 529279377Simp reg = <0x00100000 0x00080000>; 530279377Simp }; 531279377Simp partition@5 { 532279377Simp label = "NAND.u-boot"; 533279377Simp reg = <0x00180000 0x00100000>; 534279377Simp }; 535279377Simp partition@6 { 536279377Simp label = "NAND.u-boot-env"; 537279377Simp reg = <0x00280000 0x00040000>; 538279377Simp }; 539279377Simp partition@7 { 540279377Simp label = "NAND.u-boot-env.backup1"; 541279377Simp reg = <0x002C0000 0x00040000>; 542279377Simp }; 543279377Simp partition@8 { 544279377Simp label = "NAND.kernel"; 545279377Simp reg = <0x00300000 0x00700000>; 546279377Simp }; 547279377Simp partition@9 { 548279377Simp label = "NAND.file-system"; 549279377Simp reg = <0x00a00000 0x1f600000>; 550279377Simp }; 551279377Simp }; 552279377Simp}; 553279377Simp 554279377Simp&epwmss0 { 555279377Simp status = "okay"; 556279377Simp}; 557279377Simp 558279377Simp&tscadc { 559279377Simp status = "okay"; 560279377Simp 561279377Simp adc { 562279377Simp ti,adc-channels = <0 1 2 3 4 5 6 7>; 563279377Simp }; 564279377Simp}; 565279377Simp 566279377Simp&ecap0 { 567279377Simp status = "okay"; 568279377Simp pinctrl-names = "default"; 569279377Simp pinctrl-0 = <&ecap0_pins>; 570279377Simp}; 571279377Simp 572279377Simp&spi0 { 573279377Simp pinctrl-names = "default"; 574279377Simp pinctrl-0 = <&spi0_pins>; 575279377Simp status = "okay"; 576279377Simp}; 577279377Simp 578279377Simp&spi1 { 579279377Simp pinctrl-names = "default"; 580279377Simp pinctrl-0 = <&spi1_pins>; 581279377Simp status = "okay"; 582279377Simp}; 583279377Simp 584279377Simp&usb2_phy1 { 585279377Simp status = "okay"; 586279377Simp}; 587279377Simp 588279377Simp&usb1 { 589279377Simp dr_mode = "peripheral"; 590279377Simp status = "okay"; 591279377Simp}; 592279377Simp 593279377Simp&usb2_phy2 { 594279377Simp status = "okay"; 595279377Simp}; 596279377Simp 597279377Simp&usb2 { 598279377Simp dr_mode = "host"; 599279377Simp status = "okay"; 600279377Simp}; 601279377Simp 602279377Simp&qspi { 603279377Simp status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ 604279377Simp pinctrl-names = "default"; 605279377Simp pinctrl-0 = <&qspi1_default>; 606279377Simp 607279377Simp spi-max-frequency = <48000000>; 608279377Simp m25p80@0 { 609279377Simp compatible = "mx66l51235l"; 610279377Simp spi-max-frequency = <48000000>; 611279377Simp reg = <0>; 612279377Simp spi-cpol; 613279377Simp spi-cpha; 614279377Simp spi-tx-bus-width = <1>; 615279377Simp spi-rx-bus-width = <4>; 616279377Simp #address-cells = <1>; 617279377Simp #size-cells = <1>; 618279377Simp 619279377Simp /* MTD partition table. 620279377Simp * The ROM checks the first 512KiB 621279377Simp * for a valid file to boot(XIP). 622279377Simp */ 623279377Simp partition@0 { 624279377Simp label = "QSPI.U_BOOT"; 625279377Simp reg = <0x00000000 0x000080000>; 626279377Simp }; 627279377Simp partition@1 { 628279377Simp label = "QSPI.U_BOOT.backup"; 629279377Simp reg = <0x00080000 0x00080000>; 630279377Simp }; 631279377Simp partition@2 { 632279377Simp label = "QSPI.U-BOOT-SPL_OS"; 633279377Simp reg = <0x00100000 0x00010000>; 634279377Simp }; 635279377Simp partition@3 { 636279377Simp label = "QSPI.U_BOOT_ENV"; 637279377Simp reg = <0x00110000 0x00010000>; 638279377Simp }; 639279377Simp partition@4 { 640279377Simp label = "QSPI.U-BOOT-ENV.backup"; 641279377Simp reg = <0x00120000 0x00010000>; 642279377Simp }; 643279377Simp partition@5 { 644279377Simp label = "QSPI.KERNEL"; 645279377Simp reg = <0x00130000 0x0800000>; 646279377Simp }; 647279377Simp partition@6 { 648279377Simp label = "QSPI.FILESYSTEM"; 649279377Simp reg = <0x00930000 0x36D0000>; 650279377Simp }; 651279377Simp }; 652279377Simp}; 653279377Simp 654279377Simp&hdq { 655279377Simp status = "okay"; 656279377Simp pinctrl-names = "default"; 657279377Simp pinctrl-0 = <&hdq_pins>; 658279377Simp}; 659279377Simp 660279377Simp&dss { 661279377Simp status = "ok"; 662279377Simp 663279377Simp pinctrl-names = "default"; 664279377Simp pinctrl-0 = <&dss_pins>; 665279377Simp 666279377Simp port { 667279377Simp dpi_out: endpoint@0 { 668279377Simp remote-endpoint = <&lcd_in>; 669279377Simp data-lines = <24>; 670279377Simp }; 671279377Simp }; 672279377Simp}; 673279377Simp 674279377Simp&vpfe1 { 675279377Simp status = "okay"; 676279377Simp pinctrl-names = "default", "sleep"; 677279377Simp pinctrl-0 = <&vpfe1_pins_default>; 678279377Simp pinctrl-1 = <&vpfe1_pins_sleep>; 679279377Simp 680279377Simp port { 681279377Simp vpfe1_ep: endpoint { 682279377Simp /* remote-endpoint = <&sensor>; add once we have it */ 683279377Simp ti,am437x-vpfe-interface = <0>; 684279377Simp bus-width = <8>; 685279377Simp hsync-active = <0>; 686279377Simp vsync-active = <0>; 687279377Simp }; 688279377Simp }; 689279377Simp}; 690