1279377Simp/* 2279377Simp * Device Tree Source for AM33xx clock data 3279377Simp * 4279377Simp * Copyright (C) 2013 Texas Instruments, Inc. 5279377Simp * 6279377Simp * This program is free software; you can redistribute it and/or modify 7279377Simp * it under the terms of the GNU General Public License version 2 as 8279377Simp * published by the Free Software Foundation. 9279377Simp */ 10279377Simp&scrm_clocks { 11279377Simp sys_clkin_ck: sys_clkin_ck { 12279377Simp #clock-cells = <0>; 13279377Simp compatible = "ti,mux-clock"; 14279377Simp clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 15279377Simp ti,bit-shift = <22>; 16279377Simp reg = <0x0040>; 17279377Simp }; 18279377Simp 19279377Simp adc_tsc_fck: adc_tsc_fck { 20279377Simp #clock-cells = <0>; 21279377Simp compatible = "fixed-factor-clock"; 22279377Simp clocks = <&sys_clkin_ck>; 23279377Simp clock-mult = <1>; 24279377Simp clock-div = <1>; 25279377Simp }; 26279377Simp 27279377Simp dcan0_fck: dcan0_fck { 28279377Simp #clock-cells = <0>; 29279377Simp compatible = "fixed-factor-clock"; 30279377Simp clocks = <&sys_clkin_ck>; 31279377Simp clock-mult = <1>; 32279377Simp clock-div = <1>; 33279377Simp }; 34279377Simp 35279377Simp dcan1_fck: dcan1_fck { 36279377Simp #clock-cells = <0>; 37279377Simp compatible = "fixed-factor-clock"; 38279377Simp clocks = <&sys_clkin_ck>; 39279377Simp clock-mult = <1>; 40279377Simp clock-div = <1>; 41279377Simp }; 42279377Simp 43279377Simp mcasp0_fck: mcasp0_fck { 44279377Simp #clock-cells = <0>; 45279377Simp compatible = "fixed-factor-clock"; 46279377Simp clocks = <&sys_clkin_ck>; 47279377Simp clock-mult = <1>; 48279377Simp clock-div = <1>; 49279377Simp }; 50279377Simp 51279377Simp mcasp1_fck: mcasp1_fck { 52279377Simp #clock-cells = <0>; 53279377Simp compatible = "fixed-factor-clock"; 54279377Simp clocks = <&sys_clkin_ck>; 55279377Simp clock-mult = <1>; 56279377Simp clock-div = <1>; 57279377Simp }; 58279377Simp 59279377Simp smartreflex0_fck: smartreflex0_fck { 60279377Simp #clock-cells = <0>; 61279377Simp compatible = "fixed-factor-clock"; 62279377Simp clocks = <&sys_clkin_ck>; 63279377Simp clock-mult = <1>; 64279377Simp clock-div = <1>; 65279377Simp }; 66279377Simp 67279377Simp smartreflex1_fck: smartreflex1_fck { 68279377Simp #clock-cells = <0>; 69279377Simp compatible = "fixed-factor-clock"; 70279377Simp clocks = <&sys_clkin_ck>; 71279377Simp clock-mult = <1>; 72279377Simp clock-div = <1>; 73279377Simp }; 74279377Simp 75279377Simp sha0_fck: sha0_fck { 76279377Simp #clock-cells = <0>; 77279377Simp compatible = "fixed-factor-clock"; 78279377Simp clocks = <&sys_clkin_ck>; 79279377Simp clock-mult = <1>; 80279377Simp clock-div = <1>; 81279377Simp }; 82279377Simp 83279377Simp aes0_fck: aes0_fck { 84279377Simp #clock-cells = <0>; 85279377Simp compatible = "fixed-factor-clock"; 86279377Simp clocks = <&sys_clkin_ck>; 87279377Simp clock-mult = <1>; 88279377Simp clock-div = <1>; 89279377Simp }; 90279377Simp 91279377Simp rng_fck: rng_fck { 92279377Simp #clock-cells = <0>; 93279377Simp compatible = "fixed-factor-clock"; 94279377Simp clocks = <&sys_clkin_ck>; 95279377Simp clock-mult = <1>; 96279377Simp clock-div = <1>; 97279377Simp }; 98279377Simp 99279377Simp ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { 100279377Simp #clock-cells = <0>; 101279377Simp compatible = "ti,gate-clock"; 102279377Simp clocks = <&dpll_per_m2_ck>; 103279377Simp ti,bit-shift = <0>; 104279377Simp reg = <0x0664>; 105279377Simp }; 106279377Simp 107279377Simp ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { 108279377Simp #clock-cells = <0>; 109279377Simp compatible = "ti,gate-clock"; 110279377Simp clocks = <&dpll_per_m2_ck>; 111279377Simp ti,bit-shift = <1>; 112279377Simp reg = <0x0664>; 113279377Simp }; 114279377Simp 115279377Simp ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { 116279377Simp #clock-cells = <0>; 117279377Simp compatible = "ti,gate-clock"; 118279377Simp clocks = <&dpll_per_m2_ck>; 119279377Simp ti,bit-shift = <2>; 120279377Simp reg = <0x0664>; 121279377Simp }; 122279377Simp}; 123279377Simp&prcm_clocks { 124279377Simp clk_32768_ck: clk_32768_ck { 125279377Simp #clock-cells = <0>; 126279377Simp compatible = "fixed-clock"; 127279377Simp clock-frequency = <32768>; 128279377Simp }; 129279377Simp 130279377Simp clk_rc32k_ck: clk_rc32k_ck { 131279377Simp #clock-cells = <0>; 132279377Simp compatible = "fixed-clock"; 133279377Simp clock-frequency = <32000>; 134279377Simp }; 135279377Simp 136279377Simp virt_19200000_ck: virt_19200000_ck { 137279377Simp #clock-cells = <0>; 138279377Simp compatible = "fixed-clock"; 139279377Simp clock-frequency = <19200000>; 140279377Simp }; 141279377Simp 142279377Simp virt_24000000_ck: virt_24000000_ck { 143279377Simp #clock-cells = <0>; 144279377Simp compatible = "fixed-clock"; 145279377Simp clock-frequency = <24000000>; 146279377Simp }; 147279377Simp 148279377Simp virt_25000000_ck: virt_25000000_ck { 149279377Simp #clock-cells = <0>; 150279377Simp compatible = "fixed-clock"; 151279377Simp clock-frequency = <25000000>; 152279377Simp }; 153279377Simp 154279377Simp virt_26000000_ck: virt_26000000_ck { 155279377Simp #clock-cells = <0>; 156279377Simp compatible = "fixed-clock"; 157279377Simp clock-frequency = <26000000>; 158279377Simp }; 159279377Simp 160279377Simp tclkin_ck: tclkin_ck { 161279377Simp #clock-cells = <0>; 162279377Simp compatible = "fixed-clock"; 163279377Simp clock-frequency = <12000000>; 164279377Simp }; 165279377Simp 166279377Simp dpll_core_ck: dpll_core_ck { 167279377Simp #clock-cells = <0>; 168279377Simp compatible = "ti,am3-dpll-core-clock"; 169279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 170279377Simp reg = <0x0490>, <0x045c>, <0x0468>; 171279377Simp }; 172279377Simp 173279377Simp dpll_core_x2_ck: dpll_core_x2_ck { 174279377Simp #clock-cells = <0>; 175279377Simp compatible = "ti,am3-dpll-x2-clock"; 176279377Simp clocks = <&dpll_core_ck>; 177279377Simp }; 178279377Simp 179279377Simp dpll_core_m4_ck: dpll_core_m4_ck { 180279377Simp #clock-cells = <0>; 181279377Simp compatible = "ti,divider-clock"; 182279377Simp clocks = <&dpll_core_x2_ck>; 183279377Simp ti,max-div = <31>; 184279377Simp reg = <0x0480>; 185279377Simp ti,index-starts-at-one; 186279377Simp }; 187279377Simp 188279377Simp dpll_core_m5_ck: dpll_core_m5_ck { 189279377Simp #clock-cells = <0>; 190279377Simp compatible = "ti,divider-clock"; 191279377Simp clocks = <&dpll_core_x2_ck>; 192279377Simp ti,max-div = <31>; 193279377Simp reg = <0x0484>; 194279377Simp ti,index-starts-at-one; 195279377Simp }; 196279377Simp 197279377Simp dpll_core_m6_ck: dpll_core_m6_ck { 198279377Simp #clock-cells = <0>; 199279377Simp compatible = "ti,divider-clock"; 200279377Simp clocks = <&dpll_core_x2_ck>; 201279377Simp ti,max-div = <31>; 202279377Simp reg = <0x04d8>; 203279377Simp ti,index-starts-at-one; 204279377Simp }; 205279377Simp 206279377Simp dpll_mpu_ck: dpll_mpu_ck { 207279377Simp #clock-cells = <0>; 208279377Simp compatible = "ti,am3-dpll-clock"; 209279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 210279377Simp reg = <0x0488>, <0x0420>, <0x042c>; 211279377Simp }; 212279377Simp 213279377Simp dpll_mpu_m2_ck: dpll_mpu_m2_ck { 214279377Simp #clock-cells = <0>; 215279377Simp compatible = "ti,divider-clock"; 216279377Simp clocks = <&dpll_mpu_ck>; 217279377Simp ti,max-div = <31>; 218279377Simp reg = <0x04a8>; 219279377Simp ti,index-starts-at-one; 220279377Simp }; 221279377Simp 222279377Simp dpll_ddr_ck: dpll_ddr_ck { 223279377Simp #clock-cells = <0>; 224279377Simp compatible = "ti,am3-dpll-no-gate-clock"; 225279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 226279377Simp reg = <0x0494>, <0x0434>, <0x0440>; 227279377Simp }; 228279377Simp 229279377Simp dpll_ddr_m2_ck: dpll_ddr_m2_ck { 230279377Simp #clock-cells = <0>; 231279377Simp compatible = "ti,divider-clock"; 232279377Simp clocks = <&dpll_ddr_ck>; 233279377Simp ti,max-div = <31>; 234279377Simp reg = <0x04a0>; 235279377Simp ti,index-starts-at-one; 236279377Simp }; 237279377Simp 238279377Simp dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { 239279377Simp #clock-cells = <0>; 240279377Simp compatible = "fixed-factor-clock"; 241279377Simp clocks = <&dpll_ddr_m2_ck>; 242279377Simp clock-mult = <1>; 243279377Simp clock-div = <2>; 244279377Simp }; 245279377Simp 246279377Simp dpll_disp_ck: dpll_disp_ck { 247279377Simp #clock-cells = <0>; 248279377Simp compatible = "ti,am3-dpll-no-gate-clock"; 249279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 250279377Simp reg = <0x0498>, <0x0448>, <0x0454>; 251279377Simp }; 252279377Simp 253279377Simp dpll_disp_m2_ck: dpll_disp_m2_ck { 254279377Simp #clock-cells = <0>; 255279377Simp compatible = "ti,divider-clock"; 256279377Simp clocks = <&dpll_disp_ck>; 257279377Simp ti,max-div = <31>; 258279377Simp reg = <0x04a4>; 259279377Simp ti,index-starts-at-one; 260279377Simp ti,set-rate-parent; 261279377Simp }; 262279377Simp 263279377Simp dpll_per_ck: dpll_per_ck { 264279377Simp #clock-cells = <0>; 265279377Simp compatible = "ti,am3-dpll-no-gate-j-type-clock"; 266279377Simp clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 267279377Simp reg = <0x048c>, <0x0470>, <0x049c>; 268279377Simp }; 269279377Simp 270279377Simp dpll_per_m2_ck: dpll_per_m2_ck { 271279377Simp #clock-cells = <0>; 272279377Simp compatible = "ti,divider-clock"; 273279377Simp clocks = <&dpll_per_ck>; 274279377Simp ti,max-div = <31>; 275279377Simp reg = <0x04ac>; 276279377Simp ti,index-starts-at-one; 277279377Simp }; 278279377Simp 279279377Simp dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { 280279377Simp #clock-cells = <0>; 281279377Simp compatible = "fixed-factor-clock"; 282279377Simp clocks = <&dpll_per_m2_ck>; 283279377Simp clock-mult = <1>; 284279377Simp clock-div = <4>; 285279377Simp }; 286279377Simp 287279377Simp dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { 288279377Simp #clock-cells = <0>; 289279377Simp compatible = "fixed-factor-clock"; 290279377Simp clocks = <&dpll_per_m2_ck>; 291279377Simp clock-mult = <1>; 292279377Simp clock-div = <4>; 293279377Simp }; 294279377Simp 295279377Simp cefuse_fck: cefuse_fck { 296279377Simp #clock-cells = <0>; 297279377Simp compatible = "ti,gate-clock"; 298279377Simp clocks = <&sys_clkin_ck>; 299279377Simp ti,bit-shift = <1>; 300279377Simp reg = <0x0a20>; 301279377Simp }; 302279377Simp 303279377Simp clk_24mhz: clk_24mhz { 304279377Simp #clock-cells = <0>; 305279377Simp compatible = "fixed-factor-clock"; 306279377Simp clocks = <&dpll_per_m2_ck>; 307279377Simp clock-mult = <1>; 308279377Simp clock-div = <8>; 309279377Simp }; 310279377Simp 311279377Simp clkdiv32k_ck: clkdiv32k_ck { 312279377Simp #clock-cells = <0>; 313279377Simp compatible = "fixed-factor-clock"; 314279377Simp clocks = <&clk_24mhz>; 315279377Simp clock-mult = <1>; 316279377Simp clock-div = <732>; 317279377Simp }; 318279377Simp 319279377Simp clkdiv32k_ick: clkdiv32k_ick { 320279377Simp #clock-cells = <0>; 321279377Simp compatible = "ti,gate-clock"; 322279377Simp clocks = <&clkdiv32k_ck>; 323279377Simp ti,bit-shift = <1>; 324279377Simp reg = <0x014c>; 325279377Simp }; 326279377Simp 327279377Simp l3_gclk: l3_gclk { 328279377Simp #clock-cells = <0>; 329279377Simp compatible = "fixed-factor-clock"; 330279377Simp clocks = <&dpll_core_m4_ck>; 331279377Simp clock-mult = <1>; 332279377Simp clock-div = <1>; 333279377Simp }; 334279377Simp 335279377Simp pruss_ocp_gclk: pruss_ocp_gclk { 336279377Simp #clock-cells = <0>; 337279377Simp compatible = "ti,mux-clock"; 338279377Simp clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; 339279377Simp reg = <0x0530>; 340279377Simp }; 341279377Simp 342279377Simp mmu_fck: mmu_fck { 343279377Simp #clock-cells = <0>; 344279377Simp compatible = "ti,gate-clock"; 345279377Simp clocks = <&dpll_core_m4_ck>; 346279377Simp ti,bit-shift = <1>; 347279377Simp reg = <0x0914>; 348279377Simp }; 349279377Simp 350279377Simp timer1_fck: timer1_fck { 351279377Simp #clock-cells = <0>; 352279377Simp compatible = "ti,mux-clock"; 353279377Simp clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; 354279377Simp reg = <0x0528>; 355279377Simp }; 356279377Simp 357279377Simp timer2_fck: timer2_fck { 358279377Simp #clock-cells = <0>; 359279377Simp compatible = "ti,mux-clock"; 360279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 361279377Simp reg = <0x0508>; 362279377Simp }; 363279377Simp 364279377Simp timer3_fck: timer3_fck { 365279377Simp #clock-cells = <0>; 366279377Simp compatible = "ti,mux-clock"; 367279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 368279377Simp reg = <0x050c>; 369279377Simp }; 370279377Simp 371279377Simp timer4_fck: timer4_fck { 372279377Simp #clock-cells = <0>; 373279377Simp compatible = "ti,mux-clock"; 374279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 375279377Simp reg = <0x0510>; 376279377Simp }; 377279377Simp 378279377Simp timer5_fck: timer5_fck { 379279377Simp #clock-cells = <0>; 380279377Simp compatible = "ti,mux-clock"; 381279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 382279377Simp reg = <0x0518>; 383279377Simp }; 384279377Simp 385279377Simp timer6_fck: timer6_fck { 386279377Simp #clock-cells = <0>; 387279377Simp compatible = "ti,mux-clock"; 388279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 389279377Simp reg = <0x051c>; 390279377Simp }; 391279377Simp 392279377Simp timer7_fck: timer7_fck { 393279377Simp #clock-cells = <0>; 394279377Simp compatible = "ti,mux-clock"; 395279377Simp clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 396279377Simp reg = <0x0504>; 397279377Simp }; 398279377Simp 399279377Simp usbotg_fck: usbotg_fck { 400279377Simp #clock-cells = <0>; 401279377Simp compatible = "ti,gate-clock"; 402279377Simp clocks = <&dpll_per_ck>; 403279377Simp ti,bit-shift = <8>; 404279377Simp reg = <0x047c>; 405279377Simp }; 406279377Simp 407279377Simp dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { 408279377Simp #clock-cells = <0>; 409279377Simp compatible = "fixed-factor-clock"; 410279377Simp clocks = <&dpll_core_m4_ck>; 411279377Simp clock-mult = <1>; 412279377Simp clock-div = <2>; 413279377Simp }; 414279377Simp 415279377Simp ieee5000_fck: ieee5000_fck { 416279377Simp #clock-cells = <0>; 417279377Simp compatible = "ti,gate-clock"; 418279377Simp clocks = <&dpll_core_m4_div2_ck>; 419279377Simp ti,bit-shift = <1>; 420279377Simp reg = <0x00e4>; 421279377Simp }; 422279377Simp 423279377Simp wdt1_fck: wdt1_fck { 424279377Simp #clock-cells = <0>; 425279377Simp compatible = "ti,mux-clock"; 426279377Simp clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; 427279377Simp reg = <0x0538>; 428279377Simp }; 429279377Simp 430279377Simp l4_rtc_gclk: l4_rtc_gclk { 431279377Simp #clock-cells = <0>; 432279377Simp compatible = "fixed-factor-clock"; 433279377Simp clocks = <&dpll_core_m4_ck>; 434279377Simp clock-mult = <1>; 435279377Simp clock-div = <2>; 436279377Simp }; 437279377Simp 438279377Simp l4hs_gclk: l4hs_gclk { 439279377Simp #clock-cells = <0>; 440279377Simp compatible = "fixed-factor-clock"; 441279377Simp clocks = <&dpll_core_m4_ck>; 442279377Simp clock-mult = <1>; 443279377Simp clock-div = <1>; 444279377Simp }; 445279377Simp 446279377Simp l3s_gclk: l3s_gclk { 447279377Simp #clock-cells = <0>; 448279377Simp compatible = "fixed-factor-clock"; 449279377Simp clocks = <&dpll_core_m4_div2_ck>; 450279377Simp clock-mult = <1>; 451279377Simp clock-div = <1>; 452279377Simp }; 453279377Simp 454279377Simp l4fw_gclk: l4fw_gclk { 455279377Simp #clock-cells = <0>; 456279377Simp compatible = "fixed-factor-clock"; 457279377Simp clocks = <&dpll_core_m4_div2_ck>; 458279377Simp clock-mult = <1>; 459279377Simp clock-div = <1>; 460279377Simp }; 461279377Simp 462279377Simp l4ls_gclk: l4ls_gclk { 463279377Simp #clock-cells = <0>; 464279377Simp compatible = "fixed-factor-clock"; 465279377Simp clocks = <&dpll_core_m4_div2_ck>; 466279377Simp clock-mult = <1>; 467279377Simp clock-div = <1>; 468279377Simp }; 469279377Simp 470279377Simp sysclk_div_ck: sysclk_div_ck { 471279377Simp #clock-cells = <0>; 472279377Simp compatible = "fixed-factor-clock"; 473279377Simp clocks = <&dpll_core_m4_ck>; 474279377Simp clock-mult = <1>; 475279377Simp clock-div = <1>; 476279377Simp }; 477279377Simp 478279377Simp cpsw_125mhz_gclk: cpsw_125mhz_gclk { 479279377Simp #clock-cells = <0>; 480279377Simp compatible = "fixed-factor-clock"; 481279377Simp clocks = <&dpll_core_m5_ck>; 482279377Simp clock-mult = <1>; 483279377Simp clock-div = <2>; 484279377Simp }; 485279377Simp 486279377Simp cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { 487279377Simp #clock-cells = <0>; 488279377Simp compatible = "ti,mux-clock"; 489279377Simp clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; 490279377Simp reg = <0x0520>; 491279377Simp }; 492279377Simp 493279377Simp gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { 494279377Simp #clock-cells = <0>; 495279377Simp compatible = "ti,mux-clock"; 496279377Simp clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>; 497279377Simp reg = <0x053c>; 498279377Simp }; 499279377Simp 500279377Simp gpio0_dbclk: gpio0_dbclk { 501279377Simp #clock-cells = <0>; 502279377Simp compatible = "ti,gate-clock"; 503279377Simp clocks = <&gpio0_dbclk_mux_ck>; 504279377Simp ti,bit-shift = <18>; 505279377Simp reg = <0x0408>; 506279377Simp }; 507279377Simp 508279377Simp gpio1_dbclk: gpio1_dbclk { 509279377Simp #clock-cells = <0>; 510279377Simp compatible = "ti,gate-clock"; 511279377Simp clocks = <&clkdiv32k_ick>; 512279377Simp ti,bit-shift = <18>; 513279377Simp reg = <0x00ac>; 514279377Simp }; 515279377Simp 516279377Simp gpio2_dbclk: gpio2_dbclk { 517279377Simp #clock-cells = <0>; 518279377Simp compatible = "ti,gate-clock"; 519279377Simp clocks = <&clkdiv32k_ick>; 520279377Simp ti,bit-shift = <18>; 521279377Simp reg = <0x00b0>; 522279377Simp }; 523279377Simp 524279377Simp gpio3_dbclk: gpio3_dbclk { 525279377Simp #clock-cells = <0>; 526279377Simp compatible = "ti,gate-clock"; 527279377Simp clocks = <&clkdiv32k_ick>; 528279377Simp ti,bit-shift = <18>; 529279377Simp reg = <0x00b4>; 530279377Simp }; 531279377Simp 532279377Simp lcd_gclk: lcd_gclk { 533279377Simp #clock-cells = <0>; 534279377Simp compatible = "ti,mux-clock"; 535279377Simp clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; 536279377Simp reg = <0x0534>; 537279377Simp ti,set-rate-parent; 538279377Simp }; 539279377Simp 540279377Simp mmc_clk: mmc_clk { 541279377Simp #clock-cells = <0>; 542279377Simp compatible = "fixed-factor-clock"; 543279377Simp clocks = <&dpll_per_m2_ck>; 544279377Simp clock-mult = <1>; 545279377Simp clock-div = <2>; 546279377Simp }; 547279377Simp 548279377Simp gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { 549279377Simp #clock-cells = <0>; 550279377Simp compatible = "ti,mux-clock"; 551279377Simp clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; 552279377Simp ti,bit-shift = <1>; 553279377Simp reg = <0x052c>; 554279377Simp }; 555279377Simp 556279377Simp gfx_fck_div_ck: gfx_fck_div_ck { 557279377Simp #clock-cells = <0>; 558279377Simp compatible = "ti,divider-clock"; 559279377Simp clocks = <&gfx_fclk_clksel_ck>; 560279377Simp reg = <0x052c>; 561279377Simp ti,max-div = <2>; 562279377Simp }; 563279377Simp 564279377Simp sysclkout_pre_ck: sysclkout_pre_ck { 565279377Simp #clock-cells = <0>; 566279377Simp compatible = "ti,mux-clock"; 567279377Simp clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; 568279377Simp reg = <0x0700>; 569279377Simp }; 570279377Simp 571279377Simp clkout2_div_ck: clkout2_div_ck { 572279377Simp #clock-cells = <0>; 573279377Simp compatible = "ti,divider-clock"; 574279377Simp clocks = <&sysclkout_pre_ck>; 575279377Simp ti,bit-shift = <3>; 576279377Simp ti,max-div = <8>; 577279377Simp reg = <0x0700>; 578279377Simp }; 579279377Simp 580279377Simp dbg_sysclk_ck: dbg_sysclk_ck { 581279377Simp #clock-cells = <0>; 582279377Simp compatible = "ti,gate-clock"; 583279377Simp clocks = <&sys_clkin_ck>; 584279377Simp ti,bit-shift = <19>; 585279377Simp reg = <0x0414>; 586279377Simp }; 587279377Simp 588279377Simp dbg_clka_ck: dbg_clka_ck { 589279377Simp #clock-cells = <0>; 590279377Simp compatible = "ti,gate-clock"; 591279377Simp clocks = <&dpll_core_m4_ck>; 592279377Simp ti,bit-shift = <30>; 593279377Simp reg = <0x0414>; 594279377Simp }; 595279377Simp 596279377Simp stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck { 597279377Simp #clock-cells = <0>; 598279377Simp compatible = "ti,mux-clock"; 599279377Simp clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; 600279377Simp ti,bit-shift = <22>; 601279377Simp reg = <0x0414>; 602279377Simp }; 603279377Simp 604279377Simp trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck { 605279377Simp #clock-cells = <0>; 606279377Simp compatible = "ti,mux-clock"; 607279377Simp clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; 608279377Simp ti,bit-shift = <20>; 609279377Simp reg = <0x0414>; 610279377Simp }; 611279377Simp 612279377Simp stm_clk_div_ck: stm_clk_div_ck { 613279377Simp #clock-cells = <0>; 614279377Simp compatible = "ti,divider-clock"; 615279377Simp clocks = <&stm_pmd_clock_mux_ck>; 616279377Simp ti,bit-shift = <27>; 617279377Simp ti,max-div = <64>; 618279377Simp reg = <0x0414>; 619279377Simp ti,index-power-of-two; 620279377Simp }; 621279377Simp 622279377Simp trace_clk_div_ck: trace_clk_div_ck { 623279377Simp #clock-cells = <0>; 624279377Simp compatible = "ti,divider-clock"; 625279377Simp clocks = <&trace_pmd_clk_mux_ck>; 626279377Simp ti,bit-shift = <24>; 627279377Simp ti,max-div = <64>; 628279377Simp reg = <0x0414>; 629279377Simp ti,index-power-of-two; 630279377Simp }; 631279377Simp 632279377Simp clkout2_ck: clkout2_ck { 633279377Simp #clock-cells = <0>; 634279377Simp compatible = "ti,gate-clock"; 635279377Simp clocks = <&clkout2_div_ck>; 636279377Simp ti,bit-shift = <7>; 637279377Simp reg = <0x0700>; 638279377Simp }; 639279377Simp}; 640279377Simp 641279377Simp&prcm_clockdomains { 642279377Simp clk_24mhz_clkdm: clk_24mhz_clkdm { 643279377Simp compatible = "ti,clockdomain"; 644279377Simp clocks = <&clkdiv32k_ick>; 645279377Simp }; 646279377Simp}; 647