if_wb.c revision 92739
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_wb.c 92739 2002-03-20 02:08:01Z alfred $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus_memio.h> 108#include <machine/bus_pio.h> 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#include <dev/mii/mii.h> 118#include <dev/mii/miivar.h> 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <pci/if_wbreg.h> 126 127MODULE_DEPEND(wb, miibus, 1, 1, 1); 128 129#ifndef lint 130static const char rcsid[] = 131 "$FreeBSD: head/sys/pci/if_wb.c 92739 2002-03-20 02:08:01Z alfred $"; 132#endif 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137static struct wb_type wb_devs[] = { 138 { WB_VENDORID, WB_DEVICEID_840F, 139 "Winbond W89C840F 10/100BaseTX" }, 140 { CP_VENDORID, CP_DEVICEID_RL100, 141 "Compex RL100-ATX 10/100baseTX" }, 142 { 0, 0, NULL } 143}; 144 145static int wb_probe (device_t); 146static int wb_attach (device_t); 147static int wb_detach (device_t); 148 149static void wb_bfree (caddr_t, void *args); 150static int wb_newbuf (struct wb_softc *, 151 struct wb_chain_onefrag *, 152 struct mbuf *); 153static int wb_encap (struct wb_softc *, struct wb_chain *, 154 struct mbuf *); 155 156static void wb_rxeof (struct wb_softc *); 157static void wb_rxeoc (struct wb_softc *); 158static void wb_txeof (struct wb_softc *); 159static void wb_txeoc (struct wb_softc *); 160static void wb_intr (void *); 161static void wb_tick (void *); 162static void wb_start (struct ifnet *); 163static int wb_ioctl (struct ifnet *, u_long, caddr_t); 164static void wb_init (void *); 165static void wb_stop (struct wb_softc *); 166static void wb_watchdog (struct ifnet *); 167static void wb_shutdown (device_t); 168static int wb_ifmedia_upd (struct ifnet *); 169static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 170 171static void wb_eeprom_putbyte (struct wb_softc *, int); 172static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 173static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 174static void wb_mii_sync (struct wb_softc *); 175static void wb_mii_send (struct wb_softc *, u_int32_t, int); 176static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 177static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 178 179static void wb_setcfg (struct wb_softc *, u_int32_t); 180static u_int8_t wb_calchash (caddr_t); 181static void wb_setmulti (struct wb_softc *); 182static void wb_reset (struct wb_softc *); 183static void wb_fixmedia (struct wb_softc *); 184static int wb_list_rx_init (struct wb_softc *); 185static int wb_list_tx_init (struct wb_softc *); 186 187static int wb_miibus_readreg (device_t, int, int); 188static int wb_miibus_writereg (device_t, int, int, int); 189static void wb_miibus_statchg (device_t); 190 191#ifdef WB_USEIOSPACE 192#define WB_RES SYS_RES_IOPORT 193#define WB_RID WB_PCI_LOIO 194#else 195#define WB_RES SYS_RES_MEMORY 196#define WB_RID WB_PCI_LOMEM 197#endif 198 199static device_method_t wb_methods[] = { 200 /* Device interface */ 201 DEVMETHOD(device_probe, wb_probe), 202 DEVMETHOD(device_attach, wb_attach), 203 DEVMETHOD(device_detach, wb_detach), 204 DEVMETHOD(device_shutdown, wb_shutdown), 205 206 /* bus interface, for miibus */ 207 DEVMETHOD(bus_print_child, bus_generic_print_child), 208 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 209 210 /* MII interface */ 211 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 212 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 213 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 214 { 0, 0 } 215}; 216 217static driver_t wb_driver = { 218 "wb", 219 wb_methods, 220 sizeof(struct wb_softc) 221}; 222 223static devclass_t wb_devclass; 224 225DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 226DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 227 228#define WB_SETBIT(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, \ 230 CSR_READ_4(sc, reg) | x) 231 232#define WB_CLRBIT(sc, reg, x) \ 233 CSR_WRITE_4(sc, reg, \ 234 CSR_READ_4(sc, reg) & ~x) 235 236#define SIO_SET(x) \ 237 CSR_WRITE_4(sc, WB_SIO, \ 238 CSR_READ_4(sc, WB_SIO) | x) 239 240#define SIO_CLR(x) \ 241 CSR_WRITE_4(sc, WB_SIO, \ 242 CSR_READ_4(sc, WB_SIO) & ~x) 243 244/* 245 * Send a read command and address to the EEPROM, check for ACK. 246 */ 247static void wb_eeprom_putbyte(sc, addr) 248 struct wb_softc *sc; 249 int addr; 250{ 251 register int d, i; 252 253 d = addr | WB_EECMD_READ; 254 255 /* 256 * Feed in each bit and stobe the clock. 257 */ 258 for (i = 0x400; i; i >>= 1) { 259 if (d & i) { 260 SIO_SET(WB_SIO_EE_DATAIN); 261 } else { 262 SIO_CLR(WB_SIO_EE_DATAIN); 263 } 264 DELAY(100); 265 SIO_SET(WB_SIO_EE_CLK); 266 DELAY(150); 267 SIO_CLR(WB_SIO_EE_CLK); 268 DELAY(100); 269 } 270 271 return; 272} 273 274/* 275 * Read a word of data stored in the EEPROM at address 'addr.' 276 */ 277static void wb_eeprom_getword(sc, addr, dest) 278 struct wb_softc *sc; 279 int addr; 280 u_int16_t *dest; 281{ 282 register int i; 283 u_int16_t word = 0; 284 285 /* Enter EEPROM access mode. */ 286 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 287 288 /* 289 * Send address of word we want to read. 290 */ 291 wb_eeprom_putbyte(sc, addr); 292 293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 294 295 /* 296 * Start reading bits from EEPROM. 297 */ 298 for (i = 0x8000; i; i >>= 1) { 299 SIO_SET(WB_SIO_EE_CLK); 300 DELAY(100); 301 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 302 word |= i; 303 SIO_CLR(WB_SIO_EE_CLK); 304 DELAY(100); 305 } 306 307 /* Turn off EEPROM access mode. */ 308 CSR_WRITE_4(sc, WB_SIO, 0); 309 310 *dest = word; 311 312 return; 313} 314 315/* 316 * Read a sequence of words from the EEPROM. 317 */ 318static void wb_read_eeprom(sc, dest, off, cnt, swap) 319 struct wb_softc *sc; 320 caddr_t dest; 321 int off; 322 int cnt; 323 int swap; 324{ 325 int i; 326 u_int16_t word = 0, *ptr; 327 328 for (i = 0; i < cnt; i++) { 329 wb_eeprom_getword(sc, off + i, &word); 330 ptr = (u_int16_t *)(dest + (i * 2)); 331 if (swap) 332 *ptr = ntohs(word); 333 else 334 *ptr = word; 335 } 336 337 return; 338} 339 340/* 341 * Sync the PHYs by setting data bit and strobing the clock 32 times. 342 */ 343static void wb_mii_sync(sc) 344 struct wb_softc *sc; 345{ 346 register int i; 347 348 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 349 350 for (i = 0; i < 32; i++) { 351 SIO_SET(WB_SIO_MII_CLK); 352 DELAY(1); 353 SIO_CLR(WB_SIO_MII_CLK); 354 DELAY(1); 355 } 356 357 return; 358} 359 360/* 361 * Clock a series of bits through the MII. 362 */ 363static void wb_mii_send(sc, bits, cnt) 364 struct wb_softc *sc; 365 u_int32_t bits; 366 int cnt; 367{ 368 int i; 369 370 SIO_CLR(WB_SIO_MII_CLK); 371 372 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 373 if (bits & i) { 374 SIO_SET(WB_SIO_MII_DATAIN); 375 } else { 376 SIO_CLR(WB_SIO_MII_DATAIN); 377 } 378 DELAY(1); 379 SIO_CLR(WB_SIO_MII_CLK); 380 DELAY(1); 381 SIO_SET(WB_SIO_MII_CLK); 382 } 383} 384 385/* 386 * Read an PHY register through the MII. 387 */ 388static int wb_mii_readreg(sc, frame) 389 struct wb_softc *sc; 390 struct wb_mii_frame *frame; 391 392{ 393 int i, ack; 394 395 WB_LOCK(sc); 396 397 /* 398 * Set up frame for RX. 399 */ 400 frame->mii_stdelim = WB_MII_STARTDELIM; 401 frame->mii_opcode = WB_MII_READOP; 402 frame->mii_turnaround = 0; 403 frame->mii_data = 0; 404 405 CSR_WRITE_4(sc, WB_SIO, 0); 406 407 /* 408 * Turn on data xmit. 409 */ 410 SIO_SET(WB_SIO_MII_DIR); 411 412 wb_mii_sync(sc); 413 414 /* 415 * Send command/address info. 416 */ 417 wb_mii_send(sc, frame->mii_stdelim, 2); 418 wb_mii_send(sc, frame->mii_opcode, 2); 419 wb_mii_send(sc, frame->mii_phyaddr, 5); 420 wb_mii_send(sc, frame->mii_regaddr, 5); 421 422 /* Idle bit */ 423 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 424 DELAY(1); 425 SIO_SET(WB_SIO_MII_CLK); 426 DELAY(1); 427 428 /* Turn off xmit. */ 429 SIO_CLR(WB_SIO_MII_DIR); 430 /* Check for ack */ 431 SIO_CLR(WB_SIO_MII_CLK); 432 DELAY(1); 433 SIO_SET(WB_SIO_MII_CLK); 434 DELAY(1); 435 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 436 SIO_CLR(WB_SIO_MII_CLK); 437 DELAY(1); 438 SIO_SET(WB_SIO_MII_CLK); 439 DELAY(1); 440 441 /* 442 * Now try reading data bits. If the ack failed, we still 443 * need to clock through 16 cycles to keep the PHY(s) in sync. 444 */ 445 if (ack) { 446 for(i = 0; i < 16; i++) { 447 SIO_CLR(WB_SIO_MII_CLK); 448 DELAY(1); 449 SIO_SET(WB_SIO_MII_CLK); 450 DELAY(1); 451 } 452 goto fail; 453 } 454 455 for (i = 0x8000; i; i >>= 1) { 456 SIO_CLR(WB_SIO_MII_CLK); 457 DELAY(1); 458 if (!ack) { 459 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 460 frame->mii_data |= i; 461 DELAY(1); 462 } 463 SIO_SET(WB_SIO_MII_CLK); 464 DELAY(1); 465 } 466 467fail: 468 469 SIO_CLR(WB_SIO_MII_CLK); 470 DELAY(1); 471 SIO_SET(WB_SIO_MII_CLK); 472 DELAY(1); 473 474 WB_UNLOCK(sc); 475 476 if (ack) 477 return(1); 478 return(0); 479} 480 481/* 482 * Write to a PHY register through the MII. 483 */ 484static int wb_mii_writereg(sc, frame) 485 struct wb_softc *sc; 486 struct wb_mii_frame *frame; 487 488{ 489 WB_LOCK(sc); 490 491 /* 492 * Set up frame for TX. 493 */ 494 495 frame->mii_stdelim = WB_MII_STARTDELIM; 496 frame->mii_opcode = WB_MII_WRITEOP; 497 frame->mii_turnaround = WB_MII_TURNAROUND; 498 499 /* 500 * Turn on data output. 501 */ 502 SIO_SET(WB_SIO_MII_DIR); 503 504 wb_mii_sync(sc); 505 506 wb_mii_send(sc, frame->mii_stdelim, 2); 507 wb_mii_send(sc, frame->mii_opcode, 2); 508 wb_mii_send(sc, frame->mii_phyaddr, 5); 509 wb_mii_send(sc, frame->mii_regaddr, 5); 510 wb_mii_send(sc, frame->mii_turnaround, 2); 511 wb_mii_send(sc, frame->mii_data, 16); 512 513 /* Idle bit. */ 514 SIO_SET(WB_SIO_MII_CLK); 515 DELAY(1); 516 SIO_CLR(WB_SIO_MII_CLK); 517 DELAY(1); 518 519 /* 520 * Turn off xmit. 521 */ 522 SIO_CLR(WB_SIO_MII_DIR); 523 524 WB_UNLOCK(sc); 525 526 return(0); 527} 528 529static int wb_miibus_readreg(dev, phy, reg) 530 device_t dev; 531 int phy, reg; 532{ 533 struct wb_softc *sc; 534 struct wb_mii_frame frame; 535 536 sc = device_get_softc(dev); 537 538 bzero((char *)&frame, sizeof(frame)); 539 540 frame.mii_phyaddr = phy; 541 frame.mii_regaddr = reg; 542 wb_mii_readreg(sc, &frame); 543 544 return(frame.mii_data); 545} 546 547static int wb_miibus_writereg(dev, phy, reg, data) 548 device_t dev; 549 int phy, reg, data; 550{ 551 struct wb_softc *sc; 552 struct wb_mii_frame frame; 553 554 sc = device_get_softc(dev); 555 556 bzero((char *)&frame, sizeof(frame)); 557 558 frame.mii_phyaddr = phy; 559 frame.mii_regaddr = reg; 560 frame.mii_data = data; 561 562 wb_mii_writereg(sc, &frame); 563 564 return(0); 565} 566 567static void wb_miibus_statchg(dev) 568 device_t dev; 569{ 570 struct wb_softc *sc; 571 struct mii_data *mii; 572 573 sc = device_get_softc(dev); 574 WB_LOCK(sc); 575 mii = device_get_softc(sc->wb_miibus); 576 wb_setcfg(sc, mii->mii_media_active); 577 WB_UNLOCK(sc); 578 579 return; 580} 581 582static u_int8_t wb_calchash(addr) 583 caddr_t addr; 584{ 585 u_int32_t crc, carry; 586 int i, j; 587 u_int8_t c; 588 589 /* Compute CRC for the address value. */ 590 crc = 0xFFFFFFFF; /* initial value */ 591 592 for (i = 0; i < 6; i++) { 593 c = *(addr + i); 594 for (j = 0; j < 8; j++) { 595 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 596 crc <<= 1; 597 c >>= 1; 598 if (carry) 599 crc = (crc ^ 0x04c11db6) | carry; 600 } 601 } 602 603 /* 604 * return the filter bit position 605 * Note: I arrived at the following nonsense 606 * through experimentation. It's not the usual way to 607 * generate the bit position but it's the only thing 608 * I could come up with that works. 609 */ 610 return(~(crc >> 26) & 0x0000003F); 611} 612 613/* 614 * Program the 64-bit multicast hash filter. 615 */ 616static void wb_setmulti(sc) 617 struct wb_softc *sc; 618{ 619 struct ifnet *ifp; 620 int h = 0; 621 u_int32_t hashes[2] = { 0, 0 }; 622 struct ifmultiaddr *ifma; 623 u_int32_t rxfilt; 624 int mcnt = 0; 625 626 ifp = &sc->arpcom.ac_if; 627 628 rxfilt = CSR_READ_4(sc, WB_NETCFG); 629 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 rxfilt |= WB_NETCFG_RX_MULTI; 632 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 633 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 634 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 635 return; 636 } 637 638 /* first, zot all the existing hash bits */ 639 CSR_WRITE_4(sc, WB_MAR0, 0); 640 CSR_WRITE_4(sc, WB_MAR1, 0); 641 642 /* now program new ones */ 643 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 644 if (ifma->ifma_addr->sa_family != AF_LINK) 645 continue; 646 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 647 if (h < 32) 648 hashes[0] |= (1 << h); 649 else 650 hashes[1] |= (1 << (h - 32)); 651 mcnt++; 652 } 653 654 if (mcnt) 655 rxfilt |= WB_NETCFG_RX_MULTI; 656 else 657 rxfilt &= ~WB_NETCFG_RX_MULTI; 658 659 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 660 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 661 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 662 663 return; 664} 665 666/* 667 * The Winbond manual states that in order to fiddle with the 668 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 669 * first have to put the transmit and/or receive logic in the idle state. 670 */ 671static void wb_setcfg(sc, media) 672 struct wb_softc *sc; 673 u_int32_t media; 674{ 675 int i, restart = 0; 676 677 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 678 restart = 1; 679 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 680 681 for (i = 0; i < WB_TIMEOUT; i++) { 682 DELAY(10); 683 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 684 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 685 break; 686 } 687 688 if (i == WB_TIMEOUT) 689 printf("wb%d: failed to force tx and " 690 "rx to idle state\n", sc->wb_unit); 691 } 692 693 if (IFM_SUBTYPE(media) == IFM_10_T) 694 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 695 else 696 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 697 698 if ((media & IFM_GMASK) == IFM_FDX) 699 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 700 else 701 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 702 703 if (restart) 704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 705 706 return; 707} 708 709static void wb_reset(sc) 710 struct wb_softc *sc; 711{ 712 register int i; 713 struct mii_data *mii; 714 715 CSR_WRITE_4(sc, WB_NETCFG, 0); 716 CSR_WRITE_4(sc, WB_BUSCTL, 0); 717 CSR_WRITE_4(sc, WB_TXADDR, 0); 718 CSR_WRITE_4(sc, WB_RXADDR, 0); 719 720 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 721 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 722 723 for (i = 0; i < WB_TIMEOUT; i++) { 724 DELAY(10); 725 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 726 break; 727 } 728 if (i == WB_TIMEOUT) 729 printf("wb%d: reset never completed!\n", sc->wb_unit); 730 731 /* Wait a little while for the chip to get its brains in order. */ 732 DELAY(1000); 733 734 if (sc->wb_miibus == NULL) 735 return; 736 737 mii = device_get_softc(sc->wb_miibus); 738 if (mii == NULL) 739 return; 740 741 if (mii->mii_instance) { 742 struct mii_softc *miisc; 743 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 744 mii_phy_reset(miisc); 745 } 746 747 return; 748} 749 750static void wb_fixmedia(sc) 751 struct wb_softc *sc; 752{ 753 struct mii_data *mii = NULL; 754 struct ifnet *ifp; 755 u_int32_t media; 756 757 if (sc->wb_miibus == NULL) 758 return; 759 760 mii = device_get_softc(sc->wb_miibus); 761 ifp = &sc->arpcom.ac_if; 762 763 mii_pollstat(mii); 764 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 765 media = mii->mii_media_active & ~IFM_10_T; 766 media |= IFM_100_TX; 767 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 768 media = mii->mii_media_active & ~IFM_100_TX; 769 media |= IFM_10_T; 770 } else 771 return; 772 773 ifmedia_set(&mii->mii_media, media); 774 775 return; 776} 777 778/* 779 * Probe for a Winbond chip. Check the PCI vendor and device 780 * IDs against our list and return a device name if we find a match. 781 */ 782static int wb_probe(dev) 783 device_t dev; 784{ 785 struct wb_type *t; 786 787 t = wb_devs; 788 789 while(t->wb_name != NULL) { 790 if ((pci_get_vendor(dev) == t->wb_vid) && 791 (pci_get_device(dev) == t->wb_did)) { 792 device_set_desc(dev, t->wb_name); 793 return(0); 794 } 795 t++; 796 } 797 798 return(ENXIO); 799} 800 801/* 802 * Attach the interface. Allocate softc structures, do ifmedia 803 * setup and ethernet/BPF attach. 804 */ 805static int wb_attach(dev) 806 device_t dev; 807{ 808 u_char eaddr[ETHER_ADDR_LEN]; 809 u_int32_t command; 810 struct wb_softc *sc; 811 struct ifnet *ifp; 812 int unit, error = 0, rid; 813 814 sc = device_get_softc(dev); 815 unit = device_get_unit(dev); 816 817 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 818 WB_LOCK(sc); 819 820 /* 821 * Handle power management nonsense. 822 */ 823 824 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 825 u_int32_t iobase, membase, irq; 826 827 /* Save important PCI config data. */ 828 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 829 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 830 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 831 832 /* Reset the power state. */ 833 printf("wb%d: chip is in D%d power mode " 834 "-- setting to D0\n", unit, 835 pci_get_powerstate(dev)); 836 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 837 838 /* Restore PCI config data. */ 839 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 840 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 841 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 842 } 843 844 /* 845 * Map control/status registers. 846 */ 847 pci_enable_busmaster(dev); 848 pci_enable_io(dev, SYS_RES_IOPORT); 849 pci_enable_io(dev, SYS_RES_MEMORY); 850 command = pci_read_config(dev, PCIR_COMMAND, 4); 851 852#ifdef WB_USEIOSPACE 853 if (!(command & PCIM_CMD_PORTEN)) { 854 printf("wb%d: failed to enable I/O ports!\n", unit); 855 error = ENXIO; 856 goto fail; 857 } 858#else 859 if (!(command & PCIM_CMD_MEMEN)) { 860 printf("wb%d: failed to enable memory mapping!\n", unit); 861 error = ENXIO; 862 goto fail; 863 } 864#endif 865 866 rid = WB_RID; 867 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 868 0, ~0, 1, RF_ACTIVE); 869 870 if (sc->wb_res == NULL) { 871 printf("wb%d: couldn't map ports/memory\n", unit); 872 error = ENXIO; 873 goto fail; 874 } 875 876 sc->wb_btag = rman_get_bustag(sc->wb_res); 877 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 878 879 /* Allocate interrupt */ 880 rid = 0; 881 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 882 RF_SHAREABLE | RF_ACTIVE); 883 884 if (sc->wb_irq == NULL) { 885 printf("wb%d: couldn't map interrupt\n", unit); 886 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 887 error = ENXIO; 888 goto fail; 889 } 890 891 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 892 wb_intr, sc, &sc->wb_intrhand); 893 894 if (error) { 895 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 896 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 897 printf("wb%d: couldn't set up irq\n", unit); 898 goto fail; 899 } 900 901 /* Save the cache line size. */ 902 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 903 904 /* Reset the adapter. */ 905 wb_reset(sc); 906 907 /* 908 * Get station address from the EEPROM. 909 */ 910 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 911 912 /* 913 * A Winbond chip was detected. Inform the world. 914 */ 915 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 916 917 sc->wb_unit = unit; 918 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 919 920 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 921 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 922 923 if (sc->wb_ldata == NULL) { 924 printf("wb%d: no memory for list buffers!\n", unit); 925 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 926 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 927 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 928 error = ENXIO; 929 goto fail; 930 } 931 932 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 933 934 ifp = &sc->arpcom.ac_if; 935 ifp->if_softc = sc; 936 ifp->if_unit = unit; 937 ifp->if_name = "wb"; 938 ifp->if_mtu = ETHERMTU; 939 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 940 ifp->if_ioctl = wb_ioctl; 941 ifp->if_output = ether_output; 942 ifp->if_start = wb_start; 943 ifp->if_watchdog = wb_watchdog; 944 ifp->if_init = wb_init; 945 ifp->if_baudrate = 10000000; 946 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 947 948 /* 949 * Do MII setup. 950 */ 951 if (mii_phy_probe(dev, &sc->wb_miibus, 952 wb_ifmedia_upd, wb_ifmedia_sts)) { 953 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 954 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 955 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 956 free(sc->wb_ldata_ptr, M_DEVBUF); 957 error = ENXIO; 958 goto fail; 959 } 960 961 /* 962 * Call MI attach routine. 963 */ 964 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 965 WB_UNLOCK(sc); 966 return(0); 967 968fail: 969 if (error) 970 device_delete_child(dev, sc->wb_miibus); 971 WB_UNLOCK(sc); 972 mtx_destroy(&sc->wb_mtx); 973 974 return(error); 975} 976 977static int wb_detach(dev) 978 device_t dev; 979{ 980 struct wb_softc *sc; 981 struct ifnet *ifp; 982 983 sc = device_get_softc(dev); 984 WB_LOCK(sc); 985 ifp = &sc->arpcom.ac_if; 986 987 wb_stop(sc); 988 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 989 990 /* Delete any miibus and phy devices attached to this interface */ 991 bus_generic_detach(dev); 992 device_delete_child(dev, sc->wb_miibus); 993 994 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 995 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 996 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 997 998 free(sc->wb_ldata_ptr, M_DEVBUF); 999 1000 WB_UNLOCK(sc); 1001 mtx_destroy(&sc->wb_mtx); 1002 1003 return(0); 1004} 1005 1006/* 1007 * Initialize the transmit descriptors. 1008 */ 1009static int wb_list_tx_init(sc) 1010 struct wb_softc *sc; 1011{ 1012 struct wb_chain_data *cd; 1013 struct wb_list_data *ld; 1014 int i; 1015 1016 cd = &sc->wb_cdata; 1017 ld = sc->wb_ldata; 1018 1019 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1020 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1021 if (i == (WB_TX_LIST_CNT - 1)) { 1022 cd->wb_tx_chain[i].wb_nextdesc = 1023 &cd->wb_tx_chain[0]; 1024 } else { 1025 cd->wb_tx_chain[i].wb_nextdesc = 1026 &cd->wb_tx_chain[i + 1]; 1027 } 1028 } 1029 1030 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1031 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1032 1033 return(0); 1034} 1035 1036 1037/* 1038 * Initialize the RX descriptors and allocate mbufs for them. Note that 1039 * we arrange the descriptors in a closed ring, so that the last descriptor 1040 * points back to the first. 1041 */ 1042static int wb_list_rx_init(sc) 1043 struct wb_softc *sc; 1044{ 1045 struct wb_chain_data *cd; 1046 struct wb_list_data *ld; 1047 int i; 1048 1049 cd = &sc->wb_cdata; 1050 ld = sc->wb_ldata; 1051 1052 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1053 cd->wb_rx_chain[i].wb_ptr = 1054 (struct wb_desc *)&ld->wb_rx_list[i]; 1055 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1056 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1057 return(ENOBUFS); 1058 if (i == (WB_RX_LIST_CNT - 1)) { 1059 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1060 ld->wb_rx_list[i].wb_next = 1061 vtophys(&ld->wb_rx_list[0]); 1062 } else { 1063 cd->wb_rx_chain[i].wb_nextdesc = 1064 &cd->wb_rx_chain[i + 1]; 1065 ld->wb_rx_list[i].wb_next = 1066 vtophys(&ld->wb_rx_list[i + 1]); 1067 } 1068 } 1069 1070 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1071 1072 return(0); 1073} 1074 1075static void wb_bfree(buf, args) 1076 caddr_t buf; 1077 void *args; 1078{ 1079 return; 1080} 1081 1082/* 1083 * Initialize an RX descriptor and attach an MBUF cluster. 1084 */ 1085static int wb_newbuf(sc, c, m) 1086 struct wb_softc *sc; 1087 struct wb_chain_onefrag *c; 1088 struct mbuf *m; 1089{ 1090 struct mbuf *m_new = NULL; 1091 1092 if (m == NULL) { 1093 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1094 if (m_new == NULL) 1095 return(ENOBUFS); 1096 m_new->m_data = c->wb_buf; 1097 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1098 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1099 EXT_NET_DRV); 1100 } else { 1101 m_new = m; 1102 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1103 m_new->m_data = m_new->m_ext.ext_buf; 1104 } 1105 1106 m_adj(m_new, sizeof(u_int64_t)); 1107 1108 c->wb_mbuf = m_new; 1109 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1110 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1111 c->wb_ptr->wb_status = WB_RXSTAT; 1112 1113 return(0); 1114} 1115 1116/* 1117 * A frame has been uploaded: pass the resulting mbuf chain up to 1118 * the higher level protocols. 1119 */ 1120static void wb_rxeof(sc) 1121 struct wb_softc *sc; 1122{ 1123 struct ether_header *eh; 1124 struct mbuf *m = NULL; 1125 struct ifnet *ifp; 1126 struct wb_chain_onefrag *cur_rx; 1127 int total_len = 0; 1128 u_int32_t rxstat; 1129 1130 ifp = &sc->arpcom.ac_if; 1131 1132 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1133 WB_RXSTAT_OWN)) { 1134 struct mbuf *m0 = NULL; 1135 1136 cur_rx = sc->wb_cdata.wb_rx_head; 1137 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1138 1139 m = cur_rx->wb_mbuf; 1140 1141 if ((rxstat & WB_RXSTAT_MIIERR) || 1142 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1143 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1144 !(rxstat & WB_RXSTAT_LASTFRAG) || 1145 !(rxstat & WB_RXSTAT_RXCMP)) { 1146 ifp->if_ierrors++; 1147 wb_newbuf(sc, cur_rx, m); 1148 printf("wb%x: receiver babbling: possible chip " 1149 "bug, forcing reset\n", sc->wb_unit); 1150 wb_fixmedia(sc); 1151 wb_reset(sc); 1152 wb_init(sc); 1153 return; 1154 } 1155 1156 if (rxstat & WB_RXSTAT_RXERR) { 1157 ifp->if_ierrors++; 1158 wb_newbuf(sc, cur_rx, m); 1159 break; 1160 } 1161 1162 /* No errors; receive the packet. */ 1163 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1164 1165 /* 1166 * XXX The Winbond chip includes the CRC with every 1167 * received frame, and there's no way to turn this 1168 * behavior off (at least, I can't find anything in 1169 * the manual that explains how to do it) so we have 1170 * to trim off the CRC manually. 1171 */ 1172 total_len -= ETHER_CRC_LEN; 1173 1174 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1175 NULL); 1176 wb_newbuf(sc, cur_rx, m); 1177 if (m0 == NULL) { 1178 ifp->if_ierrors++; 1179 break; 1180 } 1181 m = m0; 1182 1183 ifp->if_ipackets++; 1184 eh = mtod(m, struct ether_header *); 1185 1186 /* Remove header from mbuf and pass it on. */ 1187 m_adj(m, sizeof(struct ether_header)); 1188 ether_input(ifp, eh, m); 1189 } 1190} 1191 1192void wb_rxeoc(sc) 1193 struct wb_softc *sc; 1194{ 1195 wb_rxeof(sc); 1196 1197 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1198 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1199 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1200 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1201 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1202 1203 return; 1204} 1205 1206/* 1207 * A frame was downloaded to the chip. It's safe for us to clean up 1208 * the list buffers. 1209 */ 1210static void wb_txeof(sc) 1211 struct wb_softc *sc; 1212{ 1213 struct wb_chain *cur_tx; 1214 struct ifnet *ifp; 1215 1216 ifp = &sc->arpcom.ac_if; 1217 1218 /* Clear the timeout timer. */ 1219 ifp->if_timer = 0; 1220 1221 if (sc->wb_cdata.wb_tx_head == NULL) 1222 return; 1223 1224 /* 1225 * Go through our tx list and free mbufs for those 1226 * frames that have been transmitted. 1227 */ 1228 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1229 u_int32_t txstat; 1230 1231 cur_tx = sc->wb_cdata.wb_tx_head; 1232 txstat = WB_TXSTATUS(cur_tx); 1233 1234 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1235 break; 1236 1237 if (txstat & WB_TXSTAT_TXERR) { 1238 ifp->if_oerrors++; 1239 if (txstat & WB_TXSTAT_ABORT) 1240 ifp->if_collisions++; 1241 if (txstat & WB_TXSTAT_LATECOLL) 1242 ifp->if_collisions++; 1243 } 1244 1245 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1246 1247 ifp->if_opackets++; 1248 m_freem(cur_tx->wb_mbuf); 1249 cur_tx->wb_mbuf = NULL; 1250 1251 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1252 sc->wb_cdata.wb_tx_head = NULL; 1253 sc->wb_cdata.wb_tx_tail = NULL; 1254 break; 1255 } 1256 1257 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1258 } 1259 1260 return; 1261} 1262 1263/* 1264 * TX 'end of channel' interrupt handler. 1265 */ 1266static void wb_txeoc(sc) 1267 struct wb_softc *sc; 1268{ 1269 struct ifnet *ifp; 1270 1271 ifp = &sc->arpcom.ac_if; 1272 1273 ifp->if_timer = 0; 1274 1275 if (sc->wb_cdata.wb_tx_head == NULL) { 1276 ifp->if_flags &= ~IFF_OACTIVE; 1277 sc->wb_cdata.wb_tx_tail = NULL; 1278 } else { 1279 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1280 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1281 ifp->if_timer = 5; 1282 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1283 } 1284 } 1285 1286 return; 1287} 1288 1289static void wb_intr(arg) 1290 void *arg; 1291{ 1292 struct wb_softc *sc; 1293 struct ifnet *ifp; 1294 u_int32_t status; 1295 1296 sc = arg; 1297 WB_LOCK(sc); 1298 ifp = &sc->arpcom.ac_if; 1299 1300 if (!(ifp->if_flags & IFF_UP)) { 1301 WB_UNLOCK(sc); 1302 return; 1303 } 1304 1305 /* Disable interrupts. */ 1306 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1307 1308 for (;;) { 1309 1310 status = CSR_READ_4(sc, WB_ISR); 1311 if (status) 1312 CSR_WRITE_4(sc, WB_ISR, status); 1313 1314 if ((status & WB_INTRS) == 0) 1315 break; 1316 1317 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1318 ifp->if_ierrors++; 1319 wb_reset(sc); 1320 if (status & WB_ISR_RX_ERR) 1321 wb_fixmedia(sc); 1322 wb_init(sc); 1323 continue; 1324 } 1325 1326 if (status & WB_ISR_RX_OK) 1327 wb_rxeof(sc); 1328 1329 if (status & WB_ISR_RX_IDLE) 1330 wb_rxeoc(sc); 1331 1332 if (status & WB_ISR_TX_OK) 1333 wb_txeof(sc); 1334 1335 if (status & WB_ISR_TX_NOBUF) 1336 wb_txeoc(sc); 1337 1338 if (status & WB_ISR_TX_IDLE) { 1339 wb_txeof(sc); 1340 if (sc->wb_cdata.wb_tx_head != NULL) { 1341 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1342 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1343 } 1344 } 1345 1346 if (status & WB_ISR_TX_UNDERRUN) { 1347 ifp->if_oerrors++; 1348 wb_txeof(sc); 1349 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1350 /* Jack up TX threshold */ 1351 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1352 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1353 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1354 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1355 } 1356 1357 if (status & WB_ISR_BUS_ERR) { 1358 wb_reset(sc); 1359 wb_init(sc); 1360 } 1361 1362 } 1363 1364 /* Re-enable interrupts. */ 1365 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1366 1367 if (ifp->if_snd.ifq_head != NULL) { 1368 wb_start(ifp); 1369 } 1370 1371 WB_UNLOCK(sc); 1372 1373 return; 1374} 1375 1376static void wb_tick(xsc) 1377 void *xsc; 1378{ 1379 struct wb_softc *sc; 1380 struct mii_data *mii; 1381 1382 sc = xsc; 1383 WB_LOCK(sc); 1384 mii = device_get_softc(sc->wb_miibus); 1385 1386 mii_tick(mii); 1387 1388 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1389 1390 WB_UNLOCK(sc); 1391 1392 return; 1393} 1394 1395/* 1396 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1397 * pointers to the fragment pointers. 1398 */ 1399static int wb_encap(sc, c, m_head) 1400 struct wb_softc *sc; 1401 struct wb_chain *c; 1402 struct mbuf *m_head; 1403{ 1404 int frag = 0; 1405 struct wb_desc *f = NULL; 1406 int total_len; 1407 struct mbuf *m; 1408 1409 /* 1410 * Start packing the mbufs in this chain into 1411 * the fragment pointers. Stop when we run out 1412 * of fragments or hit the end of the mbuf chain. 1413 */ 1414 m = m_head; 1415 total_len = 0; 1416 1417 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1418 if (m->m_len != 0) { 1419 if (frag == WB_MAXFRAGS) 1420 break; 1421 total_len += m->m_len; 1422 f = &c->wb_ptr->wb_frag[frag]; 1423 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1424 if (frag == 0) { 1425 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1426 f->wb_status = 0; 1427 } else 1428 f->wb_status = WB_TXSTAT_OWN; 1429 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1430 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1431 frag++; 1432 } 1433 } 1434 1435 /* 1436 * Handle special case: we used up all 16 fragments, 1437 * but we have more mbufs left in the chain. Copy the 1438 * data into an mbuf cluster. Note that we don't 1439 * bother clearing the values in the other fragment 1440 * pointers/counters; it wouldn't gain us anything, 1441 * and would waste cycles. 1442 */ 1443 if (m != NULL) { 1444 struct mbuf *m_new = NULL; 1445 1446 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1447 if (m_new == NULL) 1448 return(1); 1449 if (m_head->m_pkthdr.len > MHLEN) { 1450 MCLGET(m_new, M_DONTWAIT); 1451 if (!(m_new->m_flags & M_EXT)) { 1452 m_freem(m_new); 1453 return(1); 1454 } 1455 } 1456 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1457 mtod(m_new, caddr_t)); 1458 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1459 m_freem(m_head); 1460 m_head = m_new; 1461 f = &c->wb_ptr->wb_frag[0]; 1462 f->wb_status = 0; 1463 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1464 f->wb_ctl = total_len = m_new->m_len; 1465 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1466 frag = 1; 1467 } 1468 1469 if (total_len < WB_MIN_FRAMELEN) { 1470 f = &c->wb_ptr->wb_frag[frag]; 1471 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1472 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1473 f->wb_ctl |= WB_TXCTL_TLINK; 1474 f->wb_status = WB_TXSTAT_OWN; 1475 frag++; 1476 } 1477 1478 c->wb_mbuf = m_head; 1479 c->wb_lastdesc = frag - 1; 1480 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1481 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1482 1483 return(0); 1484} 1485 1486/* 1487 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1488 * to the mbuf data regions directly in the transmit lists. We also save a 1489 * copy of the pointers since the transmit list fragment pointers are 1490 * physical addresses. 1491 */ 1492 1493static void wb_start(ifp) 1494 struct ifnet *ifp; 1495{ 1496 struct wb_softc *sc; 1497 struct mbuf *m_head = NULL; 1498 struct wb_chain *cur_tx = NULL, *start_tx; 1499 1500 sc = ifp->if_softc; 1501 WB_LOCK(sc); 1502 1503 /* 1504 * Check for an available queue slot. If there are none, 1505 * punt. 1506 */ 1507 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1508 ifp->if_flags |= IFF_OACTIVE; 1509 WB_UNLOCK(sc); 1510 return; 1511 } 1512 1513 start_tx = sc->wb_cdata.wb_tx_free; 1514 1515 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1516 IF_DEQUEUE(&ifp->if_snd, m_head); 1517 if (m_head == NULL) 1518 break; 1519 1520 /* Pick a descriptor off the free list. */ 1521 cur_tx = sc->wb_cdata.wb_tx_free; 1522 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1523 1524 /* Pack the data into the descriptor. */ 1525 wb_encap(sc, cur_tx, m_head); 1526 1527 if (cur_tx != start_tx) 1528 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1529 1530 /* 1531 * If there's a BPF listener, bounce a copy of this frame 1532 * to him. 1533 */ 1534 if (ifp->if_bpf) 1535 bpf_mtap(ifp, cur_tx->wb_mbuf); 1536 } 1537 1538 /* 1539 * If there are no packets queued, bail. 1540 */ 1541 if (cur_tx == NULL) { 1542 WB_UNLOCK(sc); 1543 return; 1544 } 1545 1546 /* 1547 * Place the request for the upload interrupt 1548 * in the last descriptor in the chain. This way, if 1549 * we're chaining several packets at once, we'll only 1550 * get an interupt once for the whole chain rather than 1551 * once for each packet. 1552 */ 1553 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1554 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1555 sc->wb_cdata.wb_tx_tail = cur_tx; 1556 1557 if (sc->wb_cdata.wb_tx_head == NULL) { 1558 sc->wb_cdata.wb_tx_head = start_tx; 1559 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1560 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1561 } else { 1562 /* 1563 * We need to distinguish between the case where 1564 * the own bit is clear because the chip cleared it 1565 * and where the own bit is clear because we haven't 1566 * set it yet. The magic value WB_UNSET is just some 1567 * ramdomly chosen number which doesn't have the own 1568 * bit set. When we actually transmit the frame, the 1569 * status word will have _only_ the own bit set, so 1570 * the txeoc handler will be able to tell if it needs 1571 * to initiate another transmission to flush out pending 1572 * frames. 1573 */ 1574 WB_TXOWN(start_tx) = WB_UNSENT; 1575 } 1576 1577 /* 1578 * Set a timeout in case the chip goes out to lunch. 1579 */ 1580 ifp->if_timer = 5; 1581 WB_UNLOCK(sc); 1582 1583 return; 1584} 1585 1586static void wb_init(xsc) 1587 void *xsc; 1588{ 1589 struct wb_softc *sc = xsc; 1590 struct ifnet *ifp = &sc->arpcom.ac_if; 1591 int i; 1592 struct mii_data *mii; 1593 1594 WB_LOCK(sc); 1595 mii = device_get_softc(sc->wb_miibus); 1596 1597 /* 1598 * Cancel pending I/O and free all RX/TX buffers. 1599 */ 1600 wb_stop(sc); 1601 wb_reset(sc); 1602 1603 sc->wb_txthresh = WB_TXTHRESH_INIT; 1604 1605 /* 1606 * Set cache alignment and burst length. 1607 */ 1608#ifdef foo 1609 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1610 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1611 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1612#endif 1613 1614 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1615 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1616 switch(sc->wb_cachesize) { 1617 case 32: 1618 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1619 break; 1620 case 16: 1621 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1622 break; 1623 case 8: 1624 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1625 break; 1626 case 0: 1627 default: 1628 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1629 break; 1630 } 1631 1632 /* This doesn't tend to work too well at 100Mbps. */ 1633 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1634 1635 /* Init our MAC address */ 1636 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1637 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1638 } 1639 1640 /* Init circular RX list. */ 1641 if (wb_list_rx_init(sc) == ENOBUFS) { 1642 printf("wb%d: initialization failed: no " 1643 "memory for rx buffers\n", sc->wb_unit); 1644 wb_stop(sc); 1645 WB_UNLOCK(sc); 1646 return; 1647 } 1648 1649 /* Init TX descriptors. */ 1650 wb_list_tx_init(sc); 1651 1652 /* If we want promiscuous mode, set the allframes bit. */ 1653 if (ifp->if_flags & IFF_PROMISC) { 1654 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1655 } else { 1656 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1657 } 1658 1659 /* 1660 * Set capture broadcast bit to capture broadcast frames. 1661 */ 1662 if (ifp->if_flags & IFF_BROADCAST) { 1663 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1664 } else { 1665 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1666 } 1667 1668 /* 1669 * Program the multicast filter, if necessary. 1670 */ 1671 wb_setmulti(sc); 1672 1673 /* 1674 * Load the address of the RX list. 1675 */ 1676 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1677 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1678 1679 /* 1680 * Enable interrupts. 1681 */ 1682 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1683 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1684 1685 /* Enable receiver and transmitter. */ 1686 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1687 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1688 1689 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1690 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1691 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1692 1693 mii_mediachg(mii); 1694 1695 ifp->if_flags |= IFF_RUNNING; 1696 ifp->if_flags &= ~IFF_OACTIVE; 1697 1698 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1699 WB_UNLOCK(sc); 1700 1701 return; 1702} 1703 1704/* 1705 * Set media options. 1706 */ 1707static int wb_ifmedia_upd(ifp) 1708 struct ifnet *ifp; 1709{ 1710 struct wb_softc *sc; 1711 1712 sc = ifp->if_softc; 1713 1714 if (ifp->if_flags & IFF_UP) 1715 wb_init(sc); 1716 1717 return(0); 1718} 1719 1720/* 1721 * Report current media status. 1722 */ 1723static void wb_ifmedia_sts(ifp, ifmr) 1724 struct ifnet *ifp; 1725 struct ifmediareq *ifmr; 1726{ 1727 struct wb_softc *sc; 1728 struct mii_data *mii; 1729 1730 sc = ifp->if_softc; 1731 1732 mii = device_get_softc(sc->wb_miibus); 1733 1734 mii_pollstat(mii); 1735 ifmr->ifm_active = mii->mii_media_active; 1736 ifmr->ifm_status = mii->mii_media_status; 1737 1738 return; 1739} 1740 1741static int wb_ioctl(ifp, command, data) 1742 struct ifnet *ifp; 1743 u_long command; 1744 caddr_t data; 1745{ 1746 struct wb_softc *sc = ifp->if_softc; 1747 struct mii_data *mii; 1748 struct ifreq *ifr = (struct ifreq *) data; 1749 int error = 0; 1750 1751 WB_LOCK(sc); 1752 1753 switch(command) { 1754 case SIOCSIFADDR: 1755 case SIOCGIFADDR: 1756 case SIOCSIFMTU: 1757 error = ether_ioctl(ifp, command, data); 1758 break; 1759 case SIOCSIFFLAGS: 1760 if (ifp->if_flags & IFF_UP) { 1761 wb_init(sc); 1762 } else { 1763 if (ifp->if_flags & IFF_RUNNING) 1764 wb_stop(sc); 1765 } 1766 error = 0; 1767 break; 1768 case SIOCADDMULTI: 1769 case SIOCDELMULTI: 1770 wb_setmulti(sc); 1771 error = 0; 1772 break; 1773 case SIOCGIFMEDIA: 1774 case SIOCSIFMEDIA: 1775 mii = device_get_softc(sc->wb_miibus); 1776 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1777 break; 1778 default: 1779 error = EINVAL; 1780 break; 1781 } 1782 1783 WB_UNLOCK(sc); 1784 1785 return(error); 1786} 1787 1788static void wb_watchdog(ifp) 1789 struct ifnet *ifp; 1790{ 1791 struct wb_softc *sc; 1792 1793 sc = ifp->if_softc; 1794 1795 WB_LOCK(sc); 1796 ifp->if_oerrors++; 1797 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1798#ifdef foo 1799 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1800 printf("wb%d: no carrier - transceiver cable problem?\n", 1801 sc->wb_unit); 1802#endif 1803 wb_stop(sc); 1804 wb_reset(sc); 1805 wb_init(sc); 1806 1807 if (ifp->if_snd.ifq_head != NULL) 1808 wb_start(ifp); 1809 WB_UNLOCK(sc); 1810 1811 return; 1812} 1813 1814/* 1815 * Stop the adapter and free any mbufs allocated to the 1816 * RX and TX lists. 1817 */ 1818static void wb_stop(sc) 1819 struct wb_softc *sc; 1820{ 1821 register int i; 1822 struct ifnet *ifp; 1823 1824 WB_LOCK(sc); 1825 ifp = &sc->arpcom.ac_if; 1826 ifp->if_timer = 0; 1827 1828 untimeout(wb_tick, sc, sc->wb_stat_ch); 1829 1830 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1831 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1832 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1833 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1834 1835 /* 1836 * Free data in the RX lists. 1837 */ 1838 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1839 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1840 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1841 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1842 } 1843 } 1844 bzero((char *)&sc->wb_ldata->wb_rx_list, 1845 sizeof(sc->wb_ldata->wb_rx_list)); 1846 1847 /* 1848 * Free the TX list buffers. 1849 */ 1850 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1851 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1852 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1853 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1854 } 1855 } 1856 1857 bzero((char *)&sc->wb_ldata->wb_tx_list, 1858 sizeof(sc->wb_ldata->wb_tx_list)); 1859 1860 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1861 WB_UNLOCK(sc); 1862 1863 return; 1864} 1865 1866/* 1867 * Stop all chip I/O so that the kernel's probe routines don't 1868 * get confused by errant DMAs when rebooting. 1869 */ 1870static void wb_shutdown(dev) 1871 device_t dev; 1872{ 1873 struct wb_softc *sc; 1874 1875 sc = device_get_softc(dev); 1876 wb_stop(sc); 1877 1878 return; 1879} 1880