if_wb.c revision 147256
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 147256 2005-06-10 16:49:24Z brooks $"); 35 36/* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_types.h> 104 105#include <net/bpf.h> 106 107#include <vm/vm.h> /* for vtophys */ 108#include <vm/pmap.h> /* for vtophys */ 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117#include <dev/mii/mii.h> 118#include <dev/mii/miivar.h> 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <pci/if_wbreg.h> 126 127MODULE_DEPEND(wb, pci, 1, 1, 1); 128MODULE_DEPEND(wb, ether, 1, 1, 1); 129MODULE_DEPEND(wb, miibus, 1, 1, 1); 130 131/* 132 * Various supported device vendors/types and their names. 133 */ 134static struct wb_type wb_devs[] = { 135 { WB_VENDORID, WB_DEVICEID_840F, 136 "Winbond W89C840F 10/100BaseTX" }, 137 { CP_VENDORID, CP_DEVICEID_RL100, 138 "Compex RL100-ATX 10/100baseTX" }, 139 { 0, 0, NULL } 140}; 141 142static int wb_probe(device_t); 143static int wb_attach(device_t); 144static int wb_detach(device_t); 145 146static void wb_bfree(void *addr, void *args); 147static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 148 struct mbuf *); 149static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 150 151static void wb_rxeof(struct wb_softc *); 152static void wb_rxeoc(struct wb_softc *); 153static void wb_txeof(struct wb_softc *); 154static void wb_txeoc(struct wb_softc *); 155static void wb_intr(void *); 156static void wb_tick(void *); 157static void wb_start(struct ifnet *); 158static int wb_ioctl(struct ifnet *, u_long, caddr_t); 159static void wb_init(void *); 160static void wb_stop(struct wb_softc *); 161static void wb_watchdog(struct ifnet *); 162static void wb_shutdown(device_t); 163static int wb_ifmedia_upd(struct ifnet *); 164static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 165 166static void wb_eeprom_putbyte(struct wb_softc *, int); 167static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 168static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 169static void wb_mii_sync(struct wb_softc *); 170static void wb_mii_send(struct wb_softc *, u_int32_t, int); 171static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 172static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 173 174static void wb_setcfg(struct wb_softc *, u_int32_t); 175static void wb_setmulti(struct wb_softc *); 176static void wb_reset(struct wb_softc *); 177static void wb_fixmedia(struct wb_softc *); 178static int wb_list_rx_init(struct wb_softc *); 179static int wb_list_tx_init(struct wb_softc *); 180 181static int wb_miibus_readreg(device_t, int, int); 182static int wb_miibus_writereg(device_t, int, int, int); 183static void wb_miibus_statchg(device_t); 184 185#ifdef WB_USEIOSPACE 186#define WB_RES SYS_RES_IOPORT 187#define WB_RID WB_PCI_LOIO 188#else 189#define WB_RES SYS_RES_MEMORY 190#define WB_RID WB_PCI_LOMEM 191#endif 192 193static device_method_t wb_methods[] = { 194 /* Device interface */ 195 DEVMETHOD(device_probe, wb_probe), 196 DEVMETHOD(device_attach, wb_attach), 197 DEVMETHOD(device_detach, wb_detach), 198 DEVMETHOD(device_shutdown, wb_shutdown), 199 200 /* bus interface, for miibus */ 201 DEVMETHOD(bus_print_child, bus_generic_print_child), 202 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 203 204 /* MII interface */ 205 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 206 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 207 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 208 { 0, 0 } 209}; 210 211static driver_t wb_driver = { 212 "wb", 213 wb_methods, 214 sizeof(struct wb_softc) 215}; 216 217static devclass_t wb_devclass; 218 219DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 220DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 221 222#define WB_SETBIT(sc, reg, x) \ 223 CSR_WRITE_4(sc, reg, \ 224 CSR_READ_4(sc, reg) | (x)) 225 226#define WB_CLRBIT(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) & ~(x)) 229 230#define SIO_SET(x) \ 231 CSR_WRITE_4(sc, WB_SIO, \ 232 CSR_READ_4(sc, WB_SIO) | (x)) 233 234#define SIO_CLR(x) \ 235 CSR_WRITE_4(sc, WB_SIO, \ 236 CSR_READ_4(sc, WB_SIO) & ~(x)) 237 238/* 239 * Send a read command and address to the EEPROM, check for ACK. 240 */ 241static void 242wb_eeprom_putbyte(sc, addr) 243 struct wb_softc *sc; 244 int addr; 245{ 246 register int d, i; 247 248 d = addr | WB_EECMD_READ; 249 250 /* 251 * Feed in each bit and stobe the clock. 252 */ 253 for (i = 0x400; i; i >>= 1) { 254 if (d & i) { 255 SIO_SET(WB_SIO_EE_DATAIN); 256 } else { 257 SIO_CLR(WB_SIO_EE_DATAIN); 258 } 259 DELAY(100); 260 SIO_SET(WB_SIO_EE_CLK); 261 DELAY(150); 262 SIO_CLR(WB_SIO_EE_CLK); 263 DELAY(100); 264 } 265 266 return; 267} 268 269/* 270 * Read a word of data stored in the EEPROM at address 'addr.' 271 */ 272static void 273wb_eeprom_getword(sc, addr, dest) 274 struct wb_softc *sc; 275 int addr; 276 u_int16_t *dest; 277{ 278 register int i; 279 u_int16_t word = 0; 280 281 /* Enter EEPROM access mode. */ 282 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 283 284 /* 285 * Send address of word we want to read. 286 */ 287 wb_eeprom_putbyte(sc, addr); 288 289 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 290 291 /* 292 * Start reading bits from EEPROM. 293 */ 294 for (i = 0x8000; i; i >>= 1) { 295 SIO_SET(WB_SIO_EE_CLK); 296 DELAY(100); 297 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 298 word |= i; 299 SIO_CLR(WB_SIO_EE_CLK); 300 DELAY(100); 301 } 302 303 /* Turn off EEPROM access mode. */ 304 CSR_WRITE_4(sc, WB_SIO, 0); 305 306 *dest = word; 307 308 return; 309} 310 311/* 312 * Read a sequence of words from the EEPROM. 313 */ 314static void 315wb_read_eeprom(sc, dest, off, cnt, swap) 316 struct wb_softc *sc; 317 caddr_t dest; 318 int off; 319 int cnt; 320 int swap; 321{ 322 int i; 323 u_int16_t word = 0, *ptr; 324 325 for (i = 0; i < cnt; i++) { 326 wb_eeprom_getword(sc, off + i, &word); 327 ptr = (u_int16_t *)(dest + (i * 2)); 328 if (swap) 329 *ptr = ntohs(word); 330 else 331 *ptr = word; 332 } 333 334 return; 335} 336 337/* 338 * Sync the PHYs by setting data bit and strobing the clock 32 times. 339 */ 340static void 341wb_mii_sync(sc) 342 struct wb_softc *sc; 343{ 344 register int i; 345 346 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 347 348 for (i = 0; i < 32; i++) { 349 SIO_SET(WB_SIO_MII_CLK); 350 DELAY(1); 351 SIO_CLR(WB_SIO_MII_CLK); 352 DELAY(1); 353 } 354 355 return; 356} 357 358/* 359 * Clock a series of bits through the MII. 360 */ 361static void 362wb_mii_send(sc, bits, cnt) 363 struct wb_softc *sc; 364 u_int32_t bits; 365 int cnt; 366{ 367 int i; 368 369 SIO_CLR(WB_SIO_MII_CLK); 370 371 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 372 if (bits & i) { 373 SIO_SET(WB_SIO_MII_DATAIN); 374 } else { 375 SIO_CLR(WB_SIO_MII_DATAIN); 376 } 377 DELAY(1); 378 SIO_CLR(WB_SIO_MII_CLK); 379 DELAY(1); 380 SIO_SET(WB_SIO_MII_CLK); 381 } 382} 383 384/* 385 * Read an PHY register through the MII. 386 */ 387static int 388wb_mii_readreg(sc, frame) 389 struct wb_softc *sc; 390 struct wb_mii_frame *frame; 391 392{ 393 int i, ack; 394 395 WB_LOCK(sc); 396 397 /* 398 * Set up frame for RX. 399 */ 400 frame->mii_stdelim = WB_MII_STARTDELIM; 401 frame->mii_opcode = WB_MII_READOP; 402 frame->mii_turnaround = 0; 403 frame->mii_data = 0; 404 405 CSR_WRITE_4(sc, WB_SIO, 0); 406 407 /* 408 * Turn on data xmit. 409 */ 410 SIO_SET(WB_SIO_MII_DIR); 411 412 wb_mii_sync(sc); 413 414 /* 415 * Send command/address info. 416 */ 417 wb_mii_send(sc, frame->mii_stdelim, 2); 418 wb_mii_send(sc, frame->mii_opcode, 2); 419 wb_mii_send(sc, frame->mii_phyaddr, 5); 420 wb_mii_send(sc, frame->mii_regaddr, 5); 421 422 /* Idle bit */ 423 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 424 DELAY(1); 425 SIO_SET(WB_SIO_MII_CLK); 426 DELAY(1); 427 428 /* Turn off xmit. */ 429 SIO_CLR(WB_SIO_MII_DIR); 430 /* Check for ack */ 431 SIO_CLR(WB_SIO_MII_CLK); 432 DELAY(1); 433 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 434 SIO_SET(WB_SIO_MII_CLK); 435 DELAY(1); 436 SIO_CLR(WB_SIO_MII_CLK); 437 DELAY(1); 438 SIO_SET(WB_SIO_MII_CLK); 439 DELAY(1); 440 441 /* 442 * Now try reading data bits. If the ack failed, we still 443 * need to clock through 16 cycles to keep the PHY(s) in sync. 444 */ 445 if (ack) { 446 for(i = 0; i < 16; i++) { 447 SIO_CLR(WB_SIO_MII_CLK); 448 DELAY(1); 449 SIO_SET(WB_SIO_MII_CLK); 450 DELAY(1); 451 } 452 goto fail; 453 } 454 455 for (i = 0x8000; i; i >>= 1) { 456 SIO_CLR(WB_SIO_MII_CLK); 457 DELAY(1); 458 if (!ack) { 459 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 460 frame->mii_data |= i; 461 DELAY(1); 462 } 463 SIO_SET(WB_SIO_MII_CLK); 464 DELAY(1); 465 } 466 467fail: 468 469 SIO_CLR(WB_SIO_MII_CLK); 470 DELAY(1); 471 SIO_SET(WB_SIO_MII_CLK); 472 DELAY(1); 473 474 WB_UNLOCK(sc); 475 476 if (ack) 477 return(1); 478 return(0); 479} 480 481/* 482 * Write to a PHY register through the MII. 483 */ 484static int 485wb_mii_writereg(sc, frame) 486 struct wb_softc *sc; 487 struct wb_mii_frame *frame; 488 489{ 490 WB_LOCK(sc); 491 492 /* 493 * Set up frame for TX. 494 */ 495 496 frame->mii_stdelim = WB_MII_STARTDELIM; 497 frame->mii_opcode = WB_MII_WRITEOP; 498 frame->mii_turnaround = WB_MII_TURNAROUND; 499 500 /* 501 * Turn on data output. 502 */ 503 SIO_SET(WB_SIO_MII_DIR); 504 505 wb_mii_sync(sc); 506 507 wb_mii_send(sc, frame->mii_stdelim, 2); 508 wb_mii_send(sc, frame->mii_opcode, 2); 509 wb_mii_send(sc, frame->mii_phyaddr, 5); 510 wb_mii_send(sc, frame->mii_regaddr, 5); 511 wb_mii_send(sc, frame->mii_turnaround, 2); 512 wb_mii_send(sc, frame->mii_data, 16); 513 514 /* Idle bit. */ 515 SIO_SET(WB_SIO_MII_CLK); 516 DELAY(1); 517 SIO_CLR(WB_SIO_MII_CLK); 518 DELAY(1); 519 520 /* 521 * Turn off xmit. 522 */ 523 SIO_CLR(WB_SIO_MII_DIR); 524 525 WB_UNLOCK(sc); 526 527 return(0); 528} 529 530static int 531wb_miibus_readreg(dev, phy, reg) 532 device_t dev; 533 int phy, reg; 534{ 535 struct wb_softc *sc; 536 struct wb_mii_frame frame; 537 538 sc = device_get_softc(dev); 539 540 bzero((char *)&frame, sizeof(frame)); 541 542 frame.mii_phyaddr = phy; 543 frame.mii_regaddr = reg; 544 wb_mii_readreg(sc, &frame); 545 546 return(frame.mii_data); 547} 548 549static int 550wb_miibus_writereg(dev, phy, reg, data) 551 device_t dev; 552 int phy, reg, data; 553{ 554 struct wb_softc *sc; 555 struct wb_mii_frame frame; 556 557 sc = device_get_softc(dev); 558 559 bzero((char *)&frame, sizeof(frame)); 560 561 frame.mii_phyaddr = phy; 562 frame.mii_regaddr = reg; 563 frame.mii_data = data; 564 565 wb_mii_writereg(sc, &frame); 566 567 return(0); 568} 569 570static void 571wb_miibus_statchg(dev) 572 device_t dev; 573{ 574 struct wb_softc *sc; 575 struct mii_data *mii; 576 577 sc = device_get_softc(dev); 578 WB_LOCK(sc); 579 mii = device_get_softc(sc->wb_miibus); 580 wb_setcfg(sc, mii->mii_media_active); 581 WB_UNLOCK(sc); 582 583 return; 584} 585 586/* 587 * Program the 64-bit multicast hash filter. 588 */ 589static void 590wb_setmulti(sc) 591 struct wb_softc *sc; 592{ 593 struct ifnet *ifp; 594 int h = 0; 595 u_int32_t hashes[2] = { 0, 0 }; 596 struct ifmultiaddr *ifma; 597 u_int32_t rxfilt; 598 int mcnt = 0; 599 600 ifp = sc->wb_ifp; 601 602 rxfilt = CSR_READ_4(sc, WB_NETCFG); 603 604 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 605 rxfilt |= WB_NETCFG_RX_MULTI; 606 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 607 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 608 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 609 return; 610 } 611 612 /* first, zot all the existing hash bits */ 613 CSR_WRITE_4(sc, WB_MAR0, 0); 614 CSR_WRITE_4(sc, WB_MAR1, 0); 615 616 /* now program new ones */ 617 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 618 if (ifma->ifma_addr->sa_family != AF_LINK) 619 continue; 620 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 621 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 622 if (h < 32) 623 hashes[0] |= (1 << h); 624 else 625 hashes[1] |= (1 << (h - 32)); 626 mcnt++; 627 } 628 629 if (mcnt) 630 rxfilt |= WB_NETCFG_RX_MULTI; 631 else 632 rxfilt &= ~WB_NETCFG_RX_MULTI; 633 634 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 635 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 636 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 637 638 return; 639} 640 641/* 642 * The Winbond manual states that in order to fiddle with the 643 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 644 * first have to put the transmit and/or receive logic in the idle state. 645 */ 646static void 647wb_setcfg(sc, media) 648 struct wb_softc *sc; 649 u_int32_t media; 650{ 651 int i, restart = 0; 652 653 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 654 restart = 1; 655 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 656 657 for (i = 0; i < WB_TIMEOUT; i++) { 658 DELAY(10); 659 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 660 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 661 break; 662 } 663 664 if (i == WB_TIMEOUT) 665 printf("wb%d: failed to force tx and " 666 "rx to idle state\n", sc->wb_unit); 667 } 668 669 if (IFM_SUBTYPE(media) == IFM_10_T) 670 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 671 else 672 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 673 674 if ((media & IFM_GMASK) == IFM_FDX) 675 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 676 else 677 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 678 679 if (restart) 680 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 681 682 return; 683} 684 685static void 686wb_reset(sc) 687 struct wb_softc *sc; 688{ 689 register int i; 690 struct mii_data *mii; 691 692 CSR_WRITE_4(sc, WB_NETCFG, 0); 693 CSR_WRITE_4(sc, WB_BUSCTL, 0); 694 CSR_WRITE_4(sc, WB_TXADDR, 0); 695 CSR_WRITE_4(sc, WB_RXADDR, 0); 696 697 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 698 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 699 700 for (i = 0; i < WB_TIMEOUT; i++) { 701 DELAY(10); 702 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 703 break; 704 } 705 if (i == WB_TIMEOUT) 706 printf("wb%d: reset never completed!\n", sc->wb_unit); 707 708 /* Wait a little while for the chip to get its brains in order. */ 709 DELAY(1000); 710 711 if (sc->wb_miibus == NULL) 712 return; 713 714 mii = device_get_softc(sc->wb_miibus); 715 if (mii == NULL) 716 return; 717 718 if (mii->mii_instance) { 719 struct mii_softc *miisc; 720 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 721 mii_phy_reset(miisc); 722 } 723 724 return; 725} 726 727static void 728wb_fixmedia(sc) 729 struct wb_softc *sc; 730{ 731 struct mii_data *mii = NULL; 732 struct ifnet *ifp; 733 u_int32_t media; 734 735 if (sc->wb_miibus == NULL) 736 return; 737 738 mii = device_get_softc(sc->wb_miibus); 739 ifp = sc->wb_ifp; 740 741 mii_pollstat(mii); 742 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 743 media = mii->mii_media_active & ~IFM_10_T; 744 media |= IFM_100_TX; 745 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 746 media = mii->mii_media_active & ~IFM_100_TX; 747 media |= IFM_10_T; 748 } else 749 return; 750 751 ifmedia_set(&mii->mii_media, media); 752 753 return; 754} 755 756/* 757 * Probe for a Winbond chip. Check the PCI vendor and device 758 * IDs against our list and return a device name if we find a match. 759 */ 760static int 761wb_probe(dev) 762 device_t dev; 763{ 764 struct wb_type *t; 765 766 t = wb_devs; 767 768 while(t->wb_name != NULL) { 769 if ((pci_get_vendor(dev) == t->wb_vid) && 770 (pci_get_device(dev) == t->wb_did)) { 771 device_set_desc(dev, t->wb_name); 772 return (BUS_PROBE_DEFAULT); 773 } 774 t++; 775 } 776 777 return(ENXIO); 778} 779 780/* 781 * Attach the interface. Allocate softc structures, do ifmedia 782 * setup and ethernet/BPF attach. 783 */ 784static int 785wb_attach(dev) 786 device_t dev; 787{ 788 u_char eaddr[ETHER_ADDR_LEN]; 789 struct wb_softc *sc; 790 struct ifnet *ifp; 791 int unit, error = 0, rid; 792 793 sc = device_get_softc(dev); 794 unit = device_get_unit(dev); 795 796 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 797 MTX_DEF | MTX_RECURSE); 798 /* 799 * Map control/status registers. 800 */ 801 pci_enable_busmaster(dev); 802 803 rid = WB_RID; 804 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 805 806 if (sc->wb_res == NULL) { 807 printf("wb%d: couldn't map ports/memory\n", unit); 808 error = ENXIO; 809 goto fail; 810 } 811 812 sc->wb_btag = rman_get_bustag(sc->wb_res); 813 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 814 815 /* Allocate interrupt */ 816 rid = 0; 817 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 818 RF_SHAREABLE | RF_ACTIVE); 819 820 if (sc->wb_irq == NULL) { 821 printf("wb%d: couldn't map interrupt\n", unit); 822 error = ENXIO; 823 goto fail; 824 } 825 826 /* Save the cache line size. */ 827 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 828 829 /* Reset the adapter. */ 830 wb_reset(sc); 831 832 /* 833 * Get station address from the EEPROM. 834 */ 835 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 836 837 sc->wb_unit = unit; 838 839 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 840 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 841 842 if (sc->wb_ldata == NULL) { 843 printf("wb%d: no memory for list buffers!\n", unit); 844 error = ENXIO; 845 goto fail; 846 } 847 848 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 849 850 ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 851 if (ifp == NULL) { 852 printf("wb%d: can not if_alloc()\n", unit); 853 error = ENOSPC; 854 goto fail; 855 } 856 ifp->if_softc = sc; 857 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 858 ifp->if_mtu = ETHERMTU; 859 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 860 IFF_NEEDSGIANT; 861 ifp->if_ioctl = wb_ioctl; 862 ifp->if_start = wb_start; 863 ifp->if_watchdog = wb_watchdog; 864 ifp->if_init = wb_init; 865 ifp->if_baudrate = 10000000; 866 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 867 868 /* 869 * Do MII setup. 870 */ 871 if (mii_phy_probe(dev, &sc->wb_miibus, 872 wb_ifmedia_upd, wb_ifmedia_sts)) { 873 error = ENXIO; 874 goto fail; 875 } 876 877 /* 878 * Call MI attach routine. 879 */ 880 ether_ifattach(ifp, eaddr); 881 882 /* Hook interrupt last to avoid having to lock softc */ 883 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 884 wb_intr, sc, &sc->wb_intrhand); 885 886 if (error) { 887 printf("wb%d: couldn't set up irq\n", unit); 888 ether_ifdetach(ifp); 889 if_free(ifp); 890 goto fail; 891 } 892 893fail: 894 if (error) 895 wb_detach(dev); 896 897 return(error); 898} 899 900/* 901 * Shutdown hardware and free up resources. This can be called any 902 * time after the mutex has been initialized. It is called in both 903 * the error case in attach and the normal detach case so it needs 904 * to be careful about only freeing resources that have actually been 905 * allocated. 906 */ 907static int 908wb_detach(dev) 909 device_t dev; 910{ 911 struct wb_softc *sc; 912 struct ifnet *ifp; 913 914 sc = device_get_softc(dev); 915 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 916 WB_LOCK(sc); 917 ifp = sc->wb_ifp; 918 919 /* 920 * Delete any miibus and phy devices attached to this interface. 921 * This should only be done if attach succeeded. 922 */ 923 if (device_is_attached(dev)) { 924 wb_stop(sc); 925 ether_ifdetach(ifp); 926 if_free(ifp); 927 } 928 if (sc->wb_miibus) 929 device_delete_child(dev, sc->wb_miibus); 930 bus_generic_detach(dev); 931 932 if (sc->wb_intrhand) 933 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 934 if (sc->wb_irq) 935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 936 if (sc->wb_res) 937 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 938 939 if (sc->wb_ldata) { 940 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 941 M_DEVBUF); 942 } 943 944 WB_UNLOCK(sc); 945 mtx_destroy(&sc->wb_mtx); 946 947 return(0); 948} 949 950/* 951 * Initialize the transmit descriptors. 952 */ 953static int 954wb_list_tx_init(sc) 955 struct wb_softc *sc; 956{ 957 struct wb_chain_data *cd; 958 struct wb_list_data *ld; 959 int i; 960 961 cd = &sc->wb_cdata; 962 ld = sc->wb_ldata; 963 964 for (i = 0; i < WB_TX_LIST_CNT; i++) { 965 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 966 if (i == (WB_TX_LIST_CNT - 1)) { 967 cd->wb_tx_chain[i].wb_nextdesc = 968 &cd->wb_tx_chain[0]; 969 } else { 970 cd->wb_tx_chain[i].wb_nextdesc = 971 &cd->wb_tx_chain[i + 1]; 972 } 973 } 974 975 cd->wb_tx_free = &cd->wb_tx_chain[0]; 976 cd->wb_tx_tail = cd->wb_tx_head = NULL; 977 978 return(0); 979} 980 981 982/* 983 * Initialize the RX descriptors and allocate mbufs for them. Note that 984 * we arrange the descriptors in a closed ring, so that the last descriptor 985 * points back to the first. 986 */ 987static int 988wb_list_rx_init(sc) 989 struct wb_softc *sc; 990{ 991 struct wb_chain_data *cd; 992 struct wb_list_data *ld; 993 int i; 994 995 cd = &sc->wb_cdata; 996 ld = sc->wb_ldata; 997 998 for (i = 0; i < WB_RX_LIST_CNT; i++) { 999 cd->wb_rx_chain[i].wb_ptr = 1000 (struct wb_desc *)&ld->wb_rx_list[i]; 1001 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1002 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1003 return(ENOBUFS); 1004 if (i == (WB_RX_LIST_CNT - 1)) { 1005 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1006 ld->wb_rx_list[i].wb_next = 1007 vtophys(&ld->wb_rx_list[0]); 1008 } else { 1009 cd->wb_rx_chain[i].wb_nextdesc = 1010 &cd->wb_rx_chain[i + 1]; 1011 ld->wb_rx_list[i].wb_next = 1012 vtophys(&ld->wb_rx_list[i + 1]); 1013 } 1014 } 1015 1016 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1017 1018 return(0); 1019} 1020 1021static void 1022wb_bfree(buf, args) 1023 void *buf; 1024 void *args; 1025{ 1026 return; 1027} 1028 1029/* 1030 * Initialize an RX descriptor and attach an MBUF cluster. 1031 */ 1032static int 1033wb_newbuf(sc, c, m) 1034 struct wb_softc *sc; 1035 struct wb_chain_onefrag *c; 1036 struct mbuf *m; 1037{ 1038 struct mbuf *m_new = NULL; 1039 1040 if (m == NULL) { 1041 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1042 if (m_new == NULL) 1043 return(ENOBUFS); 1044 m_new->m_data = c->wb_buf; 1045 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1046 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1047 EXT_NET_DRV); 1048 } else { 1049 m_new = m; 1050 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1051 m_new->m_data = m_new->m_ext.ext_buf; 1052 } 1053 1054 m_adj(m_new, sizeof(u_int64_t)); 1055 1056 c->wb_mbuf = m_new; 1057 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1058 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1059 c->wb_ptr->wb_status = WB_RXSTAT; 1060 1061 return(0); 1062} 1063 1064/* 1065 * A frame has been uploaded: pass the resulting mbuf chain up to 1066 * the higher level protocols. 1067 */ 1068static void 1069wb_rxeof(sc) 1070 struct wb_softc *sc; 1071{ 1072 struct mbuf *m = NULL; 1073 struct ifnet *ifp; 1074 struct wb_chain_onefrag *cur_rx; 1075 int total_len = 0; 1076 u_int32_t rxstat; 1077 1078 WB_LOCK_ASSERT(sc); 1079 1080 ifp = sc->wb_ifp; 1081 1082 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1083 WB_RXSTAT_OWN)) { 1084 struct mbuf *m0 = NULL; 1085 1086 cur_rx = sc->wb_cdata.wb_rx_head; 1087 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1088 1089 m = cur_rx->wb_mbuf; 1090 1091 if ((rxstat & WB_RXSTAT_MIIERR) || 1092 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1093 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1094 !(rxstat & WB_RXSTAT_LASTFRAG) || 1095 !(rxstat & WB_RXSTAT_RXCMP)) { 1096 ifp->if_ierrors++; 1097 wb_newbuf(sc, cur_rx, m); 1098 printf("wb%x: receiver babbling: possible chip " 1099 "bug, forcing reset\n", sc->wb_unit); 1100 wb_fixmedia(sc); 1101 wb_reset(sc); 1102 wb_init(sc); 1103 return; 1104 } 1105 1106 if (rxstat & WB_RXSTAT_RXERR) { 1107 ifp->if_ierrors++; 1108 wb_newbuf(sc, cur_rx, m); 1109 break; 1110 } 1111 1112 /* No errors; receive the packet. */ 1113 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1114 1115 /* 1116 * XXX The Winbond chip includes the CRC with every 1117 * received frame, and there's no way to turn this 1118 * behavior off (at least, I can't find anything in 1119 * the manual that explains how to do it) so we have 1120 * to trim off the CRC manually. 1121 */ 1122 total_len -= ETHER_CRC_LEN; 1123 1124 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1125 NULL); 1126 wb_newbuf(sc, cur_rx, m); 1127 if (m0 == NULL) { 1128 ifp->if_ierrors++; 1129 break; 1130 } 1131 m = m0; 1132 1133 ifp->if_ipackets++; 1134 WB_UNLOCK(sc); 1135 (*ifp->if_input)(ifp, m); 1136 WB_LOCK(sc); 1137 } 1138} 1139 1140static void 1141wb_rxeoc(sc) 1142 struct wb_softc *sc; 1143{ 1144 wb_rxeof(sc); 1145 1146 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1147 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1148 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1149 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1150 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1151 1152 return; 1153} 1154 1155/* 1156 * A frame was downloaded to the chip. It's safe for us to clean up 1157 * the list buffers. 1158 */ 1159static void 1160wb_txeof(sc) 1161 struct wb_softc *sc; 1162{ 1163 struct wb_chain *cur_tx; 1164 struct ifnet *ifp; 1165 1166 ifp = sc->wb_ifp; 1167 1168 /* Clear the timeout timer. */ 1169 ifp->if_timer = 0; 1170 1171 if (sc->wb_cdata.wb_tx_head == NULL) 1172 return; 1173 1174 /* 1175 * Go through our tx list and free mbufs for those 1176 * frames that have been transmitted. 1177 */ 1178 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1179 u_int32_t txstat; 1180 1181 cur_tx = sc->wb_cdata.wb_tx_head; 1182 txstat = WB_TXSTATUS(cur_tx); 1183 1184 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1185 break; 1186 1187 if (txstat & WB_TXSTAT_TXERR) { 1188 ifp->if_oerrors++; 1189 if (txstat & WB_TXSTAT_ABORT) 1190 ifp->if_collisions++; 1191 if (txstat & WB_TXSTAT_LATECOLL) 1192 ifp->if_collisions++; 1193 } 1194 1195 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1196 1197 ifp->if_opackets++; 1198 m_freem(cur_tx->wb_mbuf); 1199 cur_tx->wb_mbuf = NULL; 1200 1201 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1202 sc->wb_cdata.wb_tx_head = NULL; 1203 sc->wb_cdata.wb_tx_tail = NULL; 1204 break; 1205 } 1206 1207 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1208 } 1209 1210 return; 1211} 1212 1213/* 1214 * TX 'end of channel' interrupt handler. 1215 */ 1216static void 1217wb_txeoc(sc) 1218 struct wb_softc *sc; 1219{ 1220 struct ifnet *ifp; 1221 1222 ifp = sc->wb_ifp; 1223 1224 ifp->if_timer = 0; 1225 1226 if (sc->wb_cdata.wb_tx_head == NULL) { 1227 ifp->if_flags &= ~IFF_OACTIVE; 1228 sc->wb_cdata.wb_tx_tail = NULL; 1229 } else { 1230 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1231 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1232 ifp->if_timer = 5; 1233 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1234 } 1235 } 1236 1237 return; 1238} 1239 1240static void 1241wb_intr(arg) 1242 void *arg; 1243{ 1244 struct wb_softc *sc; 1245 struct ifnet *ifp; 1246 u_int32_t status; 1247 1248 sc = arg; 1249 WB_LOCK(sc); 1250 ifp = sc->wb_ifp; 1251 1252 if (!(ifp->if_flags & IFF_UP)) { 1253 WB_UNLOCK(sc); 1254 return; 1255 } 1256 1257 /* Disable interrupts. */ 1258 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1259 1260 for (;;) { 1261 1262 status = CSR_READ_4(sc, WB_ISR); 1263 if (status) 1264 CSR_WRITE_4(sc, WB_ISR, status); 1265 1266 if ((status & WB_INTRS) == 0) 1267 break; 1268 1269 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1270 ifp->if_ierrors++; 1271 wb_reset(sc); 1272 if (status & WB_ISR_RX_ERR) 1273 wb_fixmedia(sc); 1274 wb_init(sc); 1275 continue; 1276 } 1277 1278 if (status & WB_ISR_RX_OK) 1279 wb_rxeof(sc); 1280 1281 if (status & WB_ISR_RX_IDLE) 1282 wb_rxeoc(sc); 1283 1284 if (status & WB_ISR_TX_OK) 1285 wb_txeof(sc); 1286 1287 if (status & WB_ISR_TX_NOBUF) 1288 wb_txeoc(sc); 1289 1290 if (status & WB_ISR_TX_IDLE) { 1291 wb_txeof(sc); 1292 if (sc->wb_cdata.wb_tx_head != NULL) { 1293 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1294 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1295 } 1296 } 1297 1298 if (status & WB_ISR_TX_UNDERRUN) { 1299 ifp->if_oerrors++; 1300 wb_txeof(sc); 1301 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1302 /* Jack up TX threshold */ 1303 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1304 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1305 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1306 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1307 } 1308 1309 if (status & WB_ISR_BUS_ERR) { 1310 wb_reset(sc); 1311 wb_init(sc); 1312 } 1313 1314 } 1315 1316 /* Re-enable interrupts. */ 1317 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1318 1319 if (ifp->if_snd.ifq_head != NULL) { 1320 wb_start(ifp); 1321 } 1322 1323 WB_UNLOCK(sc); 1324 1325 return; 1326} 1327 1328static void 1329wb_tick(xsc) 1330 void *xsc; 1331{ 1332 struct wb_softc *sc; 1333 struct mii_data *mii; 1334 1335 sc = xsc; 1336 WB_LOCK(sc); 1337 mii = device_get_softc(sc->wb_miibus); 1338 1339 mii_tick(mii); 1340 1341 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1342 1343 WB_UNLOCK(sc); 1344 1345 return; 1346} 1347 1348/* 1349 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1350 * pointers to the fragment pointers. 1351 */ 1352static int 1353wb_encap(sc, c, m_head) 1354 struct wb_softc *sc; 1355 struct wb_chain *c; 1356 struct mbuf *m_head; 1357{ 1358 int frag = 0; 1359 struct wb_desc *f = NULL; 1360 int total_len; 1361 struct mbuf *m; 1362 1363 /* 1364 * Start packing the mbufs in this chain into 1365 * the fragment pointers. Stop when we run out 1366 * of fragments or hit the end of the mbuf chain. 1367 */ 1368 m = m_head; 1369 total_len = 0; 1370 1371 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1372 if (m->m_len != 0) { 1373 if (frag == WB_MAXFRAGS) 1374 break; 1375 total_len += m->m_len; 1376 f = &c->wb_ptr->wb_frag[frag]; 1377 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1378 if (frag == 0) { 1379 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1380 f->wb_status = 0; 1381 } else 1382 f->wb_status = WB_TXSTAT_OWN; 1383 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1384 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1385 frag++; 1386 } 1387 } 1388 1389 /* 1390 * Handle special case: we used up all 16 fragments, 1391 * but we have more mbufs left in the chain. Copy the 1392 * data into an mbuf cluster. Note that we don't 1393 * bother clearing the values in the other fragment 1394 * pointers/counters; it wouldn't gain us anything, 1395 * and would waste cycles. 1396 */ 1397 if (m != NULL) { 1398 struct mbuf *m_new = NULL; 1399 1400 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1401 if (m_new == NULL) 1402 return(1); 1403 if (m_head->m_pkthdr.len > MHLEN) { 1404 MCLGET(m_new, M_DONTWAIT); 1405 if (!(m_new->m_flags & M_EXT)) { 1406 m_freem(m_new); 1407 return(1); 1408 } 1409 } 1410 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1411 mtod(m_new, caddr_t)); 1412 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1413 m_freem(m_head); 1414 m_head = m_new; 1415 f = &c->wb_ptr->wb_frag[0]; 1416 f->wb_status = 0; 1417 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1418 f->wb_ctl = total_len = m_new->m_len; 1419 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1420 frag = 1; 1421 } 1422 1423 if (total_len < WB_MIN_FRAMELEN) { 1424 f = &c->wb_ptr->wb_frag[frag]; 1425 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1426 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1427 f->wb_ctl |= WB_TXCTL_TLINK; 1428 f->wb_status = WB_TXSTAT_OWN; 1429 frag++; 1430 } 1431 1432 c->wb_mbuf = m_head; 1433 c->wb_lastdesc = frag - 1; 1434 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1435 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1436 1437 return(0); 1438} 1439 1440/* 1441 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1442 * to the mbuf data regions directly in the transmit lists. We also save a 1443 * copy of the pointers since the transmit list fragment pointers are 1444 * physical addresses. 1445 */ 1446 1447static void 1448wb_start(ifp) 1449 struct ifnet *ifp; 1450{ 1451 struct wb_softc *sc; 1452 struct mbuf *m_head = NULL; 1453 struct wb_chain *cur_tx = NULL, *start_tx; 1454 1455 sc = ifp->if_softc; 1456 WB_LOCK(sc); 1457 1458 /* 1459 * Check for an available queue slot. If there are none, 1460 * punt. 1461 */ 1462 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1463 ifp->if_flags |= IFF_OACTIVE; 1464 WB_UNLOCK(sc); 1465 return; 1466 } 1467 1468 start_tx = sc->wb_cdata.wb_tx_free; 1469 1470 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1471 IF_DEQUEUE(&ifp->if_snd, m_head); 1472 if (m_head == NULL) 1473 break; 1474 1475 /* Pick a descriptor off the free list. */ 1476 cur_tx = sc->wb_cdata.wb_tx_free; 1477 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1478 1479 /* Pack the data into the descriptor. */ 1480 wb_encap(sc, cur_tx, m_head); 1481 1482 if (cur_tx != start_tx) 1483 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1484 1485 /* 1486 * If there's a BPF listener, bounce a copy of this frame 1487 * to him. 1488 */ 1489 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1490 } 1491 1492 /* 1493 * If there are no packets queued, bail. 1494 */ 1495 if (cur_tx == NULL) { 1496 WB_UNLOCK(sc); 1497 return; 1498 } 1499 1500 /* 1501 * Place the request for the upload interrupt 1502 * in the last descriptor in the chain. This way, if 1503 * we're chaining several packets at once, we'll only 1504 * get an interupt once for the whole chain rather than 1505 * once for each packet. 1506 */ 1507 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1508 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1509 sc->wb_cdata.wb_tx_tail = cur_tx; 1510 1511 if (sc->wb_cdata.wb_tx_head == NULL) { 1512 sc->wb_cdata.wb_tx_head = start_tx; 1513 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1514 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1515 } else { 1516 /* 1517 * We need to distinguish between the case where 1518 * the own bit is clear because the chip cleared it 1519 * and where the own bit is clear because we haven't 1520 * set it yet. The magic value WB_UNSET is just some 1521 * ramdomly chosen number which doesn't have the own 1522 * bit set. When we actually transmit the frame, the 1523 * status word will have _only_ the own bit set, so 1524 * the txeoc handler will be able to tell if it needs 1525 * to initiate another transmission to flush out pending 1526 * frames. 1527 */ 1528 WB_TXOWN(start_tx) = WB_UNSENT; 1529 } 1530 1531 /* 1532 * Set a timeout in case the chip goes out to lunch. 1533 */ 1534 ifp->if_timer = 5; 1535 WB_UNLOCK(sc); 1536 1537 return; 1538} 1539 1540static void 1541wb_init(xsc) 1542 void *xsc; 1543{ 1544 struct wb_softc *sc = xsc; 1545 struct ifnet *ifp = sc->wb_ifp; 1546 int i; 1547 struct mii_data *mii; 1548 1549 WB_LOCK(sc); 1550 mii = device_get_softc(sc->wb_miibus); 1551 1552 /* 1553 * Cancel pending I/O and free all RX/TX buffers. 1554 */ 1555 wb_stop(sc); 1556 wb_reset(sc); 1557 1558 sc->wb_txthresh = WB_TXTHRESH_INIT; 1559 1560 /* 1561 * Set cache alignment and burst length. 1562 */ 1563#ifdef foo 1564 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1565 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1566 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1567#endif 1568 1569 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1570 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1571 switch(sc->wb_cachesize) { 1572 case 32: 1573 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1574 break; 1575 case 16: 1576 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1577 break; 1578 case 8: 1579 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1580 break; 1581 case 0: 1582 default: 1583 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1584 break; 1585 } 1586 1587 /* This doesn't tend to work too well at 100Mbps. */ 1588 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1589 1590 /* Init our MAC address */ 1591 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1592 CSR_WRITE_1(sc, WB_NODE0 + i, IFP2ENADDR(sc->wb_ifp)[i]); 1593 } 1594 1595 /* Init circular RX list. */ 1596 if (wb_list_rx_init(sc) == ENOBUFS) { 1597 printf("wb%d: initialization failed: no " 1598 "memory for rx buffers\n", sc->wb_unit); 1599 wb_stop(sc); 1600 WB_UNLOCK(sc); 1601 return; 1602 } 1603 1604 /* Init TX descriptors. */ 1605 wb_list_tx_init(sc); 1606 1607 /* If we want promiscuous mode, set the allframes bit. */ 1608 if (ifp->if_flags & IFF_PROMISC) { 1609 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1610 } else { 1611 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1612 } 1613 1614 /* 1615 * Set capture broadcast bit to capture broadcast frames. 1616 */ 1617 if (ifp->if_flags & IFF_BROADCAST) { 1618 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1619 } else { 1620 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1621 } 1622 1623 /* 1624 * Program the multicast filter, if necessary. 1625 */ 1626 wb_setmulti(sc); 1627 1628 /* 1629 * Load the address of the RX list. 1630 */ 1631 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1632 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1633 1634 /* 1635 * Enable interrupts. 1636 */ 1637 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1638 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1639 1640 /* Enable receiver and transmitter. */ 1641 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1642 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1643 1644 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1645 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1646 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1647 1648 mii_mediachg(mii); 1649 1650 ifp->if_flags |= IFF_RUNNING; 1651 ifp->if_flags &= ~IFF_OACTIVE; 1652 1653 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1654 WB_UNLOCK(sc); 1655 1656 return; 1657} 1658 1659/* 1660 * Set media options. 1661 */ 1662static int 1663wb_ifmedia_upd(ifp) 1664 struct ifnet *ifp; 1665{ 1666 struct wb_softc *sc; 1667 1668 sc = ifp->if_softc; 1669 1670 if (ifp->if_flags & IFF_UP) 1671 wb_init(sc); 1672 1673 return(0); 1674} 1675 1676/* 1677 * Report current media status. 1678 */ 1679static void 1680wb_ifmedia_sts(ifp, ifmr) 1681 struct ifnet *ifp; 1682 struct ifmediareq *ifmr; 1683{ 1684 struct wb_softc *sc; 1685 struct mii_data *mii; 1686 1687 sc = ifp->if_softc; 1688 1689 mii = device_get_softc(sc->wb_miibus); 1690 1691 mii_pollstat(mii); 1692 ifmr->ifm_active = mii->mii_media_active; 1693 ifmr->ifm_status = mii->mii_media_status; 1694 1695 return; 1696} 1697 1698static int 1699wb_ioctl(ifp, command, data) 1700 struct ifnet *ifp; 1701 u_long command; 1702 caddr_t data; 1703{ 1704 struct wb_softc *sc = ifp->if_softc; 1705 struct mii_data *mii; 1706 struct ifreq *ifr = (struct ifreq *) data; 1707 int error = 0; 1708 1709 WB_LOCK(sc); 1710 1711 switch(command) { 1712 case SIOCSIFFLAGS: 1713 if (ifp->if_flags & IFF_UP) { 1714 wb_init(sc); 1715 } else { 1716 if (ifp->if_flags & IFF_RUNNING) 1717 wb_stop(sc); 1718 } 1719 error = 0; 1720 break; 1721 case SIOCADDMULTI: 1722 case SIOCDELMULTI: 1723 wb_setmulti(sc); 1724 error = 0; 1725 break; 1726 case SIOCGIFMEDIA: 1727 case SIOCSIFMEDIA: 1728 mii = device_get_softc(sc->wb_miibus); 1729 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1730 break; 1731 default: 1732 error = ether_ioctl(ifp, command, data); 1733 break; 1734 } 1735 1736 WB_UNLOCK(sc); 1737 1738 return(error); 1739} 1740 1741static void 1742wb_watchdog(ifp) 1743 struct ifnet *ifp; 1744{ 1745 struct wb_softc *sc; 1746 1747 sc = ifp->if_softc; 1748 1749 WB_LOCK(sc); 1750 ifp->if_oerrors++; 1751 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1752#ifdef foo 1753 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1754 printf("wb%d: no carrier - transceiver cable problem?\n", 1755 sc->wb_unit); 1756#endif 1757 wb_stop(sc); 1758 wb_reset(sc); 1759 wb_init(sc); 1760 1761 if (ifp->if_snd.ifq_head != NULL) 1762 wb_start(ifp); 1763 WB_UNLOCK(sc); 1764 1765 return; 1766} 1767 1768/* 1769 * Stop the adapter and free any mbufs allocated to the 1770 * RX and TX lists. 1771 */ 1772static void 1773wb_stop(sc) 1774 struct wb_softc *sc; 1775{ 1776 register int i; 1777 struct ifnet *ifp; 1778 1779 WB_LOCK(sc); 1780 ifp = sc->wb_ifp; 1781 ifp->if_timer = 0; 1782 1783 untimeout(wb_tick, sc, sc->wb_stat_ch); 1784 1785 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1786 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1787 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1788 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1789 1790 /* 1791 * Free data in the RX lists. 1792 */ 1793 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1794 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1795 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1796 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1797 } 1798 } 1799 bzero((char *)&sc->wb_ldata->wb_rx_list, 1800 sizeof(sc->wb_ldata->wb_rx_list)); 1801 1802 /* 1803 * Free the TX list buffers. 1804 */ 1805 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1806 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1807 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1808 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1809 } 1810 } 1811 1812 bzero((char *)&sc->wb_ldata->wb_tx_list, 1813 sizeof(sc->wb_ldata->wb_tx_list)); 1814 1815 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1816 WB_UNLOCK(sc); 1817 1818 return; 1819} 1820 1821/* 1822 * Stop all chip I/O so that the kernel's probe routines don't 1823 * get confused by errant DMAs when rebooting. 1824 */ 1825static void 1826wb_shutdown(dev) 1827 device_t dev; 1828{ 1829 struct wb_softc *sc; 1830 1831 sc = device_get_softc(dev); 1832 wb_stop(sc); 1833 1834 return; 1835} 1836