if_wb.c revision 126966
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 126966 2004-03-14 07:12:25Z mdodd $"); 35 36/* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus_memio.h> 108#include <machine/bus_pio.h> 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117#include <dev/mii/mii.h> 118#include <dev/mii/miivar.h> 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <pci/if_wbreg.h> 126 127MODULE_DEPEND(wb, pci, 1, 1, 1); 128MODULE_DEPEND(wb, ether, 1, 1, 1); 129MODULE_DEPEND(wb, miibus, 1, 1, 1); 130 131/* 132 * Various supported device vendors/types and their names. 133 */ 134static struct wb_type wb_devs[] = { 135 { WB_VENDORID, WB_DEVICEID_840F, 136 "Winbond W89C840F 10/100BaseTX" }, 137 { CP_VENDORID, CP_DEVICEID_RL100, 138 "Compex RL100-ATX 10/100baseTX" }, 139 { 0, 0, NULL } 140}; 141 142static int wb_probe (device_t); 143static int wb_attach (device_t); 144static int wb_detach (device_t); 145 146static void wb_bfree (void *addr, void *args); 147static int wb_newbuf (struct wb_softc *, 148 struct wb_chain_onefrag *, 149 struct mbuf *); 150static int wb_encap (struct wb_softc *, struct wb_chain *, 151 struct mbuf *); 152 153static void wb_rxeof (struct wb_softc *); 154static void wb_rxeoc (struct wb_softc *); 155static void wb_txeof (struct wb_softc *); 156static void wb_txeoc (struct wb_softc *); 157static void wb_intr (void *); 158static void wb_tick (void *); 159static void wb_start (struct ifnet *); 160static int wb_ioctl (struct ifnet *, u_long, caddr_t); 161static void wb_init (void *); 162static void wb_stop (struct wb_softc *); 163static void wb_watchdog (struct ifnet *); 164static void wb_shutdown (device_t); 165static int wb_ifmedia_upd (struct ifnet *); 166static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 167 168static void wb_eeprom_putbyte (struct wb_softc *, int); 169static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 170static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 171static void wb_mii_sync (struct wb_softc *); 172static void wb_mii_send (struct wb_softc *, u_int32_t, int); 173static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 174static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 175 176static void wb_setcfg (struct wb_softc *, u_int32_t); 177static uint32_t wb_mchash (const uint8_t *); 178static void wb_setmulti (struct wb_softc *); 179static void wb_reset (struct wb_softc *); 180static void wb_fixmedia (struct wb_softc *); 181static int wb_list_rx_init (struct wb_softc *); 182static int wb_list_tx_init (struct wb_softc *); 183 184static int wb_miibus_readreg (device_t, int, int); 185static int wb_miibus_writereg (device_t, int, int, int); 186static void wb_miibus_statchg (device_t); 187 188#ifdef WB_USEIOSPACE 189#define WB_RES SYS_RES_IOPORT 190#define WB_RID WB_PCI_LOIO 191#else 192#define WB_RES SYS_RES_MEMORY 193#define WB_RID WB_PCI_LOMEM 194#endif 195 196static device_method_t wb_methods[] = { 197 /* Device interface */ 198 DEVMETHOD(device_probe, wb_probe), 199 DEVMETHOD(device_attach, wb_attach), 200 DEVMETHOD(device_detach, wb_detach), 201 DEVMETHOD(device_shutdown, wb_shutdown), 202 203 /* bus interface, for miibus */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 209 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 210 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 211 { 0, 0 } 212}; 213 214static driver_t wb_driver = { 215 "wb", 216 wb_methods, 217 sizeof(struct wb_softc) 218}; 219 220static devclass_t wb_devclass; 221 222DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 223DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 224 225#define WB_SETBIT(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) | (x)) 228 229#define WB_CLRBIT(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) & ~(x)) 232 233#define SIO_SET(x) \ 234 CSR_WRITE_4(sc, WB_SIO, \ 235 CSR_READ_4(sc, WB_SIO) | (x)) 236 237#define SIO_CLR(x) \ 238 CSR_WRITE_4(sc, WB_SIO, \ 239 CSR_READ_4(sc, WB_SIO) & ~(x)) 240 241/* 242 * Send a read command and address to the EEPROM, check for ACK. 243 */ 244static void 245wb_eeprom_putbyte(sc, addr) 246 struct wb_softc *sc; 247 int addr; 248{ 249 register int d, i; 250 251 d = addr | WB_EECMD_READ; 252 253 /* 254 * Feed in each bit and stobe the clock. 255 */ 256 for (i = 0x400; i; i >>= 1) { 257 if (d & i) { 258 SIO_SET(WB_SIO_EE_DATAIN); 259 } else { 260 SIO_CLR(WB_SIO_EE_DATAIN); 261 } 262 DELAY(100); 263 SIO_SET(WB_SIO_EE_CLK); 264 DELAY(150); 265 SIO_CLR(WB_SIO_EE_CLK); 266 DELAY(100); 267 } 268 269 return; 270} 271 272/* 273 * Read a word of data stored in the EEPROM at address 'addr.' 274 */ 275static void 276wb_eeprom_getword(sc, addr, dest) 277 struct wb_softc *sc; 278 int addr; 279 u_int16_t *dest; 280{ 281 register int i; 282 u_int16_t word = 0; 283 284 /* Enter EEPROM access mode. */ 285 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 286 287 /* 288 * Send address of word we want to read. 289 */ 290 wb_eeprom_putbyte(sc, addr); 291 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Start reading bits from EEPROM. 296 */ 297 for (i = 0x8000; i; i >>= 1) { 298 SIO_SET(WB_SIO_EE_CLK); 299 DELAY(100); 300 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 301 word |= i; 302 SIO_CLR(WB_SIO_EE_CLK); 303 DELAY(100); 304 } 305 306 /* Turn off EEPROM access mode. */ 307 CSR_WRITE_4(sc, WB_SIO, 0); 308 309 *dest = word; 310 311 return; 312} 313 314/* 315 * Read a sequence of words from the EEPROM. 316 */ 317static void 318wb_read_eeprom(sc, dest, off, cnt, swap) 319 struct wb_softc *sc; 320 caddr_t dest; 321 int off; 322 int cnt; 323 int swap; 324{ 325 int i; 326 u_int16_t word = 0, *ptr; 327 328 for (i = 0; i < cnt; i++) { 329 wb_eeprom_getword(sc, off + i, &word); 330 ptr = (u_int16_t *)(dest + (i * 2)); 331 if (swap) 332 *ptr = ntohs(word); 333 else 334 *ptr = word; 335 } 336 337 return; 338} 339 340/* 341 * Sync the PHYs by setting data bit and strobing the clock 32 times. 342 */ 343static void 344wb_mii_sync(sc) 345 struct wb_softc *sc; 346{ 347 register int i; 348 349 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 350 351 for (i = 0; i < 32; i++) { 352 SIO_SET(WB_SIO_MII_CLK); 353 DELAY(1); 354 SIO_CLR(WB_SIO_MII_CLK); 355 DELAY(1); 356 } 357 358 return; 359} 360 361/* 362 * Clock a series of bits through the MII. 363 */ 364static void 365wb_mii_send(sc, bits, cnt) 366 struct wb_softc *sc; 367 u_int32_t bits; 368 int cnt; 369{ 370 int i; 371 372 SIO_CLR(WB_SIO_MII_CLK); 373 374 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 375 if (bits & i) { 376 SIO_SET(WB_SIO_MII_DATAIN); 377 } else { 378 SIO_CLR(WB_SIO_MII_DATAIN); 379 } 380 DELAY(1); 381 SIO_CLR(WB_SIO_MII_CLK); 382 DELAY(1); 383 SIO_SET(WB_SIO_MII_CLK); 384 } 385} 386 387/* 388 * Read an PHY register through the MII. 389 */ 390static int 391wb_mii_readreg(sc, frame) 392 struct wb_softc *sc; 393 struct wb_mii_frame *frame; 394 395{ 396 int i, ack; 397 398 WB_LOCK(sc); 399 400 /* 401 * Set up frame for RX. 402 */ 403 frame->mii_stdelim = WB_MII_STARTDELIM; 404 frame->mii_opcode = WB_MII_READOP; 405 frame->mii_turnaround = 0; 406 frame->mii_data = 0; 407 408 CSR_WRITE_4(sc, WB_SIO, 0); 409 410 /* 411 * Turn on data xmit. 412 */ 413 SIO_SET(WB_SIO_MII_DIR); 414 415 wb_mii_sync(sc); 416 417 /* 418 * Send command/address info. 419 */ 420 wb_mii_send(sc, frame->mii_stdelim, 2); 421 wb_mii_send(sc, frame->mii_opcode, 2); 422 wb_mii_send(sc, frame->mii_phyaddr, 5); 423 wb_mii_send(sc, frame->mii_regaddr, 5); 424 425 /* Idle bit */ 426 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 427 DELAY(1); 428 SIO_SET(WB_SIO_MII_CLK); 429 DELAY(1); 430 431 /* Turn off xmit. */ 432 SIO_CLR(WB_SIO_MII_DIR); 433 /* Check for ack */ 434 SIO_CLR(WB_SIO_MII_CLK); 435 DELAY(1); 436 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 437 SIO_SET(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_CLR(WB_SIO_MII_CLK); 440 DELAY(1); 441 SIO_SET(WB_SIO_MII_CLK); 442 DELAY(1); 443 444 /* 445 * Now try reading data bits. If the ack failed, we still 446 * need to clock through 16 cycles to keep the PHY(s) in sync. 447 */ 448 if (ack) { 449 for(i = 0; i < 16; i++) { 450 SIO_CLR(WB_SIO_MII_CLK); 451 DELAY(1); 452 SIO_SET(WB_SIO_MII_CLK); 453 DELAY(1); 454 } 455 goto fail; 456 } 457 458 for (i = 0x8000; i; i >>= 1) { 459 SIO_CLR(WB_SIO_MII_CLK); 460 DELAY(1); 461 if (!ack) { 462 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 463 frame->mii_data |= i; 464 DELAY(1); 465 } 466 SIO_SET(WB_SIO_MII_CLK); 467 DELAY(1); 468 } 469 470fail: 471 472 SIO_CLR(WB_SIO_MII_CLK); 473 DELAY(1); 474 SIO_SET(WB_SIO_MII_CLK); 475 DELAY(1); 476 477 WB_UNLOCK(sc); 478 479 if (ack) 480 return(1); 481 return(0); 482} 483 484/* 485 * Write to a PHY register through the MII. 486 */ 487static int 488wb_mii_writereg(sc, frame) 489 struct wb_softc *sc; 490 struct wb_mii_frame *frame; 491 492{ 493 WB_LOCK(sc); 494 495 /* 496 * Set up frame for TX. 497 */ 498 499 frame->mii_stdelim = WB_MII_STARTDELIM; 500 frame->mii_opcode = WB_MII_WRITEOP; 501 frame->mii_turnaround = WB_MII_TURNAROUND; 502 503 /* 504 * Turn on data output. 505 */ 506 SIO_SET(WB_SIO_MII_DIR); 507 508 wb_mii_sync(sc); 509 510 wb_mii_send(sc, frame->mii_stdelim, 2); 511 wb_mii_send(sc, frame->mii_opcode, 2); 512 wb_mii_send(sc, frame->mii_phyaddr, 5); 513 wb_mii_send(sc, frame->mii_regaddr, 5); 514 wb_mii_send(sc, frame->mii_turnaround, 2); 515 wb_mii_send(sc, frame->mii_data, 16); 516 517 /* Idle bit. */ 518 SIO_SET(WB_SIO_MII_CLK); 519 DELAY(1); 520 SIO_CLR(WB_SIO_MII_CLK); 521 DELAY(1); 522 523 /* 524 * Turn off xmit. 525 */ 526 SIO_CLR(WB_SIO_MII_DIR); 527 528 WB_UNLOCK(sc); 529 530 return(0); 531} 532 533static int 534wb_miibus_readreg(dev, phy, reg) 535 device_t dev; 536 int phy, reg; 537{ 538 struct wb_softc *sc; 539 struct wb_mii_frame frame; 540 541 sc = device_get_softc(dev); 542 543 bzero((char *)&frame, sizeof(frame)); 544 545 frame.mii_phyaddr = phy; 546 frame.mii_regaddr = reg; 547 wb_mii_readreg(sc, &frame); 548 549 return(frame.mii_data); 550} 551 552static int 553wb_miibus_writereg(dev, phy, reg, data) 554 device_t dev; 555 int phy, reg, data; 556{ 557 struct wb_softc *sc; 558 struct wb_mii_frame frame; 559 560 sc = device_get_softc(dev); 561 562 bzero((char *)&frame, sizeof(frame)); 563 564 frame.mii_phyaddr = phy; 565 frame.mii_regaddr = reg; 566 frame.mii_data = data; 567 568 wb_mii_writereg(sc, &frame); 569 570 return(0); 571} 572 573static void 574wb_miibus_statchg(dev) 575 device_t dev; 576{ 577 struct wb_softc *sc; 578 struct mii_data *mii; 579 580 sc = device_get_softc(dev); 581 WB_LOCK(sc); 582 mii = device_get_softc(sc->wb_miibus); 583 wb_setcfg(sc, mii->mii_media_active); 584 WB_UNLOCK(sc); 585 586 return; 587} 588 589static u_int32_t 590wb_mchash(addr) 591 const uint8_t *addr; 592{ 593 uint32_t crc, carry; 594 int idx, bit; 595 uint8_t data; 596 597 /* Compute CRC for the address value. */ 598 crc = 0xFFFFFFFF; /* initial value */ 599 600 for (idx = 0; idx < 6; idx++) { 601 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 602 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 603 crc <<= 1; 604 if (carry) 605 crc = (crc ^ 0x04c11db6) | carry; 606 } 607 } 608 609 /* 610 * return the filter bit position 611 * Note: I arrived at the following nonsense 612 * through experimentation. It's not the usual way to 613 * generate the bit position but it's the only thing 614 * I could come up with that works. 615 */ 616 return(~(crc >> 26) & 0x0000003F); 617} 618 619/* 620 * Program the 64-bit multicast hash filter. 621 */ 622static void 623wb_setmulti(sc) 624 struct wb_softc *sc; 625{ 626 struct ifnet *ifp; 627 int h = 0; 628 u_int32_t hashes[2] = { 0, 0 }; 629 struct ifmultiaddr *ifma; 630 u_int32_t rxfilt; 631 int mcnt = 0; 632 633 ifp = &sc->arpcom.ac_if; 634 635 rxfilt = CSR_READ_4(sc, WB_NETCFG); 636 637 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 638 rxfilt |= WB_NETCFG_RX_MULTI; 639 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 640 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 641 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 642 return; 643 } 644 645 /* first, zot all the existing hash bits */ 646 CSR_WRITE_4(sc, WB_MAR0, 0); 647 CSR_WRITE_4(sc, WB_MAR1, 0); 648 649 /* now program new ones */ 650 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 651 if (ifma->ifma_addr->sa_family != AF_LINK) 652 continue; 653 h = wb_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 654 if (h < 32) 655 hashes[0] |= (1 << h); 656 else 657 hashes[1] |= (1 << (h - 32)); 658 mcnt++; 659 } 660 661 if (mcnt) 662 rxfilt |= WB_NETCFG_RX_MULTI; 663 else 664 rxfilt &= ~WB_NETCFG_RX_MULTI; 665 666 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 667 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 668 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 669 670 return; 671} 672 673/* 674 * The Winbond manual states that in order to fiddle with the 675 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 676 * first have to put the transmit and/or receive logic in the idle state. 677 */ 678static void 679wb_setcfg(sc, media) 680 struct wb_softc *sc; 681 u_int32_t media; 682{ 683 int i, restart = 0; 684 685 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 686 restart = 1; 687 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 688 689 for (i = 0; i < WB_TIMEOUT; i++) { 690 DELAY(10); 691 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 692 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 693 break; 694 } 695 696 if (i == WB_TIMEOUT) 697 printf("wb%d: failed to force tx and " 698 "rx to idle state\n", sc->wb_unit); 699 } 700 701 if (IFM_SUBTYPE(media) == IFM_10_T) 702 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 703 else 704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 705 706 if ((media & IFM_GMASK) == IFM_FDX) 707 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 708 else 709 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 710 711 if (restart) 712 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 713 714 return; 715} 716 717static void 718wb_reset(sc) 719 struct wb_softc *sc; 720{ 721 register int i; 722 struct mii_data *mii; 723 724 CSR_WRITE_4(sc, WB_NETCFG, 0); 725 CSR_WRITE_4(sc, WB_BUSCTL, 0); 726 CSR_WRITE_4(sc, WB_TXADDR, 0); 727 CSR_WRITE_4(sc, WB_RXADDR, 0); 728 729 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 730 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 731 732 for (i = 0; i < WB_TIMEOUT; i++) { 733 DELAY(10); 734 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 735 break; 736 } 737 if (i == WB_TIMEOUT) 738 printf("wb%d: reset never completed!\n", sc->wb_unit); 739 740 /* Wait a little while for the chip to get its brains in order. */ 741 DELAY(1000); 742 743 if (sc->wb_miibus == NULL) 744 return; 745 746 mii = device_get_softc(sc->wb_miibus); 747 if (mii == NULL) 748 return; 749 750 if (mii->mii_instance) { 751 struct mii_softc *miisc; 752 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 753 mii_phy_reset(miisc); 754 } 755 756 return; 757} 758 759static void 760wb_fixmedia(sc) 761 struct wb_softc *sc; 762{ 763 struct mii_data *mii = NULL; 764 struct ifnet *ifp; 765 u_int32_t media; 766 767 if (sc->wb_miibus == NULL) 768 return; 769 770 mii = device_get_softc(sc->wb_miibus); 771 ifp = &sc->arpcom.ac_if; 772 773 mii_pollstat(mii); 774 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 775 media = mii->mii_media_active & ~IFM_10_T; 776 media |= IFM_100_TX; 777 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 778 media = mii->mii_media_active & ~IFM_100_TX; 779 media |= IFM_10_T; 780 } else 781 return; 782 783 ifmedia_set(&mii->mii_media, media); 784 785 return; 786} 787 788/* 789 * Probe for a Winbond chip. Check the PCI vendor and device 790 * IDs against our list and return a device name if we find a match. 791 */ 792static int 793wb_probe(dev) 794 device_t dev; 795{ 796 struct wb_type *t; 797 798 t = wb_devs; 799 800 while(t->wb_name != NULL) { 801 if ((pci_get_vendor(dev) == t->wb_vid) && 802 (pci_get_device(dev) == t->wb_did)) { 803 device_set_desc(dev, t->wb_name); 804 return(0); 805 } 806 t++; 807 } 808 809 return(ENXIO); 810} 811 812/* 813 * Attach the interface. Allocate softc structures, do ifmedia 814 * setup and ethernet/BPF attach. 815 */ 816static int 817wb_attach(dev) 818 device_t dev; 819{ 820 u_char eaddr[ETHER_ADDR_LEN]; 821 struct wb_softc *sc; 822 struct ifnet *ifp; 823 int unit, error = 0, rid; 824 825 sc = device_get_softc(dev); 826 unit = device_get_unit(dev); 827 828 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 829 MTX_DEF | MTX_RECURSE); 830#ifndef BURN_BRIDGES 831 /* 832 * Handle power management nonsense. 833 */ 834 835 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 836 u_int32_t iobase, membase, irq; 837 838 /* Save important PCI config data. */ 839 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 840 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 841 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 842 843 /* Reset the power state. */ 844 printf("wb%d: chip is in D%d power mode " 845 "-- setting to D0\n", unit, 846 pci_get_powerstate(dev)); 847 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 848 849 /* Restore PCI config data. */ 850 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 851 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 852 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 853 } 854#endif 855 /* 856 * Map control/status registers. 857 */ 858 pci_enable_busmaster(dev); 859 860 rid = WB_RID; 861 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 862 0, ~0, 1, RF_ACTIVE); 863 864 if (sc->wb_res == NULL) { 865 printf("wb%d: couldn't map ports/memory\n", unit); 866 error = ENXIO; 867 goto fail; 868 } 869 870 sc->wb_btag = rman_get_bustag(sc->wb_res); 871 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 872 873 /* Allocate interrupt */ 874 rid = 0; 875 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 876 RF_SHAREABLE | RF_ACTIVE); 877 878 if (sc->wb_irq == NULL) { 879 printf("wb%d: couldn't map interrupt\n", unit); 880 error = ENXIO; 881 goto fail; 882 } 883 884 /* Save the cache line size. */ 885 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 886 887 /* Reset the adapter. */ 888 wb_reset(sc); 889 890 /* 891 * Get station address from the EEPROM. 892 */ 893 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 894 895 sc->wb_unit = unit; 896 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 897 898 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 899 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 900 901 if (sc->wb_ldata == NULL) { 902 printf("wb%d: no memory for list buffers!\n", unit); 903 error = ENXIO; 904 goto fail; 905 } 906 907 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 908 909 ifp = &sc->arpcom.ac_if; 910 ifp->if_softc = sc; 911 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 912 ifp->if_mtu = ETHERMTU; 913 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 914 ifp->if_ioctl = wb_ioctl; 915 ifp->if_start = wb_start; 916 ifp->if_watchdog = wb_watchdog; 917 ifp->if_init = wb_init; 918 ifp->if_baudrate = 10000000; 919 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 920 921 /* 922 * Do MII setup. 923 */ 924 if (mii_phy_probe(dev, &sc->wb_miibus, 925 wb_ifmedia_upd, wb_ifmedia_sts)) { 926 error = ENXIO; 927 goto fail; 928 } 929 930 /* 931 * Call MI attach routine. 932 */ 933 ether_ifattach(ifp, eaddr); 934 935 /* Hook interrupt last to avoid having to lock softc */ 936 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 937 wb_intr, sc, &sc->wb_intrhand); 938 939 if (error) { 940 printf("wb%d: couldn't set up irq\n", unit); 941 ether_ifdetach(ifp); 942 goto fail; 943 } 944 945fail: 946 if (error) 947 wb_detach(dev); 948 949 return(error); 950} 951 952/* 953 * Shutdown hardware and free up resources. This can be called any 954 * time after the mutex has been initialized. It is called in both 955 * the error case in attach and the normal detach case so it needs 956 * to be careful about only freeing resources that have actually been 957 * allocated. 958 */ 959static int 960wb_detach(dev) 961 device_t dev; 962{ 963 struct wb_softc *sc; 964 struct ifnet *ifp; 965 966 sc = device_get_softc(dev); 967 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 968 WB_LOCK(sc); 969 ifp = &sc->arpcom.ac_if; 970 971 /* 972 * Delete any miibus and phy devices attached to this interface. 973 * This should only be done if attach succeeded. 974 */ 975 if (device_is_attached(dev)) { 976 wb_stop(sc); 977 ether_ifdetach(ifp); 978 } 979 if (sc->wb_miibus) 980 device_delete_child(dev, sc->wb_miibus); 981 bus_generic_detach(dev); 982 983 if (sc->wb_intrhand) 984 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 985 if (sc->wb_irq) 986 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 987 if (sc->wb_res) 988 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 989 990 if (sc->wb_ldata) { 991 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 992 M_DEVBUF); 993 } 994 995 WB_UNLOCK(sc); 996 mtx_destroy(&sc->wb_mtx); 997 998 return(0); 999} 1000 1001/* 1002 * Initialize the transmit descriptors. 1003 */ 1004static int 1005wb_list_tx_init(sc) 1006 struct wb_softc *sc; 1007{ 1008 struct wb_chain_data *cd; 1009 struct wb_list_data *ld; 1010 int i; 1011 1012 cd = &sc->wb_cdata; 1013 ld = sc->wb_ldata; 1014 1015 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1016 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1017 if (i == (WB_TX_LIST_CNT - 1)) { 1018 cd->wb_tx_chain[i].wb_nextdesc = 1019 &cd->wb_tx_chain[0]; 1020 } else { 1021 cd->wb_tx_chain[i].wb_nextdesc = 1022 &cd->wb_tx_chain[i + 1]; 1023 } 1024 } 1025 1026 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1027 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1028 1029 return(0); 1030} 1031 1032 1033/* 1034 * Initialize the RX descriptors and allocate mbufs for them. Note that 1035 * we arrange the descriptors in a closed ring, so that the last descriptor 1036 * points back to the first. 1037 */ 1038static int 1039wb_list_rx_init(sc) 1040 struct wb_softc *sc; 1041{ 1042 struct wb_chain_data *cd; 1043 struct wb_list_data *ld; 1044 int i; 1045 1046 cd = &sc->wb_cdata; 1047 ld = sc->wb_ldata; 1048 1049 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1050 cd->wb_rx_chain[i].wb_ptr = 1051 (struct wb_desc *)&ld->wb_rx_list[i]; 1052 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1053 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1054 return(ENOBUFS); 1055 if (i == (WB_RX_LIST_CNT - 1)) { 1056 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1057 ld->wb_rx_list[i].wb_next = 1058 vtophys(&ld->wb_rx_list[0]); 1059 } else { 1060 cd->wb_rx_chain[i].wb_nextdesc = 1061 &cd->wb_rx_chain[i + 1]; 1062 ld->wb_rx_list[i].wb_next = 1063 vtophys(&ld->wb_rx_list[i + 1]); 1064 } 1065 } 1066 1067 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1068 1069 return(0); 1070} 1071 1072static void 1073wb_bfree(buf, args) 1074 void *buf; 1075 void *args; 1076{ 1077 return; 1078} 1079 1080/* 1081 * Initialize an RX descriptor and attach an MBUF cluster. 1082 */ 1083static int 1084wb_newbuf(sc, c, m) 1085 struct wb_softc *sc; 1086 struct wb_chain_onefrag *c; 1087 struct mbuf *m; 1088{ 1089 struct mbuf *m_new = NULL; 1090 1091 if (m == NULL) { 1092 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1093 if (m_new == NULL) 1094 return(ENOBUFS); 1095 m_new->m_data = c->wb_buf; 1096 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1097 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1098 EXT_NET_DRV); 1099 } else { 1100 m_new = m; 1101 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1102 m_new->m_data = m_new->m_ext.ext_buf; 1103 } 1104 1105 m_adj(m_new, sizeof(u_int64_t)); 1106 1107 c->wb_mbuf = m_new; 1108 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1109 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1110 c->wb_ptr->wb_status = WB_RXSTAT; 1111 1112 return(0); 1113} 1114 1115/* 1116 * A frame has been uploaded: pass the resulting mbuf chain up to 1117 * the higher level protocols. 1118 */ 1119static void 1120wb_rxeof(sc) 1121 struct wb_softc *sc; 1122{ 1123 struct mbuf *m = NULL; 1124 struct ifnet *ifp; 1125 struct wb_chain_onefrag *cur_rx; 1126 int total_len = 0; 1127 u_int32_t rxstat; 1128 1129 WB_LOCK_ASSERT(sc); 1130 1131 ifp = &sc->arpcom.ac_if; 1132 1133 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1134 WB_RXSTAT_OWN)) { 1135 struct mbuf *m0 = NULL; 1136 1137 cur_rx = sc->wb_cdata.wb_rx_head; 1138 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1139 1140 m = cur_rx->wb_mbuf; 1141 1142 if ((rxstat & WB_RXSTAT_MIIERR) || 1143 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1144 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1145 !(rxstat & WB_RXSTAT_LASTFRAG) || 1146 !(rxstat & WB_RXSTAT_RXCMP)) { 1147 ifp->if_ierrors++; 1148 wb_newbuf(sc, cur_rx, m); 1149 printf("wb%x: receiver babbling: possible chip " 1150 "bug, forcing reset\n", sc->wb_unit); 1151 wb_fixmedia(sc); 1152 wb_reset(sc); 1153 wb_init(sc); 1154 return; 1155 } 1156 1157 if (rxstat & WB_RXSTAT_RXERR) { 1158 ifp->if_ierrors++; 1159 wb_newbuf(sc, cur_rx, m); 1160 break; 1161 } 1162 1163 /* No errors; receive the packet. */ 1164 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1165 1166 /* 1167 * XXX The Winbond chip includes the CRC with every 1168 * received frame, and there's no way to turn this 1169 * behavior off (at least, I can't find anything in 1170 * the manual that explains how to do it) so we have 1171 * to trim off the CRC manually. 1172 */ 1173 total_len -= ETHER_CRC_LEN; 1174 1175 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1176 NULL); 1177 wb_newbuf(sc, cur_rx, m); 1178 if (m0 == NULL) { 1179 ifp->if_ierrors++; 1180 break; 1181 } 1182 m = m0; 1183 1184 ifp->if_ipackets++; 1185 WB_UNLOCK(sc); 1186 (*ifp->if_input)(ifp, m); 1187 WB_LOCK(sc); 1188 } 1189} 1190 1191static void 1192wb_rxeoc(sc) 1193 struct wb_softc *sc; 1194{ 1195 wb_rxeof(sc); 1196 1197 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1198 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1199 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1200 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1201 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1202 1203 return; 1204} 1205 1206/* 1207 * A frame was downloaded to the chip. It's safe for us to clean up 1208 * the list buffers. 1209 */ 1210static void 1211wb_txeof(sc) 1212 struct wb_softc *sc; 1213{ 1214 struct wb_chain *cur_tx; 1215 struct ifnet *ifp; 1216 1217 ifp = &sc->arpcom.ac_if; 1218 1219 /* Clear the timeout timer. */ 1220 ifp->if_timer = 0; 1221 1222 if (sc->wb_cdata.wb_tx_head == NULL) 1223 return; 1224 1225 /* 1226 * Go through our tx list and free mbufs for those 1227 * frames that have been transmitted. 1228 */ 1229 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1230 u_int32_t txstat; 1231 1232 cur_tx = sc->wb_cdata.wb_tx_head; 1233 txstat = WB_TXSTATUS(cur_tx); 1234 1235 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1236 break; 1237 1238 if (txstat & WB_TXSTAT_TXERR) { 1239 ifp->if_oerrors++; 1240 if (txstat & WB_TXSTAT_ABORT) 1241 ifp->if_collisions++; 1242 if (txstat & WB_TXSTAT_LATECOLL) 1243 ifp->if_collisions++; 1244 } 1245 1246 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1247 1248 ifp->if_opackets++; 1249 m_freem(cur_tx->wb_mbuf); 1250 cur_tx->wb_mbuf = NULL; 1251 1252 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1253 sc->wb_cdata.wb_tx_head = NULL; 1254 sc->wb_cdata.wb_tx_tail = NULL; 1255 break; 1256 } 1257 1258 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1259 } 1260 1261 return; 1262} 1263 1264/* 1265 * TX 'end of channel' interrupt handler. 1266 */ 1267static void 1268wb_txeoc(sc) 1269 struct wb_softc *sc; 1270{ 1271 struct ifnet *ifp; 1272 1273 ifp = &sc->arpcom.ac_if; 1274 1275 ifp->if_timer = 0; 1276 1277 if (sc->wb_cdata.wb_tx_head == NULL) { 1278 ifp->if_flags &= ~IFF_OACTIVE; 1279 sc->wb_cdata.wb_tx_tail = NULL; 1280 } else { 1281 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1282 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1283 ifp->if_timer = 5; 1284 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1285 } 1286 } 1287 1288 return; 1289} 1290 1291static void 1292wb_intr(arg) 1293 void *arg; 1294{ 1295 struct wb_softc *sc; 1296 struct ifnet *ifp; 1297 u_int32_t status; 1298 1299 sc = arg; 1300 WB_LOCK(sc); 1301 ifp = &sc->arpcom.ac_if; 1302 1303 if (!(ifp->if_flags & IFF_UP)) { 1304 WB_UNLOCK(sc); 1305 return; 1306 } 1307 1308 /* Disable interrupts. */ 1309 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1310 1311 for (;;) { 1312 1313 status = CSR_READ_4(sc, WB_ISR); 1314 if (status) 1315 CSR_WRITE_4(sc, WB_ISR, status); 1316 1317 if ((status & WB_INTRS) == 0) 1318 break; 1319 1320 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1321 ifp->if_ierrors++; 1322 wb_reset(sc); 1323 if (status & WB_ISR_RX_ERR) 1324 wb_fixmedia(sc); 1325 wb_init(sc); 1326 continue; 1327 } 1328 1329 if (status & WB_ISR_RX_OK) 1330 wb_rxeof(sc); 1331 1332 if (status & WB_ISR_RX_IDLE) 1333 wb_rxeoc(sc); 1334 1335 if (status & WB_ISR_TX_OK) 1336 wb_txeof(sc); 1337 1338 if (status & WB_ISR_TX_NOBUF) 1339 wb_txeoc(sc); 1340 1341 if (status & WB_ISR_TX_IDLE) { 1342 wb_txeof(sc); 1343 if (sc->wb_cdata.wb_tx_head != NULL) { 1344 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1345 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1346 } 1347 } 1348 1349 if (status & WB_ISR_TX_UNDERRUN) { 1350 ifp->if_oerrors++; 1351 wb_txeof(sc); 1352 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1353 /* Jack up TX threshold */ 1354 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1355 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1356 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1357 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1358 } 1359 1360 if (status & WB_ISR_BUS_ERR) { 1361 wb_reset(sc); 1362 wb_init(sc); 1363 } 1364 1365 } 1366 1367 /* Re-enable interrupts. */ 1368 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1369 1370 if (ifp->if_snd.ifq_head != NULL) { 1371 wb_start(ifp); 1372 } 1373 1374 WB_UNLOCK(sc); 1375 1376 return; 1377} 1378 1379static void 1380wb_tick(xsc) 1381 void *xsc; 1382{ 1383 struct wb_softc *sc; 1384 struct mii_data *mii; 1385 1386 sc = xsc; 1387 WB_LOCK(sc); 1388 mii = device_get_softc(sc->wb_miibus); 1389 1390 mii_tick(mii); 1391 1392 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1393 1394 WB_UNLOCK(sc); 1395 1396 return; 1397} 1398 1399/* 1400 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1401 * pointers to the fragment pointers. 1402 */ 1403static int 1404wb_encap(sc, c, m_head) 1405 struct wb_softc *sc; 1406 struct wb_chain *c; 1407 struct mbuf *m_head; 1408{ 1409 int frag = 0; 1410 struct wb_desc *f = NULL; 1411 int total_len; 1412 struct mbuf *m; 1413 1414 /* 1415 * Start packing the mbufs in this chain into 1416 * the fragment pointers. Stop when we run out 1417 * of fragments or hit the end of the mbuf chain. 1418 */ 1419 m = m_head; 1420 total_len = 0; 1421 1422 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1423 if (m->m_len != 0) { 1424 if (frag == WB_MAXFRAGS) 1425 break; 1426 total_len += m->m_len; 1427 f = &c->wb_ptr->wb_frag[frag]; 1428 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1429 if (frag == 0) { 1430 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1431 f->wb_status = 0; 1432 } else 1433 f->wb_status = WB_TXSTAT_OWN; 1434 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1435 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1436 frag++; 1437 } 1438 } 1439 1440 /* 1441 * Handle special case: we used up all 16 fragments, 1442 * but we have more mbufs left in the chain. Copy the 1443 * data into an mbuf cluster. Note that we don't 1444 * bother clearing the values in the other fragment 1445 * pointers/counters; it wouldn't gain us anything, 1446 * and would waste cycles. 1447 */ 1448 if (m != NULL) { 1449 struct mbuf *m_new = NULL; 1450 1451 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1452 if (m_new == NULL) 1453 return(1); 1454 if (m_head->m_pkthdr.len > MHLEN) { 1455 MCLGET(m_new, M_DONTWAIT); 1456 if (!(m_new->m_flags & M_EXT)) { 1457 m_freem(m_new); 1458 return(1); 1459 } 1460 } 1461 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1462 mtod(m_new, caddr_t)); 1463 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1464 m_freem(m_head); 1465 m_head = m_new; 1466 f = &c->wb_ptr->wb_frag[0]; 1467 f->wb_status = 0; 1468 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1469 f->wb_ctl = total_len = m_new->m_len; 1470 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1471 frag = 1; 1472 } 1473 1474 if (total_len < WB_MIN_FRAMELEN) { 1475 f = &c->wb_ptr->wb_frag[frag]; 1476 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1477 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1478 f->wb_ctl |= WB_TXCTL_TLINK; 1479 f->wb_status = WB_TXSTAT_OWN; 1480 frag++; 1481 } 1482 1483 c->wb_mbuf = m_head; 1484 c->wb_lastdesc = frag - 1; 1485 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1486 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1487 1488 return(0); 1489} 1490 1491/* 1492 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1493 * to the mbuf data regions directly in the transmit lists. We also save a 1494 * copy of the pointers since the transmit list fragment pointers are 1495 * physical addresses. 1496 */ 1497 1498static void 1499wb_start(ifp) 1500 struct ifnet *ifp; 1501{ 1502 struct wb_softc *sc; 1503 struct mbuf *m_head = NULL; 1504 struct wb_chain *cur_tx = NULL, *start_tx; 1505 1506 sc = ifp->if_softc; 1507 WB_LOCK(sc); 1508 1509 /* 1510 * Check for an available queue slot. If there are none, 1511 * punt. 1512 */ 1513 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1514 ifp->if_flags |= IFF_OACTIVE; 1515 WB_UNLOCK(sc); 1516 return; 1517 } 1518 1519 start_tx = sc->wb_cdata.wb_tx_free; 1520 1521 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1522 IF_DEQUEUE(&ifp->if_snd, m_head); 1523 if (m_head == NULL) 1524 break; 1525 1526 /* Pick a descriptor off the free list. */ 1527 cur_tx = sc->wb_cdata.wb_tx_free; 1528 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1529 1530 /* Pack the data into the descriptor. */ 1531 wb_encap(sc, cur_tx, m_head); 1532 1533 if (cur_tx != start_tx) 1534 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1535 1536 /* 1537 * If there's a BPF listener, bounce a copy of this frame 1538 * to him. 1539 */ 1540 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1541 } 1542 1543 /* 1544 * If there are no packets queued, bail. 1545 */ 1546 if (cur_tx == NULL) { 1547 WB_UNLOCK(sc); 1548 return; 1549 } 1550 1551 /* 1552 * Place the request for the upload interrupt 1553 * in the last descriptor in the chain. This way, if 1554 * we're chaining several packets at once, we'll only 1555 * get an interupt once for the whole chain rather than 1556 * once for each packet. 1557 */ 1558 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1559 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1560 sc->wb_cdata.wb_tx_tail = cur_tx; 1561 1562 if (sc->wb_cdata.wb_tx_head == NULL) { 1563 sc->wb_cdata.wb_tx_head = start_tx; 1564 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1565 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1566 } else { 1567 /* 1568 * We need to distinguish between the case where 1569 * the own bit is clear because the chip cleared it 1570 * and where the own bit is clear because we haven't 1571 * set it yet. The magic value WB_UNSET is just some 1572 * ramdomly chosen number which doesn't have the own 1573 * bit set. When we actually transmit the frame, the 1574 * status word will have _only_ the own bit set, so 1575 * the txeoc handler will be able to tell if it needs 1576 * to initiate another transmission to flush out pending 1577 * frames. 1578 */ 1579 WB_TXOWN(start_tx) = WB_UNSENT; 1580 } 1581 1582 /* 1583 * Set a timeout in case the chip goes out to lunch. 1584 */ 1585 ifp->if_timer = 5; 1586 WB_UNLOCK(sc); 1587 1588 return; 1589} 1590 1591static void 1592wb_init(xsc) 1593 void *xsc; 1594{ 1595 struct wb_softc *sc = xsc; 1596 struct ifnet *ifp = &sc->arpcom.ac_if; 1597 int i; 1598 struct mii_data *mii; 1599 1600 WB_LOCK(sc); 1601 mii = device_get_softc(sc->wb_miibus); 1602 1603 /* 1604 * Cancel pending I/O and free all RX/TX buffers. 1605 */ 1606 wb_stop(sc); 1607 wb_reset(sc); 1608 1609 sc->wb_txthresh = WB_TXTHRESH_INIT; 1610 1611 /* 1612 * Set cache alignment and burst length. 1613 */ 1614#ifdef foo 1615 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1616 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1617 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1618#endif 1619 1620 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1621 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1622 switch(sc->wb_cachesize) { 1623 case 32: 1624 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1625 break; 1626 case 16: 1627 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1628 break; 1629 case 8: 1630 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1631 break; 1632 case 0: 1633 default: 1634 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1635 break; 1636 } 1637 1638 /* This doesn't tend to work too well at 100Mbps. */ 1639 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1640 1641 /* Init our MAC address */ 1642 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1643 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1644 } 1645 1646 /* Init circular RX list. */ 1647 if (wb_list_rx_init(sc) == ENOBUFS) { 1648 printf("wb%d: initialization failed: no " 1649 "memory for rx buffers\n", sc->wb_unit); 1650 wb_stop(sc); 1651 WB_UNLOCK(sc); 1652 return; 1653 } 1654 1655 /* Init TX descriptors. */ 1656 wb_list_tx_init(sc); 1657 1658 /* If we want promiscuous mode, set the allframes bit. */ 1659 if (ifp->if_flags & IFF_PROMISC) { 1660 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1661 } else { 1662 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1663 } 1664 1665 /* 1666 * Set capture broadcast bit to capture broadcast frames. 1667 */ 1668 if (ifp->if_flags & IFF_BROADCAST) { 1669 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1670 } else { 1671 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1672 } 1673 1674 /* 1675 * Program the multicast filter, if necessary. 1676 */ 1677 wb_setmulti(sc); 1678 1679 /* 1680 * Load the address of the RX list. 1681 */ 1682 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1683 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1684 1685 /* 1686 * Enable interrupts. 1687 */ 1688 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1689 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1690 1691 /* Enable receiver and transmitter. */ 1692 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1693 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1694 1695 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1696 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1697 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1698 1699 mii_mediachg(mii); 1700 1701 ifp->if_flags |= IFF_RUNNING; 1702 ifp->if_flags &= ~IFF_OACTIVE; 1703 1704 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1705 WB_UNLOCK(sc); 1706 1707 return; 1708} 1709 1710/* 1711 * Set media options. 1712 */ 1713static int 1714wb_ifmedia_upd(ifp) 1715 struct ifnet *ifp; 1716{ 1717 struct wb_softc *sc; 1718 1719 sc = ifp->if_softc; 1720 1721 if (ifp->if_flags & IFF_UP) 1722 wb_init(sc); 1723 1724 return(0); 1725} 1726 1727/* 1728 * Report current media status. 1729 */ 1730static void 1731wb_ifmedia_sts(ifp, ifmr) 1732 struct ifnet *ifp; 1733 struct ifmediareq *ifmr; 1734{ 1735 struct wb_softc *sc; 1736 struct mii_data *mii; 1737 1738 sc = ifp->if_softc; 1739 1740 mii = device_get_softc(sc->wb_miibus); 1741 1742 mii_pollstat(mii); 1743 ifmr->ifm_active = mii->mii_media_active; 1744 ifmr->ifm_status = mii->mii_media_status; 1745 1746 return; 1747} 1748 1749static int 1750wb_ioctl(ifp, command, data) 1751 struct ifnet *ifp; 1752 u_long command; 1753 caddr_t data; 1754{ 1755 struct wb_softc *sc = ifp->if_softc; 1756 struct mii_data *mii; 1757 struct ifreq *ifr = (struct ifreq *) data; 1758 int error = 0; 1759 1760 WB_LOCK(sc); 1761 1762 switch(command) { 1763 case SIOCSIFFLAGS: 1764 if (ifp->if_flags & IFF_UP) { 1765 wb_init(sc); 1766 } else { 1767 if (ifp->if_flags & IFF_RUNNING) 1768 wb_stop(sc); 1769 } 1770 error = 0; 1771 break; 1772 case SIOCADDMULTI: 1773 case SIOCDELMULTI: 1774 wb_setmulti(sc); 1775 error = 0; 1776 break; 1777 case SIOCGIFMEDIA: 1778 case SIOCSIFMEDIA: 1779 mii = device_get_softc(sc->wb_miibus); 1780 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1781 break; 1782 default: 1783 error = ether_ioctl(ifp, command, data); 1784 break; 1785 } 1786 1787 WB_UNLOCK(sc); 1788 1789 return(error); 1790} 1791 1792static void 1793wb_watchdog(ifp) 1794 struct ifnet *ifp; 1795{ 1796 struct wb_softc *sc; 1797 1798 sc = ifp->if_softc; 1799 1800 WB_LOCK(sc); 1801 ifp->if_oerrors++; 1802 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1803#ifdef foo 1804 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1805 printf("wb%d: no carrier - transceiver cable problem?\n", 1806 sc->wb_unit); 1807#endif 1808 wb_stop(sc); 1809 wb_reset(sc); 1810 wb_init(sc); 1811 1812 if (ifp->if_snd.ifq_head != NULL) 1813 wb_start(ifp); 1814 WB_UNLOCK(sc); 1815 1816 return; 1817} 1818 1819/* 1820 * Stop the adapter and free any mbufs allocated to the 1821 * RX and TX lists. 1822 */ 1823static void 1824wb_stop(sc) 1825 struct wb_softc *sc; 1826{ 1827 register int i; 1828 struct ifnet *ifp; 1829 1830 WB_LOCK(sc); 1831 ifp = &sc->arpcom.ac_if; 1832 ifp->if_timer = 0; 1833 1834 untimeout(wb_tick, sc, sc->wb_stat_ch); 1835 1836 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1837 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1838 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1839 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1840 1841 /* 1842 * Free data in the RX lists. 1843 */ 1844 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1845 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1846 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1847 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1848 } 1849 } 1850 bzero((char *)&sc->wb_ldata->wb_rx_list, 1851 sizeof(sc->wb_ldata->wb_rx_list)); 1852 1853 /* 1854 * Free the TX list buffers. 1855 */ 1856 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1857 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1858 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1859 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1860 } 1861 } 1862 1863 bzero((char *)&sc->wb_ldata->wb_tx_list, 1864 sizeof(sc->wb_ldata->wb_tx_list)); 1865 1866 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1867 WB_UNLOCK(sc); 1868 1869 return; 1870} 1871 1872/* 1873 * Stop all chip I/O so that the kernel's probe routines don't 1874 * get confused by errant DMAs when rebooting. 1875 */ 1876static void 1877wb_shutdown(dev) 1878 device_t dev; 1879{ 1880 struct wb_softc *sc; 1881 1882 sc = device_get_softc(dev); 1883 wb_stop(sc); 1884 1885 return; 1886} 1887