if_wb.c revision 126847
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 126847 2004-03-11 14:04:59Z mux $"); 35 36/* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus_memio.h> 108#include <machine/bus_pio.h> 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117#include <dev/mii/mii.h> 118#include <dev/mii/miivar.h> 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <pci/if_wbreg.h> 126 127MODULE_DEPEND(wb, pci, 1, 1, 1); 128MODULE_DEPEND(wb, ether, 1, 1, 1); 129MODULE_DEPEND(wb, miibus, 1, 1, 1); 130 131/* 132 * Various supported device vendors/types and their names. 133 */ 134static struct wb_type wb_devs[] = { 135 { WB_VENDORID, WB_DEVICEID_840F, 136 "Winbond W89C840F 10/100BaseTX" }, 137 { CP_VENDORID, CP_DEVICEID_RL100, 138 "Compex RL100-ATX 10/100baseTX" }, 139 { 0, 0, NULL } 140}; 141 142static int wb_probe (device_t); 143static int wb_attach (device_t); 144static int wb_detach (device_t); 145 146static void wb_bfree (void *addr, void *args); 147static int wb_newbuf (struct wb_softc *, 148 struct wb_chain_onefrag *, 149 struct mbuf *); 150static int wb_encap (struct wb_softc *, struct wb_chain *, 151 struct mbuf *); 152 153static void wb_rxeof (struct wb_softc *); 154static void wb_rxeoc (struct wb_softc *); 155static void wb_txeof (struct wb_softc *); 156static void wb_txeoc (struct wb_softc *); 157static void wb_intr (void *); 158static void wb_tick (void *); 159static void wb_start (struct ifnet *); 160static int wb_ioctl (struct ifnet *, u_long, caddr_t); 161static void wb_init (void *); 162static void wb_stop (struct wb_softc *); 163static void wb_watchdog (struct ifnet *); 164static void wb_shutdown (device_t); 165static int wb_ifmedia_upd (struct ifnet *); 166static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 167 168static void wb_eeprom_putbyte (struct wb_softc *, int); 169static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 170static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 171static void wb_mii_sync (struct wb_softc *); 172static void wb_mii_send (struct wb_softc *, u_int32_t, int); 173static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 174static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 175 176static void wb_setcfg (struct wb_softc *, u_int32_t); 177static uint32_t wb_mchash (const uint8_t *); 178static void wb_setmulti (struct wb_softc *); 179static void wb_reset (struct wb_softc *); 180static void wb_fixmedia (struct wb_softc *); 181static int wb_list_rx_init (struct wb_softc *); 182static int wb_list_tx_init (struct wb_softc *); 183 184static int wb_miibus_readreg (device_t, int, int); 185static int wb_miibus_writereg (device_t, int, int, int); 186static void wb_miibus_statchg (device_t); 187 188#ifdef WB_USEIOSPACE 189#define WB_RES SYS_RES_IOPORT 190#define WB_RID WB_PCI_LOIO 191#else 192#define WB_RES SYS_RES_MEMORY 193#define WB_RID WB_PCI_LOMEM 194#endif 195 196static device_method_t wb_methods[] = { 197 /* Device interface */ 198 DEVMETHOD(device_probe, wb_probe), 199 DEVMETHOD(device_attach, wb_attach), 200 DEVMETHOD(device_detach, wb_detach), 201 DEVMETHOD(device_shutdown, wb_shutdown), 202 203 /* bus interface, for miibus */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 209 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 210 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 211 { 0, 0 } 212}; 213 214static driver_t wb_driver = { 215 "wb", 216 wb_methods, 217 sizeof(struct wb_softc) 218}; 219 220static devclass_t wb_devclass; 221 222DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 223DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 224 225#define WB_SETBIT(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) | (x)) 228 229#define WB_CLRBIT(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) & ~(x)) 232 233#define SIO_SET(x) \ 234 CSR_WRITE_4(sc, WB_SIO, \ 235 CSR_READ_4(sc, WB_SIO) | (x)) 236 237#define SIO_CLR(x) \ 238 CSR_WRITE_4(sc, WB_SIO, \ 239 CSR_READ_4(sc, WB_SIO) & ~(x)) 240 241/* 242 * Send a read command and address to the EEPROM, check for ACK. 243 */ 244static void 245wb_eeprom_putbyte(sc, addr) 246 struct wb_softc *sc; 247 int addr; 248{ 249 register int d, i; 250 251 d = addr | WB_EECMD_READ; 252 253 /* 254 * Feed in each bit and stobe the clock. 255 */ 256 for (i = 0x400; i; i >>= 1) { 257 if (d & i) { 258 SIO_SET(WB_SIO_EE_DATAIN); 259 } else { 260 SIO_CLR(WB_SIO_EE_DATAIN); 261 } 262 DELAY(100); 263 SIO_SET(WB_SIO_EE_CLK); 264 DELAY(150); 265 SIO_CLR(WB_SIO_EE_CLK); 266 DELAY(100); 267 } 268 269 return; 270} 271 272/* 273 * Read a word of data stored in the EEPROM at address 'addr.' 274 */ 275static void 276wb_eeprom_getword(sc, addr, dest) 277 struct wb_softc *sc; 278 int addr; 279 u_int16_t *dest; 280{ 281 register int i; 282 u_int16_t word = 0; 283 284 /* Enter EEPROM access mode. */ 285 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 286 287 /* 288 * Send address of word we want to read. 289 */ 290 wb_eeprom_putbyte(sc, addr); 291 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Start reading bits from EEPROM. 296 */ 297 for (i = 0x8000; i; i >>= 1) { 298 SIO_SET(WB_SIO_EE_CLK); 299 DELAY(100); 300 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 301 word |= i; 302 SIO_CLR(WB_SIO_EE_CLK); 303 DELAY(100); 304 } 305 306 /* Turn off EEPROM access mode. */ 307 CSR_WRITE_4(sc, WB_SIO, 0); 308 309 *dest = word; 310 311 return; 312} 313 314/* 315 * Read a sequence of words from the EEPROM. 316 */ 317static void 318wb_read_eeprom(sc, dest, off, cnt, swap) 319 struct wb_softc *sc; 320 caddr_t dest; 321 int off; 322 int cnt; 323 int swap; 324{ 325 int i; 326 u_int16_t word = 0, *ptr; 327 328 for (i = 0; i < cnt; i++) { 329 wb_eeprom_getword(sc, off + i, &word); 330 ptr = (u_int16_t *)(dest + (i * 2)); 331 if (swap) 332 *ptr = ntohs(word); 333 else 334 *ptr = word; 335 } 336 337 return; 338} 339 340/* 341 * Sync the PHYs by setting data bit and strobing the clock 32 times. 342 */ 343static void 344wb_mii_sync(sc) 345 struct wb_softc *sc; 346{ 347 register int i; 348 349 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 350 351 for (i = 0; i < 32; i++) { 352 SIO_SET(WB_SIO_MII_CLK); 353 DELAY(1); 354 SIO_CLR(WB_SIO_MII_CLK); 355 DELAY(1); 356 } 357 358 return; 359} 360 361/* 362 * Clock a series of bits through the MII. 363 */ 364static void 365wb_mii_send(sc, bits, cnt) 366 struct wb_softc *sc; 367 u_int32_t bits; 368 int cnt; 369{ 370 int i; 371 372 SIO_CLR(WB_SIO_MII_CLK); 373 374 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 375 if (bits & i) { 376 SIO_SET(WB_SIO_MII_DATAIN); 377 } else { 378 SIO_CLR(WB_SIO_MII_DATAIN); 379 } 380 DELAY(1); 381 SIO_CLR(WB_SIO_MII_CLK); 382 DELAY(1); 383 SIO_SET(WB_SIO_MII_CLK); 384 } 385} 386 387/* 388 * Read an PHY register through the MII. 389 */ 390static int 391wb_mii_readreg(sc, frame) 392 struct wb_softc *sc; 393 struct wb_mii_frame *frame; 394 395{ 396 int i, ack; 397 398 WB_LOCK(sc); 399 400 /* 401 * Set up frame for RX. 402 */ 403 frame->mii_stdelim = WB_MII_STARTDELIM; 404 frame->mii_opcode = WB_MII_READOP; 405 frame->mii_turnaround = 0; 406 frame->mii_data = 0; 407 408 CSR_WRITE_4(sc, WB_SIO, 0); 409 410 /* 411 * Turn on data xmit. 412 */ 413 SIO_SET(WB_SIO_MII_DIR); 414 415 wb_mii_sync(sc); 416 417 /* 418 * Send command/address info. 419 */ 420 wb_mii_send(sc, frame->mii_stdelim, 2); 421 wb_mii_send(sc, frame->mii_opcode, 2); 422 wb_mii_send(sc, frame->mii_phyaddr, 5); 423 wb_mii_send(sc, frame->mii_regaddr, 5); 424 425 /* Idle bit */ 426 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 427 DELAY(1); 428 SIO_SET(WB_SIO_MII_CLK); 429 DELAY(1); 430 431 /* Turn off xmit. */ 432 SIO_CLR(WB_SIO_MII_DIR); 433 /* Check for ack */ 434 SIO_CLR(WB_SIO_MII_CLK); 435 DELAY(1); 436 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 437 SIO_SET(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_CLR(WB_SIO_MII_CLK); 440 DELAY(1); 441 SIO_SET(WB_SIO_MII_CLK); 442 DELAY(1); 443 444 /* 445 * Now try reading data bits. If the ack failed, we still 446 * need to clock through 16 cycles to keep the PHY(s) in sync. 447 */ 448 if (ack) { 449 for(i = 0; i < 16; i++) { 450 SIO_CLR(WB_SIO_MII_CLK); 451 DELAY(1); 452 SIO_SET(WB_SIO_MII_CLK); 453 DELAY(1); 454 } 455 goto fail; 456 } 457 458 for (i = 0x8000; i; i >>= 1) { 459 SIO_CLR(WB_SIO_MII_CLK); 460 DELAY(1); 461 if (!ack) { 462 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 463 frame->mii_data |= i; 464 DELAY(1); 465 } 466 SIO_SET(WB_SIO_MII_CLK); 467 DELAY(1); 468 } 469 470fail: 471 472 SIO_CLR(WB_SIO_MII_CLK); 473 DELAY(1); 474 SIO_SET(WB_SIO_MII_CLK); 475 DELAY(1); 476 477 WB_UNLOCK(sc); 478 479 if (ack) 480 return(1); 481 return(0); 482} 483 484/* 485 * Write to a PHY register through the MII. 486 */ 487static int 488wb_mii_writereg(sc, frame) 489 struct wb_softc *sc; 490 struct wb_mii_frame *frame; 491 492{ 493 WB_LOCK(sc); 494 495 /* 496 * Set up frame for TX. 497 */ 498 499 frame->mii_stdelim = WB_MII_STARTDELIM; 500 frame->mii_opcode = WB_MII_WRITEOP; 501 frame->mii_turnaround = WB_MII_TURNAROUND; 502 503 /* 504 * Turn on data output. 505 */ 506 SIO_SET(WB_SIO_MII_DIR); 507 508 wb_mii_sync(sc); 509 510 wb_mii_send(sc, frame->mii_stdelim, 2); 511 wb_mii_send(sc, frame->mii_opcode, 2); 512 wb_mii_send(sc, frame->mii_phyaddr, 5); 513 wb_mii_send(sc, frame->mii_regaddr, 5); 514 wb_mii_send(sc, frame->mii_turnaround, 2); 515 wb_mii_send(sc, frame->mii_data, 16); 516 517 /* Idle bit. */ 518 SIO_SET(WB_SIO_MII_CLK); 519 DELAY(1); 520 SIO_CLR(WB_SIO_MII_CLK); 521 DELAY(1); 522 523 /* 524 * Turn off xmit. 525 */ 526 SIO_CLR(WB_SIO_MII_DIR); 527 528 WB_UNLOCK(sc); 529 530 return(0); 531} 532 533static int 534wb_miibus_readreg(dev, phy, reg) 535 device_t dev; 536 int phy, reg; 537{ 538 struct wb_softc *sc; 539 struct wb_mii_frame frame; 540 541 sc = device_get_softc(dev); 542 543 bzero((char *)&frame, sizeof(frame)); 544 545 frame.mii_phyaddr = phy; 546 frame.mii_regaddr = reg; 547 wb_mii_readreg(sc, &frame); 548 549 return(frame.mii_data); 550} 551 552static int 553wb_miibus_writereg(dev, phy, reg, data) 554 device_t dev; 555 int phy, reg, data; 556{ 557 struct wb_softc *sc; 558 struct wb_mii_frame frame; 559 560 sc = device_get_softc(dev); 561 562 bzero((char *)&frame, sizeof(frame)); 563 564 frame.mii_phyaddr = phy; 565 frame.mii_regaddr = reg; 566 frame.mii_data = data; 567 568 wb_mii_writereg(sc, &frame); 569 570 return(0); 571} 572 573static void 574wb_miibus_statchg(dev) 575 device_t dev; 576{ 577 struct wb_softc *sc; 578 struct mii_data *mii; 579 580 sc = device_get_softc(dev); 581 WB_LOCK(sc); 582 mii = device_get_softc(sc->wb_miibus); 583 wb_setcfg(sc, mii->mii_media_active); 584 WB_UNLOCK(sc); 585 586 return; 587} 588 589static u_int32_t 590wb_mchash(addr) 591 const uint8_t *addr; 592{ 593 uint32_t crc, carry; 594 int idx, bit; 595 uint8_t data; 596 597 /* Compute CRC for the address value. */ 598 crc = 0xFFFFFFFF; /* initial value */ 599 600 for (idx = 0; idx < 6; idx++) { 601 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 602 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 603 crc <<= 1; 604 if (carry) 605 crc = (crc ^ 0x04c11db6) | carry; 606 } 607 } 608 609 /* 610 * return the filter bit position 611 * Note: I arrived at the following nonsense 612 * through experimentation. It's not the usual way to 613 * generate the bit position but it's the only thing 614 * I could come up with that works. 615 */ 616 return(~(crc >> 26) & 0x0000003F); 617} 618 619/* 620 * Program the 64-bit multicast hash filter. 621 */ 622static void 623wb_setmulti(sc) 624 struct wb_softc *sc; 625{ 626 struct ifnet *ifp; 627 int h = 0; 628 u_int32_t hashes[2] = { 0, 0 }; 629 struct ifmultiaddr *ifma; 630 u_int32_t rxfilt; 631 int mcnt = 0; 632 633 ifp = &sc->arpcom.ac_if; 634 635 rxfilt = CSR_READ_4(sc, WB_NETCFG); 636 637 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 638 rxfilt |= WB_NETCFG_RX_MULTI; 639 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 640 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 641 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 642 return; 643 } 644 645 /* first, zot all the existing hash bits */ 646 CSR_WRITE_4(sc, WB_MAR0, 0); 647 CSR_WRITE_4(sc, WB_MAR1, 0); 648 649 /* now program new ones */ 650 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 651 if (ifma->ifma_addr->sa_family != AF_LINK) 652 continue; 653 h = wb_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 654 if (h < 32) 655 hashes[0] |= (1 << h); 656 else 657 hashes[1] |= (1 << (h - 32)); 658 mcnt++; 659 } 660 661 if (mcnt) 662 rxfilt |= WB_NETCFG_RX_MULTI; 663 else 664 rxfilt &= ~WB_NETCFG_RX_MULTI; 665 666 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 667 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 668 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 669 670 return; 671} 672 673/* 674 * The Winbond manual states that in order to fiddle with the 675 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 676 * first have to put the transmit and/or receive logic in the idle state. 677 */ 678static void 679wb_setcfg(sc, media) 680 struct wb_softc *sc; 681 u_int32_t media; 682{ 683 int i, restart = 0; 684 685 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 686 restart = 1; 687 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 688 689 for (i = 0; i < WB_TIMEOUT; i++) { 690 DELAY(10); 691 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 692 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 693 break; 694 } 695 696 if (i == WB_TIMEOUT) 697 printf("wb%d: failed to force tx and " 698 "rx to idle state\n", sc->wb_unit); 699 } 700 701 if (IFM_SUBTYPE(media) == IFM_10_T) 702 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 703 else 704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 705 706 if ((media & IFM_GMASK) == IFM_FDX) 707 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 708 else 709 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 710 711 if (restart) 712 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 713 714 return; 715} 716 717static void 718wb_reset(sc) 719 struct wb_softc *sc; 720{ 721 register int i; 722 struct mii_data *mii; 723 724 CSR_WRITE_4(sc, WB_NETCFG, 0); 725 CSR_WRITE_4(sc, WB_BUSCTL, 0); 726 CSR_WRITE_4(sc, WB_TXADDR, 0); 727 CSR_WRITE_4(sc, WB_RXADDR, 0); 728 729 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 730 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 731 732 for (i = 0; i < WB_TIMEOUT; i++) { 733 DELAY(10); 734 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 735 break; 736 } 737 if (i == WB_TIMEOUT) 738 printf("wb%d: reset never completed!\n", sc->wb_unit); 739 740 /* Wait a little while for the chip to get its brains in order. */ 741 DELAY(1000); 742 743 if (sc->wb_miibus == NULL) 744 return; 745 746 mii = device_get_softc(sc->wb_miibus); 747 if (mii == NULL) 748 return; 749 750 if (mii->mii_instance) { 751 struct mii_softc *miisc; 752 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 753 mii_phy_reset(miisc); 754 } 755 756 return; 757} 758 759static void 760wb_fixmedia(sc) 761 struct wb_softc *sc; 762{ 763 struct mii_data *mii = NULL; 764 struct ifnet *ifp; 765 u_int32_t media; 766 767 if (sc->wb_miibus == NULL) 768 return; 769 770 mii = device_get_softc(sc->wb_miibus); 771 ifp = &sc->arpcom.ac_if; 772 773 mii_pollstat(mii); 774 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 775 media = mii->mii_media_active & ~IFM_10_T; 776 media |= IFM_100_TX; 777 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 778 media = mii->mii_media_active & ~IFM_100_TX; 779 media |= IFM_10_T; 780 } else 781 return; 782 783 ifmedia_set(&mii->mii_media, media); 784 785 return; 786} 787 788/* 789 * Probe for a Winbond chip. Check the PCI vendor and device 790 * IDs against our list and return a device name if we find a match. 791 */ 792static int 793wb_probe(dev) 794 device_t dev; 795{ 796 struct wb_type *t; 797 798 t = wb_devs; 799 800 while(t->wb_name != NULL) { 801 if ((pci_get_vendor(dev) == t->wb_vid) && 802 (pci_get_device(dev) == t->wb_did)) { 803 device_set_desc(dev, t->wb_name); 804 return(0); 805 } 806 t++; 807 } 808 809 return(ENXIO); 810} 811 812/* 813 * Attach the interface. Allocate softc structures, do ifmedia 814 * setup and ethernet/BPF attach. 815 */ 816static int 817wb_attach(dev) 818 device_t dev; 819{ 820 u_char eaddr[ETHER_ADDR_LEN]; 821 struct wb_softc *sc; 822 struct ifnet *ifp; 823 int unit, error = 0, rid; 824 825 sc = device_get_softc(dev); 826 unit = device_get_unit(dev); 827 828 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 829 MTX_DEF | MTX_RECURSE); 830#ifndef BURN_BRIDGES 831 /* 832 * Handle power management nonsense. 833 */ 834 835 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 836 u_int32_t iobase, membase, irq; 837 838 /* Save important PCI config data. */ 839 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 840 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 841 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 842 843 /* Reset the power state. */ 844 printf("wb%d: chip is in D%d power mode " 845 "-- setting to D0\n", unit, 846 pci_get_powerstate(dev)); 847 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 848 849 /* Restore PCI config data. */ 850 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 851 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 852 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 853 } 854#endif 855 /* 856 * Map control/status registers. 857 */ 858 pci_enable_busmaster(dev); 859 860 rid = WB_RID; 861 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 862 0, ~0, 1, RF_ACTIVE); 863 864 if (sc->wb_res == NULL) { 865 printf("wb%d: couldn't map ports/memory\n", unit); 866 error = ENXIO; 867 goto fail; 868 } 869 870 sc->wb_btag = rman_get_bustag(sc->wb_res); 871 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 872 873 /* Allocate interrupt */ 874 rid = 0; 875 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 876 RF_SHAREABLE | RF_ACTIVE); 877 878 if (sc->wb_irq == NULL) { 879 printf("wb%d: couldn't map interrupt\n", unit); 880 error = ENXIO; 881 goto fail; 882 } 883 884 /* Save the cache line size. */ 885 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 886 887 /* Reset the adapter. */ 888 wb_reset(sc); 889 890 /* 891 * Get station address from the EEPROM. 892 */ 893 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 894 895 /* 896 * A Winbond chip was detected. Inform the world. 897 */ 898 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 899 900 sc->wb_unit = unit; 901 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 902 903 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 904 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 905 906 if (sc->wb_ldata == NULL) { 907 printf("wb%d: no memory for list buffers!\n", unit); 908 error = ENXIO; 909 goto fail; 910 } 911 912 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 913 914 ifp = &sc->arpcom.ac_if; 915 ifp->if_softc = sc; 916 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 917 ifp->if_mtu = ETHERMTU; 918 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 919 ifp->if_ioctl = wb_ioctl; 920 ifp->if_start = wb_start; 921 ifp->if_watchdog = wb_watchdog; 922 ifp->if_init = wb_init; 923 ifp->if_baudrate = 10000000; 924 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 925 926 /* 927 * Do MII setup. 928 */ 929 if (mii_phy_probe(dev, &sc->wb_miibus, 930 wb_ifmedia_upd, wb_ifmedia_sts)) { 931 error = ENXIO; 932 goto fail; 933 } 934 935 /* 936 * Call MI attach routine. 937 */ 938 ether_ifattach(ifp, eaddr); 939 940 /* Hook interrupt last to avoid having to lock softc */ 941 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 942 wb_intr, sc, &sc->wb_intrhand); 943 944 if (error) { 945 printf("wb%d: couldn't set up irq\n", unit); 946 ether_ifdetach(ifp); 947 goto fail; 948 } 949 950fail: 951 if (error) 952 wb_detach(dev); 953 954 return(error); 955} 956 957/* 958 * Shutdown hardware and free up resources. This can be called any 959 * time after the mutex has been initialized. It is called in both 960 * the error case in attach and the normal detach case so it needs 961 * to be careful about only freeing resources that have actually been 962 * allocated. 963 */ 964static int 965wb_detach(dev) 966 device_t dev; 967{ 968 struct wb_softc *sc; 969 struct ifnet *ifp; 970 971 sc = device_get_softc(dev); 972 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 973 WB_LOCK(sc); 974 ifp = &sc->arpcom.ac_if; 975 976 /* 977 * Delete any miibus and phy devices attached to this interface. 978 * This should only be done if attach succeeded. 979 */ 980 if (device_is_attached(dev)) { 981 wb_stop(sc); 982 ether_ifdetach(ifp); 983 } 984 if (sc->wb_miibus) 985 device_delete_child(dev, sc->wb_miibus); 986 bus_generic_detach(dev); 987 988 if (sc->wb_intrhand) 989 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 990 if (sc->wb_irq) 991 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 992 if (sc->wb_res) 993 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 994 995 if (sc->wb_ldata) { 996 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 997 M_DEVBUF); 998 } 999 1000 WB_UNLOCK(sc); 1001 mtx_destroy(&sc->wb_mtx); 1002 1003 return(0); 1004} 1005 1006/* 1007 * Initialize the transmit descriptors. 1008 */ 1009static int 1010wb_list_tx_init(sc) 1011 struct wb_softc *sc; 1012{ 1013 struct wb_chain_data *cd; 1014 struct wb_list_data *ld; 1015 int i; 1016 1017 cd = &sc->wb_cdata; 1018 ld = sc->wb_ldata; 1019 1020 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1021 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1022 if (i == (WB_TX_LIST_CNT - 1)) { 1023 cd->wb_tx_chain[i].wb_nextdesc = 1024 &cd->wb_tx_chain[0]; 1025 } else { 1026 cd->wb_tx_chain[i].wb_nextdesc = 1027 &cd->wb_tx_chain[i + 1]; 1028 } 1029 } 1030 1031 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1032 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1033 1034 return(0); 1035} 1036 1037 1038/* 1039 * Initialize the RX descriptors and allocate mbufs for them. Note that 1040 * we arrange the descriptors in a closed ring, so that the last descriptor 1041 * points back to the first. 1042 */ 1043static int 1044wb_list_rx_init(sc) 1045 struct wb_softc *sc; 1046{ 1047 struct wb_chain_data *cd; 1048 struct wb_list_data *ld; 1049 int i; 1050 1051 cd = &sc->wb_cdata; 1052 ld = sc->wb_ldata; 1053 1054 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1055 cd->wb_rx_chain[i].wb_ptr = 1056 (struct wb_desc *)&ld->wb_rx_list[i]; 1057 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1058 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1059 return(ENOBUFS); 1060 if (i == (WB_RX_LIST_CNT - 1)) { 1061 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1062 ld->wb_rx_list[i].wb_next = 1063 vtophys(&ld->wb_rx_list[0]); 1064 } else { 1065 cd->wb_rx_chain[i].wb_nextdesc = 1066 &cd->wb_rx_chain[i + 1]; 1067 ld->wb_rx_list[i].wb_next = 1068 vtophys(&ld->wb_rx_list[i + 1]); 1069 } 1070 } 1071 1072 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1073 1074 return(0); 1075} 1076 1077static void 1078wb_bfree(buf, args) 1079 void *buf; 1080 void *args; 1081{ 1082 return; 1083} 1084 1085/* 1086 * Initialize an RX descriptor and attach an MBUF cluster. 1087 */ 1088static int 1089wb_newbuf(sc, c, m) 1090 struct wb_softc *sc; 1091 struct wb_chain_onefrag *c; 1092 struct mbuf *m; 1093{ 1094 struct mbuf *m_new = NULL; 1095 1096 if (m == NULL) { 1097 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1098 if (m_new == NULL) 1099 return(ENOBUFS); 1100 m_new->m_data = c->wb_buf; 1101 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1102 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1103 EXT_NET_DRV); 1104 } else { 1105 m_new = m; 1106 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1107 m_new->m_data = m_new->m_ext.ext_buf; 1108 } 1109 1110 m_adj(m_new, sizeof(u_int64_t)); 1111 1112 c->wb_mbuf = m_new; 1113 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1114 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1115 c->wb_ptr->wb_status = WB_RXSTAT; 1116 1117 return(0); 1118} 1119 1120/* 1121 * A frame has been uploaded: pass the resulting mbuf chain up to 1122 * the higher level protocols. 1123 */ 1124static void 1125wb_rxeof(sc) 1126 struct wb_softc *sc; 1127{ 1128 struct mbuf *m = NULL; 1129 struct ifnet *ifp; 1130 struct wb_chain_onefrag *cur_rx; 1131 int total_len = 0; 1132 u_int32_t rxstat; 1133 1134 WB_LOCK_ASSERT(sc); 1135 1136 ifp = &sc->arpcom.ac_if; 1137 1138 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1139 WB_RXSTAT_OWN)) { 1140 struct mbuf *m0 = NULL; 1141 1142 cur_rx = sc->wb_cdata.wb_rx_head; 1143 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1144 1145 m = cur_rx->wb_mbuf; 1146 1147 if ((rxstat & WB_RXSTAT_MIIERR) || 1148 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1149 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1150 !(rxstat & WB_RXSTAT_LASTFRAG) || 1151 !(rxstat & WB_RXSTAT_RXCMP)) { 1152 ifp->if_ierrors++; 1153 wb_newbuf(sc, cur_rx, m); 1154 printf("wb%x: receiver babbling: possible chip " 1155 "bug, forcing reset\n", sc->wb_unit); 1156 wb_fixmedia(sc); 1157 wb_reset(sc); 1158 wb_init(sc); 1159 return; 1160 } 1161 1162 if (rxstat & WB_RXSTAT_RXERR) { 1163 ifp->if_ierrors++; 1164 wb_newbuf(sc, cur_rx, m); 1165 break; 1166 } 1167 1168 /* No errors; receive the packet. */ 1169 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1170 1171 /* 1172 * XXX The Winbond chip includes the CRC with every 1173 * received frame, and there's no way to turn this 1174 * behavior off (at least, I can't find anything in 1175 * the manual that explains how to do it) so we have 1176 * to trim off the CRC manually. 1177 */ 1178 total_len -= ETHER_CRC_LEN; 1179 1180 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1181 NULL); 1182 wb_newbuf(sc, cur_rx, m); 1183 if (m0 == NULL) { 1184 ifp->if_ierrors++; 1185 break; 1186 } 1187 m = m0; 1188 1189 ifp->if_ipackets++; 1190 WB_UNLOCK(sc); 1191 (*ifp->if_input)(ifp, m); 1192 WB_LOCK(sc); 1193 } 1194} 1195 1196static void 1197wb_rxeoc(sc) 1198 struct wb_softc *sc; 1199{ 1200 wb_rxeof(sc); 1201 1202 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1203 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1204 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1205 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1206 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1207 1208 return; 1209} 1210 1211/* 1212 * A frame was downloaded to the chip. It's safe for us to clean up 1213 * the list buffers. 1214 */ 1215static void 1216wb_txeof(sc) 1217 struct wb_softc *sc; 1218{ 1219 struct wb_chain *cur_tx; 1220 struct ifnet *ifp; 1221 1222 ifp = &sc->arpcom.ac_if; 1223 1224 /* Clear the timeout timer. */ 1225 ifp->if_timer = 0; 1226 1227 if (sc->wb_cdata.wb_tx_head == NULL) 1228 return; 1229 1230 /* 1231 * Go through our tx list and free mbufs for those 1232 * frames that have been transmitted. 1233 */ 1234 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1235 u_int32_t txstat; 1236 1237 cur_tx = sc->wb_cdata.wb_tx_head; 1238 txstat = WB_TXSTATUS(cur_tx); 1239 1240 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1241 break; 1242 1243 if (txstat & WB_TXSTAT_TXERR) { 1244 ifp->if_oerrors++; 1245 if (txstat & WB_TXSTAT_ABORT) 1246 ifp->if_collisions++; 1247 if (txstat & WB_TXSTAT_LATECOLL) 1248 ifp->if_collisions++; 1249 } 1250 1251 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1252 1253 ifp->if_opackets++; 1254 m_freem(cur_tx->wb_mbuf); 1255 cur_tx->wb_mbuf = NULL; 1256 1257 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1258 sc->wb_cdata.wb_tx_head = NULL; 1259 sc->wb_cdata.wb_tx_tail = NULL; 1260 break; 1261 } 1262 1263 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1264 } 1265 1266 return; 1267} 1268 1269/* 1270 * TX 'end of channel' interrupt handler. 1271 */ 1272static void 1273wb_txeoc(sc) 1274 struct wb_softc *sc; 1275{ 1276 struct ifnet *ifp; 1277 1278 ifp = &sc->arpcom.ac_if; 1279 1280 ifp->if_timer = 0; 1281 1282 if (sc->wb_cdata.wb_tx_head == NULL) { 1283 ifp->if_flags &= ~IFF_OACTIVE; 1284 sc->wb_cdata.wb_tx_tail = NULL; 1285 } else { 1286 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1287 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1288 ifp->if_timer = 5; 1289 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1290 } 1291 } 1292 1293 return; 1294} 1295 1296static void 1297wb_intr(arg) 1298 void *arg; 1299{ 1300 struct wb_softc *sc; 1301 struct ifnet *ifp; 1302 u_int32_t status; 1303 1304 sc = arg; 1305 WB_LOCK(sc); 1306 ifp = &sc->arpcom.ac_if; 1307 1308 if (!(ifp->if_flags & IFF_UP)) { 1309 WB_UNLOCK(sc); 1310 return; 1311 } 1312 1313 /* Disable interrupts. */ 1314 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1315 1316 for (;;) { 1317 1318 status = CSR_READ_4(sc, WB_ISR); 1319 if (status) 1320 CSR_WRITE_4(sc, WB_ISR, status); 1321 1322 if ((status & WB_INTRS) == 0) 1323 break; 1324 1325 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1326 ifp->if_ierrors++; 1327 wb_reset(sc); 1328 if (status & WB_ISR_RX_ERR) 1329 wb_fixmedia(sc); 1330 wb_init(sc); 1331 continue; 1332 } 1333 1334 if (status & WB_ISR_RX_OK) 1335 wb_rxeof(sc); 1336 1337 if (status & WB_ISR_RX_IDLE) 1338 wb_rxeoc(sc); 1339 1340 if (status & WB_ISR_TX_OK) 1341 wb_txeof(sc); 1342 1343 if (status & WB_ISR_TX_NOBUF) 1344 wb_txeoc(sc); 1345 1346 if (status & WB_ISR_TX_IDLE) { 1347 wb_txeof(sc); 1348 if (sc->wb_cdata.wb_tx_head != NULL) { 1349 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1350 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1351 } 1352 } 1353 1354 if (status & WB_ISR_TX_UNDERRUN) { 1355 ifp->if_oerrors++; 1356 wb_txeof(sc); 1357 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1358 /* Jack up TX threshold */ 1359 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1360 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1361 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1362 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1363 } 1364 1365 if (status & WB_ISR_BUS_ERR) { 1366 wb_reset(sc); 1367 wb_init(sc); 1368 } 1369 1370 } 1371 1372 /* Re-enable interrupts. */ 1373 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1374 1375 if (ifp->if_snd.ifq_head != NULL) { 1376 wb_start(ifp); 1377 } 1378 1379 WB_UNLOCK(sc); 1380 1381 return; 1382} 1383 1384static void 1385wb_tick(xsc) 1386 void *xsc; 1387{ 1388 struct wb_softc *sc; 1389 struct mii_data *mii; 1390 1391 sc = xsc; 1392 WB_LOCK(sc); 1393 mii = device_get_softc(sc->wb_miibus); 1394 1395 mii_tick(mii); 1396 1397 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1398 1399 WB_UNLOCK(sc); 1400 1401 return; 1402} 1403 1404/* 1405 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1406 * pointers to the fragment pointers. 1407 */ 1408static int 1409wb_encap(sc, c, m_head) 1410 struct wb_softc *sc; 1411 struct wb_chain *c; 1412 struct mbuf *m_head; 1413{ 1414 int frag = 0; 1415 struct wb_desc *f = NULL; 1416 int total_len; 1417 struct mbuf *m; 1418 1419 /* 1420 * Start packing the mbufs in this chain into 1421 * the fragment pointers. Stop when we run out 1422 * of fragments or hit the end of the mbuf chain. 1423 */ 1424 m = m_head; 1425 total_len = 0; 1426 1427 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1428 if (m->m_len != 0) { 1429 if (frag == WB_MAXFRAGS) 1430 break; 1431 total_len += m->m_len; 1432 f = &c->wb_ptr->wb_frag[frag]; 1433 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1434 if (frag == 0) { 1435 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1436 f->wb_status = 0; 1437 } else 1438 f->wb_status = WB_TXSTAT_OWN; 1439 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1440 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1441 frag++; 1442 } 1443 } 1444 1445 /* 1446 * Handle special case: we used up all 16 fragments, 1447 * but we have more mbufs left in the chain. Copy the 1448 * data into an mbuf cluster. Note that we don't 1449 * bother clearing the values in the other fragment 1450 * pointers/counters; it wouldn't gain us anything, 1451 * and would waste cycles. 1452 */ 1453 if (m != NULL) { 1454 struct mbuf *m_new = NULL; 1455 1456 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1457 if (m_new == NULL) 1458 return(1); 1459 if (m_head->m_pkthdr.len > MHLEN) { 1460 MCLGET(m_new, M_DONTWAIT); 1461 if (!(m_new->m_flags & M_EXT)) { 1462 m_freem(m_new); 1463 return(1); 1464 } 1465 } 1466 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1467 mtod(m_new, caddr_t)); 1468 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1469 m_freem(m_head); 1470 m_head = m_new; 1471 f = &c->wb_ptr->wb_frag[0]; 1472 f->wb_status = 0; 1473 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1474 f->wb_ctl = total_len = m_new->m_len; 1475 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1476 frag = 1; 1477 } 1478 1479 if (total_len < WB_MIN_FRAMELEN) { 1480 f = &c->wb_ptr->wb_frag[frag]; 1481 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1482 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1483 f->wb_ctl |= WB_TXCTL_TLINK; 1484 f->wb_status = WB_TXSTAT_OWN; 1485 frag++; 1486 } 1487 1488 c->wb_mbuf = m_head; 1489 c->wb_lastdesc = frag - 1; 1490 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1491 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1492 1493 return(0); 1494} 1495 1496/* 1497 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1498 * to the mbuf data regions directly in the transmit lists. We also save a 1499 * copy of the pointers since the transmit list fragment pointers are 1500 * physical addresses. 1501 */ 1502 1503static void 1504wb_start(ifp) 1505 struct ifnet *ifp; 1506{ 1507 struct wb_softc *sc; 1508 struct mbuf *m_head = NULL; 1509 struct wb_chain *cur_tx = NULL, *start_tx; 1510 1511 sc = ifp->if_softc; 1512 WB_LOCK(sc); 1513 1514 /* 1515 * Check for an available queue slot. If there are none, 1516 * punt. 1517 */ 1518 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1519 ifp->if_flags |= IFF_OACTIVE; 1520 WB_UNLOCK(sc); 1521 return; 1522 } 1523 1524 start_tx = sc->wb_cdata.wb_tx_free; 1525 1526 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1527 IF_DEQUEUE(&ifp->if_snd, m_head); 1528 if (m_head == NULL) 1529 break; 1530 1531 /* Pick a descriptor off the free list. */ 1532 cur_tx = sc->wb_cdata.wb_tx_free; 1533 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1534 1535 /* Pack the data into the descriptor. */ 1536 wb_encap(sc, cur_tx, m_head); 1537 1538 if (cur_tx != start_tx) 1539 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1540 1541 /* 1542 * If there's a BPF listener, bounce a copy of this frame 1543 * to him. 1544 */ 1545 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1546 } 1547 1548 /* 1549 * If there are no packets queued, bail. 1550 */ 1551 if (cur_tx == NULL) { 1552 WB_UNLOCK(sc); 1553 return; 1554 } 1555 1556 /* 1557 * Place the request for the upload interrupt 1558 * in the last descriptor in the chain. This way, if 1559 * we're chaining several packets at once, we'll only 1560 * get an interupt once for the whole chain rather than 1561 * once for each packet. 1562 */ 1563 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1564 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1565 sc->wb_cdata.wb_tx_tail = cur_tx; 1566 1567 if (sc->wb_cdata.wb_tx_head == NULL) { 1568 sc->wb_cdata.wb_tx_head = start_tx; 1569 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1570 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1571 } else { 1572 /* 1573 * We need to distinguish between the case where 1574 * the own bit is clear because the chip cleared it 1575 * and where the own bit is clear because we haven't 1576 * set it yet. The magic value WB_UNSET is just some 1577 * ramdomly chosen number which doesn't have the own 1578 * bit set. When we actually transmit the frame, the 1579 * status word will have _only_ the own bit set, so 1580 * the txeoc handler will be able to tell if it needs 1581 * to initiate another transmission to flush out pending 1582 * frames. 1583 */ 1584 WB_TXOWN(start_tx) = WB_UNSENT; 1585 } 1586 1587 /* 1588 * Set a timeout in case the chip goes out to lunch. 1589 */ 1590 ifp->if_timer = 5; 1591 WB_UNLOCK(sc); 1592 1593 return; 1594} 1595 1596static void 1597wb_init(xsc) 1598 void *xsc; 1599{ 1600 struct wb_softc *sc = xsc; 1601 struct ifnet *ifp = &sc->arpcom.ac_if; 1602 int i; 1603 struct mii_data *mii; 1604 1605 WB_LOCK(sc); 1606 mii = device_get_softc(sc->wb_miibus); 1607 1608 /* 1609 * Cancel pending I/O and free all RX/TX buffers. 1610 */ 1611 wb_stop(sc); 1612 wb_reset(sc); 1613 1614 sc->wb_txthresh = WB_TXTHRESH_INIT; 1615 1616 /* 1617 * Set cache alignment and burst length. 1618 */ 1619#ifdef foo 1620 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1621 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1622 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1623#endif 1624 1625 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1626 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1627 switch(sc->wb_cachesize) { 1628 case 32: 1629 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1630 break; 1631 case 16: 1632 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1633 break; 1634 case 8: 1635 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1636 break; 1637 case 0: 1638 default: 1639 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1640 break; 1641 } 1642 1643 /* This doesn't tend to work too well at 100Mbps. */ 1644 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1645 1646 /* Init our MAC address */ 1647 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1648 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1649 } 1650 1651 /* Init circular RX list. */ 1652 if (wb_list_rx_init(sc) == ENOBUFS) { 1653 printf("wb%d: initialization failed: no " 1654 "memory for rx buffers\n", sc->wb_unit); 1655 wb_stop(sc); 1656 WB_UNLOCK(sc); 1657 return; 1658 } 1659 1660 /* Init TX descriptors. */ 1661 wb_list_tx_init(sc); 1662 1663 /* If we want promiscuous mode, set the allframes bit. */ 1664 if (ifp->if_flags & IFF_PROMISC) { 1665 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1666 } else { 1667 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1668 } 1669 1670 /* 1671 * Set capture broadcast bit to capture broadcast frames. 1672 */ 1673 if (ifp->if_flags & IFF_BROADCAST) { 1674 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1675 } else { 1676 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1677 } 1678 1679 /* 1680 * Program the multicast filter, if necessary. 1681 */ 1682 wb_setmulti(sc); 1683 1684 /* 1685 * Load the address of the RX list. 1686 */ 1687 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1688 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1689 1690 /* 1691 * Enable interrupts. 1692 */ 1693 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1694 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1695 1696 /* Enable receiver and transmitter. */ 1697 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1698 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1699 1700 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1701 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1702 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1703 1704 mii_mediachg(mii); 1705 1706 ifp->if_flags |= IFF_RUNNING; 1707 ifp->if_flags &= ~IFF_OACTIVE; 1708 1709 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1710 WB_UNLOCK(sc); 1711 1712 return; 1713} 1714 1715/* 1716 * Set media options. 1717 */ 1718static int 1719wb_ifmedia_upd(ifp) 1720 struct ifnet *ifp; 1721{ 1722 struct wb_softc *sc; 1723 1724 sc = ifp->if_softc; 1725 1726 if (ifp->if_flags & IFF_UP) 1727 wb_init(sc); 1728 1729 return(0); 1730} 1731 1732/* 1733 * Report current media status. 1734 */ 1735static void 1736wb_ifmedia_sts(ifp, ifmr) 1737 struct ifnet *ifp; 1738 struct ifmediareq *ifmr; 1739{ 1740 struct wb_softc *sc; 1741 struct mii_data *mii; 1742 1743 sc = ifp->if_softc; 1744 1745 mii = device_get_softc(sc->wb_miibus); 1746 1747 mii_pollstat(mii); 1748 ifmr->ifm_active = mii->mii_media_active; 1749 ifmr->ifm_status = mii->mii_media_status; 1750 1751 return; 1752} 1753 1754static int 1755wb_ioctl(ifp, command, data) 1756 struct ifnet *ifp; 1757 u_long command; 1758 caddr_t data; 1759{ 1760 struct wb_softc *sc = ifp->if_softc; 1761 struct mii_data *mii; 1762 struct ifreq *ifr = (struct ifreq *) data; 1763 int error = 0; 1764 1765 WB_LOCK(sc); 1766 1767 switch(command) { 1768 case SIOCSIFFLAGS: 1769 if (ifp->if_flags & IFF_UP) { 1770 wb_init(sc); 1771 } else { 1772 if (ifp->if_flags & IFF_RUNNING) 1773 wb_stop(sc); 1774 } 1775 error = 0; 1776 break; 1777 case SIOCADDMULTI: 1778 case SIOCDELMULTI: 1779 wb_setmulti(sc); 1780 error = 0; 1781 break; 1782 case SIOCGIFMEDIA: 1783 case SIOCSIFMEDIA: 1784 mii = device_get_softc(sc->wb_miibus); 1785 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1786 break; 1787 default: 1788 error = ether_ioctl(ifp, command, data); 1789 break; 1790 } 1791 1792 WB_UNLOCK(sc); 1793 1794 return(error); 1795} 1796 1797static void 1798wb_watchdog(ifp) 1799 struct ifnet *ifp; 1800{ 1801 struct wb_softc *sc; 1802 1803 sc = ifp->if_softc; 1804 1805 WB_LOCK(sc); 1806 ifp->if_oerrors++; 1807 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1808#ifdef foo 1809 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1810 printf("wb%d: no carrier - transceiver cable problem?\n", 1811 sc->wb_unit); 1812#endif 1813 wb_stop(sc); 1814 wb_reset(sc); 1815 wb_init(sc); 1816 1817 if (ifp->if_snd.ifq_head != NULL) 1818 wb_start(ifp); 1819 WB_UNLOCK(sc); 1820 1821 return; 1822} 1823 1824/* 1825 * Stop the adapter and free any mbufs allocated to the 1826 * RX and TX lists. 1827 */ 1828static void 1829wb_stop(sc) 1830 struct wb_softc *sc; 1831{ 1832 register int i; 1833 struct ifnet *ifp; 1834 1835 WB_LOCK(sc); 1836 ifp = &sc->arpcom.ac_if; 1837 ifp->if_timer = 0; 1838 1839 untimeout(wb_tick, sc, sc->wb_stat_ch); 1840 1841 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1842 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1843 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1844 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1845 1846 /* 1847 * Free data in the RX lists. 1848 */ 1849 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1850 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1851 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1852 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1853 } 1854 } 1855 bzero((char *)&sc->wb_ldata->wb_rx_list, 1856 sizeof(sc->wb_ldata->wb_rx_list)); 1857 1858 /* 1859 * Free the TX list buffers. 1860 */ 1861 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1862 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1863 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1864 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1865 } 1866 } 1867 1868 bzero((char *)&sc->wb_ldata->wb_tx_list, 1869 sizeof(sc->wb_ldata->wb_tx_list)); 1870 1871 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1872 WB_UNLOCK(sc); 1873 1874 return; 1875} 1876 1877/* 1878 * Stop all chip I/O so that the kernel's probe routines don't 1879 * get confused by errant DMAs when rebooting. 1880 */ 1881static void 1882wb_shutdown(dev) 1883 device_t dev; 1884{ 1885 struct wb_softc *sc; 1886 1887 sc = device_get_softc(dev); 1888 wb_stop(sc); 1889 1890 return; 1891} 1892