if_wb.c revision 121816
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Winbond fast ethernet PCI NIC driver 35 * 36 * Supports various cheap network adapters based on the Winbond W89C840F 37 * fast ethernet controller chip. This includes adapters manufactured by 38 * Winbond itself and some made by Linksys. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Winbond W89C840F chip is a bus master; in some ways it resembles 47 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 48 * one major difference which is that while the registers do many of 49 * the same things as a tulip adapter, the offsets are different: where 50 * tulip registers are typically spaced 8 bytes apart, the Winbond 51 * registers are spaced 4 bytes apart. The receiver filter is also 52 * programmed differently. 53 * 54 * Like the tulip, the Winbond chip uses small descriptors containing 55 * a status word, a control word and 32-bit areas that can either be used 56 * to point to two external data blocks, or to point to a single block 57 * and another descriptor in a linked list. Descriptors can be grouped 58 * together in blocks to form fixed length rings or can be chained 59 * together in linked lists. A single packet may be spread out over 60 * several descriptors if necessary. 61 * 62 * For the receive ring, this driver uses a linked list of descriptors, 63 * each pointing to a single mbuf cluster buffer, which us large enough 64 * to hold an entire packet. The link list is looped back to created a 65 * closed ring. 66 * 67 * For transmission, the driver creates a linked list of 'super descriptors' 68 * which each contain several individual descriptors linked toghether. 69 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 70 * abuse as fragment pointers. This allows us to use a buffer managment 71 * scheme very similar to that used in the ThunderLAN and Etherlink XL 72 * drivers. 73 * 74 * Autonegotiation is performed using the external PHY via the MII bus. 75 * The sample boards I have all use a Davicom PHY. 76 * 77 * Note: the author of the Linux driver for the Winbond chip alludes 78 * to some sort of flaw in the chip's design that seems to mandate some 79 * drastic workaround which signigicantly impairs transmit performance. 80 * I have no idea what he's on about: transmit performance with all 81 * three of my test boards seems fine. 82 */ 83 84#include <sys/cdefs.h> 85__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 121816 2003-10-31 18:32:15Z brooks $"); 86 87#include "opt_bdg.h" 88 89#include <sys/param.h> 90#include <sys/systm.h> 91#include <sys/sockio.h> 92#include <sys/mbuf.h> 93#include <sys/malloc.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103 104#include <net/bpf.h> 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/bus_memio.h> 109#include <machine/bus_pio.h> 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#include <dev/pci/pcireg.h> 116#include <dev/pci/pcivar.h> 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121/* "controller miibus0" required. See GENERIC if you get errors here. */ 122#include "miibus_if.h" 123 124#define WB_USEIOSPACE 125 126#include <pci/if_wbreg.h> 127 128MODULE_DEPEND(wb, pci, 1, 1, 1); 129MODULE_DEPEND(wb, ether, 1, 1, 1); 130MODULE_DEPEND(wb, miibus, 1, 1, 1); 131 132/* 133 * Various supported device vendors/types and their names. 134 */ 135static struct wb_type wb_devs[] = { 136 { WB_VENDORID, WB_DEVICEID_840F, 137 "Winbond W89C840F 10/100BaseTX" }, 138 { CP_VENDORID, CP_DEVICEID_RL100, 139 "Compex RL100-ATX 10/100baseTX" }, 140 { 0, 0, NULL } 141}; 142 143static int wb_probe (device_t); 144static int wb_attach (device_t); 145static int wb_detach (device_t); 146 147static void wb_bfree (void *addr, void *args); 148static int wb_newbuf (struct wb_softc *, 149 struct wb_chain_onefrag *, 150 struct mbuf *); 151static int wb_encap (struct wb_softc *, struct wb_chain *, 152 struct mbuf *); 153 154static void wb_rxeof (struct wb_softc *); 155static void wb_rxeoc (struct wb_softc *); 156static void wb_txeof (struct wb_softc *); 157static void wb_txeoc (struct wb_softc *); 158static void wb_intr (void *); 159static void wb_tick (void *); 160static void wb_start (struct ifnet *); 161static int wb_ioctl (struct ifnet *, u_long, caddr_t); 162static void wb_init (void *); 163static void wb_stop (struct wb_softc *); 164static void wb_watchdog (struct ifnet *); 165static void wb_shutdown (device_t); 166static int wb_ifmedia_upd (struct ifnet *); 167static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 168 169static void wb_eeprom_putbyte (struct wb_softc *, int); 170static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 171static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 172static void wb_mii_sync (struct wb_softc *); 173static void wb_mii_send (struct wb_softc *, u_int32_t, int); 174static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 175static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 176 177static void wb_setcfg (struct wb_softc *, u_int32_t); 178static u_int8_t wb_calchash (caddr_t); 179static void wb_setmulti (struct wb_softc *); 180static void wb_reset (struct wb_softc *); 181static void wb_fixmedia (struct wb_softc *); 182static int wb_list_rx_init (struct wb_softc *); 183static int wb_list_tx_init (struct wb_softc *); 184 185static int wb_miibus_readreg (device_t, int, int); 186static int wb_miibus_writereg (device_t, int, int, int); 187static void wb_miibus_statchg (device_t); 188 189#ifdef WB_USEIOSPACE 190#define WB_RES SYS_RES_IOPORT 191#define WB_RID WB_PCI_LOIO 192#else 193#define WB_RES SYS_RES_MEMORY 194#define WB_RID WB_PCI_LOMEM 195#endif 196 197static device_method_t wb_methods[] = { 198 /* Device interface */ 199 DEVMETHOD(device_probe, wb_probe), 200 DEVMETHOD(device_attach, wb_attach), 201 DEVMETHOD(device_detach, wb_detach), 202 DEVMETHOD(device_shutdown, wb_shutdown), 203 204 /* bus interface, for miibus */ 205 DEVMETHOD(bus_print_child, bus_generic_print_child), 206 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 207 208 /* MII interface */ 209 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 210 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 211 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 212 { 0, 0 } 213}; 214 215static driver_t wb_driver = { 216 "wb", 217 wb_methods, 218 sizeof(struct wb_softc) 219}; 220 221static devclass_t wb_devclass; 222 223DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 224DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 225 226#define WB_SETBIT(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) | (x)) 229 230#define WB_CLRBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) & ~(x)) 233 234#define SIO_SET(x) \ 235 CSR_WRITE_4(sc, WB_SIO, \ 236 CSR_READ_4(sc, WB_SIO) | (x)) 237 238#define SIO_CLR(x) \ 239 CSR_WRITE_4(sc, WB_SIO, \ 240 CSR_READ_4(sc, WB_SIO) & ~(x)) 241 242/* 243 * Send a read command and address to the EEPROM, check for ACK. 244 */ 245static void 246wb_eeprom_putbyte(sc, addr) 247 struct wb_softc *sc; 248 int addr; 249{ 250 register int d, i; 251 252 d = addr | WB_EECMD_READ; 253 254 /* 255 * Feed in each bit and stobe the clock. 256 */ 257 for (i = 0x400; i; i >>= 1) { 258 if (d & i) { 259 SIO_SET(WB_SIO_EE_DATAIN); 260 } else { 261 SIO_CLR(WB_SIO_EE_DATAIN); 262 } 263 DELAY(100); 264 SIO_SET(WB_SIO_EE_CLK); 265 DELAY(150); 266 SIO_CLR(WB_SIO_EE_CLK); 267 DELAY(100); 268 } 269 270 return; 271} 272 273/* 274 * Read a word of data stored in the EEPROM at address 'addr.' 275 */ 276static void 277wb_eeprom_getword(sc, addr, dest) 278 struct wb_softc *sc; 279 int addr; 280 u_int16_t *dest; 281{ 282 register int i; 283 u_int16_t word = 0; 284 285 /* Enter EEPROM access mode. */ 286 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 287 288 /* 289 * Send address of word we want to read. 290 */ 291 wb_eeprom_putbyte(sc, addr); 292 293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 294 295 /* 296 * Start reading bits from EEPROM. 297 */ 298 for (i = 0x8000; i; i >>= 1) { 299 SIO_SET(WB_SIO_EE_CLK); 300 DELAY(100); 301 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 302 word |= i; 303 SIO_CLR(WB_SIO_EE_CLK); 304 DELAY(100); 305 } 306 307 /* Turn off EEPROM access mode. */ 308 CSR_WRITE_4(sc, WB_SIO, 0); 309 310 *dest = word; 311 312 return; 313} 314 315/* 316 * Read a sequence of words from the EEPROM. 317 */ 318static void 319wb_read_eeprom(sc, dest, off, cnt, swap) 320 struct wb_softc *sc; 321 caddr_t dest; 322 int off; 323 int cnt; 324 int swap; 325{ 326 int i; 327 u_int16_t word = 0, *ptr; 328 329 for (i = 0; i < cnt; i++) { 330 wb_eeprom_getword(sc, off + i, &word); 331 ptr = (u_int16_t *)(dest + (i * 2)); 332 if (swap) 333 *ptr = ntohs(word); 334 else 335 *ptr = word; 336 } 337 338 return; 339} 340 341/* 342 * Sync the PHYs by setting data bit and strobing the clock 32 times. 343 */ 344static void 345wb_mii_sync(sc) 346 struct wb_softc *sc; 347{ 348 register int i; 349 350 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 351 352 for (i = 0; i < 32; i++) { 353 SIO_SET(WB_SIO_MII_CLK); 354 DELAY(1); 355 SIO_CLR(WB_SIO_MII_CLK); 356 DELAY(1); 357 } 358 359 return; 360} 361 362/* 363 * Clock a series of bits through the MII. 364 */ 365static void 366wb_mii_send(sc, bits, cnt) 367 struct wb_softc *sc; 368 u_int32_t bits; 369 int cnt; 370{ 371 int i; 372 373 SIO_CLR(WB_SIO_MII_CLK); 374 375 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 376 if (bits & i) { 377 SIO_SET(WB_SIO_MII_DATAIN); 378 } else { 379 SIO_CLR(WB_SIO_MII_DATAIN); 380 } 381 DELAY(1); 382 SIO_CLR(WB_SIO_MII_CLK); 383 DELAY(1); 384 SIO_SET(WB_SIO_MII_CLK); 385 } 386} 387 388/* 389 * Read an PHY register through the MII. 390 */ 391static int 392wb_mii_readreg(sc, frame) 393 struct wb_softc *sc; 394 struct wb_mii_frame *frame; 395 396{ 397 int i, ack; 398 399 WB_LOCK(sc); 400 401 /* 402 * Set up frame for RX. 403 */ 404 frame->mii_stdelim = WB_MII_STARTDELIM; 405 frame->mii_opcode = WB_MII_READOP; 406 frame->mii_turnaround = 0; 407 frame->mii_data = 0; 408 409 CSR_WRITE_4(sc, WB_SIO, 0); 410 411 /* 412 * Turn on data xmit. 413 */ 414 SIO_SET(WB_SIO_MII_DIR); 415 416 wb_mii_sync(sc); 417 418 /* 419 * Send command/address info. 420 */ 421 wb_mii_send(sc, frame->mii_stdelim, 2); 422 wb_mii_send(sc, frame->mii_opcode, 2); 423 wb_mii_send(sc, frame->mii_phyaddr, 5); 424 wb_mii_send(sc, frame->mii_regaddr, 5); 425 426 /* Idle bit */ 427 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 428 DELAY(1); 429 SIO_SET(WB_SIO_MII_CLK); 430 DELAY(1); 431 432 /* Turn off xmit. */ 433 SIO_CLR(WB_SIO_MII_DIR); 434 /* Check for ack */ 435 SIO_CLR(WB_SIO_MII_CLK); 436 DELAY(1); 437 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 438 SIO_SET(WB_SIO_MII_CLK); 439 DELAY(1); 440 SIO_CLR(WB_SIO_MII_CLK); 441 DELAY(1); 442 SIO_SET(WB_SIO_MII_CLK); 443 DELAY(1); 444 445 /* 446 * Now try reading data bits. If the ack failed, we still 447 * need to clock through 16 cycles to keep the PHY(s) in sync. 448 */ 449 if (ack) { 450 for(i = 0; i < 16; i++) { 451 SIO_CLR(WB_SIO_MII_CLK); 452 DELAY(1); 453 SIO_SET(WB_SIO_MII_CLK); 454 DELAY(1); 455 } 456 goto fail; 457 } 458 459 for (i = 0x8000; i; i >>= 1) { 460 SIO_CLR(WB_SIO_MII_CLK); 461 DELAY(1); 462 if (!ack) { 463 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 464 frame->mii_data |= i; 465 DELAY(1); 466 } 467 SIO_SET(WB_SIO_MII_CLK); 468 DELAY(1); 469 } 470 471fail: 472 473 SIO_CLR(WB_SIO_MII_CLK); 474 DELAY(1); 475 SIO_SET(WB_SIO_MII_CLK); 476 DELAY(1); 477 478 WB_UNLOCK(sc); 479 480 if (ack) 481 return(1); 482 return(0); 483} 484 485/* 486 * Write to a PHY register through the MII. 487 */ 488static int 489wb_mii_writereg(sc, frame) 490 struct wb_softc *sc; 491 struct wb_mii_frame *frame; 492 493{ 494 WB_LOCK(sc); 495 496 /* 497 * Set up frame for TX. 498 */ 499 500 frame->mii_stdelim = WB_MII_STARTDELIM; 501 frame->mii_opcode = WB_MII_WRITEOP; 502 frame->mii_turnaround = WB_MII_TURNAROUND; 503 504 /* 505 * Turn on data output. 506 */ 507 SIO_SET(WB_SIO_MII_DIR); 508 509 wb_mii_sync(sc); 510 511 wb_mii_send(sc, frame->mii_stdelim, 2); 512 wb_mii_send(sc, frame->mii_opcode, 2); 513 wb_mii_send(sc, frame->mii_phyaddr, 5); 514 wb_mii_send(sc, frame->mii_regaddr, 5); 515 wb_mii_send(sc, frame->mii_turnaround, 2); 516 wb_mii_send(sc, frame->mii_data, 16); 517 518 /* Idle bit. */ 519 SIO_SET(WB_SIO_MII_CLK); 520 DELAY(1); 521 SIO_CLR(WB_SIO_MII_CLK); 522 DELAY(1); 523 524 /* 525 * Turn off xmit. 526 */ 527 SIO_CLR(WB_SIO_MII_DIR); 528 529 WB_UNLOCK(sc); 530 531 return(0); 532} 533 534static int 535wb_miibus_readreg(dev, phy, reg) 536 device_t dev; 537 int phy, reg; 538{ 539 struct wb_softc *sc; 540 struct wb_mii_frame frame; 541 542 sc = device_get_softc(dev); 543 544 bzero((char *)&frame, sizeof(frame)); 545 546 frame.mii_phyaddr = phy; 547 frame.mii_regaddr = reg; 548 wb_mii_readreg(sc, &frame); 549 550 return(frame.mii_data); 551} 552 553static int 554wb_miibus_writereg(dev, phy, reg, data) 555 device_t dev; 556 int phy, reg, data; 557{ 558 struct wb_softc *sc; 559 struct wb_mii_frame frame; 560 561 sc = device_get_softc(dev); 562 563 bzero((char *)&frame, sizeof(frame)); 564 565 frame.mii_phyaddr = phy; 566 frame.mii_regaddr = reg; 567 frame.mii_data = data; 568 569 wb_mii_writereg(sc, &frame); 570 571 return(0); 572} 573 574static void 575wb_miibus_statchg(dev) 576 device_t dev; 577{ 578 struct wb_softc *sc; 579 struct mii_data *mii; 580 581 sc = device_get_softc(dev); 582 WB_LOCK(sc); 583 mii = device_get_softc(sc->wb_miibus); 584 wb_setcfg(sc, mii->mii_media_active); 585 WB_UNLOCK(sc); 586 587 return; 588} 589 590static u_int8_t wb_calchash(addr) 591 caddr_t addr; 592{ 593 u_int32_t crc, carry; 594 int i, j; 595 u_int8_t c; 596 597 /* Compute CRC for the address value. */ 598 crc = 0xFFFFFFFF; /* initial value */ 599 600 for (i = 0; i < 6; i++) { 601 c = *(addr + i); 602 for (j = 0; j < 8; j++) { 603 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 604 crc <<= 1; 605 c >>= 1; 606 if (carry) 607 crc = (crc ^ 0x04c11db6) | carry; 608 } 609 } 610 611 /* 612 * return the filter bit position 613 * Note: I arrived at the following nonsense 614 * through experimentation. It's not the usual way to 615 * generate the bit position but it's the only thing 616 * I could come up with that works. 617 */ 618 return(~(crc >> 26) & 0x0000003F); 619} 620 621/* 622 * Program the 64-bit multicast hash filter. 623 */ 624static void 625wb_setmulti(sc) 626 struct wb_softc *sc; 627{ 628 struct ifnet *ifp; 629 int h = 0; 630 u_int32_t hashes[2] = { 0, 0 }; 631 struct ifmultiaddr *ifma; 632 u_int32_t rxfilt; 633 int mcnt = 0; 634 635 ifp = &sc->arpcom.ac_if; 636 637 rxfilt = CSR_READ_4(sc, WB_NETCFG); 638 639 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 640 rxfilt |= WB_NETCFG_RX_MULTI; 641 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 642 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 643 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 644 return; 645 } 646 647 /* first, zot all the existing hash bits */ 648 CSR_WRITE_4(sc, WB_MAR0, 0); 649 CSR_WRITE_4(sc, WB_MAR1, 0); 650 651 /* now program new ones */ 652 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 653 if (ifma->ifma_addr->sa_family != AF_LINK) 654 continue; 655 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 656 if (h < 32) 657 hashes[0] |= (1 << h); 658 else 659 hashes[1] |= (1 << (h - 32)); 660 mcnt++; 661 } 662 663 if (mcnt) 664 rxfilt |= WB_NETCFG_RX_MULTI; 665 else 666 rxfilt &= ~WB_NETCFG_RX_MULTI; 667 668 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 669 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 670 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 671 672 return; 673} 674 675/* 676 * The Winbond manual states that in order to fiddle with the 677 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 678 * first have to put the transmit and/or receive logic in the idle state. 679 */ 680static void 681wb_setcfg(sc, media) 682 struct wb_softc *sc; 683 u_int32_t media; 684{ 685 int i, restart = 0; 686 687 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 688 restart = 1; 689 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 690 691 for (i = 0; i < WB_TIMEOUT; i++) { 692 DELAY(10); 693 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 694 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 695 break; 696 } 697 698 if (i == WB_TIMEOUT) 699 printf("wb%d: failed to force tx and " 700 "rx to idle state\n", sc->wb_unit); 701 } 702 703 if (IFM_SUBTYPE(media) == IFM_10_T) 704 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 705 else 706 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 707 708 if ((media & IFM_GMASK) == IFM_FDX) 709 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 710 else 711 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 712 713 if (restart) 714 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 715 716 return; 717} 718 719static void 720wb_reset(sc) 721 struct wb_softc *sc; 722{ 723 register int i; 724 struct mii_data *mii; 725 726 CSR_WRITE_4(sc, WB_NETCFG, 0); 727 CSR_WRITE_4(sc, WB_BUSCTL, 0); 728 CSR_WRITE_4(sc, WB_TXADDR, 0); 729 CSR_WRITE_4(sc, WB_RXADDR, 0); 730 731 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 732 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 733 734 for (i = 0; i < WB_TIMEOUT; i++) { 735 DELAY(10); 736 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 737 break; 738 } 739 if (i == WB_TIMEOUT) 740 printf("wb%d: reset never completed!\n", sc->wb_unit); 741 742 /* Wait a little while for the chip to get its brains in order. */ 743 DELAY(1000); 744 745 if (sc->wb_miibus == NULL) 746 return; 747 748 mii = device_get_softc(sc->wb_miibus); 749 if (mii == NULL) 750 return; 751 752 if (mii->mii_instance) { 753 struct mii_softc *miisc; 754 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 755 mii_phy_reset(miisc); 756 } 757 758 return; 759} 760 761static void 762wb_fixmedia(sc) 763 struct wb_softc *sc; 764{ 765 struct mii_data *mii = NULL; 766 struct ifnet *ifp; 767 u_int32_t media; 768 769 if (sc->wb_miibus == NULL) 770 return; 771 772 mii = device_get_softc(sc->wb_miibus); 773 ifp = &sc->arpcom.ac_if; 774 775 mii_pollstat(mii); 776 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 777 media = mii->mii_media_active & ~IFM_10_T; 778 media |= IFM_100_TX; 779 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 780 media = mii->mii_media_active & ~IFM_100_TX; 781 media |= IFM_10_T; 782 } else 783 return; 784 785 ifmedia_set(&mii->mii_media, media); 786 787 return; 788} 789 790/* 791 * Probe for a Winbond chip. Check the PCI vendor and device 792 * IDs against our list and return a device name if we find a match. 793 */ 794static int 795wb_probe(dev) 796 device_t dev; 797{ 798 struct wb_type *t; 799 800 t = wb_devs; 801 802 while(t->wb_name != NULL) { 803 if ((pci_get_vendor(dev) == t->wb_vid) && 804 (pci_get_device(dev) == t->wb_did)) { 805 device_set_desc(dev, t->wb_name); 806 return(0); 807 } 808 t++; 809 } 810 811 return(ENXIO); 812} 813 814/* 815 * Attach the interface. Allocate softc structures, do ifmedia 816 * setup and ethernet/BPF attach. 817 */ 818static int 819wb_attach(dev) 820 device_t dev; 821{ 822 u_char eaddr[ETHER_ADDR_LEN]; 823 struct wb_softc *sc; 824 struct ifnet *ifp; 825 int unit, error = 0, rid; 826 827 sc = device_get_softc(dev); 828 unit = device_get_unit(dev); 829 830 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 831 MTX_DEF | MTX_RECURSE); 832#ifndef BURN_BRIDGES 833 /* 834 * Handle power management nonsense. 835 */ 836 837 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 838 u_int32_t iobase, membase, irq; 839 840 /* Save important PCI config data. */ 841 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 842 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 843 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 844 845 /* Reset the power state. */ 846 printf("wb%d: chip is in D%d power mode " 847 "-- setting to D0\n", unit, 848 pci_get_powerstate(dev)); 849 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 850 851 /* Restore PCI config data. */ 852 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 853 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 854 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 855 } 856#endif 857 /* 858 * Map control/status registers. 859 */ 860 pci_enable_busmaster(dev); 861 862 rid = WB_RID; 863 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 864 0, ~0, 1, RF_ACTIVE); 865 866 if (sc->wb_res == NULL) { 867 printf("wb%d: couldn't map ports/memory\n", unit); 868 error = ENXIO; 869 goto fail; 870 } 871 872 sc->wb_btag = rman_get_bustag(sc->wb_res); 873 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 874 875 /* Allocate interrupt */ 876 rid = 0; 877 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 878 RF_SHAREABLE | RF_ACTIVE); 879 880 if (sc->wb_irq == NULL) { 881 printf("wb%d: couldn't map interrupt\n", unit); 882 error = ENXIO; 883 goto fail; 884 } 885 886 /* Save the cache line size. */ 887 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 888 889 /* Reset the adapter. */ 890 wb_reset(sc); 891 892 /* 893 * Get station address from the EEPROM. 894 */ 895 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 896 897 /* 898 * A Winbond chip was detected. Inform the world. 899 */ 900 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 901 902 sc->wb_unit = unit; 903 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 904 905 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 906 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 907 908 if (sc->wb_ldata == NULL) { 909 printf("wb%d: no memory for list buffers!\n", unit); 910 error = ENXIO; 911 goto fail; 912 } 913 914 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 915 916 ifp = &sc->arpcom.ac_if; 917 ifp->if_softc = sc; 918 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 919 ifp->if_mtu = ETHERMTU; 920 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 921 ifp->if_ioctl = wb_ioctl; 922 ifp->if_output = ether_output; 923 ifp->if_start = wb_start; 924 ifp->if_watchdog = wb_watchdog; 925 ifp->if_init = wb_init; 926 ifp->if_baudrate = 10000000; 927 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 928 929 /* 930 * Do MII setup. 931 */ 932 if (mii_phy_probe(dev, &sc->wb_miibus, 933 wb_ifmedia_upd, wb_ifmedia_sts)) { 934 error = ENXIO; 935 goto fail; 936 } 937 938 /* 939 * Call MI attach routine. 940 */ 941 ether_ifattach(ifp, eaddr); 942 943 /* Hook interrupt last to avoid having to lock softc */ 944 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 945 wb_intr, sc, &sc->wb_intrhand); 946 947 if (error) { 948 printf("wb%d: couldn't set up irq\n", unit); 949 ether_ifdetach(ifp); 950 goto fail; 951 } 952 953fail: 954 if (error) 955 wb_detach(dev); 956 957 return(error); 958} 959 960/* 961 * Shutdown hardware and free up resources. This can be called any 962 * time after the mutex has been initialized. It is called in both 963 * the error case in attach and the normal detach case so it needs 964 * to be careful about only freeing resources that have actually been 965 * allocated. 966 */ 967static int 968wb_detach(dev) 969 device_t dev; 970{ 971 struct wb_softc *sc; 972 struct ifnet *ifp; 973 974 sc = device_get_softc(dev); 975 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 976 WB_LOCK(sc); 977 ifp = &sc->arpcom.ac_if; 978 979 /* 980 * Delete any miibus and phy devices attached to this interface. 981 * This should only be done if attach succeeded. 982 */ 983 if (device_is_attached(dev)) { 984 wb_stop(sc); 985 ether_ifdetach(ifp); 986 } 987 if (sc->wb_miibus) 988 device_delete_child(dev, sc->wb_miibus); 989 bus_generic_detach(dev); 990 991 if (sc->wb_intrhand) 992 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 993 if (sc->wb_irq) 994 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 995 if (sc->wb_res) 996 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 997 998 if (sc->wb_ldata) { 999 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 1000 M_DEVBUF); 1001 } 1002 1003 WB_UNLOCK(sc); 1004 mtx_destroy(&sc->wb_mtx); 1005 1006 return(0); 1007} 1008 1009/* 1010 * Initialize the transmit descriptors. 1011 */ 1012static int 1013wb_list_tx_init(sc) 1014 struct wb_softc *sc; 1015{ 1016 struct wb_chain_data *cd; 1017 struct wb_list_data *ld; 1018 int i; 1019 1020 cd = &sc->wb_cdata; 1021 ld = sc->wb_ldata; 1022 1023 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1024 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1025 if (i == (WB_TX_LIST_CNT - 1)) { 1026 cd->wb_tx_chain[i].wb_nextdesc = 1027 &cd->wb_tx_chain[0]; 1028 } else { 1029 cd->wb_tx_chain[i].wb_nextdesc = 1030 &cd->wb_tx_chain[i + 1]; 1031 } 1032 } 1033 1034 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1035 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1036 1037 return(0); 1038} 1039 1040 1041/* 1042 * Initialize the RX descriptors and allocate mbufs for them. Note that 1043 * we arrange the descriptors in a closed ring, so that the last descriptor 1044 * points back to the first. 1045 */ 1046static int 1047wb_list_rx_init(sc) 1048 struct wb_softc *sc; 1049{ 1050 struct wb_chain_data *cd; 1051 struct wb_list_data *ld; 1052 int i; 1053 1054 cd = &sc->wb_cdata; 1055 ld = sc->wb_ldata; 1056 1057 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1058 cd->wb_rx_chain[i].wb_ptr = 1059 (struct wb_desc *)&ld->wb_rx_list[i]; 1060 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1061 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1062 return(ENOBUFS); 1063 if (i == (WB_RX_LIST_CNT - 1)) { 1064 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1065 ld->wb_rx_list[i].wb_next = 1066 vtophys(&ld->wb_rx_list[0]); 1067 } else { 1068 cd->wb_rx_chain[i].wb_nextdesc = 1069 &cd->wb_rx_chain[i + 1]; 1070 ld->wb_rx_list[i].wb_next = 1071 vtophys(&ld->wb_rx_list[i + 1]); 1072 } 1073 } 1074 1075 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1076 1077 return(0); 1078} 1079 1080static void 1081wb_bfree(buf, args) 1082 void *buf; 1083 void *args; 1084{ 1085 return; 1086} 1087 1088/* 1089 * Initialize an RX descriptor and attach an MBUF cluster. 1090 */ 1091static int 1092wb_newbuf(sc, c, m) 1093 struct wb_softc *sc; 1094 struct wb_chain_onefrag *c; 1095 struct mbuf *m; 1096{ 1097 struct mbuf *m_new = NULL; 1098 1099 if (m == NULL) { 1100 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1101 if (m_new == NULL) 1102 return(ENOBUFS); 1103 m_new->m_data = c->wb_buf; 1104 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1105 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1106 EXT_NET_DRV); 1107 } else { 1108 m_new = m; 1109 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1110 m_new->m_data = m_new->m_ext.ext_buf; 1111 } 1112 1113 m_adj(m_new, sizeof(u_int64_t)); 1114 1115 c->wb_mbuf = m_new; 1116 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1117 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1118 c->wb_ptr->wb_status = WB_RXSTAT; 1119 1120 return(0); 1121} 1122 1123/* 1124 * A frame has been uploaded: pass the resulting mbuf chain up to 1125 * the higher level protocols. 1126 */ 1127static void 1128wb_rxeof(sc) 1129 struct wb_softc *sc; 1130{ 1131 struct mbuf *m = NULL; 1132 struct ifnet *ifp; 1133 struct wb_chain_onefrag *cur_rx; 1134 int total_len = 0; 1135 u_int32_t rxstat; 1136 1137 ifp = &sc->arpcom.ac_if; 1138 1139 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1140 WB_RXSTAT_OWN)) { 1141 struct mbuf *m0 = NULL; 1142 1143 cur_rx = sc->wb_cdata.wb_rx_head; 1144 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1145 1146 m = cur_rx->wb_mbuf; 1147 1148 if ((rxstat & WB_RXSTAT_MIIERR) || 1149 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1150 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1151 !(rxstat & WB_RXSTAT_LASTFRAG) || 1152 !(rxstat & WB_RXSTAT_RXCMP)) { 1153 ifp->if_ierrors++; 1154 wb_newbuf(sc, cur_rx, m); 1155 printf("wb%x: receiver babbling: possible chip " 1156 "bug, forcing reset\n", sc->wb_unit); 1157 wb_fixmedia(sc); 1158 wb_reset(sc); 1159 wb_init(sc); 1160 return; 1161 } 1162 1163 if (rxstat & WB_RXSTAT_RXERR) { 1164 ifp->if_ierrors++; 1165 wb_newbuf(sc, cur_rx, m); 1166 break; 1167 } 1168 1169 /* No errors; receive the packet. */ 1170 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1171 1172 /* 1173 * XXX The Winbond chip includes the CRC with every 1174 * received frame, and there's no way to turn this 1175 * behavior off (at least, I can't find anything in 1176 * the manual that explains how to do it) so we have 1177 * to trim off the CRC manually. 1178 */ 1179 total_len -= ETHER_CRC_LEN; 1180 1181 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1182 NULL); 1183 wb_newbuf(sc, cur_rx, m); 1184 if (m0 == NULL) { 1185 ifp->if_ierrors++; 1186 break; 1187 } 1188 m = m0; 1189 1190 ifp->if_ipackets++; 1191 (*ifp->if_input)(ifp, m); 1192 } 1193} 1194 1195static void 1196wb_rxeoc(sc) 1197 struct wb_softc *sc; 1198{ 1199 wb_rxeof(sc); 1200 1201 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1202 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1203 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1204 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1205 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1206 1207 return; 1208} 1209 1210/* 1211 * A frame was downloaded to the chip. It's safe for us to clean up 1212 * the list buffers. 1213 */ 1214static void 1215wb_txeof(sc) 1216 struct wb_softc *sc; 1217{ 1218 struct wb_chain *cur_tx; 1219 struct ifnet *ifp; 1220 1221 ifp = &sc->arpcom.ac_if; 1222 1223 /* Clear the timeout timer. */ 1224 ifp->if_timer = 0; 1225 1226 if (sc->wb_cdata.wb_tx_head == NULL) 1227 return; 1228 1229 /* 1230 * Go through our tx list and free mbufs for those 1231 * frames that have been transmitted. 1232 */ 1233 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1234 u_int32_t txstat; 1235 1236 cur_tx = sc->wb_cdata.wb_tx_head; 1237 txstat = WB_TXSTATUS(cur_tx); 1238 1239 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1240 break; 1241 1242 if (txstat & WB_TXSTAT_TXERR) { 1243 ifp->if_oerrors++; 1244 if (txstat & WB_TXSTAT_ABORT) 1245 ifp->if_collisions++; 1246 if (txstat & WB_TXSTAT_LATECOLL) 1247 ifp->if_collisions++; 1248 } 1249 1250 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1251 1252 ifp->if_opackets++; 1253 m_freem(cur_tx->wb_mbuf); 1254 cur_tx->wb_mbuf = NULL; 1255 1256 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1257 sc->wb_cdata.wb_tx_head = NULL; 1258 sc->wb_cdata.wb_tx_tail = NULL; 1259 break; 1260 } 1261 1262 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1263 } 1264 1265 return; 1266} 1267 1268/* 1269 * TX 'end of channel' interrupt handler. 1270 */ 1271static void 1272wb_txeoc(sc) 1273 struct wb_softc *sc; 1274{ 1275 struct ifnet *ifp; 1276 1277 ifp = &sc->arpcom.ac_if; 1278 1279 ifp->if_timer = 0; 1280 1281 if (sc->wb_cdata.wb_tx_head == NULL) { 1282 ifp->if_flags &= ~IFF_OACTIVE; 1283 sc->wb_cdata.wb_tx_tail = NULL; 1284 } else { 1285 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1286 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1287 ifp->if_timer = 5; 1288 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1289 } 1290 } 1291 1292 return; 1293} 1294 1295static void 1296wb_intr(arg) 1297 void *arg; 1298{ 1299 struct wb_softc *sc; 1300 struct ifnet *ifp; 1301 u_int32_t status; 1302 1303 sc = arg; 1304 WB_LOCK(sc); 1305 ifp = &sc->arpcom.ac_if; 1306 1307 if (!(ifp->if_flags & IFF_UP)) { 1308 WB_UNLOCK(sc); 1309 return; 1310 } 1311 1312 /* Disable interrupts. */ 1313 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1314 1315 for (;;) { 1316 1317 status = CSR_READ_4(sc, WB_ISR); 1318 if (status) 1319 CSR_WRITE_4(sc, WB_ISR, status); 1320 1321 if ((status & WB_INTRS) == 0) 1322 break; 1323 1324 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1325 ifp->if_ierrors++; 1326 wb_reset(sc); 1327 if (status & WB_ISR_RX_ERR) 1328 wb_fixmedia(sc); 1329 wb_init(sc); 1330 continue; 1331 } 1332 1333 if (status & WB_ISR_RX_OK) 1334 wb_rxeof(sc); 1335 1336 if (status & WB_ISR_RX_IDLE) 1337 wb_rxeoc(sc); 1338 1339 if (status & WB_ISR_TX_OK) 1340 wb_txeof(sc); 1341 1342 if (status & WB_ISR_TX_NOBUF) 1343 wb_txeoc(sc); 1344 1345 if (status & WB_ISR_TX_IDLE) { 1346 wb_txeof(sc); 1347 if (sc->wb_cdata.wb_tx_head != NULL) { 1348 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1349 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1350 } 1351 } 1352 1353 if (status & WB_ISR_TX_UNDERRUN) { 1354 ifp->if_oerrors++; 1355 wb_txeof(sc); 1356 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1357 /* Jack up TX threshold */ 1358 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1359 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1360 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1361 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1362 } 1363 1364 if (status & WB_ISR_BUS_ERR) { 1365 wb_reset(sc); 1366 wb_init(sc); 1367 } 1368 1369 } 1370 1371 /* Re-enable interrupts. */ 1372 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1373 1374 if (ifp->if_snd.ifq_head != NULL) { 1375 wb_start(ifp); 1376 } 1377 1378 WB_UNLOCK(sc); 1379 1380 return; 1381} 1382 1383static void 1384wb_tick(xsc) 1385 void *xsc; 1386{ 1387 struct wb_softc *sc; 1388 struct mii_data *mii; 1389 1390 sc = xsc; 1391 WB_LOCK(sc); 1392 mii = device_get_softc(sc->wb_miibus); 1393 1394 mii_tick(mii); 1395 1396 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1397 1398 WB_UNLOCK(sc); 1399 1400 return; 1401} 1402 1403/* 1404 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1405 * pointers to the fragment pointers. 1406 */ 1407static int 1408wb_encap(sc, c, m_head) 1409 struct wb_softc *sc; 1410 struct wb_chain *c; 1411 struct mbuf *m_head; 1412{ 1413 int frag = 0; 1414 struct wb_desc *f = NULL; 1415 int total_len; 1416 struct mbuf *m; 1417 1418 /* 1419 * Start packing the mbufs in this chain into 1420 * the fragment pointers. Stop when we run out 1421 * of fragments or hit the end of the mbuf chain. 1422 */ 1423 m = m_head; 1424 total_len = 0; 1425 1426 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1427 if (m->m_len != 0) { 1428 if (frag == WB_MAXFRAGS) 1429 break; 1430 total_len += m->m_len; 1431 f = &c->wb_ptr->wb_frag[frag]; 1432 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1433 if (frag == 0) { 1434 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1435 f->wb_status = 0; 1436 } else 1437 f->wb_status = WB_TXSTAT_OWN; 1438 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1439 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1440 frag++; 1441 } 1442 } 1443 1444 /* 1445 * Handle special case: we used up all 16 fragments, 1446 * but we have more mbufs left in the chain. Copy the 1447 * data into an mbuf cluster. Note that we don't 1448 * bother clearing the values in the other fragment 1449 * pointers/counters; it wouldn't gain us anything, 1450 * and would waste cycles. 1451 */ 1452 if (m != NULL) { 1453 struct mbuf *m_new = NULL; 1454 1455 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1456 if (m_new == NULL) 1457 return(1); 1458 if (m_head->m_pkthdr.len > MHLEN) { 1459 MCLGET(m_new, M_DONTWAIT); 1460 if (!(m_new->m_flags & M_EXT)) { 1461 m_freem(m_new); 1462 return(1); 1463 } 1464 } 1465 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1466 mtod(m_new, caddr_t)); 1467 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1468 m_freem(m_head); 1469 m_head = m_new; 1470 f = &c->wb_ptr->wb_frag[0]; 1471 f->wb_status = 0; 1472 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1473 f->wb_ctl = total_len = m_new->m_len; 1474 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1475 frag = 1; 1476 } 1477 1478 if (total_len < WB_MIN_FRAMELEN) { 1479 f = &c->wb_ptr->wb_frag[frag]; 1480 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1481 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1482 f->wb_ctl |= WB_TXCTL_TLINK; 1483 f->wb_status = WB_TXSTAT_OWN; 1484 frag++; 1485 } 1486 1487 c->wb_mbuf = m_head; 1488 c->wb_lastdesc = frag - 1; 1489 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1490 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1491 1492 return(0); 1493} 1494 1495/* 1496 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1497 * to the mbuf data regions directly in the transmit lists. We also save a 1498 * copy of the pointers since the transmit list fragment pointers are 1499 * physical addresses. 1500 */ 1501 1502static void 1503wb_start(ifp) 1504 struct ifnet *ifp; 1505{ 1506 struct wb_softc *sc; 1507 struct mbuf *m_head = NULL; 1508 struct wb_chain *cur_tx = NULL, *start_tx; 1509 1510 sc = ifp->if_softc; 1511 WB_LOCK(sc); 1512 1513 /* 1514 * Check for an available queue slot. If there are none, 1515 * punt. 1516 */ 1517 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1518 ifp->if_flags |= IFF_OACTIVE; 1519 WB_UNLOCK(sc); 1520 return; 1521 } 1522 1523 start_tx = sc->wb_cdata.wb_tx_free; 1524 1525 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1526 IF_DEQUEUE(&ifp->if_snd, m_head); 1527 if (m_head == NULL) 1528 break; 1529 1530 /* Pick a descriptor off the free list. */ 1531 cur_tx = sc->wb_cdata.wb_tx_free; 1532 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1533 1534 /* Pack the data into the descriptor. */ 1535 wb_encap(sc, cur_tx, m_head); 1536 1537 if (cur_tx != start_tx) 1538 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1539 1540 /* 1541 * If there's a BPF listener, bounce a copy of this frame 1542 * to him. 1543 */ 1544 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1545 } 1546 1547 /* 1548 * If there are no packets queued, bail. 1549 */ 1550 if (cur_tx == NULL) { 1551 WB_UNLOCK(sc); 1552 return; 1553 } 1554 1555 /* 1556 * Place the request for the upload interrupt 1557 * in the last descriptor in the chain. This way, if 1558 * we're chaining several packets at once, we'll only 1559 * get an interupt once for the whole chain rather than 1560 * once for each packet. 1561 */ 1562 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1563 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1564 sc->wb_cdata.wb_tx_tail = cur_tx; 1565 1566 if (sc->wb_cdata.wb_tx_head == NULL) { 1567 sc->wb_cdata.wb_tx_head = start_tx; 1568 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1569 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1570 } else { 1571 /* 1572 * We need to distinguish between the case where 1573 * the own bit is clear because the chip cleared it 1574 * and where the own bit is clear because we haven't 1575 * set it yet. The magic value WB_UNSET is just some 1576 * ramdomly chosen number which doesn't have the own 1577 * bit set. When we actually transmit the frame, the 1578 * status word will have _only_ the own bit set, so 1579 * the txeoc handler will be able to tell if it needs 1580 * to initiate another transmission to flush out pending 1581 * frames. 1582 */ 1583 WB_TXOWN(start_tx) = WB_UNSENT; 1584 } 1585 1586 /* 1587 * Set a timeout in case the chip goes out to lunch. 1588 */ 1589 ifp->if_timer = 5; 1590 WB_UNLOCK(sc); 1591 1592 return; 1593} 1594 1595static void 1596wb_init(xsc) 1597 void *xsc; 1598{ 1599 struct wb_softc *sc = xsc; 1600 struct ifnet *ifp = &sc->arpcom.ac_if; 1601 int i; 1602 struct mii_data *mii; 1603 1604 WB_LOCK(sc); 1605 mii = device_get_softc(sc->wb_miibus); 1606 1607 /* 1608 * Cancel pending I/O and free all RX/TX buffers. 1609 */ 1610 wb_stop(sc); 1611 wb_reset(sc); 1612 1613 sc->wb_txthresh = WB_TXTHRESH_INIT; 1614 1615 /* 1616 * Set cache alignment and burst length. 1617 */ 1618#ifdef foo 1619 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1620 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1621 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1622#endif 1623 1624 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1625 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1626 switch(sc->wb_cachesize) { 1627 case 32: 1628 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1629 break; 1630 case 16: 1631 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1632 break; 1633 case 8: 1634 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1635 break; 1636 case 0: 1637 default: 1638 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1639 break; 1640 } 1641 1642 /* This doesn't tend to work too well at 100Mbps. */ 1643 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1644 1645 /* Init our MAC address */ 1646 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1647 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1648 } 1649 1650 /* Init circular RX list. */ 1651 if (wb_list_rx_init(sc) == ENOBUFS) { 1652 printf("wb%d: initialization failed: no " 1653 "memory for rx buffers\n", sc->wb_unit); 1654 wb_stop(sc); 1655 WB_UNLOCK(sc); 1656 return; 1657 } 1658 1659 /* Init TX descriptors. */ 1660 wb_list_tx_init(sc); 1661 1662 /* If we want promiscuous mode, set the allframes bit. */ 1663 if (ifp->if_flags & IFF_PROMISC) { 1664 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1665 } else { 1666 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1667 } 1668 1669 /* 1670 * Set capture broadcast bit to capture broadcast frames. 1671 */ 1672 if (ifp->if_flags & IFF_BROADCAST) { 1673 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1674 } else { 1675 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1676 } 1677 1678 /* 1679 * Program the multicast filter, if necessary. 1680 */ 1681 wb_setmulti(sc); 1682 1683 /* 1684 * Load the address of the RX list. 1685 */ 1686 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1687 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1688 1689 /* 1690 * Enable interrupts. 1691 */ 1692 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1693 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1694 1695 /* Enable receiver and transmitter. */ 1696 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1697 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1698 1699 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1700 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1701 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1702 1703 mii_mediachg(mii); 1704 1705 ifp->if_flags |= IFF_RUNNING; 1706 ifp->if_flags &= ~IFF_OACTIVE; 1707 1708 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1709 WB_UNLOCK(sc); 1710 1711 return; 1712} 1713 1714/* 1715 * Set media options. 1716 */ 1717static int 1718wb_ifmedia_upd(ifp) 1719 struct ifnet *ifp; 1720{ 1721 struct wb_softc *sc; 1722 1723 sc = ifp->if_softc; 1724 1725 if (ifp->if_flags & IFF_UP) 1726 wb_init(sc); 1727 1728 return(0); 1729} 1730 1731/* 1732 * Report current media status. 1733 */ 1734static void 1735wb_ifmedia_sts(ifp, ifmr) 1736 struct ifnet *ifp; 1737 struct ifmediareq *ifmr; 1738{ 1739 struct wb_softc *sc; 1740 struct mii_data *mii; 1741 1742 sc = ifp->if_softc; 1743 1744 mii = device_get_softc(sc->wb_miibus); 1745 1746 mii_pollstat(mii); 1747 ifmr->ifm_active = mii->mii_media_active; 1748 ifmr->ifm_status = mii->mii_media_status; 1749 1750 return; 1751} 1752 1753static int 1754wb_ioctl(ifp, command, data) 1755 struct ifnet *ifp; 1756 u_long command; 1757 caddr_t data; 1758{ 1759 struct wb_softc *sc = ifp->if_softc; 1760 struct mii_data *mii; 1761 struct ifreq *ifr = (struct ifreq *) data; 1762 int error = 0; 1763 1764 WB_LOCK(sc); 1765 1766 switch(command) { 1767 case SIOCSIFFLAGS: 1768 if (ifp->if_flags & IFF_UP) { 1769 wb_init(sc); 1770 } else { 1771 if (ifp->if_flags & IFF_RUNNING) 1772 wb_stop(sc); 1773 } 1774 error = 0; 1775 break; 1776 case SIOCADDMULTI: 1777 case SIOCDELMULTI: 1778 wb_setmulti(sc); 1779 error = 0; 1780 break; 1781 case SIOCGIFMEDIA: 1782 case SIOCSIFMEDIA: 1783 mii = device_get_softc(sc->wb_miibus); 1784 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1785 break; 1786 default: 1787 error = ether_ioctl(ifp, command, data); 1788 break; 1789 } 1790 1791 WB_UNLOCK(sc); 1792 1793 return(error); 1794} 1795 1796static void 1797wb_watchdog(ifp) 1798 struct ifnet *ifp; 1799{ 1800 struct wb_softc *sc; 1801 1802 sc = ifp->if_softc; 1803 1804 WB_LOCK(sc); 1805 ifp->if_oerrors++; 1806 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1807#ifdef foo 1808 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1809 printf("wb%d: no carrier - transceiver cable problem?\n", 1810 sc->wb_unit); 1811#endif 1812 wb_stop(sc); 1813 wb_reset(sc); 1814 wb_init(sc); 1815 1816 if (ifp->if_snd.ifq_head != NULL) 1817 wb_start(ifp); 1818 WB_UNLOCK(sc); 1819 1820 return; 1821} 1822 1823/* 1824 * Stop the adapter and free any mbufs allocated to the 1825 * RX and TX lists. 1826 */ 1827static void 1828wb_stop(sc) 1829 struct wb_softc *sc; 1830{ 1831 register int i; 1832 struct ifnet *ifp; 1833 1834 WB_LOCK(sc); 1835 ifp = &sc->arpcom.ac_if; 1836 ifp->if_timer = 0; 1837 1838 untimeout(wb_tick, sc, sc->wb_stat_ch); 1839 1840 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1841 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1842 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1843 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1844 1845 /* 1846 * Free data in the RX lists. 1847 */ 1848 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1849 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1850 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1851 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1852 } 1853 } 1854 bzero((char *)&sc->wb_ldata->wb_rx_list, 1855 sizeof(sc->wb_ldata->wb_rx_list)); 1856 1857 /* 1858 * Free the TX list buffers. 1859 */ 1860 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1861 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1862 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1863 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1864 } 1865 } 1866 1867 bzero((char *)&sc->wb_ldata->wb_tx_list, 1868 sizeof(sc->wb_ldata->wb_tx_list)); 1869 1870 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1871 WB_UNLOCK(sc); 1872 1873 return; 1874} 1875 1876/* 1877 * Stop all chip I/O so that the kernel's probe routines don't 1878 * get confused by errant DMAs when rebooting. 1879 */ 1880static void 1881wb_shutdown(dev) 1882 device_t dev; 1883{ 1884 struct wb_softc *sc; 1885 1886 sc = device_get_softc(dev); 1887 wb_stop(sc); 1888 1889 return; 1890} 1891