if_wb.c revision 112880
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_wb.c 112880 2003-03-31 20:22:00Z jhb $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus_memio.h> 108#include <machine/bus_pio.h> 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#include <dev/mii/mii.h> 118#include <dev/mii/miivar.h> 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <pci/if_wbreg.h> 126 127MODULE_DEPEND(wb, miibus, 1, 1, 1); 128 129#ifndef lint 130static const char rcsid[] = 131 "$FreeBSD: head/sys/pci/if_wb.c 112880 2003-03-31 20:22:00Z jhb $"; 132#endif 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137static struct wb_type wb_devs[] = { 138 { WB_VENDORID, WB_DEVICEID_840F, 139 "Winbond W89C840F 10/100BaseTX" }, 140 { CP_VENDORID, CP_DEVICEID_RL100, 141 "Compex RL100-ATX 10/100baseTX" }, 142 { 0, 0, NULL } 143}; 144 145static int wb_probe (device_t); 146static int wb_attach (device_t); 147static int wb_detach (device_t); 148 149static void wb_bfree (void *addr, void *args); 150static int wb_newbuf (struct wb_softc *, 151 struct wb_chain_onefrag *, 152 struct mbuf *); 153static int wb_encap (struct wb_softc *, struct wb_chain *, 154 struct mbuf *); 155 156static void wb_rxeof (struct wb_softc *); 157static void wb_rxeoc (struct wb_softc *); 158static void wb_txeof (struct wb_softc *); 159static void wb_txeoc (struct wb_softc *); 160static void wb_intr (void *); 161static void wb_tick (void *); 162static void wb_start (struct ifnet *); 163static int wb_ioctl (struct ifnet *, u_long, caddr_t); 164static void wb_init (void *); 165static void wb_stop (struct wb_softc *); 166static void wb_watchdog (struct ifnet *); 167static void wb_shutdown (device_t); 168static int wb_ifmedia_upd (struct ifnet *); 169static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 170 171static void wb_eeprom_putbyte (struct wb_softc *, int); 172static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 173static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 174static void wb_mii_sync (struct wb_softc *); 175static void wb_mii_send (struct wb_softc *, u_int32_t, int); 176static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 177static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 178 179static void wb_setcfg (struct wb_softc *, u_int32_t); 180static u_int8_t wb_calchash (caddr_t); 181static void wb_setmulti (struct wb_softc *); 182static void wb_reset (struct wb_softc *); 183static void wb_fixmedia (struct wb_softc *); 184static int wb_list_rx_init (struct wb_softc *); 185static int wb_list_tx_init (struct wb_softc *); 186 187static int wb_miibus_readreg (device_t, int, int); 188static int wb_miibus_writereg (device_t, int, int, int); 189static void wb_miibus_statchg (device_t); 190 191#ifdef WB_USEIOSPACE 192#define WB_RES SYS_RES_IOPORT 193#define WB_RID WB_PCI_LOIO 194#else 195#define WB_RES SYS_RES_MEMORY 196#define WB_RID WB_PCI_LOMEM 197#endif 198 199static device_method_t wb_methods[] = { 200 /* Device interface */ 201 DEVMETHOD(device_probe, wb_probe), 202 DEVMETHOD(device_attach, wb_attach), 203 DEVMETHOD(device_detach, wb_detach), 204 DEVMETHOD(device_shutdown, wb_shutdown), 205 206 /* bus interface, for miibus */ 207 DEVMETHOD(bus_print_child, bus_generic_print_child), 208 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 209 210 /* MII interface */ 211 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 212 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 213 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 214 { 0, 0 } 215}; 216 217static driver_t wb_driver = { 218 "wb", 219 wb_methods, 220 sizeof(struct wb_softc) 221}; 222 223static devclass_t wb_devclass; 224 225DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 226DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 227 228#define WB_SETBIT(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, \ 230 CSR_READ_4(sc, reg) | (x)) 231 232#define WB_CLRBIT(sc, reg, x) \ 233 CSR_WRITE_4(sc, reg, \ 234 CSR_READ_4(sc, reg) & ~(x)) 235 236#define SIO_SET(x) \ 237 CSR_WRITE_4(sc, WB_SIO, \ 238 CSR_READ_4(sc, WB_SIO) | (x)) 239 240#define SIO_CLR(x) \ 241 CSR_WRITE_4(sc, WB_SIO, \ 242 CSR_READ_4(sc, WB_SIO) & ~(x)) 243 244/* 245 * Send a read command and address to the EEPROM, check for ACK. 246 */ 247static void 248wb_eeprom_putbyte(sc, addr) 249 struct wb_softc *sc; 250 int addr; 251{ 252 register int d, i; 253 254 d = addr | WB_EECMD_READ; 255 256 /* 257 * Feed in each bit and stobe the clock. 258 */ 259 for (i = 0x400; i; i >>= 1) { 260 if (d & i) { 261 SIO_SET(WB_SIO_EE_DATAIN); 262 } else { 263 SIO_CLR(WB_SIO_EE_DATAIN); 264 } 265 DELAY(100); 266 SIO_SET(WB_SIO_EE_CLK); 267 DELAY(150); 268 SIO_CLR(WB_SIO_EE_CLK); 269 DELAY(100); 270 } 271 272 return; 273} 274 275/* 276 * Read a word of data stored in the EEPROM at address 'addr.' 277 */ 278static void 279wb_eeprom_getword(sc, addr, dest) 280 struct wb_softc *sc; 281 int addr; 282 u_int16_t *dest; 283{ 284 register int i; 285 u_int16_t word = 0; 286 287 /* Enter EEPROM access mode. */ 288 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 289 290 /* 291 * Send address of word we want to read. 292 */ 293 wb_eeprom_putbyte(sc, addr); 294 295 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 296 297 /* 298 * Start reading bits from EEPROM. 299 */ 300 for (i = 0x8000; i; i >>= 1) { 301 SIO_SET(WB_SIO_EE_CLK); 302 DELAY(100); 303 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 304 word |= i; 305 SIO_CLR(WB_SIO_EE_CLK); 306 DELAY(100); 307 } 308 309 /* Turn off EEPROM access mode. */ 310 CSR_WRITE_4(sc, WB_SIO, 0); 311 312 *dest = word; 313 314 return; 315} 316 317/* 318 * Read a sequence of words from the EEPROM. 319 */ 320static void 321wb_read_eeprom(sc, dest, off, cnt, swap) 322 struct wb_softc *sc; 323 caddr_t dest; 324 int off; 325 int cnt; 326 int swap; 327{ 328 int i; 329 u_int16_t word = 0, *ptr; 330 331 for (i = 0; i < cnt; i++) { 332 wb_eeprom_getword(sc, off + i, &word); 333 ptr = (u_int16_t *)(dest + (i * 2)); 334 if (swap) 335 *ptr = ntohs(word); 336 else 337 *ptr = word; 338 } 339 340 return; 341} 342 343/* 344 * Sync the PHYs by setting data bit and strobing the clock 32 times. 345 */ 346static void 347wb_mii_sync(sc) 348 struct wb_softc *sc; 349{ 350 register int i; 351 352 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 353 354 for (i = 0; i < 32; i++) { 355 SIO_SET(WB_SIO_MII_CLK); 356 DELAY(1); 357 SIO_CLR(WB_SIO_MII_CLK); 358 DELAY(1); 359 } 360 361 return; 362} 363 364/* 365 * Clock a series of bits through the MII. 366 */ 367static void 368wb_mii_send(sc, bits, cnt) 369 struct wb_softc *sc; 370 u_int32_t bits; 371 int cnt; 372{ 373 int i; 374 375 SIO_CLR(WB_SIO_MII_CLK); 376 377 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 378 if (bits & i) { 379 SIO_SET(WB_SIO_MII_DATAIN); 380 } else { 381 SIO_CLR(WB_SIO_MII_DATAIN); 382 } 383 DELAY(1); 384 SIO_CLR(WB_SIO_MII_CLK); 385 DELAY(1); 386 SIO_SET(WB_SIO_MII_CLK); 387 } 388} 389 390/* 391 * Read an PHY register through the MII. 392 */ 393static int 394wb_mii_readreg(sc, frame) 395 struct wb_softc *sc; 396 struct wb_mii_frame *frame; 397 398{ 399 int i, ack; 400 401 WB_LOCK(sc); 402 403 /* 404 * Set up frame for RX. 405 */ 406 frame->mii_stdelim = WB_MII_STARTDELIM; 407 frame->mii_opcode = WB_MII_READOP; 408 frame->mii_turnaround = 0; 409 frame->mii_data = 0; 410 411 CSR_WRITE_4(sc, WB_SIO, 0); 412 413 /* 414 * Turn on data xmit. 415 */ 416 SIO_SET(WB_SIO_MII_DIR); 417 418 wb_mii_sync(sc); 419 420 /* 421 * Send command/address info. 422 */ 423 wb_mii_send(sc, frame->mii_stdelim, 2); 424 wb_mii_send(sc, frame->mii_opcode, 2); 425 wb_mii_send(sc, frame->mii_phyaddr, 5); 426 wb_mii_send(sc, frame->mii_regaddr, 5); 427 428 /* Idle bit */ 429 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 430 DELAY(1); 431 SIO_SET(WB_SIO_MII_CLK); 432 DELAY(1); 433 434 /* Turn off xmit. */ 435 SIO_CLR(WB_SIO_MII_DIR); 436 /* Check for ack */ 437 SIO_CLR(WB_SIO_MII_CLK); 438 DELAY(1); 439 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 440 SIO_SET(WB_SIO_MII_CLK); 441 DELAY(1); 442 SIO_CLR(WB_SIO_MII_CLK); 443 DELAY(1); 444 SIO_SET(WB_SIO_MII_CLK); 445 DELAY(1); 446 447 /* 448 * Now try reading data bits. If the ack failed, we still 449 * need to clock through 16 cycles to keep the PHY(s) in sync. 450 */ 451 if (ack) { 452 for(i = 0; i < 16; i++) { 453 SIO_CLR(WB_SIO_MII_CLK); 454 DELAY(1); 455 SIO_SET(WB_SIO_MII_CLK); 456 DELAY(1); 457 } 458 goto fail; 459 } 460 461 for (i = 0x8000; i; i >>= 1) { 462 SIO_CLR(WB_SIO_MII_CLK); 463 DELAY(1); 464 if (!ack) { 465 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 466 frame->mii_data |= i; 467 DELAY(1); 468 } 469 SIO_SET(WB_SIO_MII_CLK); 470 DELAY(1); 471 } 472 473fail: 474 475 SIO_CLR(WB_SIO_MII_CLK); 476 DELAY(1); 477 SIO_SET(WB_SIO_MII_CLK); 478 DELAY(1); 479 480 WB_UNLOCK(sc); 481 482 if (ack) 483 return(1); 484 return(0); 485} 486 487/* 488 * Write to a PHY register through the MII. 489 */ 490static int 491wb_mii_writereg(sc, frame) 492 struct wb_softc *sc; 493 struct wb_mii_frame *frame; 494 495{ 496 WB_LOCK(sc); 497 498 /* 499 * Set up frame for TX. 500 */ 501 502 frame->mii_stdelim = WB_MII_STARTDELIM; 503 frame->mii_opcode = WB_MII_WRITEOP; 504 frame->mii_turnaround = WB_MII_TURNAROUND; 505 506 /* 507 * Turn on data output. 508 */ 509 SIO_SET(WB_SIO_MII_DIR); 510 511 wb_mii_sync(sc); 512 513 wb_mii_send(sc, frame->mii_stdelim, 2); 514 wb_mii_send(sc, frame->mii_opcode, 2); 515 wb_mii_send(sc, frame->mii_phyaddr, 5); 516 wb_mii_send(sc, frame->mii_regaddr, 5); 517 wb_mii_send(sc, frame->mii_turnaround, 2); 518 wb_mii_send(sc, frame->mii_data, 16); 519 520 /* Idle bit. */ 521 SIO_SET(WB_SIO_MII_CLK); 522 DELAY(1); 523 SIO_CLR(WB_SIO_MII_CLK); 524 DELAY(1); 525 526 /* 527 * Turn off xmit. 528 */ 529 SIO_CLR(WB_SIO_MII_DIR); 530 531 WB_UNLOCK(sc); 532 533 return(0); 534} 535 536static int 537wb_miibus_readreg(dev, phy, reg) 538 device_t dev; 539 int phy, reg; 540{ 541 struct wb_softc *sc; 542 struct wb_mii_frame frame; 543 544 sc = device_get_softc(dev); 545 546 bzero((char *)&frame, sizeof(frame)); 547 548 frame.mii_phyaddr = phy; 549 frame.mii_regaddr = reg; 550 wb_mii_readreg(sc, &frame); 551 552 return(frame.mii_data); 553} 554 555static int 556wb_miibus_writereg(dev, phy, reg, data) 557 device_t dev; 558 int phy, reg, data; 559{ 560 struct wb_softc *sc; 561 struct wb_mii_frame frame; 562 563 sc = device_get_softc(dev); 564 565 bzero((char *)&frame, sizeof(frame)); 566 567 frame.mii_phyaddr = phy; 568 frame.mii_regaddr = reg; 569 frame.mii_data = data; 570 571 wb_mii_writereg(sc, &frame); 572 573 return(0); 574} 575 576static void 577wb_miibus_statchg(dev) 578 device_t dev; 579{ 580 struct wb_softc *sc; 581 struct mii_data *mii; 582 583 sc = device_get_softc(dev); 584 WB_LOCK(sc); 585 mii = device_get_softc(sc->wb_miibus); 586 wb_setcfg(sc, mii->mii_media_active); 587 WB_UNLOCK(sc); 588 589 return; 590} 591 592static u_int8_t wb_calchash(addr) 593 caddr_t addr; 594{ 595 u_int32_t crc, carry; 596 int i, j; 597 u_int8_t c; 598 599 /* Compute CRC for the address value. */ 600 crc = 0xFFFFFFFF; /* initial value */ 601 602 for (i = 0; i < 6; i++) { 603 c = *(addr + i); 604 for (j = 0; j < 8; j++) { 605 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 606 crc <<= 1; 607 c >>= 1; 608 if (carry) 609 crc = (crc ^ 0x04c11db6) | carry; 610 } 611 } 612 613 /* 614 * return the filter bit position 615 * Note: I arrived at the following nonsense 616 * through experimentation. It's not the usual way to 617 * generate the bit position but it's the only thing 618 * I could come up with that works. 619 */ 620 return(~(crc >> 26) & 0x0000003F); 621} 622 623/* 624 * Program the 64-bit multicast hash filter. 625 */ 626static void 627wb_setmulti(sc) 628 struct wb_softc *sc; 629{ 630 struct ifnet *ifp; 631 int h = 0; 632 u_int32_t hashes[2] = { 0, 0 }; 633 struct ifmultiaddr *ifma; 634 u_int32_t rxfilt; 635 int mcnt = 0; 636 637 ifp = &sc->arpcom.ac_if; 638 639 rxfilt = CSR_READ_4(sc, WB_NETCFG); 640 641 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 642 rxfilt |= WB_NETCFG_RX_MULTI; 643 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 644 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 645 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 646 return; 647 } 648 649 /* first, zot all the existing hash bits */ 650 CSR_WRITE_4(sc, WB_MAR0, 0); 651 CSR_WRITE_4(sc, WB_MAR1, 0); 652 653 /* now program new ones */ 654 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 655 if (ifma->ifma_addr->sa_family != AF_LINK) 656 continue; 657 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 658 if (h < 32) 659 hashes[0] |= (1 << h); 660 else 661 hashes[1] |= (1 << (h - 32)); 662 mcnt++; 663 } 664 665 if (mcnt) 666 rxfilt |= WB_NETCFG_RX_MULTI; 667 else 668 rxfilt &= ~WB_NETCFG_RX_MULTI; 669 670 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 671 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 672 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 673 674 return; 675} 676 677/* 678 * The Winbond manual states that in order to fiddle with the 679 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 680 * first have to put the transmit and/or receive logic in the idle state. 681 */ 682static void 683wb_setcfg(sc, media) 684 struct wb_softc *sc; 685 u_int32_t media; 686{ 687 int i, restart = 0; 688 689 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 690 restart = 1; 691 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 692 693 for (i = 0; i < WB_TIMEOUT; i++) { 694 DELAY(10); 695 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 696 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 697 break; 698 } 699 700 if (i == WB_TIMEOUT) 701 printf("wb%d: failed to force tx and " 702 "rx to idle state\n", sc->wb_unit); 703 } 704 705 if (IFM_SUBTYPE(media) == IFM_10_T) 706 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 707 else 708 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 709 710 if ((media & IFM_GMASK) == IFM_FDX) 711 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 712 else 713 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 714 715 if (restart) 716 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 717 718 return; 719} 720 721static void 722wb_reset(sc) 723 struct wb_softc *sc; 724{ 725 register int i; 726 struct mii_data *mii; 727 728 CSR_WRITE_4(sc, WB_NETCFG, 0); 729 CSR_WRITE_4(sc, WB_BUSCTL, 0); 730 CSR_WRITE_4(sc, WB_TXADDR, 0); 731 CSR_WRITE_4(sc, WB_RXADDR, 0); 732 733 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 734 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 735 736 for (i = 0; i < WB_TIMEOUT; i++) { 737 DELAY(10); 738 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 739 break; 740 } 741 if (i == WB_TIMEOUT) 742 printf("wb%d: reset never completed!\n", sc->wb_unit); 743 744 /* Wait a little while for the chip to get its brains in order. */ 745 DELAY(1000); 746 747 if (sc->wb_miibus == NULL) 748 return; 749 750 mii = device_get_softc(sc->wb_miibus); 751 if (mii == NULL) 752 return; 753 754 if (mii->mii_instance) { 755 struct mii_softc *miisc; 756 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 757 mii_phy_reset(miisc); 758 } 759 760 return; 761} 762 763static void 764wb_fixmedia(sc) 765 struct wb_softc *sc; 766{ 767 struct mii_data *mii = NULL; 768 struct ifnet *ifp; 769 u_int32_t media; 770 771 if (sc->wb_miibus == NULL) 772 return; 773 774 mii = device_get_softc(sc->wb_miibus); 775 ifp = &sc->arpcom.ac_if; 776 777 mii_pollstat(mii); 778 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 779 media = mii->mii_media_active & ~IFM_10_T; 780 media |= IFM_100_TX; 781 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 782 media = mii->mii_media_active & ~IFM_100_TX; 783 media |= IFM_10_T; 784 } else 785 return; 786 787 ifmedia_set(&mii->mii_media, media); 788 789 return; 790} 791 792/* 793 * Probe for a Winbond chip. Check the PCI vendor and device 794 * IDs against our list and return a device name if we find a match. 795 */ 796static int 797wb_probe(dev) 798 device_t dev; 799{ 800 struct wb_type *t; 801 802 t = wb_devs; 803 804 while(t->wb_name != NULL) { 805 if ((pci_get_vendor(dev) == t->wb_vid) && 806 (pci_get_device(dev) == t->wb_did)) { 807 device_set_desc(dev, t->wb_name); 808 return(0); 809 } 810 t++; 811 } 812 813 return(ENXIO); 814} 815 816/* 817 * Attach the interface. Allocate softc structures, do ifmedia 818 * setup and ethernet/BPF attach. 819 */ 820static int 821wb_attach(dev) 822 device_t dev; 823{ 824 u_char eaddr[ETHER_ADDR_LEN]; 825 u_int32_t command; 826 struct wb_softc *sc; 827 struct ifnet *ifp; 828 int unit, error = 0, rid; 829 830 sc = device_get_softc(dev); 831 unit = device_get_unit(dev); 832 833 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 834 MTX_DEF | MTX_RECURSE); 835 836 /* 837 * Handle power management nonsense. 838 */ 839 840 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 841 u_int32_t iobase, membase, irq; 842 843 /* Save important PCI config data. */ 844 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 845 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 846 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 847 848 /* Reset the power state. */ 849 printf("wb%d: chip is in D%d power mode " 850 "-- setting to D0\n", unit, 851 pci_get_powerstate(dev)); 852 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 853 854 /* Restore PCI config data. */ 855 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 856 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 857 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 858 } 859 860 /* 861 * Map control/status registers. 862 */ 863 pci_enable_busmaster(dev); 864 pci_enable_io(dev, SYS_RES_IOPORT); 865 pci_enable_io(dev, SYS_RES_MEMORY); 866 command = pci_read_config(dev, PCIR_COMMAND, 4); 867 868#ifdef WB_USEIOSPACE 869 if (!(command & PCIM_CMD_PORTEN)) { 870 printf("wb%d: failed to enable I/O ports!\n", unit); 871 error = ENXIO; 872 goto fail; 873 } 874#else 875 if (!(command & PCIM_CMD_MEMEN)) { 876 printf("wb%d: failed to enable memory mapping!\n", unit); 877 error = ENXIO; 878 goto fail; 879 } 880#endif 881 882 rid = WB_RID; 883 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 884 0, ~0, 1, RF_ACTIVE); 885 886 if (sc->wb_res == NULL) { 887 printf("wb%d: couldn't map ports/memory\n", unit); 888 error = ENXIO; 889 goto fail; 890 } 891 892 sc->wb_btag = rman_get_bustag(sc->wb_res); 893 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 894 895 /* Allocate interrupt */ 896 rid = 0; 897 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 898 RF_SHAREABLE | RF_ACTIVE); 899 900 if (sc->wb_irq == NULL) { 901 printf("wb%d: couldn't map interrupt\n", unit); 902 error = ENXIO; 903 goto fail; 904 } 905 906 /* Save the cache line size. */ 907 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 908 909 /* Reset the adapter. */ 910 wb_reset(sc); 911 912 /* 913 * Get station address from the EEPROM. 914 */ 915 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 916 917 /* 918 * A Winbond chip was detected. Inform the world. 919 */ 920 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 921 922 sc->wb_unit = unit; 923 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 924 925 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 926 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 927 928 if (sc->wb_ldata == NULL) { 929 printf("wb%d: no memory for list buffers!\n", unit); 930 error = ENXIO; 931 goto fail; 932 } 933 934 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 935 936 ifp = &sc->arpcom.ac_if; 937 ifp->if_softc = sc; 938 ifp->if_unit = unit; 939 ifp->if_name = "wb"; 940 ifp->if_mtu = ETHERMTU; 941 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 942 ifp->if_ioctl = wb_ioctl; 943 ifp->if_output = ether_output; 944 ifp->if_start = wb_start; 945 ifp->if_watchdog = wb_watchdog; 946 ifp->if_init = wb_init; 947 ifp->if_baudrate = 10000000; 948 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 949 950 /* 951 * Do MII setup. 952 */ 953 if (mii_phy_probe(dev, &sc->wb_miibus, 954 wb_ifmedia_upd, wb_ifmedia_sts)) { 955 error = ENXIO; 956 goto fail; 957 } 958 959 /* 960 * Call MI attach routine. 961 */ 962 ether_ifattach(ifp, eaddr); 963 964 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 965 wb_intr, sc, &sc->wb_intrhand); 966 967 if (error) { 968 printf("wb%d: couldn't set up irq\n", unit); 969 goto fail; 970 } 971 972fail: 973 if (error) 974 wb_detach(dev); 975 976 return(error); 977} 978 979static int 980wb_detach(dev) 981 device_t dev; 982{ 983 struct wb_softc *sc; 984 struct ifnet *ifp; 985 986 sc = device_get_softc(dev); 987 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 988 WB_LOCK(sc); 989 ifp = &sc->arpcom.ac_if; 990 991 /* Delete any miibus and phy devices attached to this interface */ 992 if (device_is_alive(dev)) { 993 if (bus_child_present(dev)) 994 wb_stop(sc); 995 ether_ifdetach(ifp); 996 device_delete_child(dev, sc->wb_miibus); 997 bus_generic_detach(dev); 998 } 999 1000 if (sc->wb_intrhand) 1001 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1002 if (sc->wb_irq) 1003 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1004 if (sc->wb_res) 1005 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1006 1007 if (sc->wb_ldata) { 1008 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 1009 M_DEVBUF); 1010 } 1011 1012 WB_UNLOCK(sc); 1013 mtx_destroy(&sc->wb_mtx); 1014 1015 return(0); 1016} 1017 1018/* 1019 * Initialize the transmit descriptors. 1020 */ 1021static int 1022wb_list_tx_init(sc) 1023 struct wb_softc *sc; 1024{ 1025 struct wb_chain_data *cd; 1026 struct wb_list_data *ld; 1027 int i; 1028 1029 cd = &sc->wb_cdata; 1030 ld = sc->wb_ldata; 1031 1032 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1033 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1034 if (i == (WB_TX_LIST_CNT - 1)) { 1035 cd->wb_tx_chain[i].wb_nextdesc = 1036 &cd->wb_tx_chain[0]; 1037 } else { 1038 cd->wb_tx_chain[i].wb_nextdesc = 1039 &cd->wb_tx_chain[i + 1]; 1040 } 1041 } 1042 1043 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1044 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1045 1046 return(0); 1047} 1048 1049 1050/* 1051 * Initialize the RX descriptors and allocate mbufs for them. Note that 1052 * we arrange the descriptors in a closed ring, so that the last descriptor 1053 * points back to the first. 1054 */ 1055static int 1056wb_list_rx_init(sc) 1057 struct wb_softc *sc; 1058{ 1059 struct wb_chain_data *cd; 1060 struct wb_list_data *ld; 1061 int i; 1062 1063 cd = &sc->wb_cdata; 1064 ld = sc->wb_ldata; 1065 1066 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1067 cd->wb_rx_chain[i].wb_ptr = 1068 (struct wb_desc *)&ld->wb_rx_list[i]; 1069 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1070 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1071 return(ENOBUFS); 1072 if (i == (WB_RX_LIST_CNT - 1)) { 1073 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1074 ld->wb_rx_list[i].wb_next = 1075 vtophys(&ld->wb_rx_list[0]); 1076 } else { 1077 cd->wb_rx_chain[i].wb_nextdesc = 1078 &cd->wb_rx_chain[i + 1]; 1079 ld->wb_rx_list[i].wb_next = 1080 vtophys(&ld->wb_rx_list[i + 1]); 1081 } 1082 } 1083 1084 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1085 1086 return(0); 1087} 1088 1089static void 1090wb_bfree(buf, args) 1091 void *buf; 1092 void *args; 1093{ 1094 return; 1095} 1096 1097/* 1098 * Initialize an RX descriptor and attach an MBUF cluster. 1099 */ 1100static int 1101wb_newbuf(sc, c, m) 1102 struct wb_softc *sc; 1103 struct wb_chain_onefrag *c; 1104 struct mbuf *m; 1105{ 1106 struct mbuf *m_new = NULL; 1107 1108 if (m == NULL) { 1109 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1110 if (m_new == NULL) 1111 return(ENOBUFS); 1112 m_new->m_data = c->wb_buf; 1113 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1114 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1115 EXT_NET_DRV); 1116 } else { 1117 m_new = m; 1118 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1119 m_new->m_data = m_new->m_ext.ext_buf; 1120 } 1121 1122 m_adj(m_new, sizeof(u_int64_t)); 1123 1124 c->wb_mbuf = m_new; 1125 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1126 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1127 c->wb_ptr->wb_status = WB_RXSTAT; 1128 1129 return(0); 1130} 1131 1132/* 1133 * A frame has been uploaded: pass the resulting mbuf chain up to 1134 * the higher level protocols. 1135 */ 1136static void 1137wb_rxeof(sc) 1138 struct wb_softc *sc; 1139{ 1140 struct mbuf *m = NULL; 1141 struct ifnet *ifp; 1142 struct wb_chain_onefrag *cur_rx; 1143 int total_len = 0; 1144 u_int32_t rxstat; 1145 1146 ifp = &sc->arpcom.ac_if; 1147 1148 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1149 WB_RXSTAT_OWN)) { 1150 struct mbuf *m0 = NULL; 1151 1152 cur_rx = sc->wb_cdata.wb_rx_head; 1153 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1154 1155 m = cur_rx->wb_mbuf; 1156 1157 if ((rxstat & WB_RXSTAT_MIIERR) || 1158 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1159 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1160 !(rxstat & WB_RXSTAT_LASTFRAG) || 1161 !(rxstat & WB_RXSTAT_RXCMP)) { 1162 ifp->if_ierrors++; 1163 wb_newbuf(sc, cur_rx, m); 1164 printf("wb%x: receiver babbling: possible chip " 1165 "bug, forcing reset\n", sc->wb_unit); 1166 wb_fixmedia(sc); 1167 wb_reset(sc); 1168 wb_init(sc); 1169 return; 1170 } 1171 1172 if (rxstat & WB_RXSTAT_RXERR) { 1173 ifp->if_ierrors++; 1174 wb_newbuf(sc, cur_rx, m); 1175 break; 1176 } 1177 1178 /* No errors; receive the packet. */ 1179 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1180 1181 /* 1182 * XXX The Winbond chip includes the CRC with every 1183 * received frame, and there's no way to turn this 1184 * behavior off (at least, I can't find anything in 1185 * the manual that explains how to do it) so we have 1186 * to trim off the CRC manually. 1187 */ 1188 total_len -= ETHER_CRC_LEN; 1189 1190 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1191 NULL); 1192 wb_newbuf(sc, cur_rx, m); 1193 if (m0 == NULL) { 1194 ifp->if_ierrors++; 1195 break; 1196 } 1197 m = m0; 1198 1199 ifp->if_ipackets++; 1200 (*ifp->if_input)(ifp, m); 1201 } 1202} 1203 1204static void 1205wb_rxeoc(sc) 1206 struct wb_softc *sc; 1207{ 1208 wb_rxeof(sc); 1209 1210 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1211 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1212 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1213 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1214 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1215 1216 return; 1217} 1218 1219/* 1220 * A frame was downloaded to the chip. It's safe for us to clean up 1221 * the list buffers. 1222 */ 1223static void 1224wb_txeof(sc) 1225 struct wb_softc *sc; 1226{ 1227 struct wb_chain *cur_tx; 1228 struct ifnet *ifp; 1229 1230 ifp = &sc->arpcom.ac_if; 1231 1232 /* Clear the timeout timer. */ 1233 ifp->if_timer = 0; 1234 1235 if (sc->wb_cdata.wb_tx_head == NULL) 1236 return; 1237 1238 /* 1239 * Go through our tx list and free mbufs for those 1240 * frames that have been transmitted. 1241 */ 1242 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1243 u_int32_t txstat; 1244 1245 cur_tx = sc->wb_cdata.wb_tx_head; 1246 txstat = WB_TXSTATUS(cur_tx); 1247 1248 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1249 break; 1250 1251 if (txstat & WB_TXSTAT_TXERR) { 1252 ifp->if_oerrors++; 1253 if (txstat & WB_TXSTAT_ABORT) 1254 ifp->if_collisions++; 1255 if (txstat & WB_TXSTAT_LATECOLL) 1256 ifp->if_collisions++; 1257 } 1258 1259 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1260 1261 ifp->if_opackets++; 1262 m_freem(cur_tx->wb_mbuf); 1263 cur_tx->wb_mbuf = NULL; 1264 1265 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1266 sc->wb_cdata.wb_tx_head = NULL; 1267 sc->wb_cdata.wb_tx_tail = NULL; 1268 break; 1269 } 1270 1271 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1272 } 1273 1274 return; 1275} 1276 1277/* 1278 * TX 'end of channel' interrupt handler. 1279 */ 1280static void 1281wb_txeoc(sc) 1282 struct wb_softc *sc; 1283{ 1284 struct ifnet *ifp; 1285 1286 ifp = &sc->arpcom.ac_if; 1287 1288 ifp->if_timer = 0; 1289 1290 if (sc->wb_cdata.wb_tx_head == NULL) { 1291 ifp->if_flags &= ~IFF_OACTIVE; 1292 sc->wb_cdata.wb_tx_tail = NULL; 1293 } else { 1294 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1295 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1296 ifp->if_timer = 5; 1297 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1298 } 1299 } 1300 1301 return; 1302} 1303 1304static void 1305wb_intr(arg) 1306 void *arg; 1307{ 1308 struct wb_softc *sc; 1309 struct ifnet *ifp; 1310 u_int32_t status; 1311 1312 sc = arg; 1313 WB_LOCK(sc); 1314 ifp = &sc->arpcom.ac_if; 1315 1316 if (!(ifp->if_flags & IFF_UP)) { 1317 WB_UNLOCK(sc); 1318 return; 1319 } 1320 1321 /* Disable interrupts. */ 1322 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1323 1324 for (;;) { 1325 1326 status = CSR_READ_4(sc, WB_ISR); 1327 if (status) 1328 CSR_WRITE_4(sc, WB_ISR, status); 1329 1330 if ((status & WB_INTRS) == 0) 1331 break; 1332 1333 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1334 ifp->if_ierrors++; 1335 wb_reset(sc); 1336 if (status & WB_ISR_RX_ERR) 1337 wb_fixmedia(sc); 1338 wb_init(sc); 1339 continue; 1340 } 1341 1342 if (status & WB_ISR_RX_OK) 1343 wb_rxeof(sc); 1344 1345 if (status & WB_ISR_RX_IDLE) 1346 wb_rxeoc(sc); 1347 1348 if (status & WB_ISR_TX_OK) 1349 wb_txeof(sc); 1350 1351 if (status & WB_ISR_TX_NOBUF) 1352 wb_txeoc(sc); 1353 1354 if (status & WB_ISR_TX_IDLE) { 1355 wb_txeof(sc); 1356 if (sc->wb_cdata.wb_tx_head != NULL) { 1357 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1358 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1359 } 1360 } 1361 1362 if (status & WB_ISR_TX_UNDERRUN) { 1363 ifp->if_oerrors++; 1364 wb_txeof(sc); 1365 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1366 /* Jack up TX threshold */ 1367 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1368 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1369 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1370 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1371 } 1372 1373 if (status & WB_ISR_BUS_ERR) { 1374 wb_reset(sc); 1375 wb_init(sc); 1376 } 1377 1378 } 1379 1380 /* Re-enable interrupts. */ 1381 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1382 1383 if (ifp->if_snd.ifq_head != NULL) { 1384 wb_start(ifp); 1385 } 1386 1387 WB_UNLOCK(sc); 1388 1389 return; 1390} 1391 1392static void 1393wb_tick(xsc) 1394 void *xsc; 1395{ 1396 struct wb_softc *sc; 1397 struct mii_data *mii; 1398 1399 sc = xsc; 1400 WB_LOCK(sc); 1401 mii = device_get_softc(sc->wb_miibus); 1402 1403 mii_tick(mii); 1404 1405 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1406 1407 WB_UNLOCK(sc); 1408 1409 return; 1410} 1411 1412/* 1413 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1414 * pointers to the fragment pointers. 1415 */ 1416static int 1417wb_encap(sc, c, m_head) 1418 struct wb_softc *sc; 1419 struct wb_chain *c; 1420 struct mbuf *m_head; 1421{ 1422 int frag = 0; 1423 struct wb_desc *f = NULL; 1424 int total_len; 1425 struct mbuf *m; 1426 1427 /* 1428 * Start packing the mbufs in this chain into 1429 * the fragment pointers. Stop when we run out 1430 * of fragments or hit the end of the mbuf chain. 1431 */ 1432 m = m_head; 1433 total_len = 0; 1434 1435 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1436 if (m->m_len != 0) { 1437 if (frag == WB_MAXFRAGS) 1438 break; 1439 total_len += m->m_len; 1440 f = &c->wb_ptr->wb_frag[frag]; 1441 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1442 if (frag == 0) { 1443 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1444 f->wb_status = 0; 1445 } else 1446 f->wb_status = WB_TXSTAT_OWN; 1447 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1448 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1449 frag++; 1450 } 1451 } 1452 1453 /* 1454 * Handle special case: we used up all 16 fragments, 1455 * but we have more mbufs left in the chain. Copy the 1456 * data into an mbuf cluster. Note that we don't 1457 * bother clearing the values in the other fragment 1458 * pointers/counters; it wouldn't gain us anything, 1459 * and would waste cycles. 1460 */ 1461 if (m != NULL) { 1462 struct mbuf *m_new = NULL; 1463 1464 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1465 if (m_new == NULL) 1466 return(1); 1467 if (m_head->m_pkthdr.len > MHLEN) { 1468 MCLGET(m_new, M_DONTWAIT); 1469 if (!(m_new->m_flags & M_EXT)) { 1470 m_freem(m_new); 1471 return(1); 1472 } 1473 } 1474 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1475 mtod(m_new, caddr_t)); 1476 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1477 m_freem(m_head); 1478 m_head = m_new; 1479 f = &c->wb_ptr->wb_frag[0]; 1480 f->wb_status = 0; 1481 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1482 f->wb_ctl = total_len = m_new->m_len; 1483 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1484 frag = 1; 1485 } 1486 1487 if (total_len < WB_MIN_FRAMELEN) { 1488 f = &c->wb_ptr->wb_frag[frag]; 1489 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1490 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1491 f->wb_ctl |= WB_TXCTL_TLINK; 1492 f->wb_status = WB_TXSTAT_OWN; 1493 frag++; 1494 } 1495 1496 c->wb_mbuf = m_head; 1497 c->wb_lastdesc = frag - 1; 1498 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1499 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1500 1501 return(0); 1502} 1503 1504/* 1505 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1506 * to the mbuf data regions directly in the transmit lists. We also save a 1507 * copy of the pointers since the transmit list fragment pointers are 1508 * physical addresses. 1509 */ 1510 1511static void 1512wb_start(ifp) 1513 struct ifnet *ifp; 1514{ 1515 struct wb_softc *sc; 1516 struct mbuf *m_head = NULL; 1517 struct wb_chain *cur_tx = NULL, *start_tx; 1518 1519 sc = ifp->if_softc; 1520 WB_LOCK(sc); 1521 1522 /* 1523 * Check for an available queue slot. If there are none, 1524 * punt. 1525 */ 1526 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1527 ifp->if_flags |= IFF_OACTIVE; 1528 WB_UNLOCK(sc); 1529 return; 1530 } 1531 1532 start_tx = sc->wb_cdata.wb_tx_free; 1533 1534 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1535 IF_DEQUEUE(&ifp->if_snd, m_head); 1536 if (m_head == NULL) 1537 break; 1538 1539 /* Pick a descriptor off the free list. */ 1540 cur_tx = sc->wb_cdata.wb_tx_free; 1541 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1542 1543 /* Pack the data into the descriptor. */ 1544 wb_encap(sc, cur_tx, m_head); 1545 1546 if (cur_tx != start_tx) 1547 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1548 1549 /* 1550 * If there's a BPF listener, bounce a copy of this frame 1551 * to him. 1552 */ 1553 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1554 } 1555 1556 /* 1557 * If there are no packets queued, bail. 1558 */ 1559 if (cur_tx == NULL) { 1560 WB_UNLOCK(sc); 1561 return; 1562 } 1563 1564 /* 1565 * Place the request for the upload interrupt 1566 * in the last descriptor in the chain. This way, if 1567 * we're chaining several packets at once, we'll only 1568 * get an interupt once for the whole chain rather than 1569 * once for each packet. 1570 */ 1571 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1572 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1573 sc->wb_cdata.wb_tx_tail = cur_tx; 1574 1575 if (sc->wb_cdata.wb_tx_head == NULL) { 1576 sc->wb_cdata.wb_tx_head = start_tx; 1577 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1578 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1579 } else { 1580 /* 1581 * We need to distinguish between the case where 1582 * the own bit is clear because the chip cleared it 1583 * and where the own bit is clear because we haven't 1584 * set it yet. The magic value WB_UNSET is just some 1585 * ramdomly chosen number which doesn't have the own 1586 * bit set. When we actually transmit the frame, the 1587 * status word will have _only_ the own bit set, so 1588 * the txeoc handler will be able to tell if it needs 1589 * to initiate another transmission to flush out pending 1590 * frames. 1591 */ 1592 WB_TXOWN(start_tx) = WB_UNSENT; 1593 } 1594 1595 /* 1596 * Set a timeout in case the chip goes out to lunch. 1597 */ 1598 ifp->if_timer = 5; 1599 WB_UNLOCK(sc); 1600 1601 return; 1602} 1603 1604static void 1605wb_init(xsc) 1606 void *xsc; 1607{ 1608 struct wb_softc *sc = xsc; 1609 struct ifnet *ifp = &sc->arpcom.ac_if; 1610 int i; 1611 struct mii_data *mii; 1612 1613 WB_LOCK(sc); 1614 mii = device_get_softc(sc->wb_miibus); 1615 1616 /* 1617 * Cancel pending I/O and free all RX/TX buffers. 1618 */ 1619 wb_stop(sc); 1620 wb_reset(sc); 1621 1622 sc->wb_txthresh = WB_TXTHRESH_INIT; 1623 1624 /* 1625 * Set cache alignment and burst length. 1626 */ 1627#ifdef foo 1628 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1629 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1630 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1631#endif 1632 1633 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1634 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1635 switch(sc->wb_cachesize) { 1636 case 32: 1637 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1638 break; 1639 case 16: 1640 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1641 break; 1642 case 8: 1643 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1644 break; 1645 case 0: 1646 default: 1647 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1648 break; 1649 } 1650 1651 /* This doesn't tend to work too well at 100Mbps. */ 1652 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1653 1654 /* Init our MAC address */ 1655 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1656 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1657 } 1658 1659 /* Init circular RX list. */ 1660 if (wb_list_rx_init(sc) == ENOBUFS) { 1661 printf("wb%d: initialization failed: no " 1662 "memory for rx buffers\n", sc->wb_unit); 1663 wb_stop(sc); 1664 WB_UNLOCK(sc); 1665 return; 1666 } 1667 1668 /* Init TX descriptors. */ 1669 wb_list_tx_init(sc); 1670 1671 /* If we want promiscuous mode, set the allframes bit. */ 1672 if (ifp->if_flags & IFF_PROMISC) { 1673 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1674 } else { 1675 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1676 } 1677 1678 /* 1679 * Set capture broadcast bit to capture broadcast frames. 1680 */ 1681 if (ifp->if_flags & IFF_BROADCAST) { 1682 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1683 } else { 1684 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1685 } 1686 1687 /* 1688 * Program the multicast filter, if necessary. 1689 */ 1690 wb_setmulti(sc); 1691 1692 /* 1693 * Load the address of the RX list. 1694 */ 1695 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1696 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1697 1698 /* 1699 * Enable interrupts. 1700 */ 1701 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1702 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1703 1704 /* Enable receiver and transmitter. */ 1705 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1706 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1707 1708 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1709 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1710 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1711 1712 mii_mediachg(mii); 1713 1714 ifp->if_flags |= IFF_RUNNING; 1715 ifp->if_flags &= ~IFF_OACTIVE; 1716 1717 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1718 WB_UNLOCK(sc); 1719 1720 return; 1721} 1722 1723/* 1724 * Set media options. 1725 */ 1726static int 1727wb_ifmedia_upd(ifp) 1728 struct ifnet *ifp; 1729{ 1730 struct wb_softc *sc; 1731 1732 sc = ifp->if_softc; 1733 1734 if (ifp->if_flags & IFF_UP) 1735 wb_init(sc); 1736 1737 return(0); 1738} 1739 1740/* 1741 * Report current media status. 1742 */ 1743static void 1744wb_ifmedia_sts(ifp, ifmr) 1745 struct ifnet *ifp; 1746 struct ifmediareq *ifmr; 1747{ 1748 struct wb_softc *sc; 1749 struct mii_data *mii; 1750 1751 sc = ifp->if_softc; 1752 1753 mii = device_get_softc(sc->wb_miibus); 1754 1755 mii_pollstat(mii); 1756 ifmr->ifm_active = mii->mii_media_active; 1757 ifmr->ifm_status = mii->mii_media_status; 1758 1759 return; 1760} 1761 1762static int 1763wb_ioctl(ifp, command, data) 1764 struct ifnet *ifp; 1765 u_long command; 1766 caddr_t data; 1767{ 1768 struct wb_softc *sc = ifp->if_softc; 1769 struct mii_data *mii; 1770 struct ifreq *ifr = (struct ifreq *) data; 1771 int error = 0; 1772 1773 WB_LOCK(sc); 1774 1775 switch(command) { 1776 case SIOCSIFFLAGS: 1777 if (ifp->if_flags & IFF_UP) { 1778 wb_init(sc); 1779 } else { 1780 if (ifp->if_flags & IFF_RUNNING) 1781 wb_stop(sc); 1782 } 1783 error = 0; 1784 break; 1785 case SIOCADDMULTI: 1786 case SIOCDELMULTI: 1787 wb_setmulti(sc); 1788 error = 0; 1789 break; 1790 case SIOCGIFMEDIA: 1791 case SIOCSIFMEDIA: 1792 mii = device_get_softc(sc->wb_miibus); 1793 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1794 break; 1795 default: 1796 error = ether_ioctl(ifp, command, data); 1797 break; 1798 } 1799 1800 WB_UNLOCK(sc); 1801 1802 return(error); 1803} 1804 1805static void 1806wb_watchdog(ifp) 1807 struct ifnet *ifp; 1808{ 1809 struct wb_softc *sc; 1810 1811 sc = ifp->if_softc; 1812 1813 WB_LOCK(sc); 1814 ifp->if_oerrors++; 1815 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1816#ifdef foo 1817 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1818 printf("wb%d: no carrier - transceiver cable problem?\n", 1819 sc->wb_unit); 1820#endif 1821 wb_stop(sc); 1822 wb_reset(sc); 1823 wb_init(sc); 1824 1825 if (ifp->if_snd.ifq_head != NULL) 1826 wb_start(ifp); 1827 WB_UNLOCK(sc); 1828 1829 return; 1830} 1831 1832/* 1833 * Stop the adapter and free any mbufs allocated to the 1834 * RX and TX lists. 1835 */ 1836static void 1837wb_stop(sc) 1838 struct wb_softc *sc; 1839{ 1840 register int i; 1841 struct ifnet *ifp; 1842 1843 WB_LOCK(sc); 1844 ifp = &sc->arpcom.ac_if; 1845 ifp->if_timer = 0; 1846 1847 untimeout(wb_tick, sc, sc->wb_stat_ch); 1848 1849 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1850 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1851 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1852 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1853 1854 /* 1855 * Free data in the RX lists. 1856 */ 1857 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1858 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1859 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1860 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1861 } 1862 } 1863 bzero((char *)&sc->wb_ldata->wb_rx_list, 1864 sizeof(sc->wb_ldata->wb_rx_list)); 1865 1866 /* 1867 * Free the TX list buffers. 1868 */ 1869 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1870 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1871 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1872 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1873 } 1874 } 1875 1876 bzero((char *)&sc->wb_ldata->wb_tx_list, 1877 sizeof(sc->wb_ldata->wb_tx_list)); 1878 1879 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1880 WB_UNLOCK(sc); 1881 1882 return; 1883} 1884 1885/* 1886 * Stop all chip I/O so that the kernel's probe routines don't 1887 * get confused by errant DMAs when rebooting. 1888 */ 1889static void 1890wb_shutdown(dev) 1891 device_t dev; 1892{ 1893 struct wb_softc *sc; 1894 1895 sc = device_get_softc(dev); 1896 wb_stop(sc); 1897 1898 return; 1899} 1900