if_wb.c revision 102336
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_wb.c 102336 2002-08-24 00:02:03Z alfred $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus_memio.h> 108#include <machine/bus_pio.h> 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#include <dev/mii/mii.h> 118#include <dev/mii/miivar.h> 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <pci/if_wbreg.h> 126 127MODULE_DEPEND(wb, miibus, 1, 1, 1); 128 129#ifndef lint 130static const char rcsid[] = 131 "$FreeBSD: head/sys/pci/if_wb.c 102336 2002-08-24 00:02:03Z alfred $"; 132#endif 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137static struct wb_type wb_devs[] = { 138 { WB_VENDORID, WB_DEVICEID_840F, 139 "Winbond W89C840F 10/100BaseTX" }, 140 { CP_VENDORID, CP_DEVICEID_RL100, 141 "Compex RL100-ATX 10/100baseTX" }, 142 { 0, 0, NULL } 143}; 144 145static int wb_probe (device_t); 146static int wb_attach (device_t); 147static int wb_detach (device_t); 148 149static void wb_bfree (void *addr, void *args); 150static int wb_newbuf (struct wb_softc *, 151 struct wb_chain_onefrag *, 152 struct mbuf *); 153static int wb_encap (struct wb_softc *, struct wb_chain *, 154 struct mbuf *); 155 156static void wb_rxeof (struct wb_softc *); 157static void wb_rxeoc (struct wb_softc *); 158static void wb_txeof (struct wb_softc *); 159static void wb_txeoc (struct wb_softc *); 160static void wb_intr (void *); 161static void wb_tick (void *); 162static void wb_start (struct ifnet *); 163static int wb_ioctl (struct ifnet *, u_long, caddr_t); 164static void wb_init (void *); 165static void wb_stop (struct wb_softc *); 166static void wb_watchdog (struct ifnet *); 167static void wb_shutdown (device_t); 168static int wb_ifmedia_upd (struct ifnet *); 169static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 170 171static void wb_eeprom_putbyte (struct wb_softc *, int); 172static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 173static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 174static void wb_mii_sync (struct wb_softc *); 175static void wb_mii_send (struct wb_softc *, u_int32_t, int); 176static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 177static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 178 179static void wb_setcfg (struct wb_softc *, u_int32_t); 180static u_int8_t wb_calchash (caddr_t); 181static void wb_setmulti (struct wb_softc *); 182static void wb_reset (struct wb_softc *); 183static void wb_fixmedia (struct wb_softc *); 184static int wb_list_rx_init (struct wb_softc *); 185static int wb_list_tx_init (struct wb_softc *); 186 187static int wb_miibus_readreg (device_t, int, int); 188static int wb_miibus_writereg (device_t, int, int, int); 189static void wb_miibus_statchg (device_t); 190 191#ifdef WB_USEIOSPACE 192#define WB_RES SYS_RES_IOPORT 193#define WB_RID WB_PCI_LOIO 194#else 195#define WB_RES SYS_RES_MEMORY 196#define WB_RID WB_PCI_LOMEM 197#endif 198 199static device_method_t wb_methods[] = { 200 /* Device interface */ 201 DEVMETHOD(device_probe, wb_probe), 202 DEVMETHOD(device_attach, wb_attach), 203 DEVMETHOD(device_detach, wb_detach), 204 DEVMETHOD(device_shutdown, wb_shutdown), 205 206 /* bus interface, for miibus */ 207 DEVMETHOD(bus_print_child, bus_generic_print_child), 208 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 209 210 /* MII interface */ 211 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 212 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 213 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 214 { 0, 0 } 215}; 216 217static driver_t wb_driver = { 218 "wb", 219 wb_methods, 220 sizeof(struct wb_softc) 221}; 222 223static devclass_t wb_devclass; 224 225DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 226DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 227 228#define WB_SETBIT(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, \ 230 CSR_READ_4(sc, reg) | x) 231 232#define WB_CLRBIT(sc, reg, x) \ 233 CSR_WRITE_4(sc, reg, \ 234 CSR_READ_4(sc, reg) & ~x) 235 236#define SIO_SET(x) \ 237 CSR_WRITE_4(sc, WB_SIO, \ 238 CSR_READ_4(sc, WB_SIO) | x) 239 240#define SIO_CLR(x) \ 241 CSR_WRITE_4(sc, WB_SIO, \ 242 CSR_READ_4(sc, WB_SIO) & ~x) 243 244/* 245 * Send a read command and address to the EEPROM, check for ACK. 246 */ 247static void 248wb_eeprom_putbyte(sc, addr) 249 struct wb_softc *sc; 250 int addr; 251{ 252 register int d, i; 253 254 d = addr | WB_EECMD_READ; 255 256 /* 257 * Feed in each bit and stobe the clock. 258 */ 259 for (i = 0x400; i; i >>= 1) { 260 if (d & i) { 261 SIO_SET(WB_SIO_EE_DATAIN); 262 } else { 263 SIO_CLR(WB_SIO_EE_DATAIN); 264 } 265 DELAY(100); 266 SIO_SET(WB_SIO_EE_CLK); 267 DELAY(150); 268 SIO_CLR(WB_SIO_EE_CLK); 269 DELAY(100); 270 } 271 272 return; 273} 274 275/* 276 * Read a word of data stored in the EEPROM at address 'addr.' 277 */ 278static void 279wb_eeprom_getword(sc, addr, dest) 280 struct wb_softc *sc; 281 int addr; 282 u_int16_t *dest; 283{ 284 register int i; 285 u_int16_t word = 0; 286 287 /* Enter EEPROM access mode. */ 288 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 289 290 /* 291 * Send address of word we want to read. 292 */ 293 wb_eeprom_putbyte(sc, addr); 294 295 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 296 297 /* 298 * Start reading bits from EEPROM. 299 */ 300 for (i = 0x8000; i; i >>= 1) { 301 SIO_SET(WB_SIO_EE_CLK); 302 DELAY(100); 303 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 304 word |= i; 305 SIO_CLR(WB_SIO_EE_CLK); 306 DELAY(100); 307 } 308 309 /* Turn off EEPROM access mode. */ 310 CSR_WRITE_4(sc, WB_SIO, 0); 311 312 *dest = word; 313 314 return; 315} 316 317/* 318 * Read a sequence of words from the EEPROM. 319 */ 320static void 321wb_read_eeprom(sc, dest, off, cnt, swap) 322 struct wb_softc *sc; 323 caddr_t dest; 324 int off; 325 int cnt; 326 int swap; 327{ 328 int i; 329 u_int16_t word = 0, *ptr; 330 331 for (i = 0; i < cnt; i++) { 332 wb_eeprom_getword(sc, off + i, &word); 333 ptr = (u_int16_t *)(dest + (i * 2)); 334 if (swap) 335 *ptr = ntohs(word); 336 else 337 *ptr = word; 338 } 339 340 return; 341} 342 343/* 344 * Sync the PHYs by setting data bit and strobing the clock 32 times. 345 */ 346static void 347wb_mii_sync(sc) 348 struct wb_softc *sc; 349{ 350 register int i; 351 352 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 353 354 for (i = 0; i < 32; i++) { 355 SIO_SET(WB_SIO_MII_CLK); 356 DELAY(1); 357 SIO_CLR(WB_SIO_MII_CLK); 358 DELAY(1); 359 } 360 361 return; 362} 363 364/* 365 * Clock a series of bits through the MII. 366 */ 367static void 368wb_mii_send(sc, bits, cnt) 369 struct wb_softc *sc; 370 u_int32_t bits; 371 int cnt; 372{ 373 int i; 374 375 SIO_CLR(WB_SIO_MII_CLK); 376 377 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 378 if (bits & i) { 379 SIO_SET(WB_SIO_MII_DATAIN); 380 } else { 381 SIO_CLR(WB_SIO_MII_DATAIN); 382 } 383 DELAY(1); 384 SIO_CLR(WB_SIO_MII_CLK); 385 DELAY(1); 386 SIO_SET(WB_SIO_MII_CLK); 387 } 388} 389 390/* 391 * Read an PHY register through the MII. 392 */ 393static int 394wb_mii_readreg(sc, frame) 395 struct wb_softc *sc; 396 struct wb_mii_frame *frame; 397 398{ 399 int i, ack; 400 401 WB_LOCK(sc); 402 403 /* 404 * Set up frame for RX. 405 */ 406 frame->mii_stdelim = WB_MII_STARTDELIM; 407 frame->mii_opcode = WB_MII_READOP; 408 frame->mii_turnaround = 0; 409 frame->mii_data = 0; 410 411 CSR_WRITE_4(sc, WB_SIO, 0); 412 413 /* 414 * Turn on data xmit. 415 */ 416 SIO_SET(WB_SIO_MII_DIR); 417 418 wb_mii_sync(sc); 419 420 /* 421 * Send command/address info. 422 */ 423 wb_mii_send(sc, frame->mii_stdelim, 2); 424 wb_mii_send(sc, frame->mii_opcode, 2); 425 wb_mii_send(sc, frame->mii_phyaddr, 5); 426 wb_mii_send(sc, frame->mii_regaddr, 5); 427 428 /* Idle bit */ 429 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 430 DELAY(1); 431 SIO_SET(WB_SIO_MII_CLK); 432 DELAY(1); 433 434 /* Turn off xmit. */ 435 SIO_CLR(WB_SIO_MII_DIR); 436 /* Check for ack */ 437 SIO_CLR(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_SET(WB_SIO_MII_CLK); 440 DELAY(1); 441 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 442 SIO_CLR(WB_SIO_MII_CLK); 443 DELAY(1); 444 SIO_SET(WB_SIO_MII_CLK); 445 DELAY(1); 446 447 /* 448 * Now try reading data bits. If the ack failed, we still 449 * need to clock through 16 cycles to keep the PHY(s) in sync. 450 */ 451 if (ack) { 452 for(i = 0; i < 16; i++) { 453 SIO_CLR(WB_SIO_MII_CLK); 454 DELAY(1); 455 SIO_SET(WB_SIO_MII_CLK); 456 DELAY(1); 457 } 458 goto fail; 459 } 460 461 for (i = 0x8000; i; i >>= 1) { 462 SIO_CLR(WB_SIO_MII_CLK); 463 DELAY(1); 464 if (!ack) { 465 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 466 frame->mii_data |= i; 467 DELAY(1); 468 } 469 SIO_SET(WB_SIO_MII_CLK); 470 DELAY(1); 471 } 472 473fail: 474 475 SIO_CLR(WB_SIO_MII_CLK); 476 DELAY(1); 477 SIO_SET(WB_SIO_MII_CLK); 478 DELAY(1); 479 480 WB_UNLOCK(sc); 481 482 if (ack) 483 return(1); 484 return(0); 485} 486 487/* 488 * Write to a PHY register through the MII. 489 */ 490static int 491wb_mii_writereg(sc, frame) 492 struct wb_softc *sc; 493 struct wb_mii_frame *frame; 494 495{ 496 WB_LOCK(sc); 497 498 /* 499 * Set up frame for TX. 500 */ 501 502 frame->mii_stdelim = WB_MII_STARTDELIM; 503 frame->mii_opcode = WB_MII_WRITEOP; 504 frame->mii_turnaround = WB_MII_TURNAROUND; 505 506 /* 507 * Turn on data output. 508 */ 509 SIO_SET(WB_SIO_MII_DIR); 510 511 wb_mii_sync(sc); 512 513 wb_mii_send(sc, frame->mii_stdelim, 2); 514 wb_mii_send(sc, frame->mii_opcode, 2); 515 wb_mii_send(sc, frame->mii_phyaddr, 5); 516 wb_mii_send(sc, frame->mii_regaddr, 5); 517 wb_mii_send(sc, frame->mii_turnaround, 2); 518 wb_mii_send(sc, frame->mii_data, 16); 519 520 /* Idle bit. */ 521 SIO_SET(WB_SIO_MII_CLK); 522 DELAY(1); 523 SIO_CLR(WB_SIO_MII_CLK); 524 DELAY(1); 525 526 /* 527 * Turn off xmit. 528 */ 529 SIO_CLR(WB_SIO_MII_DIR); 530 531 WB_UNLOCK(sc); 532 533 return(0); 534} 535 536static int 537wb_miibus_readreg(dev, phy, reg) 538 device_t dev; 539 int phy, reg; 540{ 541 struct wb_softc *sc; 542 struct wb_mii_frame frame; 543 544 sc = device_get_softc(dev); 545 546 bzero((char *)&frame, sizeof(frame)); 547 548 frame.mii_phyaddr = phy; 549 frame.mii_regaddr = reg; 550 wb_mii_readreg(sc, &frame); 551 552 return(frame.mii_data); 553} 554 555static int 556wb_miibus_writereg(dev, phy, reg, data) 557 device_t dev; 558 int phy, reg, data; 559{ 560 struct wb_softc *sc; 561 struct wb_mii_frame frame; 562 563 sc = device_get_softc(dev); 564 565 bzero((char *)&frame, sizeof(frame)); 566 567 frame.mii_phyaddr = phy; 568 frame.mii_regaddr = reg; 569 frame.mii_data = data; 570 571 wb_mii_writereg(sc, &frame); 572 573 return(0); 574} 575 576static void 577wb_miibus_statchg(dev) 578 device_t dev; 579{ 580 struct wb_softc *sc; 581 struct mii_data *mii; 582 583 sc = device_get_softc(dev); 584 WB_LOCK(sc); 585 mii = device_get_softc(sc->wb_miibus); 586 wb_setcfg(sc, mii->mii_media_active); 587 WB_UNLOCK(sc); 588 589 return; 590} 591 592static u_int8_t wb_calchash(addr) 593 caddr_t addr; 594{ 595 u_int32_t crc, carry; 596 int i, j; 597 u_int8_t c; 598 599 /* Compute CRC for the address value. */ 600 crc = 0xFFFFFFFF; /* initial value */ 601 602 for (i = 0; i < 6; i++) { 603 c = *(addr + i); 604 for (j = 0; j < 8; j++) { 605 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 606 crc <<= 1; 607 c >>= 1; 608 if (carry) 609 crc = (crc ^ 0x04c11db6) | carry; 610 } 611 } 612 613 /* 614 * return the filter bit position 615 * Note: I arrived at the following nonsense 616 * through experimentation. It's not the usual way to 617 * generate the bit position but it's the only thing 618 * I could come up with that works. 619 */ 620 return(~(crc >> 26) & 0x0000003F); 621} 622 623/* 624 * Program the 64-bit multicast hash filter. 625 */ 626static void 627wb_setmulti(sc) 628 struct wb_softc *sc; 629{ 630 struct ifnet *ifp; 631 int h = 0; 632 u_int32_t hashes[2] = { 0, 0 }; 633 struct ifmultiaddr *ifma; 634 u_int32_t rxfilt; 635 int mcnt = 0; 636 637 ifp = &sc->arpcom.ac_if; 638 639 rxfilt = CSR_READ_4(sc, WB_NETCFG); 640 641 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 642 rxfilt |= WB_NETCFG_RX_MULTI; 643 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 644 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 645 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 646 return; 647 } 648 649 /* first, zot all the existing hash bits */ 650 CSR_WRITE_4(sc, WB_MAR0, 0); 651 CSR_WRITE_4(sc, WB_MAR1, 0); 652 653 /* now program new ones */ 654 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 655 if (ifma->ifma_addr->sa_family != AF_LINK) 656 continue; 657 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 658 if (h < 32) 659 hashes[0] |= (1 << h); 660 else 661 hashes[1] |= (1 << (h - 32)); 662 mcnt++; 663 } 664 665 if (mcnt) 666 rxfilt |= WB_NETCFG_RX_MULTI; 667 else 668 rxfilt &= ~WB_NETCFG_RX_MULTI; 669 670 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 671 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 672 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 673 674 return; 675} 676 677/* 678 * The Winbond manual states that in order to fiddle with the 679 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 680 * first have to put the transmit and/or receive logic in the idle state. 681 */ 682static void 683wb_setcfg(sc, media) 684 struct wb_softc *sc; 685 u_int32_t media; 686{ 687 int i, restart = 0; 688 689 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 690 restart = 1; 691 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 692 693 for (i = 0; i < WB_TIMEOUT; i++) { 694 DELAY(10); 695 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 696 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 697 break; 698 } 699 700 if (i == WB_TIMEOUT) 701 printf("wb%d: failed to force tx and " 702 "rx to idle state\n", sc->wb_unit); 703 } 704 705 if (IFM_SUBTYPE(media) == IFM_10_T) 706 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 707 else 708 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 709 710 if ((media & IFM_GMASK) == IFM_FDX) 711 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 712 else 713 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 714 715 if (restart) 716 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 717 718 return; 719} 720 721static void 722wb_reset(sc) 723 struct wb_softc *sc; 724{ 725 register int i; 726 struct mii_data *mii; 727 728 CSR_WRITE_4(sc, WB_NETCFG, 0); 729 CSR_WRITE_4(sc, WB_BUSCTL, 0); 730 CSR_WRITE_4(sc, WB_TXADDR, 0); 731 CSR_WRITE_4(sc, WB_RXADDR, 0); 732 733 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 734 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 735 736 for (i = 0; i < WB_TIMEOUT; i++) { 737 DELAY(10); 738 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 739 break; 740 } 741 if (i == WB_TIMEOUT) 742 printf("wb%d: reset never completed!\n", sc->wb_unit); 743 744 /* Wait a little while for the chip to get its brains in order. */ 745 DELAY(1000); 746 747 if (sc->wb_miibus == NULL) 748 return; 749 750 mii = device_get_softc(sc->wb_miibus); 751 if (mii == NULL) 752 return; 753 754 if (mii->mii_instance) { 755 struct mii_softc *miisc; 756 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 757 mii_phy_reset(miisc); 758 } 759 760 return; 761} 762 763static void 764wb_fixmedia(sc) 765 struct wb_softc *sc; 766{ 767 struct mii_data *mii = NULL; 768 struct ifnet *ifp; 769 u_int32_t media; 770 771 if (sc->wb_miibus == NULL) 772 return; 773 774 mii = device_get_softc(sc->wb_miibus); 775 ifp = &sc->arpcom.ac_if; 776 777 mii_pollstat(mii); 778 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 779 media = mii->mii_media_active & ~IFM_10_T; 780 media |= IFM_100_TX; 781 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 782 media = mii->mii_media_active & ~IFM_100_TX; 783 media |= IFM_10_T; 784 } else 785 return; 786 787 ifmedia_set(&mii->mii_media, media); 788 789 return; 790} 791 792/* 793 * Probe for a Winbond chip. Check the PCI vendor and device 794 * IDs against our list and return a device name if we find a match. 795 */ 796static int 797wb_probe(dev) 798 device_t dev; 799{ 800 struct wb_type *t; 801 802 t = wb_devs; 803 804 while(t->wb_name != NULL) { 805 if ((pci_get_vendor(dev) == t->wb_vid) && 806 (pci_get_device(dev) == t->wb_did)) { 807 device_set_desc(dev, t->wb_name); 808 return(0); 809 } 810 t++; 811 } 812 813 return(ENXIO); 814} 815 816/* 817 * Attach the interface. Allocate softc structures, do ifmedia 818 * setup and ethernet/BPF attach. 819 */ 820static int 821wb_attach(dev) 822 device_t dev; 823{ 824 u_char eaddr[ETHER_ADDR_LEN]; 825 u_int32_t command; 826 struct wb_softc *sc; 827 struct ifnet *ifp; 828 int unit, error = 0, rid; 829 830 sc = device_get_softc(dev); 831 unit = device_get_unit(dev); 832 833 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 834 MTX_DEF | MTX_RECURSE); 835 WB_LOCK(sc); 836 837 /* 838 * Handle power management nonsense. 839 */ 840 841 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 842 u_int32_t iobase, membase, irq; 843 844 /* Save important PCI config data. */ 845 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 846 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 847 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 848 849 /* Reset the power state. */ 850 printf("wb%d: chip is in D%d power mode " 851 "-- setting to D0\n", unit, 852 pci_get_powerstate(dev)); 853 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 854 855 /* Restore PCI config data. */ 856 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 857 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 858 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 859 } 860 861 /* 862 * Map control/status registers. 863 */ 864 pci_enable_busmaster(dev); 865 pci_enable_io(dev, SYS_RES_IOPORT); 866 pci_enable_io(dev, SYS_RES_MEMORY); 867 command = pci_read_config(dev, PCIR_COMMAND, 4); 868 869#ifdef WB_USEIOSPACE 870 if (!(command & PCIM_CMD_PORTEN)) { 871 printf("wb%d: failed to enable I/O ports!\n", unit); 872 error = ENXIO; 873 goto fail; 874 } 875#else 876 if (!(command & PCIM_CMD_MEMEN)) { 877 printf("wb%d: failed to enable memory mapping!\n", unit); 878 error = ENXIO; 879 goto fail; 880 } 881#endif 882 883 rid = WB_RID; 884 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 885 0, ~0, 1, RF_ACTIVE); 886 887 if (sc->wb_res == NULL) { 888 printf("wb%d: couldn't map ports/memory\n", unit); 889 error = ENXIO; 890 goto fail; 891 } 892 893 sc->wb_btag = rman_get_bustag(sc->wb_res); 894 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 895 896 /* Allocate interrupt */ 897 rid = 0; 898 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 899 RF_SHAREABLE | RF_ACTIVE); 900 901 if (sc->wb_irq == NULL) { 902 printf("wb%d: couldn't map interrupt\n", unit); 903 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 904 error = ENXIO; 905 goto fail; 906 } 907 908 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 909 wb_intr, sc, &sc->wb_intrhand); 910 911 if (error) { 912 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 913 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 914 printf("wb%d: couldn't set up irq\n", unit); 915 goto fail; 916 } 917 918 /* Save the cache line size. */ 919 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 920 921 /* Reset the adapter. */ 922 wb_reset(sc); 923 924 /* 925 * Get station address from the EEPROM. 926 */ 927 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 928 929 /* 930 * A Winbond chip was detected. Inform the world. 931 */ 932 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 933 934 sc->wb_unit = unit; 935 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 936 937 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 938 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 939 940 if (sc->wb_ldata == NULL) { 941 printf("wb%d: no memory for list buffers!\n", unit); 942 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 943 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 944 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 945 error = ENXIO; 946 goto fail; 947 } 948 949 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 950 951 ifp = &sc->arpcom.ac_if; 952 ifp->if_softc = sc; 953 ifp->if_unit = unit; 954 ifp->if_name = "wb"; 955 ifp->if_mtu = ETHERMTU; 956 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 957 ifp->if_ioctl = wb_ioctl; 958 ifp->if_output = ether_output; 959 ifp->if_start = wb_start; 960 ifp->if_watchdog = wb_watchdog; 961 ifp->if_init = wb_init; 962 ifp->if_baudrate = 10000000; 963 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 964 965 /* 966 * Do MII setup. 967 */ 968 if (mii_phy_probe(dev, &sc->wb_miibus, 969 wb_ifmedia_upd, wb_ifmedia_sts)) { 970 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 971 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 972 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 973 free(sc->wb_ldata_ptr, M_DEVBUF); 974 error = ENXIO; 975 goto fail; 976 } 977 978 /* 979 * Call MI attach routine. 980 */ 981 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 982 WB_UNLOCK(sc); 983 return(0); 984 985fail: 986 if (error) 987 device_delete_child(dev, sc->wb_miibus); 988 WB_UNLOCK(sc); 989 mtx_destroy(&sc->wb_mtx); 990 991 return(error); 992} 993 994static int 995wb_detach(dev) 996 device_t dev; 997{ 998 struct wb_softc *sc; 999 struct ifnet *ifp; 1000 1001 sc = device_get_softc(dev); 1002 WB_LOCK(sc); 1003 ifp = &sc->arpcom.ac_if; 1004 1005 wb_stop(sc); 1006 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1007 1008 /* Delete any miibus and phy devices attached to this interface */ 1009 bus_generic_detach(dev); 1010 device_delete_child(dev, sc->wb_miibus); 1011 1012 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1013 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1014 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1015 1016 free(sc->wb_ldata_ptr, M_DEVBUF); 1017 1018 WB_UNLOCK(sc); 1019 mtx_destroy(&sc->wb_mtx); 1020 1021 return(0); 1022} 1023 1024/* 1025 * Initialize the transmit descriptors. 1026 */ 1027static int 1028wb_list_tx_init(sc) 1029 struct wb_softc *sc; 1030{ 1031 struct wb_chain_data *cd; 1032 struct wb_list_data *ld; 1033 int i; 1034 1035 cd = &sc->wb_cdata; 1036 ld = sc->wb_ldata; 1037 1038 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1039 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1040 if (i == (WB_TX_LIST_CNT - 1)) { 1041 cd->wb_tx_chain[i].wb_nextdesc = 1042 &cd->wb_tx_chain[0]; 1043 } else { 1044 cd->wb_tx_chain[i].wb_nextdesc = 1045 &cd->wb_tx_chain[i + 1]; 1046 } 1047 } 1048 1049 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1050 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1051 1052 return(0); 1053} 1054 1055 1056/* 1057 * Initialize the RX descriptors and allocate mbufs for them. Note that 1058 * we arrange the descriptors in a closed ring, so that the last descriptor 1059 * points back to the first. 1060 */ 1061static int 1062wb_list_rx_init(sc) 1063 struct wb_softc *sc; 1064{ 1065 struct wb_chain_data *cd; 1066 struct wb_list_data *ld; 1067 int i; 1068 1069 cd = &sc->wb_cdata; 1070 ld = sc->wb_ldata; 1071 1072 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1073 cd->wb_rx_chain[i].wb_ptr = 1074 (struct wb_desc *)&ld->wb_rx_list[i]; 1075 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1076 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1077 return(ENOBUFS); 1078 if (i == (WB_RX_LIST_CNT - 1)) { 1079 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1080 ld->wb_rx_list[i].wb_next = 1081 vtophys(&ld->wb_rx_list[0]); 1082 } else { 1083 cd->wb_rx_chain[i].wb_nextdesc = 1084 &cd->wb_rx_chain[i + 1]; 1085 ld->wb_rx_list[i].wb_next = 1086 vtophys(&ld->wb_rx_list[i + 1]); 1087 } 1088 } 1089 1090 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1091 1092 return(0); 1093} 1094 1095static void 1096wb_bfree(buf, args) 1097 void *buf; 1098 void *args; 1099{ 1100 return; 1101} 1102 1103/* 1104 * Initialize an RX descriptor and attach an MBUF cluster. 1105 */ 1106static int 1107wb_newbuf(sc, c, m) 1108 struct wb_softc *sc; 1109 struct wb_chain_onefrag *c; 1110 struct mbuf *m; 1111{ 1112 struct mbuf *m_new = NULL; 1113 1114 if (m == NULL) { 1115 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1116 if (m_new == NULL) 1117 return(ENOBUFS); 1118 m_new->m_data = c->wb_buf; 1119 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1120 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1121 EXT_NET_DRV); 1122 } else { 1123 m_new = m; 1124 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1125 m_new->m_data = m_new->m_ext.ext_buf; 1126 } 1127 1128 m_adj(m_new, sizeof(u_int64_t)); 1129 1130 c->wb_mbuf = m_new; 1131 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1132 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1133 c->wb_ptr->wb_status = WB_RXSTAT; 1134 1135 return(0); 1136} 1137 1138/* 1139 * A frame has been uploaded: pass the resulting mbuf chain up to 1140 * the higher level protocols. 1141 */ 1142static void 1143wb_rxeof(sc) 1144 struct wb_softc *sc; 1145{ 1146 struct ether_header *eh; 1147 struct mbuf *m = NULL; 1148 struct ifnet *ifp; 1149 struct wb_chain_onefrag *cur_rx; 1150 int total_len = 0; 1151 u_int32_t rxstat; 1152 1153 ifp = &sc->arpcom.ac_if; 1154 1155 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1156 WB_RXSTAT_OWN)) { 1157 struct mbuf *m0 = NULL; 1158 1159 cur_rx = sc->wb_cdata.wb_rx_head; 1160 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1161 1162 m = cur_rx->wb_mbuf; 1163 1164 if ((rxstat & WB_RXSTAT_MIIERR) || 1165 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1166 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1167 !(rxstat & WB_RXSTAT_LASTFRAG) || 1168 !(rxstat & WB_RXSTAT_RXCMP)) { 1169 ifp->if_ierrors++; 1170 wb_newbuf(sc, cur_rx, m); 1171 printf("wb%x: receiver babbling: possible chip " 1172 "bug, forcing reset\n", sc->wb_unit); 1173 wb_fixmedia(sc); 1174 wb_reset(sc); 1175 wb_init(sc); 1176 return; 1177 } 1178 1179 if (rxstat & WB_RXSTAT_RXERR) { 1180 ifp->if_ierrors++; 1181 wb_newbuf(sc, cur_rx, m); 1182 break; 1183 } 1184 1185 /* No errors; receive the packet. */ 1186 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1187 1188 /* 1189 * XXX The Winbond chip includes the CRC with every 1190 * received frame, and there's no way to turn this 1191 * behavior off (at least, I can't find anything in 1192 * the manual that explains how to do it) so we have 1193 * to trim off the CRC manually. 1194 */ 1195 total_len -= ETHER_CRC_LEN; 1196 1197 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1198 NULL); 1199 wb_newbuf(sc, cur_rx, m); 1200 if (m0 == NULL) { 1201 ifp->if_ierrors++; 1202 break; 1203 } 1204 m = m0; 1205 1206 ifp->if_ipackets++; 1207 eh = mtod(m, struct ether_header *); 1208 1209 /* Remove header from mbuf and pass it on. */ 1210 m_adj(m, sizeof(struct ether_header)); 1211 ether_input(ifp, eh, m); 1212 } 1213} 1214 1215void 1216wb_rxeoc(sc) 1217 struct wb_softc *sc; 1218{ 1219 wb_rxeof(sc); 1220 1221 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1222 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1223 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1224 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1225 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1226 1227 return; 1228} 1229 1230/* 1231 * A frame was downloaded to the chip. It's safe for us to clean up 1232 * the list buffers. 1233 */ 1234static void 1235wb_txeof(sc) 1236 struct wb_softc *sc; 1237{ 1238 struct wb_chain *cur_tx; 1239 struct ifnet *ifp; 1240 1241 ifp = &sc->arpcom.ac_if; 1242 1243 /* Clear the timeout timer. */ 1244 ifp->if_timer = 0; 1245 1246 if (sc->wb_cdata.wb_tx_head == NULL) 1247 return; 1248 1249 /* 1250 * Go through our tx list and free mbufs for those 1251 * frames that have been transmitted. 1252 */ 1253 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1254 u_int32_t txstat; 1255 1256 cur_tx = sc->wb_cdata.wb_tx_head; 1257 txstat = WB_TXSTATUS(cur_tx); 1258 1259 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1260 break; 1261 1262 if (txstat & WB_TXSTAT_TXERR) { 1263 ifp->if_oerrors++; 1264 if (txstat & WB_TXSTAT_ABORT) 1265 ifp->if_collisions++; 1266 if (txstat & WB_TXSTAT_LATECOLL) 1267 ifp->if_collisions++; 1268 } 1269 1270 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1271 1272 ifp->if_opackets++; 1273 m_freem(cur_tx->wb_mbuf); 1274 cur_tx->wb_mbuf = NULL; 1275 1276 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1277 sc->wb_cdata.wb_tx_head = NULL; 1278 sc->wb_cdata.wb_tx_tail = NULL; 1279 break; 1280 } 1281 1282 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1283 } 1284 1285 return; 1286} 1287 1288/* 1289 * TX 'end of channel' interrupt handler. 1290 */ 1291static void 1292wb_txeoc(sc) 1293 struct wb_softc *sc; 1294{ 1295 struct ifnet *ifp; 1296 1297 ifp = &sc->arpcom.ac_if; 1298 1299 ifp->if_timer = 0; 1300 1301 if (sc->wb_cdata.wb_tx_head == NULL) { 1302 ifp->if_flags &= ~IFF_OACTIVE; 1303 sc->wb_cdata.wb_tx_tail = NULL; 1304 } else { 1305 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1306 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1307 ifp->if_timer = 5; 1308 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1309 } 1310 } 1311 1312 return; 1313} 1314 1315static void 1316wb_intr(arg) 1317 void *arg; 1318{ 1319 struct wb_softc *sc; 1320 struct ifnet *ifp; 1321 u_int32_t status; 1322 1323 sc = arg; 1324 WB_LOCK(sc); 1325 ifp = &sc->arpcom.ac_if; 1326 1327 if (!(ifp->if_flags & IFF_UP)) { 1328 WB_UNLOCK(sc); 1329 return; 1330 } 1331 1332 /* Disable interrupts. */ 1333 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1334 1335 for (;;) { 1336 1337 status = CSR_READ_4(sc, WB_ISR); 1338 if (status) 1339 CSR_WRITE_4(sc, WB_ISR, status); 1340 1341 if ((status & WB_INTRS) == 0) 1342 break; 1343 1344 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1345 ifp->if_ierrors++; 1346 wb_reset(sc); 1347 if (status & WB_ISR_RX_ERR) 1348 wb_fixmedia(sc); 1349 wb_init(sc); 1350 continue; 1351 } 1352 1353 if (status & WB_ISR_RX_OK) 1354 wb_rxeof(sc); 1355 1356 if (status & WB_ISR_RX_IDLE) 1357 wb_rxeoc(sc); 1358 1359 if (status & WB_ISR_TX_OK) 1360 wb_txeof(sc); 1361 1362 if (status & WB_ISR_TX_NOBUF) 1363 wb_txeoc(sc); 1364 1365 if (status & WB_ISR_TX_IDLE) { 1366 wb_txeof(sc); 1367 if (sc->wb_cdata.wb_tx_head != NULL) { 1368 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1369 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1370 } 1371 } 1372 1373 if (status & WB_ISR_TX_UNDERRUN) { 1374 ifp->if_oerrors++; 1375 wb_txeof(sc); 1376 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1377 /* Jack up TX threshold */ 1378 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1379 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1380 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1381 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1382 } 1383 1384 if (status & WB_ISR_BUS_ERR) { 1385 wb_reset(sc); 1386 wb_init(sc); 1387 } 1388 1389 } 1390 1391 /* Re-enable interrupts. */ 1392 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1393 1394 if (ifp->if_snd.ifq_head != NULL) { 1395 wb_start(ifp); 1396 } 1397 1398 WB_UNLOCK(sc); 1399 1400 return; 1401} 1402 1403static void 1404wb_tick(xsc) 1405 void *xsc; 1406{ 1407 struct wb_softc *sc; 1408 struct mii_data *mii; 1409 1410 sc = xsc; 1411 WB_LOCK(sc); 1412 mii = device_get_softc(sc->wb_miibus); 1413 1414 mii_tick(mii); 1415 1416 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1417 1418 WB_UNLOCK(sc); 1419 1420 return; 1421} 1422 1423/* 1424 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1425 * pointers to the fragment pointers. 1426 */ 1427static int 1428wb_encap(sc, c, m_head) 1429 struct wb_softc *sc; 1430 struct wb_chain *c; 1431 struct mbuf *m_head; 1432{ 1433 int frag = 0; 1434 struct wb_desc *f = NULL; 1435 int total_len; 1436 struct mbuf *m; 1437 1438 /* 1439 * Start packing the mbufs in this chain into 1440 * the fragment pointers. Stop when we run out 1441 * of fragments or hit the end of the mbuf chain. 1442 */ 1443 m = m_head; 1444 total_len = 0; 1445 1446 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1447 if (m->m_len != 0) { 1448 if (frag == WB_MAXFRAGS) 1449 break; 1450 total_len += m->m_len; 1451 f = &c->wb_ptr->wb_frag[frag]; 1452 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1453 if (frag == 0) { 1454 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1455 f->wb_status = 0; 1456 } else 1457 f->wb_status = WB_TXSTAT_OWN; 1458 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1459 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1460 frag++; 1461 } 1462 } 1463 1464 /* 1465 * Handle special case: we used up all 16 fragments, 1466 * but we have more mbufs left in the chain. Copy the 1467 * data into an mbuf cluster. Note that we don't 1468 * bother clearing the values in the other fragment 1469 * pointers/counters; it wouldn't gain us anything, 1470 * and would waste cycles. 1471 */ 1472 if (m != NULL) { 1473 struct mbuf *m_new = NULL; 1474 1475 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1476 if (m_new == NULL) 1477 return(1); 1478 if (m_head->m_pkthdr.len > MHLEN) { 1479 MCLGET(m_new, M_DONTWAIT); 1480 if (!(m_new->m_flags & M_EXT)) { 1481 m_freem(m_new); 1482 return(1); 1483 } 1484 } 1485 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1486 mtod(m_new, caddr_t)); 1487 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1488 m_freem(m_head); 1489 m_head = m_new; 1490 f = &c->wb_ptr->wb_frag[0]; 1491 f->wb_status = 0; 1492 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1493 f->wb_ctl = total_len = m_new->m_len; 1494 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1495 frag = 1; 1496 } 1497 1498 if (total_len < WB_MIN_FRAMELEN) { 1499 f = &c->wb_ptr->wb_frag[frag]; 1500 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1501 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1502 f->wb_ctl |= WB_TXCTL_TLINK; 1503 f->wb_status = WB_TXSTAT_OWN; 1504 frag++; 1505 } 1506 1507 c->wb_mbuf = m_head; 1508 c->wb_lastdesc = frag - 1; 1509 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1510 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1511 1512 return(0); 1513} 1514 1515/* 1516 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1517 * to the mbuf data regions directly in the transmit lists. We also save a 1518 * copy of the pointers since the transmit list fragment pointers are 1519 * physical addresses. 1520 */ 1521 1522static void 1523wb_start(ifp) 1524 struct ifnet *ifp; 1525{ 1526 struct wb_softc *sc; 1527 struct mbuf *m_head = NULL; 1528 struct wb_chain *cur_tx = NULL, *start_tx; 1529 1530 sc = ifp->if_softc; 1531 WB_LOCK(sc); 1532 1533 /* 1534 * Check for an available queue slot. If there are none, 1535 * punt. 1536 */ 1537 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1538 ifp->if_flags |= IFF_OACTIVE; 1539 WB_UNLOCK(sc); 1540 return; 1541 } 1542 1543 start_tx = sc->wb_cdata.wb_tx_free; 1544 1545 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1546 IF_DEQUEUE(&ifp->if_snd, m_head); 1547 if (m_head == NULL) 1548 break; 1549 1550 /* Pick a descriptor off the free list. */ 1551 cur_tx = sc->wb_cdata.wb_tx_free; 1552 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1553 1554 /* Pack the data into the descriptor. */ 1555 wb_encap(sc, cur_tx, m_head); 1556 1557 if (cur_tx != start_tx) 1558 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1559 1560 /* 1561 * If there's a BPF listener, bounce a copy of this frame 1562 * to him. 1563 */ 1564 if (ifp->if_bpf) 1565 bpf_mtap(ifp, cur_tx->wb_mbuf); 1566 } 1567 1568 /* 1569 * If there are no packets queued, bail. 1570 */ 1571 if (cur_tx == NULL) { 1572 WB_UNLOCK(sc); 1573 return; 1574 } 1575 1576 /* 1577 * Place the request for the upload interrupt 1578 * in the last descriptor in the chain. This way, if 1579 * we're chaining several packets at once, we'll only 1580 * get an interupt once for the whole chain rather than 1581 * once for each packet. 1582 */ 1583 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1584 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1585 sc->wb_cdata.wb_tx_tail = cur_tx; 1586 1587 if (sc->wb_cdata.wb_tx_head == NULL) { 1588 sc->wb_cdata.wb_tx_head = start_tx; 1589 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1590 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1591 } else { 1592 /* 1593 * We need to distinguish between the case where 1594 * the own bit is clear because the chip cleared it 1595 * and where the own bit is clear because we haven't 1596 * set it yet. The magic value WB_UNSET is just some 1597 * ramdomly chosen number which doesn't have the own 1598 * bit set. When we actually transmit the frame, the 1599 * status word will have _only_ the own bit set, so 1600 * the txeoc handler will be able to tell if it needs 1601 * to initiate another transmission to flush out pending 1602 * frames. 1603 */ 1604 WB_TXOWN(start_tx) = WB_UNSENT; 1605 } 1606 1607 /* 1608 * Set a timeout in case the chip goes out to lunch. 1609 */ 1610 ifp->if_timer = 5; 1611 WB_UNLOCK(sc); 1612 1613 return; 1614} 1615 1616static void 1617wb_init(xsc) 1618 void *xsc; 1619{ 1620 struct wb_softc *sc = xsc; 1621 struct ifnet *ifp = &sc->arpcom.ac_if; 1622 int i; 1623 struct mii_data *mii; 1624 1625 WB_LOCK(sc); 1626 mii = device_get_softc(sc->wb_miibus); 1627 1628 /* 1629 * Cancel pending I/O and free all RX/TX buffers. 1630 */ 1631 wb_stop(sc); 1632 wb_reset(sc); 1633 1634 sc->wb_txthresh = WB_TXTHRESH_INIT; 1635 1636 /* 1637 * Set cache alignment and burst length. 1638 */ 1639#ifdef foo 1640 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1641 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1642 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1643#endif 1644 1645 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1646 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1647 switch(sc->wb_cachesize) { 1648 case 32: 1649 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1650 break; 1651 case 16: 1652 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1653 break; 1654 case 8: 1655 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1656 break; 1657 case 0: 1658 default: 1659 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1660 break; 1661 } 1662 1663 /* This doesn't tend to work too well at 100Mbps. */ 1664 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1665 1666 /* Init our MAC address */ 1667 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1668 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1669 } 1670 1671 /* Init circular RX list. */ 1672 if (wb_list_rx_init(sc) == ENOBUFS) { 1673 printf("wb%d: initialization failed: no " 1674 "memory for rx buffers\n", sc->wb_unit); 1675 wb_stop(sc); 1676 WB_UNLOCK(sc); 1677 return; 1678 } 1679 1680 /* Init TX descriptors. */ 1681 wb_list_tx_init(sc); 1682 1683 /* If we want promiscuous mode, set the allframes bit. */ 1684 if (ifp->if_flags & IFF_PROMISC) { 1685 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1686 } else { 1687 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1688 } 1689 1690 /* 1691 * Set capture broadcast bit to capture broadcast frames. 1692 */ 1693 if (ifp->if_flags & IFF_BROADCAST) { 1694 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1695 } else { 1696 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1697 } 1698 1699 /* 1700 * Program the multicast filter, if necessary. 1701 */ 1702 wb_setmulti(sc); 1703 1704 /* 1705 * Load the address of the RX list. 1706 */ 1707 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1708 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1709 1710 /* 1711 * Enable interrupts. 1712 */ 1713 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1714 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1715 1716 /* Enable receiver and transmitter. */ 1717 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1718 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1719 1720 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1721 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1722 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1723 1724 mii_mediachg(mii); 1725 1726 ifp->if_flags |= IFF_RUNNING; 1727 ifp->if_flags &= ~IFF_OACTIVE; 1728 1729 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1730 WB_UNLOCK(sc); 1731 1732 return; 1733} 1734 1735/* 1736 * Set media options. 1737 */ 1738static int 1739wb_ifmedia_upd(ifp) 1740 struct ifnet *ifp; 1741{ 1742 struct wb_softc *sc; 1743 1744 sc = ifp->if_softc; 1745 1746 if (ifp->if_flags & IFF_UP) 1747 wb_init(sc); 1748 1749 return(0); 1750} 1751 1752/* 1753 * Report current media status. 1754 */ 1755static void 1756wb_ifmedia_sts(ifp, ifmr) 1757 struct ifnet *ifp; 1758 struct ifmediareq *ifmr; 1759{ 1760 struct wb_softc *sc; 1761 struct mii_data *mii; 1762 1763 sc = ifp->if_softc; 1764 1765 mii = device_get_softc(sc->wb_miibus); 1766 1767 mii_pollstat(mii); 1768 ifmr->ifm_active = mii->mii_media_active; 1769 ifmr->ifm_status = mii->mii_media_status; 1770 1771 return; 1772} 1773 1774static int 1775wb_ioctl(ifp, command, data) 1776 struct ifnet *ifp; 1777 u_long command; 1778 caddr_t data; 1779{ 1780 struct wb_softc *sc = ifp->if_softc; 1781 struct mii_data *mii; 1782 struct ifreq *ifr = (struct ifreq *) data; 1783 int error = 0; 1784 1785 WB_LOCK(sc); 1786 1787 switch(command) { 1788 case SIOCSIFADDR: 1789 case SIOCGIFADDR: 1790 case SIOCSIFMTU: 1791 error = ether_ioctl(ifp, command, data); 1792 break; 1793 case SIOCSIFFLAGS: 1794 if (ifp->if_flags & IFF_UP) { 1795 wb_init(sc); 1796 } else { 1797 if (ifp->if_flags & IFF_RUNNING) 1798 wb_stop(sc); 1799 } 1800 error = 0; 1801 break; 1802 case SIOCADDMULTI: 1803 case SIOCDELMULTI: 1804 wb_setmulti(sc); 1805 error = 0; 1806 break; 1807 case SIOCGIFMEDIA: 1808 case SIOCSIFMEDIA: 1809 mii = device_get_softc(sc->wb_miibus); 1810 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1811 break; 1812 default: 1813 error = EINVAL; 1814 break; 1815 } 1816 1817 WB_UNLOCK(sc); 1818 1819 return(error); 1820} 1821 1822static void 1823wb_watchdog(ifp) 1824 struct ifnet *ifp; 1825{ 1826 struct wb_softc *sc; 1827 1828 sc = ifp->if_softc; 1829 1830 WB_LOCK(sc); 1831 ifp->if_oerrors++; 1832 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1833#ifdef foo 1834 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1835 printf("wb%d: no carrier - transceiver cable problem?\n", 1836 sc->wb_unit); 1837#endif 1838 wb_stop(sc); 1839 wb_reset(sc); 1840 wb_init(sc); 1841 1842 if (ifp->if_snd.ifq_head != NULL) 1843 wb_start(ifp); 1844 WB_UNLOCK(sc); 1845 1846 return; 1847} 1848 1849/* 1850 * Stop the adapter and free any mbufs allocated to the 1851 * RX and TX lists. 1852 */ 1853static void 1854wb_stop(sc) 1855 struct wb_softc *sc; 1856{ 1857 register int i; 1858 struct ifnet *ifp; 1859 1860 WB_LOCK(sc); 1861 ifp = &sc->arpcom.ac_if; 1862 ifp->if_timer = 0; 1863 1864 untimeout(wb_tick, sc, sc->wb_stat_ch); 1865 1866 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1867 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1868 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1869 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1870 1871 /* 1872 * Free data in the RX lists. 1873 */ 1874 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1875 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1876 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1877 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1878 } 1879 } 1880 bzero((char *)&sc->wb_ldata->wb_rx_list, 1881 sizeof(sc->wb_ldata->wb_rx_list)); 1882 1883 /* 1884 * Free the TX list buffers. 1885 */ 1886 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1887 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1888 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1889 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1890 } 1891 } 1892 1893 bzero((char *)&sc->wb_ldata->wb_tx_list, 1894 sizeof(sc->wb_ldata->wb_tx_list)); 1895 1896 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1897 WB_UNLOCK(sc); 1898 1899 return; 1900} 1901 1902/* 1903 * Stop all chip I/O so that the kernel's probe routines don't 1904 * get confused by errant DMAs when rebooting. 1905 */ 1906static void 1907wb_shutdown(dev) 1908 device_t dev; 1909{ 1910 struct wb_softc *sc; 1911 1912 sc = device_get_softc(dev); 1913 wb_stop(sc); 1914 1915 return; 1916} 1917