if_wb.c revision 72084
141502Swpaul/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_wb.c 72084 2001-02-06 10:12:15Z phk $ 3341502Swpaul */ 3441502Swpaul 3541502Swpaul/* 3641502Swpaul * Winbond fast ethernet PCI NIC driver 3741502Swpaul * 3841502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 3941502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 4041502Swpaul * Winbond itself and some made by Linksys. 4141502Swpaul * 4241502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4341502Swpaul * Electrical Engineering Department 4441502Swpaul * Columbia University, New York City 4541502Swpaul */ 4641502Swpaul 4741502Swpaul/* 4841502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4941502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 5041502Swpaul * one major difference which is that while the registers do many of 5141502Swpaul * the same things as a tulip adapter, the offsets are different: where 5241502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5341502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5441502Swpaul * programmed differently. 5541502Swpaul * 5641502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5741502Swpaul * a status word, a control word and 32-bit areas that can either be used 5841502Swpaul * to point to two external data blocks, or to point to a single block 5941502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 6041502Swpaul * together in blocks to form fixed length rings or can be chained 6141502Swpaul * together in linked lists. A single packet may be spread out over 6241502Swpaul * several descriptors if necessary. 6341502Swpaul * 6441502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6541502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6641502Swpaul * to hold an entire packet. The link list is looped back to created a 6741502Swpaul * closed ring. 6841502Swpaul * 6941502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 7041502Swpaul * which each contain several individual descriptors linked toghether. 7141502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7241502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7341502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7441502Swpaul * drivers. 7541502Swpaul * 7641502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7741502Swpaul * The sample boards I have all use a Davicom PHY. 7841502Swpaul * 7941502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 8041502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 8141502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8241502Swpaul * I have no idea what he's on about: transmit performance with all 8341502Swpaul * three of my test boards seems fine. 8441502Swpaul */ 8541502Swpaul 8648745Swpaul#include "opt_bdg.h" 8741502Swpaul 8841502Swpaul#include <sys/param.h> 8941502Swpaul#include <sys/systm.h> 9041502Swpaul#include <sys/sockio.h> 9141502Swpaul#include <sys/mbuf.h> 9241502Swpaul#include <sys/malloc.h> 9341502Swpaul#include <sys/kernel.h> 9441502Swpaul#include <sys/socket.h> 9550675Swpaul#include <sys/queue.h> 9641502Swpaul 9741502Swpaul#include <net/if.h> 9841502Swpaul#include <net/if_arp.h> 9941502Swpaul#include <net/ethernet.h> 10041502Swpaul#include <net/if_dl.h> 10141502Swpaul#include <net/if_media.h> 10241502Swpaul 10341502Swpaul#include <net/bpf.h> 10441502Swpaul 10541502Swpaul#include <vm/vm.h> /* for vtophys */ 10641502Swpaul#include <vm/pmap.h> /* for vtophys */ 10741502Swpaul#include <machine/bus_memio.h> 10841502Swpaul#include <machine/bus_pio.h> 10941502Swpaul#include <machine/bus.h> 11049611Swpaul#include <machine/resource.h> 11149611Swpaul#include <sys/bus.h> 11249611Swpaul#include <sys/rman.h> 11341502Swpaul 11441502Swpaul#include <pci/pcireg.h> 11541502Swpaul#include <pci/pcivar.h> 11641502Swpaul 11750675Swpaul#include <dev/mii/mii.h> 11850675Swpaul#include <dev/mii/miivar.h> 11950675Swpaul 12051089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12150675Swpaul#include "miibus_if.h" 12250675Swpaul 12341502Swpaul#define WB_USEIOSPACE 12441502Swpaul 12541502Swpaul#include <pci/if_wbreg.h> 12641502Swpaul 12759758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 12859758Speter 12941502Swpaul#ifndef lint 13041633Sarchiestatic const char rcsid[] = 13150477Speter "$FreeBSD: head/sys/pci/if_wb.c 72084 2001-02-06 10:12:15Z phk $"; 13241502Swpaul#endif 13341502Swpaul 13441502Swpaul/* 13541502Swpaul * Various supported device vendors/types and their names. 13641502Swpaul */ 13741502Swpaulstatic struct wb_type wb_devs[] = { 13841502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13941502Swpaul "Winbond W89C840F 10/100BaseTX" }, 14041502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 14141502Swpaul "Compex RL100-ATX 10/100baseTX" }, 14241502Swpaul { 0, 0, NULL } 14341502Swpaul}; 14441502Swpaul 14549611Swpaulstatic int wb_probe __P((device_t)); 14649611Swpaulstatic int wb_attach __P((device_t)); 14749611Swpaulstatic int wb_detach __P((device_t)); 14841502Swpaul 14964837Sdwmalonestatic void wb_bfree __P((caddr_t, void *args)); 15041502Swpaulstatic int wb_newbuf __P((struct wb_softc *, 15148745Swpaul struct wb_chain_onefrag *, 15248745Swpaul struct mbuf *)); 15341502Swpaulstatic int wb_encap __P((struct wb_softc *, struct wb_chain *, 15450675Swpaul struct mbuf *)); 15541502Swpaul 15641502Swpaulstatic void wb_rxeof __P((struct wb_softc *)); 15741502Swpaulstatic void wb_rxeoc __P((struct wb_softc *)); 15841502Swpaulstatic void wb_txeof __P((struct wb_softc *)); 15941502Swpaulstatic void wb_txeoc __P((struct wb_softc *)); 16041502Swpaulstatic void wb_intr __P((void *)); 16150675Swpaulstatic void wb_tick __P((void *)); 16241502Swpaulstatic void wb_start __P((struct ifnet *)); 16341502Swpaulstatic int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 16441502Swpaulstatic void wb_init __P((void *)); 16541502Swpaulstatic void wb_stop __P((struct wb_softc *)); 16641502Swpaulstatic void wb_watchdog __P((struct ifnet *)); 16749611Swpaulstatic void wb_shutdown __P((device_t)); 16841502Swpaulstatic int wb_ifmedia_upd __P((struct ifnet *)); 16941502Swpaulstatic void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 17041502Swpaul 17142718Swpaulstatic void wb_eeprom_putbyte __P((struct wb_softc *, int)); 17242718Swpaulstatic void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 17341502Swpaulstatic void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 17441502Swpaul int, int)); 17541502Swpaulstatic void wb_mii_sync __P((struct wb_softc *)); 17641502Swpaulstatic void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 17741502Swpaulstatic int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 17841502Swpaulstatic int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 17941502Swpaul 18050675Swpaulstatic void wb_setcfg __P((struct wb_softc *, u_int32_t)); 18142718Swpaulstatic u_int8_t wb_calchash __P((caddr_t)); 18241502Swpaulstatic void wb_setmulti __P((struct wb_softc *)); 18341502Swpaulstatic void wb_reset __P((struct wb_softc *)); 18450675Swpaulstatic void wb_fixmedia __P((struct wb_softc *)); 18541502Swpaulstatic int wb_list_rx_init __P((struct wb_softc *)); 18641502Swpaulstatic int wb_list_tx_init __P((struct wb_softc *)); 18741502Swpaul 18850675Swpaulstatic int wb_miibus_readreg __P((device_t, int, int)); 18950675Swpaulstatic int wb_miibus_writereg __P((device_t, int, int, int)); 19050675Swpaulstatic void wb_miibus_statchg __P((device_t)); 19150675Swpaul 19249611Swpaul#ifdef WB_USEIOSPACE 19349611Swpaul#define WB_RES SYS_RES_IOPORT 19449611Swpaul#define WB_RID WB_PCI_LOIO 19549611Swpaul#else 19649611Swpaul#define WB_RES SYS_RES_MEMORY 19749611Swpaul#define WB_RID WB_PCI_LOMEM 19849611Swpaul#endif 19949611Swpaul 20049611Swpaulstatic device_method_t wb_methods[] = { 20149611Swpaul /* Device interface */ 20249611Swpaul DEVMETHOD(device_probe, wb_probe), 20349611Swpaul DEVMETHOD(device_attach, wb_attach), 20449611Swpaul DEVMETHOD(device_detach, wb_detach), 20549611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 20650675Swpaul 20750675Swpaul /* bus interface, for miibus */ 20850675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20950675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 21050675Swpaul 21150675Swpaul /* MII interface */ 21250675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 21350675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 21450675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 21549611Swpaul { 0, 0 } 21649611Swpaul}; 21749611Swpaul 21849611Swpaulstatic driver_t wb_driver = { 21951455Swpaul "wb", 22049611Swpaul wb_methods, 22149611Swpaul sizeof(struct wb_softc) 22249611Swpaul}; 22349611Swpaul 22449611Swpaulstatic devclass_t wb_devclass; 22549611Swpaul 22651533SwpaulDRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 22751473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22849611Swpaul 22941502Swpaul#define WB_SETBIT(sc, reg, x) \ 23041502Swpaul CSR_WRITE_4(sc, reg, \ 23141502Swpaul CSR_READ_4(sc, reg) | x) 23241502Swpaul 23341502Swpaul#define WB_CLRBIT(sc, reg, x) \ 23441502Swpaul CSR_WRITE_4(sc, reg, \ 23541502Swpaul CSR_READ_4(sc, reg) & ~x) 23641502Swpaul 23741502Swpaul#define SIO_SET(x) \ 23841502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 23941502Swpaul CSR_READ_4(sc, WB_SIO) | x) 24041502Swpaul 24141502Swpaul#define SIO_CLR(x) \ 24241502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 24341502Swpaul CSR_READ_4(sc, WB_SIO) & ~x) 24441502Swpaul 24541502Swpaul/* 24641502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24741502Swpaul */ 24841502Swpaulstatic void wb_eeprom_putbyte(sc, addr) 24941502Swpaul struct wb_softc *sc; 25042718Swpaul int addr; 25141502Swpaul{ 25241502Swpaul register int d, i; 25341502Swpaul 25441502Swpaul d = addr | WB_EECMD_READ; 25541502Swpaul 25641502Swpaul /* 25741502Swpaul * Feed in each bit and stobe the clock. 25841502Swpaul */ 25941502Swpaul for (i = 0x400; i; i >>= 1) { 26041502Swpaul if (d & i) { 26141502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 26241502Swpaul } else { 26341502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 26441502Swpaul } 26541502Swpaul DELAY(100); 26641502Swpaul SIO_SET(WB_SIO_EE_CLK); 26741502Swpaul DELAY(150); 26841502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26941502Swpaul DELAY(100); 27041502Swpaul } 27141502Swpaul 27241502Swpaul return; 27341502Swpaul} 27441502Swpaul 27541502Swpaul/* 27641502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27741502Swpaul */ 27841502Swpaulstatic void wb_eeprom_getword(sc, addr, dest) 27941502Swpaul struct wb_softc *sc; 28042718Swpaul int addr; 28141502Swpaul u_int16_t *dest; 28241502Swpaul{ 28341502Swpaul register int i; 28441502Swpaul u_int16_t word = 0; 28541502Swpaul 28641502Swpaul /* Enter EEPROM access mode. */ 28741502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28841502Swpaul 28941502Swpaul /* 29041502Swpaul * Send address of word we want to read. 29141502Swpaul */ 29241502Swpaul wb_eeprom_putbyte(sc, addr); 29341502Swpaul 29441502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29541502Swpaul 29641502Swpaul /* 29741502Swpaul * Start reading bits from EEPROM. 29841502Swpaul */ 29941502Swpaul for (i = 0x8000; i; i >>= 1) { 30041502Swpaul SIO_SET(WB_SIO_EE_CLK); 30141502Swpaul DELAY(100); 30241502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 30341502Swpaul word |= i; 30441502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30541502Swpaul DELAY(100); 30641502Swpaul } 30741502Swpaul 30841502Swpaul /* Turn off EEPROM access mode. */ 30941502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 31041502Swpaul 31141502Swpaul *dest = word; 31241502Swpaul 31341502Swpaul return; 31441502Swpaul} 31541502Swpaul 31641502Swpaul/* 31741502Swpaul * Read a sequence of words from the EEPROM. 31841502Swpaul */ 31941502Swpaulstatic void wb_read_eeprom(sc, dest, off, cnt, swap) 32041502Swpaul struct wb_softc *sc; 32141502Swpaul caddr_t dest; 32241502Swpaul int off; 32341502Swpaul int cnt; 32441502Swpaul int swap; 32541502Swpaul{ 32641502Swpaul int i; 32741502Swpaul u_int16_t word = 0, *ptr; 32841502Swpaul 32941502Swpaul for (i = 0; i < cnt; i++) { 33041502Swpaul wb_eeprom_getword(sc, off + i, &word); 33141502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 33241502Swpaul if (swap) 33341502Swpaul *ptr = ntohs(word); 33441502Swpaul else 33541502Swpaul *ptr = word; 33641502Swpaul } 33741502Swpaul 33841502Swpaul return; 33941502Swpaul} 34041502Swpaul 34141502Swpaul/* 34241502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 34341502Swpaul */ 34441502Swpaulstatic void wb_mii_sync(sc) 34541502Swpaul struct wb_softc *sc; 34641502Swpaul{ 34741502Swpaul register int i; 34841502Swpaul 34941502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 35041502Swpaul 35141502Swpaul for (i = 0; i < 32; i++) { 35241502Swpaul SIO_SET(WB_SIO_MII_CLK); 35341502Swpaul DELAY(1); 35441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35541502Swpaul DELAY(1); 35641502Swpaul } 35741502Swpaul 35841502Swpaul return; 35941502Swpaul} 36041502Swpaul 36141502Swpaul/* 36241502Swpaul * Clock a series of bits through the MII. 36341502Swpaul */ 36441502Swpaulstatic void wb_mii_send(sc, bits, cnt) 36541502Swpaul struct wb_softc *sc; 36641502Swpaul u_int32_t bits; 36741502Swpaul int cnt; 36841502Swpaul{ 36941502Swpaul int i; 37041502Swpaul 37141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37241502Swpaul 37341502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37441502Swpaul if (bits & i) { 37541502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37641502Swpaul } else { 37741502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 37841502Swpaul } 37941502Swpaul DELAY(1); 38041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 38141502Swpaul DELAY(1); 38241502Swpaul SIO_SET(WB_SIO_MII_CLK); 38341502Swpaul } 38441502Swpaul} 38541502Swpaul 38641502Swpaul/* 38741502Swpaul * Read an PHY register through the MII. 38841502Swpaul */ 38941502Swpaulstatic int wb_mii_readreg(sc, frame) 39041502Swpaul struct wb_softc *sc; 39141502Swpaul struct wb_mii_frame *frame; 39241502Swpaul 39341502Swpaul{ 39467087Swpaul int i, ack; 39541502Swpaul 39667087Swpaul WB_LOCK(sc); 39741502Swpaul 39841502Swpaul /* 39941502Swpaul * Set up frame for RX. 40041502Swpaul */ 40141502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 40241502Swpaul frame->mii_opcode = WB_MII_READOP; 40341502Swpaul frame->mii_turnaround = 0; 40441502Swpaul frame->mii_data = 0; 40541502Swpaul 40641502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 40741502Swpaul 40841502Swpaul /* 40941502Swpaul * Turn on data xmit. 41041502Swpaul */ 41141502Swpaul SIO_SET(WB_SIO_MII_DIR); 41241502Swpaul 41341502Swpaul wb_mii_sync(sc); 41441502Swpaul 41541502Swpaul /* 41641502Swpaul * Send command/address info. 41741502Swpaul */ 41841502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 41941502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 42041502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 42141502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 42241502Swpaul 42341502Swpaul /* Idle bit */ 42441502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42541502Swpaul DELAY(1); 42641502Swpaul SIO_SET(WB_SIO_MII_CLK); 42741502Swpaul DELAY(1); 42841502Swpaul 42941502Swpaul /* Turn off xmit. */ 43041502Swpaul SIO_CLR(WB_SIO_MII_DIR); 43141502Swpaul /* Check for ack */ 43241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43341502Swpaul DELAY(1); 43441502Swpaul SIO_SET(WB_SIO_MII_CLK); 43541502Swpaul DELAY(1); 43641502Swpaul ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43741502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43841502Swpaul DELAY(1); 43941502Swpaul SIO_SET(WB_SIO_MII_CLK); 44041502Swpaul DELAY(1); 44141502Swpaul 44241502Swpaul /* 44341502Swpaul * Now try reading data bits. If the ack failed, we still 44441502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44541502Swpaul */ 44641502Swpaul if (ack) { 44741502Swpaul for(i = 0; i < 16; i++) { 44841502Swpaul SIO_CLR(WB_SIO_MII_CLK); 44941502Swpaul DELAY(1); 45041502Swpaul SIO_SET(WB_SIO_MII_CLK); 45141502Swpaul DELAY(1); 45241502Swpaul } 45341502Swpaul goto fail; 45441502Swpaul } 45541502Swpaul 45641502Swpaul for (i = 0x8000; i; i >>= 1) { 45741502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45841502Swpaul DELAY(1); 45941502Swpaul if (!ack) { 46041502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 46141502Swpaul frame->mii_data |= i; 46241502Swpaul DELAY(1); 46341502Swpaul } 46441502Swpaul SIO_SET(WB_SIO_MII_CLK); 46541502Swpaul DELAY(1); 46641502Swpaul } 46741502Swpaul 46841502Swpaulfail: 46941502Swpaul 47041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 47141502Swpaul DELAY(1); 47241502Swpaul SIO_SET(WB_SIO_MII_CLK); 47341502Swpaul DELAY(1); 47441502Swpaul 47567087Swpaul WB_UNLOCK(sc); 47641502Swpaul 47741502Swpaul if (ack) 47841502Swpaul return(1); 47941502Swpaul return(0); 48041502Swpaul} 48141502Swpaul 48241502Swpaul/* 48341502Swpaul * Write to a PHY register through the MII. 48441502Swpaul */ 48541502Swpaulstatic int wb_mii_writereg(sc, frame) 48641502Swpaul struct wb_softc *sc; 48741502Swpaul struct wb_mii_frame *frame; 48841502Swpaul 48941502Swpaul{ 49067087Swpaul WB_LOCK(sc); 49141502Swpaul 49241502Swpaul /* 49341502Swpaul * Set up frame for TX. 49441502Swpaul */ 49541502Swpaul 49641502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 49741502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 49841502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 49941502Swpaul 50041502Swpaul /* 50141502Swpaul * Turn on data output. 50241502Swpaul */ 50341502Swpaul SIO_SET(WB_SIO_MII_DIR); 50441502Swpaul 50541502Swpaul wb_mii_sync(sc); 50641502Swpaul 50741502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 50841502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 50941502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 51041502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 51141502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 51241502Swpaul wb_mii_send(sc, frame->mii_data, 16); 51341502Swpaul 51441502Swpaul /* Idle bit. */ 51541502Swpaul SIO_SET(WB_SIO_MII_CLK); 51641502Swpaul DELAY(1); 51741502Swpaul SIO_CLR(WB_SIO_MII_CLK); 51841502Swpaul DELAY(1); 51941502Swpaul 52041502Swpaul /* 52141502Swpaul * Turn off xmit. 52241502Swpaul */ 52341502Swpaul SIO_CLR(WB_SIO_MII_DIR); 52441502Swpaul 52567087Swpaul WB_UNLOCK(sc); 52641502Swpaul 52741502Swpaul return(0); 52841502Swpaul} 52941502Swpaul 53050675Swpaulstatic int wb_miibus_readreg(dev, phy, reg) 53150675Swpaul device_t dev; 53250675Swpaul int phy, reg; 53350675Swpaul{ 53441502Swpaul struct wb_softc *sc; 53541502Swpaul struct wb_mii_frame frame; 53641502Swpaul 53750675Swpaul sc = device_get_softc(dev); 53850675Swpaul 53941502Swpaul bzero((char *)&frame, sizeof(frame)); 54041502Swpaul 54150675Swpaul frame.mii_phyaddr = phy; 54241502Swpaul frame.mii_regaddr = reg; 54341502Swpaul wb_mii_readreg(sc, &frame); 54441502Swpaul 54541502Swpaul return(frame.mii_data); 54641502Swpaul} 54741502Swpaul 54850675Swpaulstatic int wb_miibus_writereg(dev, phy, reg, data) 54950675Swpaul device_t dev; 55050675Swpaul int phy, reg, data; 55150675Swpaul{ 55241502Swpaul struct wb_softc *sc; 55341502Swpaul struct wb_mii_frame frame; 55441502Swpaul 55550675Swpaul sc = device_get_softc(dev); 55650675Swpaul 55741502Swpaul bzero((char *)&frame, sizeof(frame)); 55841502Swpaul 55950675Swpaul frame.mii_phyaddr = phy; 56041502Swpaul frame.mii_regaddr = reg; 56141502Swpaul frame.mii_data = data; 56241502Swpaul 56341502Swpaul wb_mii_writereg(sc, &frame); 56441502Swpaul 56550675Swpaul return(0); 56650675Swpaul} 56750675Swpaul 56850675Swpaulstatic void wb_miibus_statchg(dev) 56950675Swpaul device_t dev; 57050675Swpaul{ 57150675Swpaul struct wb_softc *sc; 57250675Swpaul struct mii_data *mii; 57350675Swpaul 57450675Swpaul sc = device_get_softc(dev); 57567087Swpaul WB_LOCK(sc); 57650675Swpaul mii = device_get_softc(sc->wb_miibus); 57750675Swpaul wb_setcfg(sc, mii->mii_media_active); 57867087Swpaul WB_UNLOCK(sc); 57950675Swpaul 58041502Swpaul return; 58141502Swpaul} 58241502Swpaul 58341502Swpaulstatic u_int8_t wb_calchash(addr) 58442718Swpaul caddr_t addr; 58541502Swpaul{ 58641502Swpaul u_int32_t crc, carry; 58741502Swpaul int i, j; 58841502Swpaul u_int8_t c; 58941502Swpaul 59041502Swpaul /* Compute CRC for the address value. */ 59141502Swpaul crc = 0xFFFFFFFF; /* initial value */ 59241502Swpaul 59341502Swpaul for (i = 0; i < 6; i++) { 59441502Swpaul c = *(addr + i); 59541502Swpaul for (j = 0; j < 8; j++) { 59641502Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 59741502Swpaul crc <<= 1; 59841502Swpaul c >>= 1; 59941502Swpaul if (carry) 60041502Swpaul crc = (crc ^ 0x04c11db6) | carry; 60141502Swpaul } 60241502Swpaul } 60341502Swpaul 60441502Swpaul /* 60541502Swpaul * return the filter bit position 60641502Swpaul * Note: I arrived at the following nonsense 60741502Swpaul * through experimentation. It's not the usual way to 60841502Swpaul * generate the bit position but it's the only thing 60941502Swpaul * I could come up with that works. 61041502Swpaul */ 61141502Swpaul return(~(crc >> 26) & 0x0000003F); 61241502Swpaul} 61341502Swpaul 61441502Swpaul/* 61541502Swpaul * Program the 64-bit multicast hash filter. 61641502Swpaul */ 61741502Swpaulstatic void wb_setmulti(sc) 61841502Swpaul struct wb_softc *sc; 61941502Swpaul{ 62041502Swpaul struct ifnet *ifp; 62141502Swpaul int h = 0; 62241502Swpaul u_int32_t hashes[2] = { 0, 0 }; 62341502Swpaul struct ifmultiaddr *ifma; 62441502Swpaul u_int32_t rxfilt; 62541502Swpaul int mcnt = 0; 62641502Swpaul 62741502Swpaul ifp = &sc->arpcom.ac_if; 62841502Swpaul 62941502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 63041502Swpaul 63141502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 63241502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 63341502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 63441502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 63541502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 63641502Swpaul return; 63741502Swpaul } 63841502Swpaul 63941502Swpaul /* first, zot all the existing hash bits */ 64041502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 64141502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 64241502Swpaul 64341502Swpaul /* now program new ones */ 64472084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 64541502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 64641502Swpaul continue; 64741502Swpaul h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 64841502Swpaul if (h < 32) 64941502Swpaul hashes[0] |= (1 << h); 65041502Swpaul else 65141502Swpaul hashes[1] |= (1 << (h - 32)); 65241502Swpaul mcnt++; 65341502Swpaul } 65441502Swpaul 65541502Swpaul if (mcnt) 65641502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 65741502Swpaul else 65841502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 65941502Swpaul 66041502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 66141502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 66241502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 66341502Swpaul 66441502Swpaul return; 66541502Swpaul} 66641502Swpaul 66741502Swpaul/* 66841502Swpaul * The Winbond manual states that in order to fiddle with the 66941502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 67041502Swpaul * first have to put the transmit and/or receive logic in the idle state. 67141502Swpaul */ 67250675Swpaulstatic void wb_setcfg(sc, media) 67341502Swpaul struct wb_softc *sc; 67450675Swpaul u_int32_t media; 67541502Swpaul{ 67641502Swpaul int i, restart = 0; 67741502Swpaul 67841502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 67941502Swpaul restart = 1; 68041502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 68141502Swpaul 68241502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 68341502Swpaul DELAY(10); 68441502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 68541502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 68641502Swpaul break; 68741502Swpaul } 68841502Swpaul 68941502Swpaul if (i == WB_TIMEOUT) 69041502Swpaul printf("wb%d: failed to force tx and " 69141502Swpaul "rx to idle state\n", sc->wb_unit); 69241502Swpaul } 69341502Swpaul 69450675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 69550675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 69650675Swpaul else 69741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 69841502Swpaul 69950675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 70041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 70141502Swpaul else 70241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 70341502Swpaul 70441502Swpaul if (restart) 70541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 70641502Swpaul 70741502Swpaul return; 70841502Swpaul} 70941502Swpaul 71041502Swpaulstatic void wb_reset(sc) 71141502Swpaul struct wb_softc *sc; 71241502Swpaul{ 71341502Swpaul register int i; 71450675Swpaul struct mii_data *mii; 71541502Swpaul 71650675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 71750675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 71850675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 71950675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 72050675Swpaul 72141502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 72250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 72341502Swpaul 72441502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 72541502Swpaul DELAY(10); 72641502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 72741502Swpaul break; 72841502Swpaul } 72941502Swpaul if (i == WB_TIMEOUT) 73041502Swpaul printf("wb%d: reset never completed!\n", sc->wb_unit); 73141502Swpaul 73241502Swpaul /* Wait a little while for the chip to get its brains in order. */ 73341502Swpaul DELAY(1000); 73441502Swpaul 73550675Swpaul if (sc->wb_miibus == NULL) 73650675Swpaul return; 73741502Swpaul 73850675Swpaul mii = device_get_softc(sc->wb_miibus); 73950675Swpaul if (mii == NULL) 74050675Swpaul return; 74150675Swpaul 74250675Swpaul if (mii->mii_instance) { 74350675Swpaul struct mii_softc *miisc; 74472012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 74550675Swpaul mii_phy_reset(miisc); 74650675Swpaul } 74750675Swpaul 74841502Swpaul return; 74941502Swpaul} 75041502Swpaul 75150675Swpaulstatic void wb_fixmedia(sc) 75250675Swpaul struct wb_softc *sc; 75350675Swpaul{ 75450675Swpaul struct mii_data *mii = NULL; 75550675Swpaul struct ifnet *ifp; 75650675Swpaul u_int32_t media; 75750675Swpaul 75850675Swpaul if (sc->wb_miibus == NULL) 75950675Swpaul return; 76050675Swpaul 76150675Swpaul mii = device_get_softc(sc->wb_miibus); 76250675Swpaul ifp = &sc->arpcom.ac_if; 76350675Swpaul 76450675Swpaul mii_pollstat(mii); 76550675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 76650675Swpaul media = mii->mii_media_active & ~IFM_10_T; 76750675Swpaul media |= IFM_100_TX; 76850675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 76950675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 77050675Swpaul media |= IFM_10_T; 77150675Swpaul } else 77250675Swpaul return; 77350675Swpaul 77450675Swpaul ifmedia_set(&mii->mii_media, media); 77550675Swpaul 77650675Swpaul return; 77750675Swpaul} 77850675Swpaul 77941502Swpaul/* 78041502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 78141502Swpaul * IDs against our list and return a device name if we find a match. 78241502Swpaul */ 78349611Swpaulstatic int wb_probe(dev) 78449611Swpaul device_t dev; 78541502Swpaul{ 78641502Swpaul struct wb_type *t; 78741502Swpaul 78841502Swpaul t = wb_devs; 78941502Swpaul 79041502Swpaul while(t->wb_name != NULL) { 79149611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 79249611Swpaul (pci_get_device(dev) == t->wb_did)) { 79349611Swpaul device_set_desc(dev, t->wb_name); 79449611Swpaul return(0); 79541502Swpaul } 79641502Swpaul t++; 79741502Swpaul } 79841502Swpaul 79949611Swpaul return(ENXIO); 80041502Swpaul} 80141502Swpaul 80241502Swpaul/* 80341502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 80441502Swpaul * setup and ethernet/BPF attach. 80541502Swpaul */ 80649611Swpaulstatic int wb_attach(dev) 80749611Swpaul device_t dev; 80841502Swpaul{ 80941502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 81041502Swpaul u_int32_t command; 81141502Swpaul struct wb_softc *sc; 81241502Swpaul struct ifnet *ifp; 81349611Swpaul int unit, error = 0, rid; 81441502Swpaul 81549611Swpaul sc = device_get_softc(dev); 81649611Swpaul unit = device_get_unit(dev); 81741502Swpaul 81871228Sbmilekic mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 81969583Swpaul WB_LOCK(sc); 82069583Swpaul 82141502Swpaul /* 82241502Swpaul * Handle power management nonsense. 82341502Swpaul */ 82441502Swpaul 82549611Swpaul command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 82641502Swpaul if (command == 0x01) { 82741502Swpaul 82849611Swpaul command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 82941502Swpaul if (command & WB_PSTATE_MASK) { 83041502Swpaul u_int32_t iobase, membase, irq; 83141502Swpaul 83241502Swpaul /* Save important PCI config data. */ 83349611Swpaul iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 83449611Swpaul membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 83549611Swpaul irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 83641502Swpaul 83741502Swpaul /* Reset the power state. */ 83841502Swpaul printf("wb%d: chip is in D%d power mode " 83941502Swpaul "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 84041502Swpaul command &= 0xFFFFFFFC; 84149611Swpaul pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 84241502Swpaul 84341502Swpaul /* Restore PCI config data. */ 84449611Swpaul pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 84549611Swpaul pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 84649611Swpaul pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 84741502Swpaul } 84841502Swpaul } 84941502Swpaul 85041502Swpaul /* 85141502Swpaul * Map control/status registers. 85241502Swpaul */ 85361041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 85441502Swpaul command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 85561041Speter pci_write_config(dev, PCIR_COMMAND, command, 4); 85661041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 85741502Swpaul 85841502Swpaul#ifdef WB_USEIOSPACE 85941502Swpaul if (!(command & PCIM_CMD_PORTEN)) { 86041502Swpaul printf("wb%d: failed to enable I/O ports!\n", unit); 86149611Swpaul error = ENXIO; 86241502Swpaul goto fail; 86341502Swpaul } 86441502Swpaul#else 86541502Swpaul if (!(command & PCIM_CMD_MEMEN)) { 86641502Swpaul printf("wb%d: failed to enable memory mapping!\n", unit); 86749611Swpaul error = ENXIO; 86841502Swpaul goto fail; 86941502Swpaul } 87049611Swpaul#endif 87141502Swpaul 87249611Swpaul rid = WB_RID; 87349611Swpaul sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 87449611Swpaul 0, ~0, 1, RF_ACTIVE); 87549611Swpaul 87649611Swpaul if (sc->wb_res == NULL) { 87749611Swpaul printf("wb%d: couldn't map ports/memory\n", unit); 87849611Swpaul error = ENXIO; 87941502Swpaul goto fail; 88041502Swpaul } 88141502Swpaul 88249611Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 88349611Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 88449611Swpaul 88541502Swpaul /* Allocate interrupt */ 88649611Swpaul rid = 0; 88749611Swpaul sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 88849611Swpaul RF_SHAREABLE | RF_ACTIVE); 88949611Swpaul 89049611Swpaul if (sc->wb_irq == NULL) { 89141502Swpaul printf("wb%d: couldn't map interrupt\n", unit); 89249611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 89349611Swpaul error = ENXIO; 89441502Swpaul goto fail; 89541502Swpaul } 89641502Swpaul 89749611Swpaul error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 89849611Swpaul wb_intr, sc, &sc->wb_intrhand); 89949611Swpaul 90049611Swpaul if (error) { 90149611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 90249611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 90349611Swpaul printf("wb%d: couldn't set up irq\n", unit); 90449611Swpaul goto fail; 90549611Swpaul } 90650675Swpaul 90750675Swpaul /* Save the cache line size. */ 90850675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 90950675Swpaul 91041502Swpaul /* Reset the adapter. */ 91141502Swpaul wb_reset(sc); 91241502Swpaul 91341502Swpaul /* 91441502Swpaul * Get station address from the EEPROM. 91541502Swpaul */ 91641502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 91741502Swpaul 91841502Swpaul /* 91941502Swpaul * A Winbond chip was detected. Inform the world. 92041502Swpaul */ 92141502Swpaul printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 92241502Swpaul 92341502Swpaul sc->wb_unit = unit; 92441502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 92541502Swpaul 92650675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 92751657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 92850675Swpaul 92950675Swpaul if (sc->wb_ldata == NULL) { 93041502Swpaul printf("wb%d: no memory for list buffers!\n", unit); 93149611Swpaul bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 93249611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 93349611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 93449611Swpaul error = ENXIO; 93549611Swpaul goto fail; 93641502Swpaul } 93741502Swpaul 93841502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 93941502Swpaul 94041502Swpaul ifp = &sc->arpcom.ac_if; 94141502Swpaul ifp->if_softc = sc; 94241502Swpaul ifp->if_unit = unit; 94341502Swpaul ifp->if_name = "wb"; 94441502Swpaul ifp->if_mtu = ETHERMTU; 94541502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 94641502Swpaul ifp->if_ioctl = wb_ioctl; 94741502Swpaul ifp->if_output = ether_output; 94841502Swpaul ifp->if_start = wb_start; 94941502Swpaul ifp->if_watchdog = wb_watchdog; 95041502Swpaul ifp->if_init = wb_init; 95141502Swpaul ifp->if_baudrate = 10000000; 95243515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 95341502Swpaul 95450675Swpaul /* 95550675Swpaul * Do MII setup. 95650675Swpaul */ 95750675Swpaul if (mii_phy_probe(dev, &sc->wb_miibus, 95850675Swpaul wb_ifmedia_upd, wb_ifmedia_sts)) { 95949611Swpaul bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 96049611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 96149611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 96249611Swpaul free(sc->wb_ldata_ptr, M_DEVBUF); 96349611Swpaul error = ENXIO; 96441502Swpaul goto fail; 96541502Swpaul } 96641502Swpaul 96741502Swpaul /* 96863090Sarchie * Call MI attach routine. 96941502Swpaul */ 97063090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 97167087Swpaul WB_UNLOCK(sc); 97267087Swpaul return(0); 97341502Swpaul 97441502Swpaulfail: 97550675Swpaul if (error) 97650675Swpaul device_delete_child(dev, sc->wb_miibus); 97767087Swpaul WB_UNLOCK(sc); 97867087Swpaul mtx_destroy(&sc->wb_mtx); 97950675Swpaul 98049611Swpaul return(error); 98141502Swpaul} 98241502Swpaul 98349611Swpaulstatic int wb_detach(dev) 98449611Swpaul device_t dev; 98549611Swpaul{ 98649611Swpaul struct wb_softc *sc; 98749611Swpaul struct ifnet *ifp; 98849611Swpaul 98949611Swpaul sc = device_get_softc(dev); 99067087Swpaul WB_LOCK(sc); 99149611Swpaul ifp = &sc->arpcom.ac_if; 99249611Swpaul 99349611Swpaul wb_stop(sc); 99463090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 99549611Swpaul 99650675Swpaul /* Delete any miibus and phy devices attached to this interface */ 99750675Swpaul bus_generic_detach(dev); 99850675Swpaul device_delete_child(dev, sc->wb_miibus); 99950675Swpaul 100049611Swpaul bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 100149611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 100249611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 100349611Swpaul 100449611Swpaul free(sc->wb_ldata_ptr, M_DEVBUF); 100549611Swpaul 100667087Swpaul WB_UNLOCK(sc); 100767087Swpaul mtx_destroy(&sc->wb_mtx); 100849611Swpaul 100949611Swpaul return(0); 101049611Swpaul} 101149611Swpaul 101241502Swpaul/* 101341502Swpaul * Initialize the transmit descriptors. 101441502Swpaul */ 101541502Swpaulstatic int wb_list_tx_init(sc) 101641502Swpaul struct wb_softc *sc; 101741502Swpaul{ 101841502Swpaul struct wb_chain_data *cd; 101941502Swpaul struct wb_list_data *ld; 102041502Swpaul int i; 102141502Swpaul 102241502Swpaul cd = &sc->wb_cdata; 102341502Swpaul ld = sc->wb_ldata; 102441502Swpaul 102541502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 102641502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 102741502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 102841502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 102941502Swpaul &cd->wb_tx_chain[0]; 103041502Swpaul } else { 103141502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 103241502Swpaul &cd->wb_tx_chain[i + 1]; 103341502Swpaul } 103441502Swpaul } 103541502Swpaul 103641502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 103741502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 103841502Swpaul 103941502Swpaul return(0); 104041502Swpaul} 104141502Swpaul 104241502Swpaul 104341502Swpaul/* 104441502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 104541502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 104641502Swpaul * points back to the first. 104741502Swpaul */ 104841502Swpaulstatic int wb_list_rx_init(sc) 104941502Swpaul struct wb_softc *sc; 105041502Swpaul{ 105141502Swpaul struct wb_chain_data *cd; 105241502Swpaul struct wb_list_data *ld; 105341502Swpaul int i; 105441502Swpaul 105541502Swpaul cd = &sc->wb_cdata; 105641502Swpaul ld = sc->wb_ldata; 105741502Swpaul 105841502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 105941502Swpaul cd->wb_rx_chain[i].wb_ptr = 106041502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 106150675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 106248745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 106341502Swpaul return(ENOBUFS); 106441502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 106541502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 106641502Swpaul ld->wb_rx_list[i].wb_next = 106741502Swpaul vtophys(&ld->wb_rx_list[0]); 106841502Swpaul } else { 106941502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 107041502Swpaul &cd->wb_rx_chain[i + 1]; 107141502Swpaul ld->wb_rx_list[i].wb_next = 107241502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 107341502Swpaul } 107441502Swpaul } 107541502Swpaul 107641502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 107741502Swpaul 107841502Swpaul return(0); 107941502Swpaul} 108041502Swpaul 108164837Sdwmalonestatic void wb_bfree(buf, args) 108250675Swpaul caddr_t buf; 108364837Sdwmalone void *args; 108450675Swpaul{ 108550675Swpaul return; 108650675Swpaul} 108750675Swpaul 108841502Swpaul/* 108941502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 109041502Swpaul */ 109148745Swpaulstatic int wb_newbuf(sc, c, m) 109241502Swpaul struct wb_softc *sc; 109341502Swpaul struct wb_chain_onefrag *c; 109448745Swpaul struct mbuf *m; 109541502Swpaul{ 109641502Swpaul struct mbuf *m_new = NULL; 109741502Swpaul 109848745Swpaul if (m == NULL) { 109948745Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 110048745Swpaul if (m_new == NULL) { 110148745Swpaul printf("wb%d: no memory for rx " 110248745Swpaul "list -- packet dropped!\n", sc->wb_unit); 110348745Swpaul return(ENOBUFS); 110448745Swpaul } 110564837Sdwmalone m_new->m_data = c->wb_buf; 110664837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 110768621Sbmilekic MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 110868621Sbmilekic EXT_NET_DRV); 110948745Swpaul } else { 111048745Swpaul m_new = m; 111150675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 111248745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 111341502Swpaul } 111441502Swpaul 111548745Swpaul m_adj(m_new, sizeof(u_int64_t)); 111648745Swpaul 111741502Swpaul c->wb_mbuf = m_new; 111841502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 111950675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 112041502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 112141502Swpaul 112241502Swpaul return(0); 112341502Swpaul} 112441502Swpaul 112541502Swpaul/* 112641502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 112741502Swpaul * the higher level protocols. 112841502Swpaul */ 112941502Swpaulstatic void wb_rxeof(sc) 113041502Swpaul struct wb_softc *sc; 113141502Swpaul{ 113241502Swpaul struct ether_header *eh; 113350675Swpaul struct mbuf *m = NULL; 113441502Swpaul struct ifnet *ifp; 113541502Swpaul struct wb_chain_onefrag *cur_rx; 113641502Swpaul int total_len = 0; 113741502Swpaul u_int32_t rxstat; 113841502Swpaul 113941502Swpaul ifp = &sc->arpcom.ac_if; 114041502Swpaul 114141502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 114241502Swpaul WB_RXSTAT_OWN)) { 114348745Swpaul struct mbuf *m0 = NULL; 114448745Swpaul 114541502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 114641502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 114750675Swpaul 114848745Swpaul m = cur_rx->wb_mbuf; 114941502Swpaul 115050675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 115150675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 115250675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 115350675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 115450675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 115541502Swpaul ifp->if_ierrors++; 115650675Swpaul wb_newbuf(sc, cur_rx, m); 115741502Swpaul printf("wb%x: receiver babbling: possible chip " 115841502Swpaul "bug, forcing reset\n", sc->wb_unit); 115950675Swpaul wb_fixmedia(sc); 116050675Swpaul wb_reset(sc); 116150675Swpaul wb_init(sc); 116241502Swpaul return; 116341502Swpaul } 116441502Swpaul 116542718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 116642718Swpaul ifp->if_ierrors++; 116748745Swpaul wb_newbuf(sc, cur_rx, m); 116850675Swpaul break; 116942718Swpaul } 117042718Swpaul 117141502Swpaul /* No errors; receive the packet. */ 117241502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 117341502Swpaul 117441502Swpaul /* 117541934Swpaul * XXX The Winbond chip includes the CRC with every 117641934Swpaul * received frame, and there's no way to turn this 117741934Swpaul * behavior off (at least, I can't find anything in 117841934Swpaul * the manual that explains how to do it) so we have 117941934Swpaul * to trim off the CRC manually. 118041934Swpaul */ 118141934Swpaul total_len -= ETHER_CRC_LEN; 118241934Swpaul 118348745Swpaul m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 118448745Swpaul total_len + ETHER_ALIGN, 0, ifp, NULL); 118548745Swpaul wb_newbuf(sc, cur_rx, m); 118648745Swpaul if (m0 == NULL) { 118748745Swpaul ifp->if_ierrors++; 118850675Swpaul break; 118941502Swpaul } 119048745Swpaul m_adj(m0, ETHER_ALIGN); 119148745Swpaul m = m0; 119241502Swpaul 119341502Swpaul ifp->if_ipackets++; 119441502Swpaul eh = mtod(m, struct ether_header *); 119541502Swpaul 119641502Swpaul /* Remove header from mbuf and pass it on. */ 119741502Swpaul m_adj(m, sizeof(struct ether_header)); 119841502Swpaul ether_input(ifp, eh, m); 119941502Swpaul } 120041502Swpaul} 120141502Swpaul 120241502Swpaulvoid wb_rxeoc(sc) 120341502Swpaul struct wb_softc *sc; 120441502Swpaul{ 120541502Swpaul wb_rxeof(sc); 120641502Swpaul 120741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120841502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 120941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 121041502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 121141502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 121241502Swpaul 121341502Swpaul return; 121441502Swpaul} 121541502Swpaul 121641502Swpaul/* 121741502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 121841502Swpaul * the list buffers. 121941502Swpaul */ 122041502Swpaulstatic void wb_txeof(sc) 122141502Swpaul struct wb_softc *sc; 122241502Swpaul{ 122341502Swpaul struct wb_chain *cur_tx; 122441502Swpaul struct ifnet *ifp; 122541502Swpaul 122641502Swpaul ifp = &sc->arpcom.ac_if; 122741502Swpaul 122841502Swpaul /* Clear the timeout timer. */ 122941502Swpaul ifp->if_timer = 0; 123041502Swpaul 123141502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 123241502Swpaul return; 123341502Swpaul 123441502Swpaul /* 123541502Swpaul * Go through our tx list and free mbufs for those 123641502Swpaul * frames that have been transmitted. 123741502Swpaul */ 123841502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 123941502Swpaul u_int32_t txstat; 124041502Swpaul 124141502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 124241502Swpaul txstat = WB_TXSTATUS(cur_tx); 124341502Swpaul 124441502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 124541502Swpaul break; 124641502Swpaul 124741502Swpaul if (txstat & WB_TXSTAT_TXERR) { 124841502Swpaul ifp->if_oerrors++; 124941502Swpaul if (txstat & WB_TXSTAT_ABORT) 125041502Swpaul ifp->if_collisions++; 125141502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 125241502Swpaul ifp->if_collisions++; 125341502Swpaul } 125441502Swpaul 125541502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 125641502Swpaul 125741502Swpaul ifp->if_opackets++; 125841502Swpaul m_freem(cur_tx->wb_mbuf); 125941502Swpaul cur_tx->wb_mbuf = NULL; 126041502Swpaul 126141502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 126241502Swpaul sc->wb_cdata.wb_tx_head = NULL; 126341502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 126441502Swpaul break; 126541502Swpaul } 126641502Swpaul 126741502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 126841502Swpaul } 126941502Swpaul 127041502Swpaul return; 127141502Swpaul} 127241502Swpaul 127341502Swpaul/* 127441502Swpaul * TX 'end of channel' interrupt handler. 127541502Swpaul */ 127641502Swpaulstatic void wb_txeoc(sc) 127741502Swpaul struct wb_softc *sc; 127841502Swpaul{ 127941502Swpaul struct ifnet *ifp; 128041502Swpaul 128141502Swpaul ifp = &sc->arpcom.ac_if; 128241502Swpaul 128341502Swpaul ifp->if_timer = 0; 128441502Swpaul 128541502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 128641502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 128741502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 128841502Swpaul } else { 128941502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 129041502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 129141502Swpaul ifp->if_timer = 5; 129241502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 129341502Swpaul } 129441502Swpaul } 129541502Swpaul 129641502Swpaul return; 129741502Swpaul} 129841502Swpaul 129941502Swpaulstatic void wb_intr(arg) 130041502Swpaul void *arg; 130141502Swpaul{ 130241502Swpaul struct wb_softc *sc; 130341502Swpaul struct ifnet *ifp; 130441502Swpaul u_int32_t status; 130541502Swpaul 130641502Swpaul sc = arg; 130767087Swpaul WB_LOCK(sc); 130841502Swpaul ifp = &sc->arpcom.ac_if; 130941502Swpaul 131067087Swpaul if (!(ifp->if_flags & IFF_UP)) { 131167087Swpaul WB_UNLOCK(sc); 131241502Swpaul return; 131367087Swpaul } 131441502Swpaul 131541502Swpaul /* Disable interrupts. */ 131641502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 131741502Swpaul 131841502Swpaul for (;;) { 131941502Swpaul 132041502Swpaul status = CSR_READ_4(sc, WB_ISR); 132141502Swpaul if (status) 132241502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 132341502Swpaul 132441502Swpaul if ((status & WB_INTRS) == 0) 132541502Swpaul break; 132641502Swpaul 132741502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 132841502Swpaul ifp->if_ierrors++; 132941502Swpaul wb_reset(sc); 133050675Swpaul if (status & WB_ISR_RX_ERR) 133150675Swpaul wb_fixmedia(sc); 133241502Swpaul wb_init(sc); 133350675Swpaul continue; 133441502Swpaul } 133541502Swpaul 133650675Swpaul if (status & WB_ISR_RX_OK) 133750675Swpaul wb_rxeof(sc); 133850675Swpaul 133950675Swpaul if (status & WB_ISR_RX_IDLE) 134050675Swpaul wb_rxeoc(sc); 134150675Swpaul 134241502Swpaul if (status & WB_ISR_TX_OK) 134341502Swpaul wb_txeof(sc); 134441502Swpaul 134541502Swpaul if (status & WB_ISR_TX_NOBUF) 134641502Swpaul wb_txeoc(sc); 134741502Swpaul 134841502Swpaul if (status & WB_ISR_TX_IDLE) { 134941502Swpaul wb_txeof(sc); 135041502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 135141502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 135241502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 135341502Swpaul } 135441502Swpaul } 135541502Swpaul 135641502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 135741502Swpaul ifp->if_oerrors++; 135841502Swpaul wb_txeof(sc); 135941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 136041502Swpaul /* Jack up TX threshold */ 136141502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 136241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 136341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 136441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 136541502Swpaul } 136641502Swpaul 136741502Swpaul if (status & WB_ISR_BUS_ERR) { 136841502Swpaul wb_reset(sc); 136941502Swpaul wb_init(sc); 137041502Swpaul } 137141502Swpaul 137241502Swpaul } 137341502Swpaul 137441502Swpaul /* Re-enable interrupts. */ 137541502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 137641502Swpaul 137741502Swpaul if (ifp->if_snd.ifq_head != NULL) { 137841502Swpaul wb_start(ifp); 137941502Swpaul } 138041502Swpaul 138167087Swpaul WB_UNLOCK(sc); 138267087Swpaul 138341502Swpaul return; 138441502Swpaul} 138541502Swpaul 138650675Swpaulstatic void wb_tick(xsc) 138750675Swpaul void *xsc; 138850675Swpaul{ 138950675Swpaul struct wb_softc *sc; 139050675Swpaul struct mii_data *mii; 139150675Swpaul 139250675Swpaul sc = xsc; 139367087Swpaul WB_LOCK(sc); 139450675Swpaul mii = device_get_softc(sc->wb_miibus); 139550675Swpaul 139650675Swpaul mii_tick(mii); 139750675Swpaul 139850675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 139950675Swpaul 140067087Swpaul WB_UNLOCK(sc); 140150685Swpaul 140250675Swpaul return; 140350675Swpaul} 140450675Swpaul 140541502Swpaul/* 140641502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 140741502Swpaul * pointers to the fragment pointers. 140841502Swpaul */ 140941502Swpaulstatic int wb_encap(sc, c, m_head) 141041502Swpaul struct wb_softc *sc; 141141502Swpaul struct wb_chain *c; 141241502Swpaul struct mbuf *m_head; 141341502Swpaul{ 141441502Swpaul int frag = 0; 141541502Swpaul struct wb_desc *f = NULL; 141641502Swpaul int total_len; 141741502Swpaul struct mbuf *m; 141841502Swpaul 141941502Swpaul /* 142041502Swpaul * Start packing the mbufs in this chain into 142141502Swpaul * the fragment pointers. Stop when we run out 142241502Swpaul * of fragments or hit the end of the mbuf chain. 142341502Swpaul */ 142441502Swpaul m = m_head; 142541502Swpaul total_len = 0; 142641502Swpaul 142741502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 142841502Swpaul if (m->m_len != 0) { 142941502Swpaul if (frag == WB_MAXFRAGS) 143041502Swpaul break; 143141502Swpaul total_len += m->m_len; 143241502Swpaul f = &c->wb_ptr->wb_frag[frag]; 143341502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 143441502Swpaul if (frag == 0) { 143541502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 143641502Swpaul f->wb_status = 0; 143741502Swpaul } else 143841502Swpaul f->wb_status = WB_TXSTAT_OWN; 143941502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 144041502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 144141502Swpaul frag++; 144241502Swpaul } 144341502Swpaul } 144441502Swpaul 144541502Swpaul /* 144641502Swpaul * Handle special case: we used up all 16 fragments, 144741502Swpaul * but we have more mbufs left in the chain. Copy the 144841502Swpaul * data into an mbuf cluster. Note that we don't 144941502Swpaul * bother clearing the values in the other fragment 145041502Swpaul * pointers/counters; it wouldn't gain us anything, 145141502Swpaul * and would waste cycles. 145241502Swpaul */ 145341502Swpaul if (m != NULL) { 145441502Swpaul struct mbuf *m_new = NULL; 145541502Swpaul 145641502Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 145741502Swpaul if (m_new == NULL) { 145841502Swpaul printf("wb%d: no memory for tx list", sc->wb_unit); 145941502Swpaul return(1); 146041502Swpaul } 146141502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 146241502Swpaul MCLGET(m_new, M_DONTWAIT); 146341502Swpaul if (!(m_new->m_flags & M_EXT)) { 146441502Swpaul m_freem(m_new); 146541502Swpaul printf("wb%d: no memory for tx list", 146641502Swpaul sc->wb_unit); 146741502Swpaul return(1); 146841502Swpaul } 146941502Swpaul } 147041502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 147141502Swpaul mtod(m_new, caddr_t)); 147241502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 147341502Swpaul m_freem(m_head); 147441502Swpaul m_head = m_new; 147541502Swpaul f = &c->wb_ptr->wb_frag[0]; 147641502Swpaul f->wb_status = 0; 147741502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 147841502Swpaul f->wb_ctl = total_len = m_new->m_len; 147941502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 148041502Swpaul frag = 1; 148141502Swpaul } 148241502Swpaul 148341502Swpaul if (total_len < WB_MIN_FRAMELEN) { 148441502Swpaul f = &c->wb_ptr->wb_frag[frag]; 148541502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 148641502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 148741502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 148841502Swpaul f->wb_status = WB_TXSTAT_OWN; 148941502Swpaul frag++; 149041502Swpaul } 149141502Swpaul 149241502Swpaul c->wb_mbuf = m_head; 149341502Swpaul c->wb_lastdesc = frag - 1; 149441502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 149541502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 149641502Swpaul 149741502Swpaul return(0); 149841502Swpaul} 149941502Swpaul 150041502Swpaul/* 150141502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 150241502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 150341502Swpaul * copy of the pointers since the transmit list fragment pointers are 150441502Swpaul * physical addresses. 150541502Swpaul */ 150641502Swpaul 150741502Swpaulstatic void wb_start(ifp) 150841502Swpaul struct ifnet *ifp; 150941502Swpaul{ 151041502Swpaul struct wb_softc *sc; 151141502Swpaul struct mbuf *m_head = NULL; 151241502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 151341502Swpaul 151441502Swpaul sc = ifp->if_softc; 151567087Swpaul WB_LOCK(sc); 151641502Swpaul 151741502Swpaul /* 151841502Swpaul * Check for an available queue slot. If there are none, 151941502Swpaul * punt. 152041502Swpaul */ 152141502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 152241502Swpaul ifp->if_flags |= IFF_OACTIVE; 152367087Swpaul WB_UNLOCK(sc); 152441502Swpaul return; 152541502Swpaul } 152641502Swpaul 152741502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 152841502Swpaul 152941502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 153041502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 153141502Swpaul if (m_head == NULL) 153241502Swpaul break; 153341502Swpaul 153441502Swpaul /* Pick a descriptor off the free list. */ 153541502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 153641502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 153741502Swpaul 153841502Swpaul /* Pack the data into the descriptor. */ 153941502Swpaul wb_encap(sc, cur_tx, m_head); 154041502Swpaul 154141502Swpaul if (cur_tx != start_tx) 154241502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 154341502Swpaul 154441502Swpaul /* 154541502Swpaul * If there's a BPF listener, bounce a copy of this frame 154641502Swpaul * to him. 154741502Swpaul */ 154841502Swpaul if (ifp->if_bpf) 154941502Swpaul bpf_mtap(ifp, cur_tx->wb_mbuf); 155041502Swpaul } 155141502Swpaul 155241502Swpaul /* 155341526Swpaul * If there are no packets queued, bail. 155441526Swpaul */ 155567087Swpaul if (cur_tx == NULL) { 155667087Swpaul WB_UNLOCK(sc); 155741526Swpaul return; 155867087Swpaul } 155941526Swpaul 156041526Swpaul /* 156141502Swpaul * Place the request for the upload interrupt 156241502Swpaul * in the last descriptor in the chain. This way, if 156341502Swpaul * we're chaining several packets at once, we'll only 156441502Swpaul * get an interupt once for the whole chain rather than 156541502Swpaul * once for each packet. 156641502Swpaul */ 156741502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 156842718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 156941502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 157041502Swpaul 157141502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 157241502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 157341502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 157441502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 157541502Swpaul } else { 157641502Swpaul /* 157741502Swpaul * We need to distinguish between the case where 157841502Swpaul * the own bit is clear because the chip cleared it 157941502Swpaul * and where the own bit is clear because we haven't 158041502Swpaul * set it yet. The magic value WB_UNSET is just some 158141502Swpaul * ramdomly chosen number which doesn't have the own 158241502Swpaul * bit set. When we actually transmit the frame, the 158341502Swpaul * status word will have _only_ the own bit set, so 158441502Swpaul * the txeoc handler will be able to tell if it needs 158541502Swpaul * to initiate another transmission to flush out pending 158641502Swpaul * frames. 158741502Swpaul */ 158841502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 158941502Swpaul } 159041502Swpaul 159141502Swpaul /* 159241502Swpaul * Set a timeout in case the chip goes out to lunch. 159341502Swpaul */ 159441502Swpaul ifp->if_timer = 5; 159567087Swpaul WB_UNLOCK(sc); 159641502Swpaul 159741502Swpaul return; 159841502Swpaul} 159941502Swpaul 160041502Swpaulstatic void wb_init(xsc) 160141502Swpaul void *xsc; 160241502Swpaul{ 160341502Swpaul struct wb_softc *sc = xsc; 160441502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 160567087Swpaul int i; 160650675Swpaul struct mii_data *mii; 160741502Swpaul 160867087Swpaul WB_LOCK(sc); 160950675Swpaul mii = device_get_softc(sc->wb_miibus); 161041502Swpaul 161141502Swpaul /* 161241502Swpaul * Cancel pending I/O and free all RX/TX buffers. 161341502Swpaul */ 161441502Swpaul wb_stop(sc); 161541502Swpaul wb_reset(sc); 161641502Swpaul 161741502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 161841502Swpaul 161941502Swpaul /* 162041502Swpaul * Set cache alignment and burst length. 162141502Swpaul */ 162250675Swpaul#ifdef foo 162341502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 162441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 162541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 162650675Swpaul#endif 162741502Swpaul 162850675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 162950675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 163050675Swpaul switch(sc->wb_cachesize) { 163150675Swpaul case 32: 163250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 163350675Swpaul break; 163450675Swpaul case 16: 163550675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 163650675Swpaul break; 163750675Swpaul case 8: 163850675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 163950675Swpaul break; 164050675Swpaul case 0: 164150675Swpaul default: 164250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 164350675Swpaul break; 164450675Swpaul } 164550675Swpaul 164641502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 164741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 164841502Swpaul 164941502Swpaul /* Init our MAC address */ 165041502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 165141502Swpaul CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 165241502Swpaul } 165341502Swpaul 165441502Swpaul /* Init circular RX list. */ 165541502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 165641502Swpaul printf("wb%d: initialization failed: no " 165741502Swpaul "memory for rx buffers\n", sc->wb_unit); 165841502Swpaul wb_stop(sc); 165967087Swpaul WB_UNLOCK(sc); 166041502Swpaul return; 166141502Swpaul } 166241502Swpaul 166341502Swpaul /* Init TX descriptors. */ 166441502Swpaul wb_list_tx_init(sc); 166541502Swpaul 166641502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 166741502Swpaul if (ifp->if_flags & IFF_PROMISC) { 166841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 166941502Swpaul } else { 167041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 167141502Swpaul } 167241502Swpaul 167341502Swpaul /* 167441502Swpaul * Set capture broadcast bit to capture broadcast frames. 167541502Swpaul */ 167641502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 167741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 167841502Swpaul } else { 167941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 168041502Swpaul } 168141502Swpaul 168241502Swpaul /* 168341502Swpaul * Program the multicast filter, if necessary. 168441502Swpaul */ 168541502Swpaul wb_setmulti(sc); 168641502Swpaul 168741502Swpaul /* 168841502Swpaul * Load the address of the RX list. 168941502Swpaul */ 169041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 169141502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 169241502Swpaul 169341502Swpaul /* 169441502Swpaul * Enable interrupts. 169541502Swpaul */ 169641502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 169741502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 169841502Swpaul 169941502Swpaul /* Enable receiver and transmitter. */ 170041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 170141502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 170241502Swpaul 170341502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 170441502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 170541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 170641502Swpaul 170750675Swpaul mii_mediachg(mii); 170841502Swpaul 170941502Swpaul ifp->if_flags |= IFF_RUNNING; 171041502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 171141502Swpaul 171250675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 171367087Swpaul WB_UNLOCK(sc); 171450675Swpaul 171541502Swpaul return; 171641502Swpaul} 171741502Swpaul 171841502Swpaul/* 171941502Swpaul * Set media options. 172041502Swpaul */ 172141502Swpaulstatic int wb_ifmedia_upd(ifp) 172241502Swpaul struct ifnet *ifp; 172341502Swpaul{ 172441502Swpaul struct wb_softc *sc; 172541502Swpaul 172641502Swpaul sc = ifp->if_softc; 172741502Swpaul 172850675Swpaul if (ifp->if_flags & IFF_UP) 172950675Swpaul wb_init(sc); 173041502Swpaul 173141502Swpaul return(0); 173241502Swpaul} 173341502Swpaul 173441502Swpaul/* 173541502Swpaul * Report current media status. 173641502Swpaul */ 173741502Swpaulstatic void wb_ifmedia_sts(ifp, ifmr) 173841502Swpaul struct ifnet *ifp; 173941502Swpaul struct ifmediareq *ifmr; 174041502Swpaul{ 174141502Swpaul struct wb_softc *sc; 174250675Swpaul struct mii_data *mii; 174341502Swpaul 174441502Swpaul sc = ifp->if_softc; 174541502Swpaul 174650675Swpaul mii = device_get_softc(sc->wb_miibus); 174741502Swpaul 174850675Swpaul mii_pollstat(mii); 174950675Swpaul ifmr->ifm_active = mii->mii_media_active; 175050675Swpaul ifmr->ifm_status = mii->mii_media_status; 175141502Swpaul 175241502Swpaul return; 175341502Swpaul} 175441502Swpaul 175541502Swpaulstatic int wb_ioctl(ifp, command, data) 175641502Swpaul struct ifnet *ifp; 175741502Swpaul u_long command; 175841502Swpaul caddr_t data; 175941502Swpaul{ 176041502Swpaul struct wb_softc *sc = ifp->if_softc; 176150675Swpaul struct mii_data *mii; 176241502Swpaul struct ifreq *ifr = (struct ifreq *) data; 176367087Swpaul int error = 0; 176441502Swpaul 176567087Swpaul WB_LOCK(sc); 176641502Swpaul 176741502Swpaul switch(command) { 176841502Swpaul case SIOCSIFADDR: 176941502Swpaul case SIOCGIFADDR: 177041502Swpaul case SIOCSIFMTU: 177141502Swpaul error = ether_ioctl(ifp, command, data); 177241502Swpaul break; 177341502Swpaul case SIOCSIFFLAGS: 177441502Swpaul if (ifp->if_flags & IFF_UP) { 177541502Swpaul wb_init(sc); 177641502Swpaul } else { 177741502Swpaul if (ifp->if_flags & IFF_RUNNING) 177841502Swpaul wb_stop(sc); 177941502Swpaul } 178041502Swpaul error = 0; 178141502Swpaul break; 178241502Swpaul case SIOCADDMULTI: 178341502Swpaul case SIOCDELMULTI: 178441502Swpaul wb_setmulti(sc); 178541502Swpaul error = 0; 178641502Swpaul break; 178741502Swpaul case SIOCGIFMEDIA: 178841502Swpaul case SIOCSIFMEDIA: 178950675Swpaul mii = device_get_softc(sc->wb_miibus); 179050675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 179141502Swpaul break; 179241502Swpaul default: 179341502Swpaul error = EINVAL; 179441502Swpaul break; 179541502Swpaul } 179641502Swpaul 179767087Swpaul WB_UNLOCK(sc); 179841502Swpaul 179941502Swpaul return(error); 180041502Swpaul} 180141502Swpaul 180241502Swpaulstatic void wb_watchdog(ifp) 180341502Swpaul struct ifnet *ifp; 180441502Swpaul{ 180541502Swpaul struct wb_softc *sc; 180641502Swpaul 180741502Swpaul sc = ifp->if_softc; 180841502Swpaul 180967087Swpaul WB_LOCK(sc); 181041502Swpaul ifp->if_oerrors++; 181141502Swpaul printf("wb%d: watchdog timeout\n", sc->wb_unit); 181250675Swpaul#ifdef foo 181341502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 181441502Swpaul printf("wb%d: no carrier - transceiver cable problem?\n", 181541502Swpaul sc->wb_unit); 181650675Swpaul#endif 181741502Swpaul wb_stop(sc); 181841502Swpaul wb_reset(sc); 181941502Swpaul wb_init(sc); 182041502Swpaul 182141502Swpaul if (ifp->if_snd.ifq_head != NULL) 182241502Swpaul wb_start(ifp); 182367087Swpaul WB_UNLOCK(sc); 182441502Swpaul 182541502Swpaul return; 182641502Swpaul} 182741502Swpaul 182841502Swpaul/* 182941502Swpaul * Stop the adapter and free any mbufs allocated to the 183041502Swpaul * RX and TX lists. 183141502Swpaul */ 183241502Swpaulstatic void wb_stop(sc) 183341502Swpaul struct wb_softc *sc; 183441502Swpaul{ 183541502Swpaul register int i; 183641502Swpaul struct ifnet *ifp; 183741502Swpaul 183867087Swpaul WB_LOCK(sc); 183941502Swpaul ifp = &sc->arpcom.ac_if; 184041502Swpaul ifp->if_timer = 0; 184141502Swpaul 184250675Swpaul untimeout(wb_tick, sc, sc->wb_stat_ch); 184350675Swpaul 184441502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 184541502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 184641502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 184741502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 184841502Swpaul 184941502Swpaul /* 185041502Swpaul * Free data in the RX lists. 185141502Swpaul */ 185241502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 185341502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 185441502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 185541502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 185641502Swpaul } 185741502Swpaul } 185841502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 185941502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 186041502Swpaul 186141502Swpaul /* 186241502Swpaul * Free the TX list buffers. 186341502Swpaul */ 186441502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 186541502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 186641502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 186741502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 186841502Swpaul } 186941502Swpaul } 187041502Swpaul 187141502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 187241502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 187341502Swpaul 187441502Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 187567087Swpaul WB_UNLOCK(sc); 187641502Swpaul 187741502Swpaul return; 187841502Swpaul} 187941502Swpaul 188041502Swpaul/* 188141502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 188241502Swpaul * get confused by errant DMAs when rebooting. 188341502Swpaul */ 188449611Swpaulstatic void wb_shutdown(dev) 188549611Swpaul device_t dev; 188641502Swpaul{ 188749611Swpaul struct wb_softc *sc; 188841502Swpaul 188949611Swpaul sc = device_get_softc(dev); 189041502Swpaul wb_stop(sc); 189141502Swpaul 189241502Swpaul return; 189341502Swpaul} 1894