if_wb.c revision 213894
1139825Simp/*- 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/dev/wb/if_wb.c 213894 2010-10-15 15:00:30Z marius $"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * Winbond fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 4041502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 4141502Swpaul * Winbond itself and some made by Linksys. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 4741502Swpaul/* 4841502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4941502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 5041502Swpaul * one major difference which is that while the registers do many of 5141502Swpaul * the same things as a tulip adapter, the offsets are different: where 5241502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5341502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5441502Swpaul * programmed differently. 5541502Swpaul * 5641502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5741502Swpaul * a status word, a control word and 32-bit areas that can either be used 5841502Swpaul * to point to two external data blocks, or to point to a single block 5941502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 6041502Swpaul * together in blocks to form fixed length rings or can be chained 6141502Swpaul * together in linked lists. A single packet may be spread out over 6241502Swpaul * several descriptors if necessary. 6341502Swpaul * 6441502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6541502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6641502Swpaul * to hold an entire packet. The link list is looped back to created a 6741502Swpaul * closed ring. 6841502Swpaul * 6941502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 7041502Swpaul * which each contain several individual descriptors linked toghether. 7141502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7241502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7341502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7441502Swpaul * drivers. 7541502Swpaul * 7641502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7741502Swpaul * The sample boards I have all use a Davicom PHY. 7841502Swpaul * 7941502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 8041502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 8141502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8241502Swpaul * I have no idea what he's on about: transmit performance with all 8341502Swpaul * three of my test boards seems fine. 8441502Swpaul */ 8541502Swpaul 8641502Swpaul#include <sys/param.h> 8741502Swpaul#include <sys/systm.h> 8841502Swpaul#include <sys/sockio.h> 8941502Swpaul#include <sys/mbuf.h> 9041502Swpaul#include <sys/malloc.h> 91129878Sphk#include <sys/module.h> 9241502Swpaul#include <sys/kernel.h> 9341502Swpaul#include <sys/socket.h> 9450675Swpaul#include <sys/queue.h> 9541502Swpaul 9641502Swpaul#include <net/if.h> 9741502Swpaul#include <net/if_arp.h> 9841502Swpaul#include <net/ethernet.h> 9941502Swpaul#include <net/if_dl.h> 10041502Swpaul#include <net/if_media.h> 101147256Sbrooks#include <net/if_types.h> 10241502Swpaul 10341502Swpaul#include <net/bpf.h> 10441502Swpaul 10541502Swpaul#include <vm/vm.h> /* for vtophys */ 10641502Swpaul#include <vm/pmap.h> /* for vtophys */ 10741502Swpaul#include <machine/bus.h> 10849611Swpaul#include <machine/resource.h> 10949611Swpaul#include <sys/bus.h> 11049611Swpaul#include <sys/rman.h> 11141502Swpaul 112119288Simp#include <dev/pci/pcireg.h> 113119288Simp#include <dev/pci/pcivar.h> 11441502Swpaul 11550675Swpaul#include <dev/mii/mii.h> 11650675Swpaul#include <dev/mii/miivar.h> 11750675Swpaul 118151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 11950675Swpaul#include "miibus_if.h" 12050675Swpaul 12141502Swpaul#define WB_USEIOSPACE 12241502Swpaul 123181741Simp#include <dev/wb/if_wbreg.h> 12441502Swpaul 125113506SmdoddMODULE_DEPEND(wb, pci, 1, 1, 1); 126113506SmdoddMODULE_DEPEND(wb, ether, 1, 1, 1); 12759758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 12859758Speter 12941502Swpaul/* 13041502Swpaul * Various supported device vendors/types and their names. 13141502Swpaul */ 13241502Swpaulstatic struct wb_type wb_devs[] = { 13341502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13441502Swpaul "Winbond W89C840F 10/100BaseTX" }, 13541502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 13641502Swpaul "Compex RL100-ATX 10/100baseTX" }, 13741502Swpaul { 0, 0, NULL } 13841502Swpaul}; 13941502Swpaul 140142407Simpstatic int wb_probe(device_t); 141142407Simpstatic int wb_attach(device_t); 142142407Simpstatic int wb_detach(device_t); 14341502Swpaul 144142407Simpstatic void wb_bfree(void *addr, void *args); 145142407Simpstatic int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 146142407Simp struct mbuf *); 147142407Simpstatic int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 14841502Swpaul 149142407Simpstatic void wb_rxeof(struct wb_softc *); 150142407Simpstatic void wb_rxeoc(struct wb_softc *); 151142407Simpstatic void wb_txeof(struct wb_softc *); 152142407Simpstatic void wb_txeoc(struct wb_softc *); 153142407Simpstatic void wb_intr(void *); 154142407Simpstatic void wb_tick(void *); 155142407Simpstatic void wb_start(struct ifnet *); 156151774Sjhbstatic void wb_start_locked(struct ifnet *); 157142407Simpstatic int wb_ioctl(struct ifnet *, u_long, caddr_t); 158142407Simpstatic void wb_init(void *); 159151774Sjhbstatic void wb_init_locked(struct wb_softc *); 160142407Simpstatic void wb_stop(struct wb_softc *); 161199560Sjhbstatic void wb_watchdog(struct wb_softc *); 162194023Savgstatic int wb_shutdown(device_t); 163142407Simpstatic int wb_ifmedia_upd(struct ifnet *); 164142407Simpstatic void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 16541502Swpaul 166142407Simpstatic void wb_eeprom_putbyte(struct wb_softc *, int); 167142407Simpstatic void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 168142407Simpstatic void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 169142407Simpstatic void wb_mii_sync(struct wb_softc *); 170142407Simpstatic void wb_mii_send(struct wb_softc *, u_int32_t, int); 171142407Simpstatic int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 172142407Simpstatic int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 17341502Swpaul 174142407Simpstatic void wb_setcfg(struct wb_softc *, u_int32_t); 175142407Simpstatic void wb_setmulti(struct wb_softc *); 176142407Simpstatic void wb_reset(struct wb_softc *); 177142407Simpstatic void wb_fixmedia(struct wb_softc *); 178142407Simpstatic int wb_list_rx_init(struct wb_softc *); 179142407Simpstatic int wb_list_tx_init(struct wb_softc *); 18041502Swpaul 181142407Simpstatic int wb_miibus_readreg(device_t, int, int); 182142407Simpstatic int wb_miibus_writereg(device_t, int, int, int); 183142407Simpstatic void wb_miibus_statchg(device_t); 18450675Swpaul 18549611Swpaul#ifdef WB_USEIOSPACE 18649611Swpaul#define WB_RES SYS_RES_IOPORT 18749611Swpaul#define WB_RID WB_PCI_LOIO 18849611Swpaul#else 18949611Swpaul#define WB_RES SYS_RES_MEMORY 19049611Swpaul#define WB_RID WB_PCI_LOMEM 19149611Swpaul#endif 19249611Swpaul 19349611Swpaulstatic device_method_t wb_methods[] = { 19449611Swpaul /* Device interface */ 19549611Swpaul DEVMETHOD(device_probe, wb_probe), 19649611Swpaul DEVMETHOD(device_attach, wb_attach), 19749611Swpaul DEVMETHOD(device_detach, wb_detach), 19849611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 19950675Swpaul 20050675Swpaul /* bus interface, for miibus */ 20150675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20250675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 20350675Swpaul 20450675Swpaul /* MII interface */ 20550675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 20650675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 20750675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 20849611Swpaul { 0, 0 } 20949611Swpaul}; 21049611Swpaul 21149611Swpaulstatic driver_t wb_driver = { 21251455Swpaul "wb", 21349611Swpaul wb_methods, 21449611Swpaul sizeof(struct wb_softc) 21549611Swpaul}; 21649611Swpaul 21749611Swpaulstatic devclass_t wb_devclass; 21849611Swpaul 219113506SmdoddDRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 22051473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22149611Swpaul 22241502Swpaul#define WB_SETBIT(sc, reg, x) \ 22341502Swpaul CSR_WRITE_4(sc, reg, \ 224105221Sphk CSR_READ_4(sc, reg) | (x)) 22541502Swpaul 22641502Swpaul#define WB_CLRBIT(sc, reg, x) \ 22741502Swpaul CSR_WRITE_4(sc, reg, \ 228105221Sphk CSR_READ_4(sc, reg) & ~(x)) 22941502Swpaul 23041502Swpaul#define SIO_SET(x) \ 23141502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 232105221Sphk CSR_READ_4(sc, WB_SIO) | (x)) 23341502Swpaul 23441502Swpaul#define SIO_CLR(x) \ 23541502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 236105221Sphk CSR_READ_4(sc, WB_SIO) & ~(x)) 23741502Swpaul 23841502Swpaul/* 23941502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24041502Swpaul */ 241102336Salfredstatic void 242102336Salfredwb_eeprom_putbyte(sc, addr) 24341502Swpaul struct wb_softc *sc; 24442718Swpaul int addr; 24541502Swpaul{ 24641502Swpaul register int d, i; 24741502Swpaul 24841502Swpaul d = addr | WB_EECMD_READ; 24941502Swpaul 25041502Swpaul /* 25141502Swpaul * Feed in each bit and stobe the clock. 25241502Swpaul */ 25341502Swpaul for (i = 0x400; i; i >>= 1) { 25441502Swpaul if (d & i) { 25541502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 25641502Swpaul } else { 25741502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 25841502Swpaul } 25941502Swpaul DELAY(100); 26041502Swpaul SIO_SET(WB_SIO_EE_CLK); 26141502Swpaul DELAY(150); 26241502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26341502Swpaul DELAY(100); 26441502Swpaul } 26541502Swpaul 26641502Swpaul return; 26741502Swpaul} 26841502Swpaul 26941502Swpaul/* 27041502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27141502Swpaul */ 272102336Salfredstatic void 273102336Salfredwb_eeprom_getword(sc, addr, dest) 27441502Swpaul struct wb_softc *sc; 27542718Swpaul int addr; 27641502Swpaul u_int16_t *dest; 27741502Swpaul{ 27841502Swpaul register int i; 27941502Swpaul u_int16_t word = 0; 28041502Swpaul 28141502Swpaul /* Enter EEPROM access mode. */ 28241502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28341502Swpaul 28441502Swpaul /* 28541502Swpaul * Send address of word we want to read. 28641502Swpaul */ 28741502Swpaul wb_eeprom_putbyte(sc, addr); 28841502Swpaul 28941502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29041502Swpaul 29141502Swpaul /* 29241502Swpaul * Start reading bits from EEPROM. 29341502Swpaul */ 29441502Swpaul for (i = 0x8000; i; i >>= 1) { 29541502Swpaul SIO_SET(WB_SIO_EE_CLK); 29641502Swpaul DELAY(100); 29741502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 29841502Swpaul word |= i; 29941502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30041502Swpaul DELAY(100); 30141502Swpaul } 30241502Swpaul 30341502Swpaul /* Turn off EEPROM access mode. */ 30441502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 30541502Swpaul 30641502Swpaul *dest = word; 30741502Swpaul 30841502Swpaul return; 30941502Swpaul} 31041502Swpaul 31141502Swpaul/* 31241502Swpaul * Read a sequence of words from the EEPROM. 31341502Swpaul */ 314102336Salfredstatic void 315102336Salfredwb_read_eeprom(sc, dest, off, cnt, swap) 31641502Swpaul struct wb_softc *sc; 31741502Swpaul caddr_t dest; 31841502Swpaul int off; 31941502Swpaul int cnt; 32041502Swpaul int swap; 32141502Swpaul{ 32241502Swpaul int i; 32341502Swpaul u_int16_t word = 0, *ptr; 32441502Swpaul 32541502Swpaul for (i = 0; i < cnt; i++) { 32641502Swpaul wb_eeprom_getword(sc, off + i, &word); 32741502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 32841502Swpaul if (swap) 32941502Swpaul *ptr = ntohs(word); 33041502Swpaul else 33141502Swpaul *ptr = word; 33241502Swpaul } 33341502Swpaul 33441502Swpaul return; 33541502Swpaul} 33641502Swpaul 33741502Swpaul/* 33841502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 33941502Swpaul */ 340102336Salfredstatic void 341102336Salfredwb_mii_sync(sc) 34241502Swpaul struct wb_softc *sc; 34341502Swpaul{ 34441502Swpaul register int i; 34541502Swpaul 34641502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 34741502Swpaul 34841502Swpaul for (i = 0; i < 32; i++) { 34941502Swpaul SIO_SET(WB_SIO_MII_CLK); 35041502Swpaul DELAY(1); 35141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35241502Swpaul DELAY(1); 35341502Swpaul } 35441502Swpaul 35541502Swpaul return; 35641502Swpaul} 35741502Swpaul 35841502Swpaul/* 35941502Swpaul * Clock a series of bits through the MII. 36041502Swpaul */ 361102336Salfredstatic void 362102336Salfredwb_mii_send(sc, bits, cnt) 36341502Swpaul struct wb_softc *sc; 36441502Swpaul u_int32_t bits; 36541502Swpaul int cnt; 36641502Swpaul{ 36741502Swpaul int i; 36841502Swpaul 36941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37041502Swpaul 37141502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37241502Swpaul if (bits & i) { 37341502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37441502Swpaul } else { 37541502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 37641502Swpaul } 37741502Swpaul DELAY(1); 37841502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37941502Swpaul DELAY(1); 38041502Swpaul SIO_SET(WB_SIO_MII_CLK); 38141502Swpaul } 38241502Swpaul} 38341502Swpaul 38441502Swpaul/* 38541502Swpaul * Read an PHY register through the MII. 38641502Swpaul */ 387102336Salfredstatic int 388102336Salfredwb_mii_readreg(sc, frame) 38941502Swpaul struct wb_softc *sc; 39041502Swpaul struct wb_mii_frame *frame; 39141502Swpaul 39241502Swpaul{ 39367087Swpaul int i, ack; 39441502Swpaul 39541502Swpaul /* 39641502Swpaul * Set up frame for RX. 39741502Swpaul */ 39841502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 39941502Swpaul frame->mii_opcode = WB_MII_READOP; 40041502Swpaul frame->mii_turnaround = 0; 40141502Swpaul frame->mii_data = 0; 40241502Swpaul 40341502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 40441502Swpaul 40541502Swpaul /* 40641502Swpaul * Turn on data xmit. 40741502Swpaul */ 40841502Swpaul SIO_SET(WB_SIO_MII_DIR); 40941502Swpaul 41041502Swpaul wb_mii_sync(sc); 41141502Swpaul 41241502Swpaul /* 41341502Swpaul * Send command/address info. 41441502Swpaul */ 41541502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 41641502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 41741502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 41841502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 41941502Swpaul 42041502Swpaul /* Idle bit */ 42141502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42241502Swpaul DELAY(1); 42341502Swpaul SIO_SET(WB_SIO_MII_CLK); 42441502Swpaul DELAY(1); 42541502Swpaul 42641502Swpaul /* Turn off xmit. */ 42741502Swpaul SIO_CLR(WB_SIO_MII_DIR); 42841502Swpaul /* Check for ack */ 42941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43041502Swpaul DELAY(1); 431109058Smbr ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43241502Swpaul SIO_SET(WB_SIO_MII_CLK); 43341502Swpaul DELAY(1); 43441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43541502Swpaul DELAY(1); 43641502Swpaul SIO_SET(WB_SIO_MII_CLK); 43741502Swpaul DELAY(1); 43841502Swpaul 43941502Swpaul /* 44041502Swpaul * Now try reading data bits. If the ack failed, we still 44141502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44241502Swpaul */ 44341502Swpaul if (ack) { 44441502Swpaul for(i = 0; i < 16; i++) { 44541502Swpaul SIO_CLR(WB_SIO_MII_CLK); 44641502Swpaul DELAY(1); 44741502Swpaul SIO_SET(WB_SIO_MII_CLK); 44841502Swpaul DELAY(1); 44941502Swpaul } 45041502Swpaul goto fail; 45141502Swpaul } 45241502Swpaul 45341502Swpaul for (i = 0x8000; i; i >>= 1) { 45441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45541502Swpaul DELAY(1); 45641502Swpaul if (!ack) { 45741502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 45841502Swpaul frame->mii_data |= i; 45941502Swpaul DELAY(1); 46041502Swpaul } 46141502Swpaul SIO_SET(WB_SIO_MII_CLK); 46241502Swpaul DELAY(1); 46341502Swpaul } 46441502Swpaul 46541502Swpaulfail: 46641502Swpaul 46741502Swpaul SIO_CLR(WB_SIO_MII_CLK); 46841502Swpaul DELAY(1); 46941502Swpaul SIO_SET(WB_SIO_MII_CLK); 47041502Swpaul DELAY(1); 47141502Swpaul 47241502Swpaul if (ack) 47341502Swpaul return(1); 47441502Swpaul return(0); 47541502Swpaul} 47641502Swpaul 47741502Swpaul/* 47841502Swpaul * Write to a PHY register through the MII. 47941502Swpaul */ 480102336Salfredstatic int 481102336Salfredwb_mii_writereg(sc, frame) 48241502Swpaul struct wb_softc *sc; 48341502Swpaul struct wb_mii_frame *frame; 48441502Swpaul 48541502Swpaul{ 48641502Swpaul 48741502Swpaul /* 48841502Swpaul * Set up frame for TX. 48941502Swpaul */ 49041502Swpaul 49141502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 49241502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 49341502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 49441502Swpaul 49541502Swpaul /* 49641502Swpaul * Turn on data output. 49741502Swpaul */ 49841502Swpaul SIO_SET(WB_SIO_MII_DIR); 49941502Swpaul 50041502Swpaul wb_mii_sync(sc); 50141502Swpaul 50241502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 50341502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 50441502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 50541502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 50641502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 50741502Swpaul wb_mii_send(sc, frame->mii_data, 16); 50841502Swpaul 50941502Swpaul /* Idle bit. */ 51041502Swpaul SIO_SET(WB_SIO_MII_CLK); 51141502Swpaul DELAY(1); 51241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 51341502Swpaul DELAY(1); 51441502Swpaul 51541502Swpaul /* 51641502Swpaul * Turn off xmit. 51741502Swpaul */ 51841502Swpaul SIO_CLR(WB_SIO_MII_DIR); 51941502Swpaul 52041502Swpaul return(0); 52141502Swpaul} 52241502Swpaul 523102336Salfredstatic int 524102336Salfredwb_miibus_readreg(dev, phy, reg) 52550675Swpaul device_t dev; 52650675Swpaul int phy, reg; 52750675Swpaul{ 52841502Swpaul struct wb_softc *sc; 52941502Swpaul struct wb_mii_frame frame; 53041502Swpaul 53150675Swpaul sc = device_get_softc(dev); 53250675Swpaul 53341502Swpaul bzero((char *)&frame, sizeof(frame)); 53441502Swpaul 53550675Swpaul frame.mii_phyaddr = phy; 53641502Swpaul frame.mii_regaddr = reg; 53741502Swpaul wb_mii_readreg(sc, &frame); 53841502Swpaul 53941502Swpaul return(frame.mii_data); 54041502Swpaul} 54141502Swpaul 542102336Salfredstatic int 543102336Salfredwb_miibus_writereg(dev, phy, reg, data) 54450675Swpaul device_t dev; 54550675Swpaul int phy, reg, data; 54650675Swpaul{ 54741502Swpaul struct wb_softc *sc; 54841502Swpaul struct wb_mii_frame frame; 54941502Swpaul 55050675Swpaul sc = device_get_softc(dev); 55150675Swpaul 55241502Swpaul bzero((char *)&frame, sizeof(frame)); 55341502Swpaul 55450675Swpaul frame.mii_phyaddr = phy; 55541502Swpaul frame.mii_regaddr = reg; 55641502Swpaul frame.mii_data = data; 55741502Swpaul 55841502Swpaul wb_mii_writereg(sc, &frame); 55941502Swpaul 56050675Swpaul return(0); 56150675Swpaul} 56250675Swpaul 563102336Salfredstatic void 564102336Salfredwb_miibus_statchg(dev) 56550675Swpaul device_t dev; 56650675Swpaul{ 56750675Swpaul struct wb_softc *sc; 56850675Swpaul struct mii_data *mii; 56950675Swpaul 57050675Swpaul sc = device_get_softc(dev); 57150675Swpaul mii = device_get_softc(sc->wb_miibus); 57250675Swpaul wb_setcfg(sc, mii->mii_media_active); 57350675Swpaul 57441502Swpaul return; 57541502Swpaul} 57641502Swpaul 57741502Swpaul/* 57841502Swpaul * Program the 64-bit multicast hash filter. 57941502Swpaul */ 580102336Salfredstatic void 581102336Salfredwb_setmulti(sc) 58241502Swpaul struct wb_softc *sc; 58341502Swpaul{ 58441502Swpaul struct ifnet *ifp; 58541502Swpaul int h = 0; 58641502Swpaul u_int32_t hashes[2] = { 0, 0 }; 58741502Swpaul struct ifmultiaddr *ifma; 58841502Swpaul u_int32_t rxfilt; 58941502Swpaul int mcnt = 0; 59041502Swpaul 591147256Sbrooks ifp = sc->wb_ifp; 59241502Swpaul 59341502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 59441502Swpaul 59541502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 59641502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 59741502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 59841502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 59941502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 60041502Swpaul return; 60141502Swpaul } 60241502Swpaul 60341502Swpaul /* first, zot all the existing hash bits */ 60441502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 60541502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 60641502Swpaul 60741502Swpaul /* now program new ones */ 608195049Srwatson if_maddr_rlock(ifp); 60972084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 61041502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 61141502Swpaul continue; 612130270Snaddy h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 613130270Snaddy ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 61441502Swpaul if (h < 32) 61541502Swpaul hashes[0] |= (1 << h); 61641502Swpaul else 61741502Swpaul hashes[1] |= (1 << (h - 32)); 61841502Swpaul mcnt++; 61941502Swpaul } 620195049Srwatson if_maddr_runlock(ifp); 62141502Swpaul 62241502Swpaul if (mcnt) 62341502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 62441502Swpaul else 62541502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 62641502Swpaul 62741502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 62841502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 62941502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 63041502Swpaul 63141502Swpaul return; 63241502Swpaul} 63341502Swpaul 63441502Swpaul/* 63541502Swpaul * The Winbond manual states that in order to fiddle with the 63641502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 63741502Swpaul * first have to put the transmit and/or receive logic in the idle state. 63841502Swpaul */ 639102336Salfredstatic void 640102336Salfredwb_setcfg(sc, media) 64141502Swpaul struct wb_softc *sc; 64250675Swpaul u_int32_t media; 64341502Swpaul{ 64441502Swpaul int i, restart = 0; 64541502Swpaul 64641502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 64741502Swpaul restart = 1; 64841502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 64941502Swpaul 65041502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 65141502Swpaul DELAY(10); 65241502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 65341502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 65441502Swpaul break; 65541502Swpaul } 65641502Swpaul 65741502Swpaul if (i == WB_TIMEOUT) 658162315Sglebius device_printf(sc->wb_dev, 659149677Sjhb "failed to force tx and rx to idle state\n"); 66041502Swpaul } 66141502Swpaul 66250675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 66350675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 66450675Swpaul else 66541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 66641502Swpaul 66750675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 66841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 66941502Swpaul else 67041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 67141502Swpaul 67241502Swpaul if (restart) 67341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 67441502Swpaul 67541502Swpaul return; 67641502Swpaul} 67741502Swpaul 678102336Salfredstatic void 679102336Salfredwb_reset(sc) 68041502Swpaul struct wb_softc *sc; 68141502Swpaul{ 68241502Swpaul register int i; 68350675Swpaul struct mii_data *mii; 68441502Swpaul 68550675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 68650675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 68750675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 68850675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 68950675Swpaul 69041502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 69150675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 69241502Swpaul 69341502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 69441502Swpaul DELAY(10); 69541502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 69641502Swpaul break; 69741502Swpaul } 69841502Swpaul if (i == WB_TIMEOUT) 699162315Sglebius device_printf(sc->wb_dev, "reset never completed!\n"); 70041502Swpaul 70141502Swpaul /* Wait a little while for the chip to get its brains in order. */ 70241502Swpaul DELAY(1000); 70341502Swpaul 70450675Swpaul if (sc->wb_miibus == NULL) 70550675Swpaul return; 70641502Swpaul 70750675Swpaul mii = device_get_softc(sc->wb_miibus); 70850675Swpaul if (mii == NULL) 70950675Swpaul return; 71050675Swpaul 71150675Swpaul if (mii->mii_instance) { 71250675Swpaul struct mii_softc *miisc; 71372012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 71450675Swpaul mii_phy_reset(miisc); 71550675Swpaul } 71650675Swpaul 71741502Swpaul return; 71841502Swpaul} 71941502Swpaul 720102336Salfredstatic void 721102336Salfredwb_fixmedia(sc) 72250675Swpaul struct wb_softc *sc; 72350675Swpaul{ 72450675Swpaul struct mii_data *mii = NULL; 72550675Swpaul struct ifnet *ifp; 72650675Swpaul u_int32_t media; 72750675Swpaul 72850675Swpaul if (sc->wb_miibus == NULL) 72950675Swpaul return; 73050675Swpaul 73150675Swpaul mii = device_get_softc(sc->wb_miibus); 732147256Sbrooks ifp = sc->wb_ifp; 73350675Swpaul 73450675Swpaul mii_pollstat(mii); 73550675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 73650675Swpaul media = mii->mii_media_active & ~IFM_10_T; 73750675Swpaul media |= IFM_100_TX; 73850675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 73950675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 74050675Swpaul media |= IFM_10_T; 74150675Swpaul } else 74250675Swpaul return; 74350675Swpaul 74450675Swpaul ifmedia_set(&mii->mii_media, media); 74550675Swpaul 74650675Swpaul return; 74750675Swpaul} 74850675Swpaul 74941502Swpaul/* 75041502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 75141502Swpaul * IDs against our list and return a device name if we find a match. 75241502Swpaul */ 753102336Salfredstatic int 754102336Salfredwb_probe(dev) 75549611Swpaul device_t dev; 75641502Swpaul{ 75741502Swpaul struct wb_type *t; 75841502Swpaul 75941502Swpaul t = wb_devs; 76041502Swpaul 76141502Swpaul while(t->wb_name != NULL) { 76249611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 76349611Swpaul (pci_get_device(dev) == t->wb_did)) { 76449611Swpaul device_set_desc(dev, t->wb_name); 765142398Simp return (BUS_PROBE_DEFAULT); 76641502Swpaul } 76741502Swpaul t++; 76841502Swpaul } 76941502Swpaul 77049611Swpaul return(ENXIO); 77141502Swpaul} 77241502Swpaul 77341502Swpaul/* 77441502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 77541502Swpaul * setup and ethernet/BPF attach. 77641502Swpaul */ 777102336Salfredstatic int 778102336Salfredwb_attach(dev) 77949611Swpaul device_t dev; 78041502Swpaul{ 78141502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 78241502Swpaul struct wb_softc *sc; 78341502Swpaul struct ifnet *ifp; 784149677Sjhb int error = 0, rid; 78541502Swpaul 78649611Swpaul sc = device_get_softc(dev); 787162315Sglebius sc->wb_dev = dev; 78841502Swpaul 78993818Sjhb mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 790151774Sjhb MTX_DEF); 791151774Sjhb callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0); 792151774Sjhb 79341502Swpaul /* 79441502Swpaul * Map control/status registers. 79541502Swpaul */ 79672813Swpaul pci_enable_busmaster(dev); 79741502Swpaul 79849611Swpaul rid = WB_RID; 799127135Snjl sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 80049611Swpaul 80149611Swpaul if (sc->wb_res == NULL) { 802149677Sjhb device_printf(dev, "couldn't map ports/memory\n"); 80349611Swpaul error = ENXIO; 80441502Swpaul goto fail; 80541502Swpaul } 80641502Swpaul 80741502Swpaul /* Allocate interrupt */ 80849611Swpaul rid = 0; 809127135Snjl sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 81049611Swpaul RF_SHAREABLE | RF_ACTIVE); 81149611Swpaul 81249611Swpaul if (sc->wb_irq == NULL) { 813149677Sjhb device_printf(dev, "couldn't map interrupt\n"); 81449611Swpaul error = ENXIO; 81541502Swpaul goto fail; 81641502Swpaul } 81741502Swpaul 81850675Swpaul /* Save the cache line size. */ 81950675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 82050675Swpaul 82141502Swpaul /* Reset the adapter. */ 82241502Swpaul wb_reset(sc); 82341502Swpaul 82441502Swpaul /* 82541502Swpaul * Get station address from the EEPROM. 82641502Swpaul */ 82741502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 82841502Swpaul 82950675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 83051657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 83150675Swpaul 83250675Swpaul if (sc->wb_ldata == NULL) { 833149677Sjhb device_printf(dev, "no memory for list buffers!\n"); 83449611Swpaul error = ENXIO; 83549611Swpaul goto fail; 83641502Swpaul } 83741502Swpaul 83841502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 83941502Swpaul 840147256Sbrooks ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 841147256Sbrooks if (ifp == NULL) { 842149677Sjhb device_printf(dev, "can not if_alloc()\n"); 843147256Sbrooks error = ENOSPC; 844147256Sbrooks goto fail; 845147256Sbrooks } 84641502Swpaul ifp->if_softc = sc; 847121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 84841502Swpaul ifp->if_mtu = ETHERMTU; 849151774Sjhb ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 85041502Swpaul ifp->if_ioctl = wb_ioctl; 85141502Swpaul ifp->if_start = wb_start; 85241502Swpaul ifp->if_init = wb_init; 85343515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 85441502Swpaul 85550675Swpaul /* 85650675Swpaul * Do MII setup. 85750675Swpaul */ 858213894Smarius error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd, 859213894Smarius wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 860213894Smarius if (error != 0) { 861213894Smarius device_printf(dev, "attaching PHYs failed\n"); 86241502Swpaul goto fail; 86341502Swpaul } 86441502Swpaul 86541502Swpaul /* 86663090Sarchie * Call MI attach routine. 86741502Swpaul */ 868106936Ssam ether_ifattach(ifp, eaddr); 86941502Swpaul 870113609Snjl /* Hook interrupt last to avoid having to lock softc */ 871151774Sjhb error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE, 872166901Spiso NULL, wb_intr, sc, &sc->wb_intrhand); 873112872Snjl 874112872Snjl if (error) { 875149677Sjhb device_printf(dev, "couldn't set up irq\n"); 876113609Snjl ether_ifdetach(ifp); 877112872Snjl goto fail; 878112872Snjl } 879112872Snjl 88041502Swpaulfail: 88150675Swpaul if (error) 882112872Snjl wb_detach(dev); 88350675Swpaul 88449611Swpaul return(error); 88541502Swpaul} 88641502Swpaul 887113609Snjl/* 888113609Snjl * Shutdown hardware and free up resources. This can be called any 889113609Snjl * time after the mutex has been initialized. It is called in both 890113609Snjl * the error case in attach and the normal detach case so it needs 891113609Snjl * to be careful about only freeing resources that have actually been 892113609Snjl * allocated. 893113609Snjl */ 894102336Salfredstatic int 895102336Salfredwb_detach(dev) 89649611Swpaul device_t dev; 89749611Swpaul{ 89849611Swpaul struct wb_softc *sc; 89949611Swpaul struct ifnet *ifp; 90049611Swpaul 90149611Swpaul sc = device_get_softc(dev); 902112880Sjhb KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 903147256Sbrooks ifp = sc->wb_ifp; 90449611Swpaul 905113609Snjl /* 906113609Snjl * Delete any miibus and phy devices attached to this interface. 907113609Snjl * This should only be done if attach succeeded. 908113609Snjl */ 909113812Simp if (device_is_attached(dev)) { 910199560Sjhb ether_ifdetach(ifp); 911151774Sjhb WB_LOCK(sc); 912113609Snjl wb_stop(sc); 913151774Sjhb WB_UNLOCK(sc); 914151774Sjhb callout_drain(&sc->wb_stat_callout); 915150213Sru } 916113609Snjl if (sc->wb_miibus) 917112872Snjl device_delete_child(dev, sc->wb_miibus); 918113609Snjl bus_generic_detach(dev); 91950675Swpaul 920112872Snjl if (sc->wb_intrhand) 921112872Snjl bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 922112872Snjl if (sc->wb_irq) 923112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 924112872Snjl if (sc->wb_res) 925112872Snjl bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 92649611Swpaul 927151297Sru if (ifp) 928151297Sru if_free(ifp); 929151297Sru 930112872Snjl if (sc->wb_ldata) { 931112872Snjl contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 932112872Snjl M_DEVBUF); 933112872Snjl } 93449611Swpaul 93567087Swpaul mtx_destroy(&sc->wb_mtx); 93649611Swpaul 93749611Swpaul return(0); 93849611Swpaul} 93949611Swpaul 94041502Swpaul/* 94141502Swpaul * Initialize the transmit descriptors. 94241502Swpaul */ 943102336Salfredstatic int 944102336Salfredwb_list_tx_init(sc) 94541502Swpaul struct wb_softc *sc; 94641502Swpaul{ 94741502Swpaul struct wb_chain_data *cd; 94841502Swpaul struct wb_list_data *ld; 94941502Swpaul int i; 95041502Swpaul 95141502Swpaul cd = &sc->wb_cdata; 95241502Swpaul ld = sc->wb_ldata; 95341502Swpaul 95441502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 95541502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 95641502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 95741502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 95841502Swpaul &cd->wb_tx_chain[0]; 95941502Swpaul } else { 96041502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 96141502Swpaul &cd->wb_tx_chain[i + 1]; 96241502Swpaul } 96341502Swpaul } 96441502Swpaul 96541502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 96641502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 96741502Swpaul 96841502Swpaul return(0); 96941502Swpaul} 97041502Swpaul 97141502Swpaul 97241502Swpaul/* 97341502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 97441502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 97541502Swpaul * points back to the first. 97641502Swpaul */ 977102336Salfredstatic int 978102336Salfredwb_list_rx_init(sc) 97941502Swpaul struct wb_softc *sc; 98041502Swpaul{ 98141502Swpaul struct wb_chain_data *cd; 98241502Swpaul struct wb_list_data *ld; 98341502Swpaul int i; 98441502Swpaul 98541502Swpaul cd = &sc->wb_cdata; 98641502Swpaul ld = sc->wb_ldata; 98741502Swpaul 98841502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 98941502Swpaul cd->wb_rx_chain[i].wb_ptr = 99041502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 99150675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 99248745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 99341502Swpaul return(ENOBUFS); 99441502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 99541502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 99641502Swpaul ld->wb_rx_list[i].wb_next = 99741502Swpaul vtophys(&ld->wb_rx_list[0]); 99841502Swpaul } else { 99941502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 100041502Swpaul &cd->wb_rx_chain[i + 1]; 100141502Swpaul ld->wb_rx_list[i].wb_next = 100241502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 100341502Swpaul } 100441502Swpaul } 100541502Swpaul 100641502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 100741502Swpaul 100841502Swpaul return(0); 100941502Swpaul} 101041502Swpaul 1011102336Salfredstatic void 1012102336Salfredwb_bfree(buf, args) 101398995Salfred void *buf; 101464837Sdwmalone void *args; 101550675Swpaul{ 101650675Swpaul return; 101750675Swpaul} 101850675Swpaul 101941502Swpaul/* 102041502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 102141502Swpaul */ 1022102336Salfredstatic int 1023102336Salfredwb_newbuf(sc, c, m) 102441502Swpaul struct wb_softc *sc; 102541502Swpaul struct wb_chain_onefrag *c; 102648745Swpaul struct mbuf *m; 102741502Swpaul{ 102841502Swpaul struct mbuf *m_new = NULL; 102941502Swpaul 103048745Swpaul if (m == NULL) { 1031111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 103287846Sluigi if (m_new == NULL) 103348745Swpaul return(ENOBUFS); 103464837Sdwmalone m_new->m_data = c->wb_buf; 103564837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1036175872Sphk MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf, 1037175872Sphk NULL, 0, EXT_NET_DRV); 103848745Swpaul } else { 103948745Swpaul m_new = m; 104050675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 104148745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 104241502Swpaul } 104341502Swpaul 104448745Swpaul m_adj(m_new, sizeof(u_int64_t)); 104548745Swpaul 104641502Swpaul c->wb_mbuf = m_new; 104741502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 104850675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 104941502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 105041502Swpaul 105141502Swpaul return(0); 105241502Swpaul} 105341502Swpaul 105441502Swpaul/* 105541502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 105641502Swpaul * the higher level protocols. 105741502Swpaul */ 1058102336Salfredstatic void 1059102336Salfredwb_rxeof(sc) 106041502Swpaul struct wb_softc *sc; 106141502Swpaul{ 106250675Swpaul struct mbuf *m = NULL; 106341502Swpaul struct ifnet *ifp; 106441502Swpaul struct wb_chain_onefrag *cur_rx; 106541502Swpaul int total_len = 0; 106641502Swpaul u_int32_t rxstat; 106741502Swpaul 1068122689Ssam WB_LOCK_ASSERT(sc); 1069122689Ssam 1070147256Sbrooks ifp = sc->wb_ifp; 107141502Swpaul 107241502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 107341502Swpaul WB_RXSTAT_OWN)) { 107448745Swpaul struct mbuf *m0 = NULL; 107548745Swpaul 107641502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 107741502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 107850675Swpaul 107948745Swpaul m = cur_rx->wb_mbuf; 108041502Swpaul 108150675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 108250675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 108350675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 108450675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 108550675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 108641502Swpaul ifp->if_ierrors++; 108750675Swpaul wb_newbuf(sc, cur_rx, m); 1088162315Sglebius device_printf(sc->wb_dev, 1089162315Sglebius "receiver babbling: possible chip bug," 1090162315Sglebius " forcing reset\n"); 109150675Swpaul wb_fixmedia(sc); 109250675Swpaul wb_reset(sc); 1093151774Sjhb wb_init_locked(sc); 109441502Swpaul return; 109541502Swpaul } 109641502Swpaul 109742718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 109842718Swpaul ifp->if_ierrors++; 109948745Swpaul wb_newbuf(sc, cur_rx, m); 110050675Swpaul break; 110142718Swpaul } 110242718Swpaul 110341502Swpaul /* No errors; receive the packet. */ 110441502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 110541502Swpaul 110641502Swpaul /* 110741934Swpaul * XXX The Winbond chip includes the CRC with every 110841934Swpaul * received frame, and there's no way to turn this 110941934Swpaul * behavior off (at least, I can't find anything in 111041934Swpaul * the manual that explains how to do it) so we have 111141934Swpaul * to trim off the CRC manually. 111241934Swpaul */ 111341934Swpaul total_len -= ETHER_CRC_LEN; 111441934Swpaul 111578508Sbmilekic m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 111678508Sbmilekic NULL); 111748745Swpaul wb_newbuf(sc, cur_rx, m); 111848745Swpaul if (m0 == NULL) { 111948745Swpaul ifp->if_ierrors++; 112050675Swpaul break; 112141502Swpaul } 112248745Swpaul m = m0; 112341502Swpaul 112441502Swpaul ifp->if_ipackets++; 1125122689Ssam WB_UNLOCK(sc); 1126106936Ssam (*ifp->if_input)(ifp, m); 1127122689Ssam WB_LOCK(sc); 112841502Swpaul } 112941502Swpaul} 113041502Swpaul 1131105221Sphkstatic void 1132102336Salfredwb_rxeoc(sc) 113341502Swpaul struct wb_softc *sc; 113441502Swpaul{ 113541502Swpaul wb_rxeof(sc); 113641502Swpaul 113741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 113841502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 113941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 114041502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 114141502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 114241502Swpaul 114341502Swpaul return; 114441502Swpaul} 114541502Swpaul 114641502Swpaul/* 114741502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 114841502Swpaul * the list buffers. 114941502Swpaul */ 1150102336Salfredstatic void 1151102336Salfredwb_txeof(sc) 115241502Swpaul struct wb_softc *sc; 115341502Swpaul{ 115441502Swpaul struct wb_chain *cur_tx; 115541502Swpaul struct ifnet *ifp; 115641502Swpaul 1157147256Sbrooks ifp = sc->wb_ifp; 115841502Swpaul 115941502Swpaul /* Clear the timeout timer. */ 1160199560Sjhb sc->wb_timer = 0; 116141502Swpaul 116241502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 116341502Swpaul return; 116441502Swpaul 116541502Swpaul /* 116641502Swpaul * Go through our tx list and free mbufs for those 116741502Swpaul * frames that have been transmitted. 116841502Swpaul */ 116941502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 117041502Swpaul u_int32_t txstat; 117141502Swpaul 117241502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 117341502Swpaul txstat = WB_TXSTATUS(cur_tx); 117441502Swpaul 117541502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 117641502Swpaul break; 117741502Swpaul 117841502Swpaul if (txstat & WB_TXSTAT_TXERR) { 117941502Swpaul ifp->if_oerrors++; 118041502Swpaul if (txstat & WB_TXSTAT_ABORT) 118141502Swpaul ifp->if_collisions++; 118241502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 118341502Swpaul ifp->if_collisions++; 118441502Swpaul } 118541502Swpaul 118641502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 118741502Swpaul 118841502Swpaul ifp->if_opackets++; 118941502Swpaul m_freem(cur_tx->wb_mbuf); 119041502Swpaul cur_tx->wb_mbuf = NULL; 119141502Swpaul 119241502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 119341502Swpaul sc->wb_cdata.wb_tx_head = NULL; 119441502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 119541502Swpaul break; 119641502Swpaul } 119741502Swpaul 119841502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 119941502Swpaul } 120041502Swpaul 120141502Swpaul return; 120241502Swpaul} 120341502Swpaul 120441502Swpaul/* 120541502Swpaul * TX 'end of channel' interrupt handler. 120641502Swpaul */ 1207102336Salfredstatic void 1208102336Salfredwb_txeoc(sc) 120941502Swpaul struct wb_softc *sc; 121041502Swpaul{ 121141502Swpaul struct ifnet *ifp; 121241502Swpaul 1213147256Sbrooks ifp = sc->wb_ifp; 121441502Swpaul 1215199560Sjhb sc->wb_timer = 0; 121641502Swpaul 121741502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 1218148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 121941502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 122041502Swpaul } else { 122141502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 122241502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1223199560Sjhb sc->wb_timer = 5; 122441502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 122541502Swpaul } 122641502Swpaul } 122741502Swpaul 122841502Swpaul return; 122941502Swpaul} 123041502Swpaul 1231102336Salfredstatic void 1232102336Salfredwb_intr(arg) 123341502Swpaul void *arg; 123441502Swpaul{ 123541502Swpaul struct wb_softc *sc; 123641502Swpaul struct ifnet *ifp; 123741502Swpaul u_int32_t status; 123841502Swpaul 123941502Swpaul sc = arg; 124067087Swpaul WB_LOCK(sc); 1241147256Sbrooks ifp = sc->wb_ifp; 124241502Swpaul 1243151774Sjhb if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 124467087Swpaul WB_UNLOCK(sc); 124541502Swpaul return; 124667087Swpaul } 124741502Swpaul 124841502Swpaul /* Disable interrupts. */ 124941502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 125041502Swpaul 125141502Swpaul for (;;) { 125241502Swpaul 125341502Swpaul status = CSR_READ_4(sc, WB_ISR); 125441502Swpaul if (status) 125541502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 125641502Swpaul 125741502Swpaul if ((status & WB_INTRS) == 0) 125841502Swpaul break; 125941502Swpaul 126041502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 126141502Swpaul ifp->if_ierrors++; 126241502Swpaul wb_reset(sc); 126350675Swpaul if (status & WB_ISR_RX_ERR) 126450675Swpaul wb_fixmedia(sc); 1265151774Sjhb wb_init_locked(sc); 126650675Swpaul continue; 126741502Swpaul } 126841502Swpaul 126950675Swpaul if (status & WB_ISR_RX_OK) 127050675Swpaul wb_rxeof(sc); 127150675Swpaul 127250675Swpaul if (status & WB_ISR_RX_IDLE) 127350675Swpaul wb_rxeoc(sc); 127450675Swpaul 127541502Swpaul if (status & WB_ISR_TX_OK) 127641502Swpaul wb_txeof(sc); 127741502Swpaul 127841502Swpaul if (status & WB_ISR_TX_NOBUF) 127941502Swpaul wb_txeoc(sc); 128041502Swpaul 128141502Swpaul if (status & WB_ISR_TX_IDLE) { 128241502Swpaul wb_txeof(sc); 128341502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 128441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 128541502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 128641502Swpaul } 128741502Swpaul } 128841502Swpaul 128941502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 129041502Swpaul ifp->if_oerrors++; 129141502Swpaul wb_txeof(sc); 129241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 129341502Swpaul /* Jack up TX threshold */ 129441502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 129541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 129641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 129741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 129841502Swpaul } 129941502Swpaul 130041502Swpaul if (status & WB_ISR_BUS_ERR) { 130141502Swpaul wb_reset(sc); 1302151774Sjhb wb_init_locked(sc); 130341502Swpaul } 130441502Swpaul 130541502Swpaul } 130641502Swpaul 130741502Swpaul /* Re-enable interrupts. */ 130841502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 130941502Swpaul 131041502Swpaul if (ifp->if_snd.ifq_head != NULL) { 1311151774Sjhb wb_start_locked(ifp); 131241502Swpaul } 131341502Swpaul 131467087Swpaul WB_UNLOCK(sc); 131567087Swpaul 131641502Swpaul return; 131741502Swpaul} 131841502Swpaul 1319102336Salfredstatic void 1320102336Salfredwb_tick(xsc) 132150675Swpaul void *xsc; 132250675Swpaul{ 132350675Swpaul struct wb_softc *sc; 132450675Swpaul struct mii_data *mii; 132550675Swpaul 132650675Swpaul sc = xsc; 1327151774Sjhb WB_LOCK_ASSERT(sc); 132850675Swpaul mii = device_get_softc(sc->wb_miibus); 132950675Swpaul 133050675Swpaul mii_tick(mii); 133150675Swpaul 1332199560Sjhb if (sc->wb_timer > 0 && --sc->wb_timer == 0) 1333199560Sjhb wb_watchdog(sc); 1334151774Sjhb callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 133550675Swpaul 133650675Swpaul return; 133750675Swpaul} 133850675Swpaul 133941502Swpaul/* 134041502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 134141502Swpaul * pointers to the fragment pointers. 134241502Swpaul */ 1343102336Salfredstatic int 1344102336Salfredwb_encap(sc, c, m_head) 134541502Swpaul struct wb_softc *sc; 134641502Swpaul struct wb_chain *c; 134741502Swpaul struct mbuf *m_head; 134841502Swpaul{ 134941502Swpaul int frag = 0; 135041502Swpaul struct wb_desc *f = NULL; 135141502Swpaul int total_len; 135241502Swpaul struct mbuf *m; 135341502Swpaul 135441502Swpaul /* 135541502Swpaul * Start packing the mbufs in this chain into 135641502Swpaul * the fragment pointers. Stop when we run out 135741502Swpaul * of fragments or hit the end of the mbuf chain. 135841502Swpaul */ 135941502Swpaul m = m_head; 136041502Swpaul total_len = 0; 136141502Swpaul 136241502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 136341502Swpaul if (m->m_len != 0) { 136441502Swpaul if (frag == WB_MAXFRAGS) 136541502Swpaul break; 136641502Swpaul total_len += m->m_len; 136741502Swpaul f = &c->wb_ptr->wb_frag[frag]; 136841502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 136941502Swpaul if (frag == 0) { 137041502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 137141502Swpaul f->wb_status = 0; 137241502Swpaul } else 137341502Swpaul f->wb_status = WB_TXSTAT_OWN; 137441502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 137541502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 137641502Swpaul frag++; 137741502Swpaul } 137841502Swpaul } 137941502Swpaul 138041502Swpaul /* 138141502Swpaul * Handle special case: we used up all 16 fragments, 138241502Swpaul * but we have more mbufs left in the chain. Copy the 138341502Swpaul * data into an mbuf cluster. Note that we don't 138441502Swpaul * bother clearing the values in the other fragment 138541502Swpaul * pointers/counters; it wouldn't gain us anything, 138641502Swpaul * and would waste cycles. 138741502Swpaul */ 138841502Swpaul if (m != NULL) { 138941502Swpaul struct mbuf *m_new = NULL; 139041502Swpaul 1391111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 139287846Sluigi if (m_new == NULL) 139341502Swpaul return(1); 139441502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1395111119Simp MCLGET(m_new, M_DONTWAIT); 139641502Swpaul if (!(m_new->m_flags & M_EXT)) { 139741502Swpaul m_freem(m_new); 139841502Swpaul return(1); 139941502Swpaul } 140041502Swpaul } 140141502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 140241502Swpaul mtod(m_new, caddr_t)); 140341502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 140441502Swpaul m_freem(m_head); 140541502Swpaul m_head = m_new; 140641502Swpaul f = &c->wb_ptr->wb_frag[0]; 140741502Swpaul f->wb_status = 0; 140841502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 140941502Swpaul f->wb_ctl = total_len = m_new->m_len; 141041502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 141141502Swpaul frag = 1; 141241502Swpaul } 141341502Swpaul 141441502Swpaul if (total_len < WB_MIN_FRAMELEN) { 141541502Swpaul f = &c->wb_ptr->wb_frag[frag]; 141641502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 141741502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 141841502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 141941502Swpaul f->wb_status = WB_TXSTAT_OWN; 142041502Swpaul frag++; 142141502Swpaul } 142241502Swpaul 142341502Swpaul c->wb_mbuf = m_head; 142441502Swpaul c->wb_lastdesc = frag - 1; 142541502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 142641502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 142741502Swpaul 142841502Swpaul return(0); 142941502Swpaul} 143041502Swpaul 143141502Swpaul/* 143241502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 143341502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 143441502Swpaul * copy of the pointers since the transmit list fragment pointers are 143541502Swpaul * physical addresses. 143641502Swpaul */ 143741502Swpaul 1438102336Salfredstatic void 1439102336Salfredwb_start(ifp) 144041502Swpaul struct ifnet *ifp; 144141502Swpaul{ 144241502Swpaul struct wb_softc *sc; 1443151774Sjhb 1444151774Sjhb sc = ifp->if_softc; 1445151774Sjhb WB_LOCK(sc); 1446151774Sjhb wb_start_locked(ifp); 1447151774Sjhb WB_UNLOCK(sc); 1448151774Sjhb} 1449151774Sjhb 1450151774Sjhbstatic void 1451151774Sjhbwb_start_locked(ifp) 1452151774Sjhb struct ifnet *ifp; 1453151774Sjhb{ 1454151774Sjhb struct wb_softc *sc; 145541502Swpaul struct mbuf *m_head = NULL; 145641502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 145741502Swpaul 145841502Swpaul sc = ifp->if_softc; 1459151774Sjhb WB_LOCK_ASSERT(sc); 146041502Swpaul 146141502Swpaul /* 146241502Swpaul * Check for an available queue slot. If there are none, 146341502Swpaul * punt. 146441502Swpaul */ 146541502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1466148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 146741502Swpaul return; 146841502Swpaul } 146941502Swpaul 147041502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 147141502Swpaul 147241502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 147341502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 147441502Swpaul if (m_head == NULL) 147541502Swpaul break; 147641502Swpaul 147741502Swpaul /* Pick a descriptor off the free list. */ 147841502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 147941502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 148041502Swpaul 148141502Swpaul /* Pack the data into the descriptor. */ 148241502Swpaul wb_encap(sc, cur_tx, m_head); 148341502Swpaul 148441502Swpaul if (cur_tx != start_tx) 148541502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 148641502Swpaul 148741502Swpaul /* 148841502Swpaul * If there's a BPF listener, bounce a copy of this frame 148941502Swpaul * to him. 149041502Swpaul */ 1491106936Ssam BPF_MTAP(ifp, cur_tx->wb_mbuf); 149241502Swpaul } 149341502Swpaul 149441502Swpaul /* 149541526Swpaul * If there are no packets queued, bail. 149641526Swpaul */ 1497151774Sjhb if (cur_tx == NULL) 149841526Swpaul return; 149941526Swpaul 150041526Swpaul /* 150141502Swpaul * Place the request for the upload interrupt 150241502Swpaul * in the last descriptor in the chain. This way, if 150341502Swpaul * we're chaining several packets at once, we'll only 1504172568Skevlo * get an interrupt once for the whole chain rather than 150541502Swpaul * once for each packet. 150641502Swpaul */ 150741502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 150842718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 150941502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 151041502Swpaul 151141502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 151241502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 151341502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 151441502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 151541502Swpaul } else { 151641502Swpaul /* 151741502Swpaul * We need to distinguish between the case where 151841502Swpaul * the own bit is clear because the chip cleared it 151941502Swpaul * and where the own bit is clear because we haven't 152041502Swpaul * set it yet. The magic value WB_UNSET is just some 152141502Swpaul * ramdomly chosen number which doesn't have the own 152241502Swpaul * bit set. When we actually transmit the frame, the 152341502Swpaul * status word will have _only_ the own bit set, so 152441502Swpaul * the txeoc handler will be able to tell if it needs 152541502Swpaul * to initiate another transmission to flush out pending 152641502Swpaul * frames. 152741502Swpaul */ 152841502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 152941502Swpaul } 153041502Swpaul 153141502Swpaul /* 153241502Swpaul * Set a timeout in case the chip goes out to lunch. 153341502Swpaul */ 1534199560Sjhb sc->wb_timer = 5; 153541502Swpaul 153641502Swpaul return; 153741502Swpaul} 153841502Swpaul 1539102336Salfredstatic void 1540102336Salfredwb_init(xsc) 154141502Swpaul void *xsc; 154241502Swpaul{ 154341502Swpaul struct wb_softc *sc = xsc; 1544151774Sjhb 1545151774Sjhb WB_LOCK(sc); 1546151774Sjhb wb_init_locked(sc); 1547151774Sjhb WB_UNLOCK(sc); 1548151774Sjhb} 1549151774Sjhb 1550151774Sjhbstatic void 1551151774Sjhbwb_init_locked(sc) 1552151774Sjhb struct wb_softc *sc; 1553151774Sjhb{ 1554147256Sbrooks struct ifnet *ifp = sc->wb_ifp; 155567087Swpaul int i; 155650675Swpaul struct mii_data *mii; 155741502Swpaul 1558151774Sjhb WB_LOCK_ASSERT(sc); 155950675Swpaul mii = device_get_softc(sc->wb_miibus); 156041502Swpaul 156141502Swpaul /* 156241502Swpaul * Cancel pending I/O and free all RX/TX buffers. 156341502Swpaul */ 156441502Swpaul wb_stop(sc); 156541502Swpaul wb_reset(sc); 156641502Swpaul 156741502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 156841502Swpaul 156941502Swpaul /* 157041502Swpaul * Set cache alignment and burst length. 157141502Swpaul */ 157250675Swpaul#ifdef foo 157341502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 157441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 157541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 157650675Swpaul#endif 157741502Swpaul 157850675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 157950675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 158050675Swpaul switch(sc->wb_cachesize) { 158150675Swpaul case 32: 158250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 158350675Swpaul break; 158450675Swpaul case 16: 158550675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 158650675Swpaul break; 158750675Swpaul case 8: 158850675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 158950675Swpaul break; 159050675Swpaul case 0: 159150675Swpaul default: 159250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 159350675Swpaul break; 159450675Swpaul } 159550675Swpaul 159641502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 159741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 159841502Swpaul 159941502Swpaul /* Init our MAC address */ 160041502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 1601152315Sru CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]); 160241502Swpaul } 160341502Swpaul 160441502Swpaul /* Init circular RX list. */ 160541502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 1606162315Sglebius device_printf(sc->wb_dev, 1607149677Sjhb "initialization failed: no memory for rx buffers\n"); 160841502Swpaul wb_stop(sc); 160941502Swpaul return; 161041502Swpaul } 161141502Swpaul 161241502Swpaul /* Init TX descriptors. */ 161341502Swpaul wb_list_tx_init(sc); 161441502Swpaul 161541502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 161641502Swpaul if (ifp->if_flags & IFF_PROMISC) { 161741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 161841502Swpaul } else { 161941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 162041502Swpaul } 162141502Swpaul 162241502Swpaul /* 162341502Swpaul * Set capture broadcast bit to capture broadcast frames. 162441502Swpaul */ 162541502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 162641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 162741502Swpaul } else { 162841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 162941502Swpaul } 163041502Swpaul 163141502Swpaul /* 163241502Swpaul * Program the multicast filter, if necessary. 163341502Swpaul */ 163441502Swpaul wb_setmulti(sc); 163541502Swpaul 163641502Swpaul /* 163741502Swpaul * Load the address of the RX list. 163841502Swpaul */ 163941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 164041502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 164141502Swpaul 164241502Swpaul /* 164341502Swpaul * Enable interrupts. 164441502Swpaul */ 164541502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 164641502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 164741502Swpaul 164841502Swpaul /* Enable receiver and transmitter. */ 164941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 165041502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 165141502Swpaul 165241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 165341502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 165441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 165541502Swpaul 165650675Swpaul mii_mediachg(mii); 165741502Swpaul 1658148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 1659148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 166041502Swpaul 1661151774Sjhb callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 166250675Swpaul 166341502Swpaul return; 166441502Swpaul} 166541502Swpaul 166641502Swpaul/* 166741502Swpaul * Set media options. 166841502Swpaul */ 1669102336Salfredstatic int 1670102336Salfredwb_ifmedia_upd(ifp) 167141502Swpaul struct ifnet *ifp; 167241502Swpaul{ 167341502Swpaul struct wb_softc *sc; 167441502Swpaul 167541502Swpaul sc = ifp->if_softc; 167641502Swpaul 1677151774Sjhb WB_LOCK(sc); 167850675Swpaul if (ifp->if_flags & IFF_UP) 1679151774Sjhb wb_init_locked(sc); 1680151774Sjhb WB_UNLOCK(sc); 168141502Swpaul 168241502Swpaul return(0); 168341502Swpaul} 168441502Swpaul 168541502Swpaul/* 168641502Swpaul * Report current media status. 168741502Swpaul */ 1688102336Salfredstatic void 1689102336Salfredwb_ifmedia_sts(ifp, ifmr) 169041502Swpaul struct ifnet *ifp; 169141502Swpaul struct ifmediareq *ifmr; 169241502Swpaul{ 169341502Swpaul struct wb_softc *sc; 169450675Swpaul struct mii_data *mii; 169541502Swpaul 169641502Swpaul sc = ifp->if_softc; 169741502Swpaul 1698151774Sjhb WB_LOCK(sc); 169950675Swpaul mii = device_get_softc(sc->wb_miibus); 170041502Swpaul 170150675Swpaul mii_pollstat(mii); 170250675Swpaul ifmr->ifm_active = mii->mii_media_active; 170350675Swpaul ifmr->ifm_status = mii->mii_media_status; 1704151774Sjhb WB_UNLOCK(sc); 170541502Swpaul 170641502Swpaul return; 170741502Swpaul} 170841502Swpaul 1709102336Salfredstatic int 1710102336Salfredwb_ioctl(ifp, command, data) 171141502Swpaul struct ifnet *ifp; 171241502Swpaul u_long command; 171341502Swpaul caddr_t data; 171441502Swpaul{ 171541502Swpaul struct wb_softc *sc = ifp->if_softc; 171650675Swpaul struct mii_data *mii; 171741502Swpaul struct ifreq *ifr = (struct ifreq *) data; 171867087Swpaul int error = 0; 171941502Swpaul 172041502Swpaul switch(command) { 172141502Swpaul case SIOCSIFFLAGS: 1722151774Sjhb WB_LOCK(sc); 172341502Swpaul if (ifp->if_flags & IFF_UP) { 1724151774Sjhb wb_init_locked(sc); 172541502Swpaul } else { 1726148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 172741502Swpaul wb_stop(sc); 172841502Swpaul } 1729151774Sjhb WB_UNLOCK(sc); 173041502Swpaul error = 0; 173141502Swpaul break; 173241502Swpaul case SIOCADDMULTI: 173341502Swpaul case SIOCDELMULTI: 1734151774Sjhb WB_LOCK(sc); 173541502Swpaul wb_setmulti(sc); 1736151774Sjhb WB_UNLOCK(sc); 173741502Swpaul error = 0; 173841502Swpaul break; 173941502Swpaul case SIOCGIFMEDIA: 174041502Swpaul case SIOCSIFMEDIA: 174150675Swpaul mii = device_get_softc(sc->wb_miibus); 174250675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 174341502Swpaul break; 174441502Swpaul default: 1745106936Ssam error = ether_ioctl(ifp, command, data); 174641502Swpaul break; 174741502Swpaul } 174841502Swpaul 174941502Swpaul return(error); 175041502Swpaul} 175141502Swpaul 1752102336Salfredstatic void 1753199560Sjhbwb_watchdog(sc) 1754199560Sjhb struct wb_softc *sc; 1755199560Sjhb{ 175641502Swpaul struct ifnet *ifp; 175741502Swpaul 1758199560Sjhb WB_LOCK_ASSERT(sc); 1759199560Sjhb ifp = sc->wb_ifp; 176041502Swpaul ifp->if_oerrors++; 1761149677Sjhb if_printf(ifp, "watchdog timeout\n"); 176250675Swpaul#ifdef foo 176341502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1764149677Sjhb if_printf(ifp, "no carrier - transceiver cable problem?\n"); 176550675Swpaul#endif 176641502Swpaul wb_stop(sc); 176741502Swpaul wb_reset(sc); 1768151774Sjhb wb_init_locked(sc); 176941502Swpaul 177041502Swpaul if (ifp->if_snd.ifq_head != NULL) 1771151774Sjhb wb_start_locked(ifp); 177241502Swpaul 177341502Swpaul return; 177441502Swpaul} 177541502Swpaul 177641502Swpaul/* 177741502Swpaul * Stop the adapter and free any mbufs allocated to the 177841502Swpaul * RX and TX lists. 177941502Swpaul */ 1780102336Salfredstatic void 1781102336Salfredwb_stop(sc) 178241502Swpaul struct wb_softc *sc; 178341502Swpaul{ 178441502Swpaul register int i; 178541502Swpaul struct ifnet *ifp; 178641502Swpaul 1787151774Sjhb WB_LOCK_ASSERT(sc); 1788147256Sbrooks ifp = sc->wb_ifp; 1789199560Sjhb sc->wb_timer = 0; 179041502Swpaul 1791151774Sjhb callout_stop(&sc->wb_stat_callout); 179250675Swpaul 179341502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 179441502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 179541502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 179641502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 179741502Swpaul 179841502Swpaul /* 179941502Swpaul * Free data in the RX lists. 180041502Swpaul */ 180141502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 180241502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 180341502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 180441502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 180541502Swpaul } 180641502Swpaul } 180741502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 180841502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 180941502Swpaul 181041502Swpaul /* 181141502Swpaul * Free the TX list buffers. 181241502Swpaul */ 181341502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 181441502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 181541502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 181641502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 181741502Swpaul } 181841502Swpaul } 181941502Swpaul 182041502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 182141502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 182241502Swpaul 1823148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 182441502Swpaul 182541502Swpaul return; 182641502Swpaul} 182741502Swpaul 182841502Swpaul/* 182941502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 183041502Swpaul * get confused by errant DMAs when rebooting. 183141502Swpaul */ 1832194023Savgstatic int 1833102336Salfredwb_shutdown(dev) 183449611Swpaul device_t dev; 183541502Swpaul{ 183649611Swpaul struct wb_softc *sc; 183741502Swpaul 183849611Swpaul sc = device_get_softc(dev); 1839151774Sjhb 1840151774Sjhb WB_LOCK(sc); 184141502Swpaul wb_stop(sc); 1842151774Sjhb WB_UNLOCK(sc); 184341502Swpaul 1844194023Savg return (0); 184541502Swpaul} 1846