if_wb.c revision 166901
1139825Simp/*- 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 166901 2007-02-23 12:19:07Z piso $"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * Winbond fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 4041502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 4141502Swpaul * Winbond itself and some made by Linksys. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 4741502Swpaul/* 4841502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4941502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 5041502Swpaul * one major difference which is that while the registers do many of 5141502Swpaul * the same things as a tulip adapter, the offsets are different: where 5241502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5341502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5441502Swpaul * programmed differently. 5541502Swpaul * 5641502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5741502Swpaul * a status word, a control word and 32-bit areas that can either be used 5841502Swpaul * to point to two external data blocks, or to point to a single block 5941502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 6041502Swpaul * together in blocks to form fixed length rings or can be chained 6141502Swpaul * together in linked lists. A single packet may be spread out over 6241502Swpaul * several descriptors if necessary. 6341502Swpaul * 6441502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6541502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6641502Swpaul * to hold an entire packet. The link list is looped back to created a 6741502Swpaul * closed ring. 6841502Swpaul * 6941502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 7041502Swpaul * which each contain several individual descriptors linked toghether. 7141502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7241502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7341502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7441502Swpaul * drivers. 7541502Swpaul * 7641502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7741502Swpaul * The sample boards I have all use a Davicom PHY. 7841502Swpaul * 7941502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 8041502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 8141502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8241502Swpaul * I have no idea what he's on about: transmit performance with all 8341502Swpaul * three of my test boards seems fine. 8441502Swpaul */ 8541502Swpaul 8641502Swpaul#include <sys/param.h> 8741502Swpaul#include <sys/systm.h> 8841502Swpaul#include <sys/sockio.h> 8941502Swpaul#include <sys/mbuf.h> 9041502Swpaul#include <sys/malloc.h> 91129878Sphk#include <sys/module.h> 9241502Swpaul#include <sys/kernel.h> 9341502Swpaul#include <sys/socket.h> 9450675Swpaul#include <sys/queue.h> 9541502Swpaul 9641502Swpaul#include <net/if.h> 9741502Swpaul#include <net/if_arp.h> 9841502Swpaul#include <net/ethernet.h> 9941502Swpaul#include <net/if_dl.h> 10041502Swpaul#include <net/if_media.h> 101147256Sbrooks#include <net/if_types.h> 10241502Swpaul 10341502Swpaul#include <net/bpf.h> 10441502Swpaul 10541502Swpaul#include <vm/vm.h> /* for vtophys */ 10641502Swpaul#include <vm/pmap.h> /* for vtophys */ 10741502Swpaul#include <machine/bus.h> 10849611Swpaul#include <machine/resource.h> 10949611Swpaul#include <sys/bus.h> 11049611Swpaul#include <sys/rman.h> 11141502Swpaul 112119288Simp#include <dev/pci/pcireg.h> 113119288Simp#include <dev/pci/pcivar.h> 11441502Swpaul 11550675Swpaul#include <dev/mii/mii.h> 11650675Swpaul#include <dev/mii/miivar.h> 11750675Swpaul 118151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 11950675Swpaul#include "miibus_if.h" 12050675Swpaul 12141502Swpaul#define WB_USEIOSPACE 12241502Swpaul 123181741Simp#include <pci/if_wbreg.h> 12441502Swpaul 125113506SmdoddMODULE_DEPEND(wb, pci, 1, 1, 1); 126113506SmdoddMODULE_DEPEND(wb, ether, 1, 1, 1); 12759758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 12859758Speter 12941502Swpaul/* 13041502Swpaul * Various supported device vendors/types and their names. 13141502Swpaul */ 13241502Swpaulstatic struct wb_type wb_devs[] = { 13341502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13441502Swpaul "Winbond W89C840F 10/100BaseTX" }, 13541502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 13641502Swpaul "Compex RL100-ATX 10/100baseTX" }, 13741502Swpaul { 0, 0, NULL } 13841502Swpaul}; 13941502Swpaul 140142407Simpstatic int wb_probe(device_t); 141142407Simpstatic int wb_attach(device_t); 142142407Simpstatic int wb_detach(device_t); 14341502Swpaul 144142407Simpstatic void wb_bfree(void *addr, void *args); 145142407Simpstatic int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 146142407Simp struct mbuf *); 147142407Simpstatic int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 14841502Swpaul 149142407Simpstatic void wb_rxeof(struct wb_softc *); 150142407Simpstatic void wb_rxeoc(struct wb_softc *); 151142407Simpstatic void wb_txeof(struct wb_softc *); 152142407Simpstatic void wb_txeoc(struct wb_softc *); 153142407Simpstatic void wb_intr(void *); 154142407Simpstatic void wb_tick(void *); 155142407Simpstatic void wb_start(struct ifnet *); 156151774Sjhbstatic void wb_start_locked(struct ifnet *); 157142407Simpstatic int wb_ioctl(struct ifnet *, u_long, caddr_t); 158142407Simpstatic void wb_init(void *); 159151774Sjhbstatic void wb_init_locked(struct wb_softc *); 160142407Simpstatic void wb_stop(struct wb_softc *); 161199560Sjhbstatic void wb_watchdog(struct ifnet *); 162194023Savgstatic void wb_shutdown(device_t); 163142407Simpstatic int wb_ifmedia_upd(struct ifnet *); 164142407Simpstatic void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 16541502Swpaul 166142407Simpstatic void wb_eeprom_putbyte(struct wb_softc *, int); 167142407Simpstatic void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 168142407Simpstatic void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 169142407Simpstatic void wb_mii_sync(struct wb_softc *); 170142407Simpstatic void wb_mii_send(struct wb_softc *, u_int32_t, int); 171142407Simpstatic int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 172142407Simpstatic int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 17341502Swpaul 174142407Simpstatic void wb_setcfg(struct wb_softc *, u_int32_t); 175142407Simpstatic void wb_setmulti(struct wb_softc *); 176142407Simpstatic void wb_reset(struct wb_softc *); 177142407Simpstatic void wb_fixmedia(struct wb_softc *); 178142407Simpstatic int wb_list_rx_init(struct wb_softc *); 179142407Simpstatic int wb_list_tx_init(struct wb_softc *); 18041502Swpaul 181142407Simpstatic int wb_miibus_readreg(device_t, int, int); 182142407Simpstatic int wb_miibus_writereg(device_t, int, int, int); 183142407Simpstatic void wb_miibus_statchg(device_t); 18450675Swpaul 18549611Swpaul#ifdef WB_USEIOSPACE 18649611Swpaul#define WB_RES SYS_RES_IOPORT 18749611Swpaul#define WB_RID WB_PCI_LOIO 18849611Swpaul#else 18949611Swpaul#define WB_RES SYS_RES_MEMORY 19049611Swpaul#define WB_RID WB_PCI_LOMEM 19149611Swpaul#endif 19249611Swpaul 19349611Swpaulstatic device_method_t wb_methods[] = { 19449611Swpaul /* Device interface */ 19549611Swpaul DEVMETHOD(device_probe, wb_probe), 19649611Swpaul DEVMETHOD(device_attach, wb_attach), 19749611Swpaul DEVMETHOD(device_detach, wb_detach), 19849611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 19950675Swpaul 20050675Swpaul /* bus interface, for miibus */ 20150675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20250675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 20350675Swpaul 20450675Swpaul /* MII interface */ 20550675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 20650675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 20750675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 20849611Swpaul { 0, 0 } 20949611Swpaul}; 21049611Swpaul 21149611Swpaulstatic driver_t wb_driver = { 21251455Swpaul "wb", 21349611Swpaul wb_methods, 21449611Swpaul sizeof(struct wb_softc) 21549611Swpaul}; 21649611Swpaul 21749611Swpaulstatic devclass_t wb_devclass; 21849611Swpaul 219113506SmdoddDRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 22051473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22149611Swpaul 22241502Swpaul#define WB_SETBIT(sc, reg, x) \ 22341502Swpaul CSR_WRITE_4(sc, reg, \ 224105221Sphk CSR_READ_4(sc, reg) | (x)) 22541502Swpaul 22641502Swpaul#define WB_CLRBIT(sc, reg, x) \ 22741502Swpaul CSR_WRITE_4(sc, reg, \ 228105221Sphk CSR_READ_4(sc, reg) & ~(x)) 22941502Swpaul 23041502Swpaul#define SIO_SET(x) \ 23141502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 232105221Sphk CSR_READ_4(sc, WB_SIO) | (x)) 23341502Swpaul 23441502Swpaul#define SIO_CLR(x) \ 23541502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 236105221Sphk CSR_READ_4(sc, WB_SIO) & ~(x)) 23741502Swpaul 23841502Swpaul/* 23941502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24041502Swpaul */ 241102336Salfredstatic void 242102336Salfredwb_eeprom_putbyte(sc, addr) 24341502Swpaul struct wb_softc *sc; 24442718Swpaul int addr; 24541502Swpaul{ 24641502Swpaul register int d, i; 24741502Swpaul 24841502Swpaul d = addr | WB_EECMD_READ; 24941502Swpaul 25041502Swpaul /* 25141502Swpaul * Feed in each bit and stobe the clock. 25241502Swpaul */ 25341502Swpaul for (i = 0x400; i; i >>= 1) { 25441502Swpaul if (d & i) { 25541502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 25641502Swpaul } else { 25741502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 25841502Swpaul } 25941502Swpaul DELAY(100); 26041502Swpaul SIO_SET(WB_SIO_EE_CLK); 26141502Swpaul DELAY(150); 26241502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26341502Swpaul DELAY(100); 26441502Swpaul } 26541502Swpaul 26641502Swpaul return; 26741502Swpaul} 26841502Swpaul 26941502Swpaul/* 27041502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27141502Swpaul */ 272102336Salfredstatic void 273102336Salfredwb_eeprom_getword(sc, addr, dest) 27441502Swpaul struct wb_softc *sc; 27542718Swpaul int addr; 27641502Swpaul u_int16_t *dest; 27741502Swpaul{ 27841502Swpaul register int i; 27941502Swpaul u_int16_t word = 0; 28041502Swpaul 28141502Swpaul /* Enter EEPROM access mode. */ 28241502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28341502Swpaul 28441502Swpaul /* 28541502Swpaul * Send address of word we want to read. 28641502Swpaul */ 28741502Swpaul wb_eeprom_putbyte(sc, addr); 28841502Swpaul 28941502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29041502Swpaul 29141502Swpaul /* 29241502Swpaul * Start reading bits from EEPROM. 29341502Swpaul */ 29441502Swpaul for (i = 0x8000; i; i >>= 1) { 29541502Swpaul SIO_SET(WB_SIO_EE_CLK); 29641502Swpaul DELAY(100); 29741502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 29841502Swpaul word |= i; 29941502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30041502Swpaul DELAY(100); 30141502Swpaul } 30241502Swpaul 30341502Swpaul /* Turn off EEPROM access mode. */ 30441502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 30541502Swpaul 30641502Swpaul *dest = word; 30741502Swpaul 30841502Swpaul return; 30941502Swpaul} 31041502Swpaul 31141502Swpaul/* 31241502Swpaul * Read a sequence of words from the EEPROM. 31341502Swpaul */ 314102336Salfredstatic void 315102336Salfredwb_read_eeprom(sc, dest, off, cnt, swap) 31641502Swpaul struct wb_softc *sc; 31741502Swpaul caddr_t dest; 31841502Swpaul int off; 31941502Swpaul int cnt; 32041502Swpaul int swap; 32141502Swpaul{ 32241502Swpaul int i; 32341502Swpaul u_int16_t word = 0, *ptr; 32441502Swpaul 32541502Swpaul for (i = 0; i < cnt; i++) { 32641502Swpaul wb_eeprom_getword(sc, off + i, &word); 32741502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 32841502Swpaul if (swap) 32941502Swpaul *ptr = ntohs(word); 33041502Swpaul else 33141502Swpaul *ptr = word; 33241502Swpaul } 33341502Swpaul 33441502Swpaul return; 33541502Swpaul} 33641502Swpaul 33741502Swpaul/* 33841502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 33941502Swpaul */ 340102336Salfredstatic void 341102336Salfredwb_mii_sync(sc) 34241502Swpaul struct wb_softc *sc; 34341502Swpaul{ 34441502Swpaul register int i; 34541502Swpaul 34641502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 34741502Swpaul 34841502Swpaul for (i = 0; i < 32; i++) { 34941502Swpaul SIO_SET(WB_SIO_MII_CLK); 35041502Swpaul DELAY(1); 35141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35241502Swpaul DELAY(1); 35341502Swpaul } 35441502Swpaul 35541502Swpaul return; 35641502Swpaul} 35741502Swpaul 35841502Swpaul/* 35941502Swpaul * Clock a series of bits through the MII. 36041502Swpaul */ 361102336Salfredstatic void 362102336Salfredwb_mii_send(sc, bits, cnt) 36341502Swpaul struct wb_softc *sc; 36441502Swpaul u_int32_t bits; 36541502Swpaul int cnt; 36641502Swpaul{ 36741502Swpaul int i; 36841502Swpaul 36941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37041502Swpaul 37141502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37241502Swpaul if (bits & i) { 37341502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37441502Swpaul } else { 37541502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 37641502Swpaul } 37741502Swpaul DELAY(1); 37841502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37941502Swpaul DELAY(1); 38041502Swpaul SIO_SET(WB_SIO_MII_CLK); 38141502Swpaul } 38241502Swpaul} 38341502Swpaul 38441502Swpaul/* 38541502Swpaul * Read an PHY register through the MII. 38641502Swpaul */ 387102336Salfredstatic int 388102336Salfredwb_mii_readreg(sc, frame) 38941502Swpaul struct wb_softc *sc; 39041502Swpaul struct wb_mii_frame *frame; 39141502Swpaul 39241502Swpaul{ 39367087Swpaul int i, ack; 39441502Swpaul 39541502Swpaul /* 39641502Swpaul * Set up frame for RX. 39741502Swpaul */ 39841502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 39941502Swpaul frame->mii_opcode = WB_MII_READOP; 40041502Swpaul frame->mii_turnaround = 0; 40141502Swpaul frame->mii_data = 0; 40241502Swpaul 40341502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 40441502Swpaul 40541502Swpaul /* 40641502Swpaul * Turn on data xmit. 40741502Swpaul */ 40841502Swpaul SIO_SET(WB_SIO_MII_DIR); 40941502Swpaul 41041502Swpaul wb_mii_sync(sc); 41141502Swpaul 41241502Swpaul /* 41341502Swpaul * Send command/address info. 41441502Swpaul */ 41541502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 41641502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 41741502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 41841502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 41941502Swpaul 42041502Swpaul /* Idle bit */ 42141502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42241502Swpaul DELAY(1); 42341502Swpaul SIO_SET(WB_SIO_MII_CLK); 42441502Swpaul DELAY(1); 42541502Swpaul 42641502Swpaul /* Turn off xmit. */ 42741502Swpaul SIO_CLR(WB_SIO_MII_DIR); 42841502Swpaul /* Check for ack */ 42941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43041502Swpaul DELAY(1); 431109058Smbr ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43241502Swpaul SIO_SET(WB_SIO_MII_CLK); 43341502Swpaul DELAY(1); 43441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43541502Swpaul DELAY(1); 43641502Swpaul SIO_SET(WB_SIO_MII_CLK); 43741502Swpaul DELAY(1); 43841502Swpaul 43941502Swpaul /* 44041502Swpaul * Now try reading data bits. If the ack failed, we still 44141502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44241502Swpaul */ 44341502Swpaul if (ack) { 44441502Swpaul for(i = 0; i < 16; i++) { 44541502Swpaul SIO_CLR(WB_SIO_MII_CLK); 44641502Swpaul DELAY(1); 44741502Swpaul SIO_SET(WB_SIO_MII_CLK); 44841502Swpaul DELAY(1); 44941502Swpaul } 45041502Swpaul goto fail; 45141502Swpaul } 45241502Swpaul 45341502Swpaul for (i = 0x8000; i; i >>= 1) { 45441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45541502Swpaul DELAY(1); 45641502Swpaul if (!ack) { 45741502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 45841502Swpaul frame->mii_data |= i; 45941502Swpaul DELAY(1); 46041502Swpaul } 46141502Swpaul SIO_SET(WB_SIO_MII_CLK); 46241502Swpaul DELAY(1); 46341502Swpaul } 46441502Swpaul 46541502Swpaulfail: 46641502Swpaul 46741502Swpaul SIO_CLR(WB_SIO_MII_CLK); 46841502Swpaul DELAY(1); 46941502Swpaul SIO_SET(WB_SIO_MII_CLK); 47041502Swpaul DELAY(1); 47141502Swpaul 47241502Swpaul if (ack) 47341502Swpaul return(1); 47441502Swpaul return(0); 47541502Swpaul} 47641502Swpaul 47741502Swpaul/* 47841502Swpaul * Write to a PHY register through the MII. 47941502Swpaul */ 480102336Salfredstatic int 481102336Salfredwb_mii_writereg(sc, frame) 48241502Swpaul struct wb_softc *sc; 48341502Swpaul struct wb_mii_frame *frame; 48441502Swpaul 48541502Swpaul{ 48641502Swpaul 48741502Swpaul /* 48841502Swpaul * Set up frame for TX. 48941502Swpaul */ 49041502Swpaul 49141502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 49241502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 49341502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 49441502Swpaul 49541502Swpaul /* 49641502Swpaul * Turn on data output. 49741502Swpaul */ 49841502Swpaul SIO_SET(WB_SIO_MII_DIR); 49941502Swpaul 50041502Swpaul wb_mii_sync(sc); 50141502Swpaul 50241502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 50341502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 50441502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 50541502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 50641502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 50741502Swpaul wb_mii_send(sc, frame->mii_data, 16); 50841502Swpaul 50941502Swpaul /* Idle bit. */ 51041502Swpaul SIO_SET(WB_SIO_MII_CLK); 51141502Swpaul DELAY(1); 51241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 51341502Swpaul DELAY(1); 51441502Swpaul 51541502Swpaul /* 51641502Swpaul * Turn off xmit. 51741502Swpaul */ 51841502Swpaul SIO_CLR(WB_SIO_MII_DIR); 51941502Swpaul 52041502Swpaul return(0); 52141502Swpaul} 52241502Swpaul 523102336Salfredstatic int 524102336Salfredwb_miibus_readreg(dev, phy, reg) 52550675Swpaul device_t dev; 52650675Swpaul int phy, reg; 52750675Swpaul{ 52841502Swpaul struct wb_softc *sc; 52941502Swpaul struct wb_mii_frame frame; 53041502Swpaul 53150675Swpaul sc = device_get_softc(dev); 53250675Swpaul 53341502Swpaul bzero((char *)&frame, sizeof(frame)); 53441502Swpaul 53550675Swpaul frame.mii_phyaddr = phy; 53641502Swpaul frame.mii_regaddr = reg; 53741502Swpaul wb_mii_readreg(sc, &frame); 53841502Swpaul 53941502Swpaul return(frame.mii_data); 54041502Swpaul} 54141502Swpaul 542102336Salfredstatic int 543102336Salfredwb_miibus_writereg(dev, phy, reg, data) 54450675Swpaul device_t dev; 54550675Swpaul int phy, reg, data; 54650675Swpaul{ 54741502Swpaul struct wb_softc *sc; 54841502Swpaul struct wb_mii_frame frame; 54941502Swpaul 55050675Swpaul sc = device_get_softc(dev); 55150675Swpaul 55241502Swpaul bzero((char *)&frame, sizeof(frame)); 55341502Swpaul 55450675Swpaul frame.mii_phyaddr = phy; 55541502Swpaul frame.mii_regaddr = reg; 55641502Swpaul frame.mii_data = data; 55741502Swpaul 55841502Swpaul wb_mii_writereg(sc, &frame); 55941502Swpaul 56050675Swpaul return(0); 56150675Swpaul} 56250675Swpaul 563102336Salfredstatic void 564102336Salfredwb_miibus_statchg(dev) 56550675Swpaul device_t dev; 56650675Swpaul{ 56750675Swpaul struct wb_softc *sc; 56850675Swpaul struct mii_data *mii; 56950675Swpaul 57050675Swpaul sc = device_get_softc(dev); 57150675Swpaul mii = device_get_softc(sc->wb_miibus); 57250675Swpaul wb_setcfg(sc, mii->mii_media_active); 57350675Swpaul 57441502Swpaul return; 57541502Swpaul} 57641502Swpaul 57741502Swpaul/* 57841502Swpaul * Program the 64-bit multicast hash filter. 57941502Swpaul */ 580102336Salfredstatic void 581102336Salfredwb_setmulti(sc) 58241502Swpaul struct wb_softc *sc; 58341502Swpaul{ 58441502Swpaul struct ifnet *ifp; 58541502Swpaul int h = 0; 58641502Swpaul u_int32_t hashes[2] = { 0, 0 }; 58741502Swpaul struct ifmultiaddr *ifma; 58841502Swpaul u_int32_t rxfilt; 58941502Swpaul int mcnt = 0; 59041502Swpaul 591147256Sbrooks ifp = sc->wb_ifp; 59241502Swpaul 59341502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 59441502Swpaul 59541502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 59641502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 59741502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 59841502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 59941502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 60041502Swpaul return; 60141502Swpaul } 60241502Swpaul 60341502Swpaul /* first, zot all the existing hash bits */ 60441502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 60541502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 60641502Swpaul 60741502Swpaul /* now program new ones */ 608195049Srwatson IF_ADDR_LOCK(ifp); 60972084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 61041502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 61141502Swpaul continue; 612130270Snaddy h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 613130270Snaddy ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 61441502Swpaul if (h < 32) 61541502Swpaul hashes[0] |= (1 << h); 61641502Swpaul else 61741502Swpaul hashes[1] |= (1 << (h - 32)); 61841502Swpaul mcnt++; 61941502Swpaul } 620195049Srwatson IF_ADDR_UNLOCK(ifp); 62141502Swpaul 62241502Swpaul if (mcnt) 62341502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 62441502Swpaul else 62541502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 62641502Swpaul 62741502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 62841502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 62941502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 63041502Swpaul 63141502Swpaul return; 63241502Swpaul} 63341502Swpaul 63441502Swpaul/* 63541502Swpaul * The Winbond manual states that in order to fiddle with the 63641502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 63741502Swpaul * first have to put the transmit and/or receive logic in the idle state. 63841502Swpaul */ 639102336Salfredstatic void 640102336Salfredwb_setcfg(sc, media) 64141502Swpaul struct wb_softc *sc; 64250675Swpaul u_int32_t media; 64341502Swpaul{ 64441502Swpaul int i, restart = 0; 64541502Swpaul 64641502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 64741502Swpaul restart = 1; 64841502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 64941502Swpaul 65041502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 65141502Swpaul DELAY(10); 65241502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 65341502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 65441502Swpaul break; 65541502Swpaul } 65641502Swpaul 65741502Swpaul if (i == WB_TIMEOUT) 658162315Sglebius device_printf(sc->wb_dev, 659149677Sjhb "failed to force tx and rx to idle state\n"); 66041502Swpaul } 66141502Swpaul 66250675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 66350675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 66450675Swpaul else 66541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 66641502Swpaul 66750675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 66841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 66941502Swpaul else 67041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 67141502Swpaul 67241502Swpaul if (restart) 67341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 67441502Swpaul 67541502Swpaul return; 67641502Swpaul} 67741502Swpaul 678102336Salfredstatic void 679102336Salfredwb_reset(sc) 68041502Swpaul struct wb_softc *sc; 68141502Swpaul{ 68241502Swpaul register int i; 68350675Swpaul struct mii_data *mii; 684221407Smarius 68541502Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 68650675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 68750675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 68850675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 68950675Swpaul 69050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 69141502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 69250675Swpaul 69341502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 69441502Swpaul DELAY(10); 69541502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 69641502Swpaul break; 69741502Swpaul } 69841502Swpaul if (i == WB_TIMEOUT) 69941502Swpaul device_printf(sc->wb_dev, "reset never completed!\n"); 700162315Sglebius 70141502Swpaul /* Wait a little while for the chip to get its brains in order. */ 70241502Swpaul DELAY(1000); 70341502Swpaul 70441502Swpaul if (sc->wb_miibus == NULL) 70550675Swpaul return; 70650675Swpaul 70741502Swpaul mii = device_get_softc(sc->wb_miibus); 70850675Swpaul if (mii == NULL) 709221407Smarius return; 710221407Smarius 71141502Swpaul if (mii->mii_instance) { 71241502Swpaul struct mii_softc *miisc; 713102336Salfred LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 714102336Salfred mii_phy_reset(miisc); 71550675Swpaul } 71650675Swpaul 71750675Swpaul return; 71850675Swpaul} 71950675Swpaul 72050675Swpaulstatic void 72150675Swpaulwb_fixmedia(sc) 722147256Sbrooks struct wb_softc *sc; 72350675Swpaul{ 72450675Swpaul struct mii_data *mii = NULL; 72550675Swpaul struct ifnet *ifp; 72650675Swpaul u_int32_t media; 72750675Swpaul 72850675Swpaul if (sc->wb_miibus == NULL) 72950675Swpaul return; 73050675Swpaul 73150675Swpaul mii = device_get_softc(sc->wb_miibus); 73250675Swpaul ifp = sc->wb_ifp; 73350675Swpaul 73450675Swpaul mii_pollstat(mii); 73550675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 73650675Swpaul media = mii->mii_media_active & ~IFM_10_T; 73741502Swpaul media |= IFM_100_TX; 73841502Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 73941502Swpaul media = mii->mii_media_active & ~IFM_100_TX; 74041502Swpaul media |= IFM_10_T; 741102336Salfred } else 742102336Salfred return; 74349611Swpaul 74441502Swpaul ifmedia_set(&mii->mii_media, media); 74541502Swpaul 74641502Swpaul return; 74741502Swpaul} 74841502Swpaul 74941502Swpaul/* 75049611Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 75149611Swpaul * IDs against our list and return a device name if we find a match. 75249611Swpaul */ 753142398Simpstatic int 75441502Swpaulwb_probe(dev) 75541502Swpaul device_t dev; 75641502Swpaul{ 75741502Swpaul struct wb_type *t; 75849611Swpaul 75941502Swpaul t = wb_devs; 76041502Swpaul 76141502Swpaul while(t->wb_name != NULL) { 76241502Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 76341502Swpaul (pci_get_device(dev) == t->wb_did)) { 76441502Swpaul device_set_desc(dev, t->wb_name); 765102336Salfred return (BUS_PROBE_DEFAULT); 766102336Salfred } 76749611Swpaul t++; 76841502Swpaul } 76941502Swpaul 77041502Swpaul return(ENXIO); 77141502Swpaul} 772149677Sjhb 77341502Swpaul/* 77449611Swpaul * Attach the interface. Allocate softc structures, do ifmedia 775162315Sglebius * setup and ethernet/BPF attach. 77641502Swpaul */ 77793818Sjhbstatic int 778151774Sjhbwb_attach(dev) 779151774Sjhb device_t dev; 780151774Sjhb{ 78141502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 78241502Swpaul struct wb_softc *sc; 78341502Swpaul struct ifnet *ifp; 78472813Swpaul int error = 0, rid; 78541502Swpaul 78649611Swpaul sc = device_get_softc(dev); 787127135Snjl sc->wb_dev = dev; 78849611Swpaul 78949611Swpaul mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 790149677Sjhb MTX_DEF); 79149611Swpaul callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0); 79241502Swpaul 79341502Swpaul /* 79441502Swpaul * Map control/status registers. 79541502Swpaul */ 79649611Swpaul pci_enable_busmaster(dev); 797127135Snjl 79849611Swpaul rid = WB_RID; 79949611Swpaul sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 80049611Swpaul 801149677Sjhb if (sc->wb_res == NULL) { 80249611Swpaul device_printf(dev, "couldn't map ports/memory\n"); 80341502Swpaul error = ENXIO; 80441502Swpaul goto fail; 80541502Swpaul } 80650675Swpaul 80750675Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 80850675Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 80941502Swpaul 81041502Swpaul /* Allocate interrupt */ 81141502Swpaul rid = 0; 81241502Swpaul sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 81341502Swpaul RF_SHAREABLE | RF_ACTIVE); 81441502Swpaul 81541502Swpaul if (sc->wb_irq == NULL) { 81641502Swpaul device_printf(dev, "couldn't map interrupt\n"); 81750675Swpaul error = ENXIO; 81851657Swpaul goto fail; 81950675Swpaul } 82050675Swpaul 821149677Sjhb /* Save the cache line size. */ 82249611Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 82349611Swpaul 82441502Swpaul /* Reset the adapter. */ 82541502Swpaul wb_reset(sc); 82641502Swpaul 82741502Swpaul /* 828147256Sbrooks * Get station address from the EEPROM. 829147256Sbrooks */ 830149677Sjhb wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 831147256Sbrooks 832147256Sbrooks sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 833147256Sbrooks M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 83441502Swpaul 835121816Sbrooks if (sc->wb_ldata == NULL) { 83641502Swpaul device_printf(dev, "no memory for list buffers!\n"); 837151774Sjhb error = ENXIO; 83841502Swpaul goto fail; 83941502Swpaul } 84041502Swpaul 84143515Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 84241502Swpaul 84350675Swpaul ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 84450675Swpaul if (ifp == NULL) { 84550675Swpaul device_printf(dev, "can not if_alloc()\n"); 846213894Smarius error = ENOSPC; 847213894Smarius goto fail; 848214913Smarius } 849213894Smarius ifp->if_softc = sc; 85041502Swpaul if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 85141502Swpaul ifp->if_mtu = ETHERMTU; 85241502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 85341502Swpaul ifp->if_ioctl = wb_ioctl; 85463090Sarchie ifp->if_start = wb_start; 85541502Swpaul ifp->if_watchdog = wb_watchdog; 856106936Ssam ifp->if_init = wb_init; 85741502Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 858113609Snjl 859151774Sjhb /* 860166901Spiso * Do MII setup. 861112872Snjl */ 862112872Snjl if (mii_phy_probe(dev, &sc->wb_miibus, 863149677Sjhb wb_ifmedia_upd, wb_ifmedia_sts)) { 864113609Snjl error = ENXIO; 865112872Snjl goto fail; 866112872Snjl } 867112872Snjl 86841502Swpaul /* 86950675Swpaul * Call MI attach routine. 870112872Snjl */ 87150675Swpaul ether_ifattach(ifp, eaddr); 87249611Swpaul 87341502Swpaul /* Hook interrupt last to avoid having to lock softc */ 87441502Swpaul error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE, 875113609Snjl NULL, wb_intr, sc, &sc->wb_intrhand); 876113609Snjl 877113609Snjl if (error) { 878113609Snjl device_printf(dev, "couldn't set up irq\n"); 879113609Snjl ether_ifdetach(ifp); 880113609Snjl goto fail; 881113609Snjl } 882102336Salfred 883102336Salfredfail: 88449611Swpaul if (error) 88549611Swpaul wb_detach(dev); 88649611Swpaul 88749611Swpaul return(error); 88849611Swpaul} 88949611Swpaul 890112880Sjhb/* 891147256Sbrooks * Shutdown hardware and free up resources. This can be called any 89249611Swpaul * time after the mutex has been initialized. It is called in both 893113609Snjl * the error case in attach and the normal detach case so it needs 894113609Snjl * to be careful about only freeing resources that have actually been 895113609Snjl * allocated. 896113609Snjl */ 897113812Simpstatic int 898199560Sjhbwb_detach(dev) 899151774Sjhb device_t dev; 900113609Snjl{ 901151774Sjhb struct wb_softc *sc; 902151774Sjhb struct ifnet *ifp; 903150213Sru 904113609Snjl sc = device_get_softc(dev); 905112872Snjl KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 906113609Snjl ifp = sc->wb_ifp; 90750675Swpaul 908112872Snjl /* 909112872Snjl * Delete any miibus and phy devices attached to this interface. 910112872Snjl * This should only be done if attach succeeded. 911112872Snjl */ 912112872Snjl if (device_is_attached(dev)) { 913112872Snjl WB_LOCK(sc); 91449611Swpaul wb_stop(sc); 915151297Sru WB_UNLOCK(sc); 916151297Sru callout_drain(&sc->wb_stat_callout); 917151297Sru ether_ifdetach(ifp); 918112872Snjl } 919112872Snjl if (sc->wb_miibus) 920112872Snjl device_delete_child(dev, sc->wb_miibus); 921112872Snjl bus_generic_detach(dev); 92249611Swpaul 92367087Swpaul if (sc->wb_intrhand) 92449611Swpaul bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 92549611Swpaul if (sc->wb_irq) 92649611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 92749611Swpaul if (sc->wb_res) 92841502Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 92941502Swpaul 93041502Swpaul if (ifp) 931102336Salfred if_free(ifp); 932102336Salfred 93341502Swpaul if (sc->wb_ldata) { 93441502Swpaul contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 93541502Swpaul M_DEVBUF); 93641502Swpaul } 93741502Swpaul 93841502Swpaul mtx_destroy(&sc->wb_mtx); 93941502Swpaul 94041502Swpaul return(0); 94141502Swpaul} 94241502Swpaul 94341502Swpaul/* 94441502Swpaul * Initialize the transmit descriptors. 94541502Swpaul */ 94641502Swpaulstatic int 94741502Swpaulwb_list_tx_init(sc) 94841502Swpaul struct wb_softc *sc; 94941502Swpaul{ 95041502Swpaul struct wb_chain_data *cd; 95141502Swpaul struct wb_list_data *ld; 95241502Swpaul int i; 95341502Swpaul 95441502Swpaul cd = &sc->wb_cdata; 95541502Swpaul ld = sc->wb_ldata; 95641502Swpaul 95741502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 95841502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 95941502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 96041502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 96141502Swpaul &cd->wb_tx_chain[0]; 96241502Swpaul } else { 96341502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 96441502Swpaul &cd->wb_tx_chain[i + 1]; 965102336Salfred } 966102336Salfred } 96741502Swpaul 96841502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 96941502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 97041502Swpaul 97141502Swpaul return(0); 97241502Swpaul} 97341502Swpaul 97441502Swpaul 97541502Swpaul/* 97641502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 97741502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 97841502Swpaul * points back to the first. 97950675Swpaul */ 98048745Swpaulstatic int 98141502Swpaulwb_list_rx_init(sc) 98241502Swpaul struct wb_softc *sc; 98341502Swpaul{ 98441502Swpaul struct wb_chain_data *cd; 98541502Swpaul struct wb_list_data *ld; 98641502Swpaul int i; 98741502Swpaul 98841502Swpaul cd = &sc->wb_cdata; 98941502Swpaul ld = sc->wb_ldata; 99041502Swpaul 99141502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 99241502Swpaul cd->wb_rx_chain[i].wb_ptr = 99341502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 99441502Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 99541502Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 99641502Swpaul return(ENOBUFS); 99741502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 99841502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 999102336Salfred ld->wb_rx_list[i].wb_next = 1000102336Salfred vtophys(&ld->wb_rx_list[0]); 100198995Salfred } else { 100264837Sdwmalone cd->wb_rx_chain[i].wb_nextdesc = 100350675Swpaul &cd->wb_rx_chain[i + 1]; 100450675Swpaul ld->wb_rx_list[i].wb_next = 100550675Swpaul vtophys(&ld->wb_rx_list[i + 1]); 100650675Swpaul } 100741502Swpaul } 100841502Swpaul 100941502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 1010102336Salfred 1011102336Salfred return(0); 101241502Swpaul} 101341502Swpaul 101448745Swpaulstatic void 101541502Swpaulwb_bfree(buf, args) 101641502Swpaul void *buf; 101741502Swpaul void *args; 101848745Swpaul{ 1019111119Simp return; 102087846Sluigi} 102148745Swpaul 102264837Sdwmalone/* 102364837Sdwmalone * Initialize an RX descriptor and attach an MBUF cluster. 1024175872Sphk */ 1025175872Sphkstatic int 102648745Swpaulwb_newbuf(sc, c, m) 102748745Swpaul struct wb_softc *sc; 102850675Swpaul struct wb_chain_onefrag *c; 102948745Swpaul struct mbuf *m; 103041502Swpaul{ 103141502Swpaul struct mbuf *m_new = NULL; 103248745Swpaul 103348745Swpaul if (m == NULL) { 103441502Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 103541502Swpaul if (m_new == NULL) 103650675Swpaul return(ENOBUFS); 103741502Swpaul m_new->m_data = c->wb_buf; 103841502Swpaul m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 103941502Swpaul MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 104041502Swpaul EXT_NET_DRV); 104141502Swpaul } else { 104241502Swpaul m_new = m; 104341502Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 104441502Swpaul m_new->m_data = m_new->m_ext.ext_buf; 104541502Swpaul } 1046102336Salfred 1047102336Salfred m_adj(m_new, sizeof(u_int64_t)); 104841502Swpaul 104941502Swpaul c->wb_mbuf = m_new; 105050675Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 105141502Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 105241502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 105341502Swpaul 105441502Swpaul return(0); 105541502Swpaul} 1056122689Ssam 1057122689Ssam/* 1058147256Sbrooks * A frame has been uploaded: pass the resulting mbuf chain up to 105941502Swpaul * the higher level protocols. 106041502Swpaul */ 106141502Swpaulstatic void 106248745Swpaulwb_rxeof(sc) 106348745Swpaul struct wb_softc *sc; 106441502Swpaul{ 106541502Swpaul struct mbuf *m = NULL; 106650675Swpaul struct ifnet *ifp; 106748745Swpaul struct wb_chain_onefrag *cur_rx; 106841502Swpaul int total_len = 0; 106950675Swpaul u_int32_t rxstat; 107050675Swpaul 107150675Swpaul WB_LOCK_ASSERT(sc); 107250675Swpaul 107350675Swpaul ifp = sc->wb_ifp; 107441502Swpaul 107550675Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1076162315Sglebius WB_RXSTAT_OWN)) { 1077162315Sglebius struct mbuf *m0 = NULL; 1078162315Sglebius 107950675Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 108050675Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1081151774Sjhb 108241502Swpaul m = cur_rx->wb_mbuf; 108341502Swpaul 108441502Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 108542718Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 108642718Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 108748745Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 108850675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 108942718Swpaul ifp->if_ierrors++; 109042718Swpaul wb_newbuf(sc, cur_rx, m); 109141502Swpaul device_printf(sc->wb_dev, 109241502Swpaul "receiver babbling: possible chip bug," 109341502Swpaul " forcing reset\n"); 109441502Swpaul wb_fixmedia(sc); 109541934Swpaul wb_reset(sc); 109641934Swpaul wb_init_locked(sc); 109741934Swpaul return; 109841934Swpaul } 109941934Swpaul 110041934Swpaul if (rxstat & WB_RXSTAT_RXERR) { 110141934Swpaul ifp->if_ierrors++; 110241934Swpaul wb_newbuf(sc, cur_rx, m); 110378508Sbmilekic break; 110478508Sbmilekic } 110548745Swpaul 110648745Swpaul /* No errors; receive the packet. */ 110748745Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 110850675Swpaul 110941502Swpaul /* 111048745Swpaul * XXX The Winbond chip includes the CRC with every 111141502Swpaul * received frame, and there's no way to turn this 111241502Swpaul * behavior off (at least, I can't find anything in 1113122689Ssam * the manual that explains how to do it) so we have 1114106936Ssam * to trim off the CRC manually. 1115122689Ssam */ 111641502Swpaul total_len -= ETHER_CRC_LEN; 111741502Swpaul 111841502Swpaul m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1119105221Sphk NULL); 1120102336Salfred wb_newbuf(sc, cur_rx, m); 112141502Swpaul if (m0 == NULL) { 112241502Swpaul ifp->if_ierrors++; 112341502Swpaul break; 112441502Swpaul } 112541502Swpaul m = m0; 112641502Swpaul 112741502Swpaul ifp->if_ipackets++; 112841502Swpaul WB_UNLOCK(sc); 112941502Swpaul (*ifp->if_input)(ifp, m); 113041502Swpaul WB_LOCK(sc); 113141502Swpaul } 113241502Swpaul} 113341502Swpaul 113441502Swpaulstatic void 113541502Swpaulwb_rxeoc(sc) 113641502Swpaul struct wb_softc *sc; 113741502Swpaul{ 1138102336Salfred wb_rxeof(sc); 1139102336Salfred 114041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 114141502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 114241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 114341502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 114441502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1145147256Sbrooks 114641502Swpaul return; 114741502Swpaul} 1148199560Sjhb 114941502Swpaul/* 115041502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 115141502Swpaul * the list buffers. 115241502Swpaul */ 115341502Swpaulstatic void 115441502Swpaulwb_txeof(sc) 115541502Swpaul struct wb_softc *sc; 115641502Swpaul{ 115741502Swpaul struct wb_chain *cur_tx; 115841502Swpaul struct ifnet *ifp; 115941502Swpaul 116041502Swpaul ifp = sc->wb_ifp; 116141502Swpaul 116241502Swpaul /* Clear the timeout timer. */ 116341502Swpaul ifp->if_timer = 0; 116441502Swpaul 116541502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 116641502Swpaul return; 116741502Swpaul 116841502Swpaul /* 116941502Swpaul * Go through our tx list and free mbufs for those 117041502Swpaul * frames that have been transmitted. 117141502Swpaul */ 117241502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 117341502Swpaul u_int32_t txstat; 117441502Swpaul 117541502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 117641502Swpaul txstat = WB_TXSTATUS(cur_tx); 117741502Swpaul 117841502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 117941502Swpaul break; 118041502Swpaul 118141502Swpaul if (txstat & WB_TXSTAT_TXERR) { 118241502Swpaul ifp->if_oerrors++; 118341502Swpaul if (txstat & WB_TXSTAT_ABORT) 118441502Swpaul ifp->if_collisions++; 118541502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 118641502Swpaul ifp->if_collisions++; 118741502Swpaul } 118841502Swpaul 118941502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 119041502Swpaul 119141502Swpaul ifp->if_opackets++; 119241502Swpaul m_freem(cur_tx->wb_mbuf); 119341502Swpaul cur_tx->wb_mbuf = NULL; 119441502Swpaul 1195102336Salfred if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1196102336Salfred sc->wb_cdata.wb_tx_head = NULL; 119741502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 119841502Swpaul break; 119941502Swpaul } 120041502Swpaul 1201147256Sbrooks sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 120241502Swpaul } 1203199560Sjhb 120441502Swpaul return; 120541502Swpaul} 1206148887Srwatson 120741502Swpaul/* 120841502Swpaul * TX 'end of channel' interrupt handler. 120941502Swpaul */ 121041502Swpaulstatic void 1211199560Sjhbwb_txeoc(sc) 121241502Swpaul struct wb_softc *sc; 121341502Swpaul{ 121441502Swpaul struct ifnet *ifp; 121541502Swpaul 121641502Swpaul ifp = sc->wb_ifp; 121741502Swpaul 121841502Swpaul ifp->if_timer = 0; 1219102336Salfred 1220102336Salfred if (sc->wb_cdata.wb_tx_head == NULL) { 122141502Swpaul ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 122241502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 122341502Swpaul } else { 122441502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 122541502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 122641502Swpaul ifp->if_timer = 5; 122741502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 122867087Swpaul } 1229147256Sbrooks } 123041502Swpaul 1231151774Sjhb return; 123267087Swpaul} 123341502Swpaul 123467087Swpaulstatic void 123541502Swpaulwb_intr(arg) 123641502Swpaul void *arg; 123741502Swpaul{ 123841502Swpaul struct wb_softc *sc; 123941502Swpaul struct ifnet *ifp; 124041502Swpaul u_int32_t status; 124141502Swpaul 124241502Swpaul sc = arg; 124341502Swpaul WB_LOCK(sc); 124441502Swpaul ifp = sc->wb_ifp; 124541502Swpaul 124641502Swpaul if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 124741502Swpaul WB_UNLOCK(sc); 124841502Swpaul return; 124941502Swpaul } 125041502Swpaul 125150675Swpaul /* Disable interrupts. */ 125250675Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1253151774Sjhb 125450675Swpaul for (;;) { 125541502Swpaul 125641502Swpaul status = CSR_READ_4(sc, WB_ISR); 125750675Swpaul if (status) 125850675Swpaul CSR_WRITE_4(sc, WB_ISR, status); 125950675Swpaul 126050675Swpaul if ((status & WB_INTRS) == 0) 126150675Swpaul break; 126250675Swpaul 126341502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 126441502Swpaul ifp->if_ierrors++; 126541502Swpaul wb_reset(sc); 126641502Swpaul if (status & WB_ISR_RX_ERR) 126741502Swpaul wb_fixmedia(sc); 126841502Swpaul wb_init_locked(sc); 126941502Swpaul continue; 127041502Swpaul } 127141502Swpaul 127241502Swpaul if (status & WB_ISR_RX_OK) 127341502Swpaul wb_rxeof(sc); 127441502Swpaul 127541502Swpaul if (status & WB_ISR_RX_IDLE) 127641502Swpaul wb_rxeoc(sc); 127741502Swpaul 127841502Swpaul if (status & WB_ISR_TX_OK) 127941502Swpaul wb_txeof(sc); 128041502Swpaul 128141502Swpaul if (status & WB_ISR_TX_NOBUF) 128241502Swpaul wb_txeoc(sc); 128341502Swpaul 128441502Swpaul if (status & WB_ISR_TX_IDLE) { 128541502Swpaul wb_txeof(sc); 128641502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 128741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 128841502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 128941502Swpaul } 1290151774Sjhb } 129141502Swpaul 129241502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 129341502Swpaul ifp->if_oerrors++; 129441502Swpaul wb_txeof(sc); 129541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 129641502Swpaul /* Jack up TX threshold */ 129741502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 129841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1299151774Sjhb WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 130041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 130141502Swpaul } 130267087Swpaul 130367087Swpaul if (status & WB_ISR_BUS_ERR) { 130441502Swpaul wb_reset(sc); 130541502Swpaul wb_init_locked(sc); 130641502Swpaul } 1307102336Salfred 1308102336Salfred } 130950675Swpaul 131050675Swpaul /* Re-enable interrupts. */ 131150675Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 131250675Swpaul 131350675Swpaul if (ifp->if_snd.ifq_head != NULL) { 131450675Swpaul wb_start_locked(ifp); 1315151774Sjhb } 131650675Swpaul 131750675Swpaul WB_UNLOCK(sc); 131850675Swpaul 131950675Swpaul return; 1320199560Sjhb} 1321199560Sjhb 1322151774Sjhbstatic void 132350675Swpaulwb_tick(xsc) 132450675Swpaul void *xsc; 132550675Swpaul{ 132650675Swpaul struct wb_softc *sc; 132741502Swpaul struct mii_data *mii; 132841502Swpaul 132941502Swpaul sc = xsc; 133041502Swpaul WB_LOCK_ASSERT(sc); 1331102336Salfred mii = device_get_softc(sc->wb_miibus); 1332102336Salfred 133341502Swpaul mii_tick(mii); 133441502Swpaul 133541502Swpaul callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 133641502Swpaul 133741502Swpaul return; 133841502Swpaul} 133941502Swpaul 134041502Swpaul/* 134141502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 134241502Swpaul * pointers to the fragment pointers. 134341502Swpaul */ 134441502Swpaulstatic int 134541502Swpaulwb_encap(sc, c, m_head) 134641502Swpaul struct wb_softc *sc; 134741502Swpaul struct wb_chain *c; 134841502Swpaul struct mbuf *m_head; 134941502Swpaul{ 135041502Swpaul int frag = 0; 135141502Swpaul struct wb_desc *f = NULL; 135241502Swpaul int total_len; 135341502Swpaul struct mbuf *m; 135441502Swpaul 135541502Swpaul /* 135641502Swpaul * Start packing the mbufs in this chain into 135741502Swpaul * the fragment pointers. Stop when we run out 135841502Swpaul * of fragments or hit the end of the mbuf chain. 135941502Swpaul */ 136041502Swpaul m = m_head; 136141502Swpaul total_len = 0; 136241502Swpaul 136341502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 136441502Swpaul if (m->m_len != 0) { 136541502Swpaul if (frag == WB_MAXFRAGS) 136641502Swpaul break; 136741502Swpaul total_len += m->m_len; 136841502Swpaul f = &c->wb_ptr->wb_frag[frag]; 136941502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 137041502Swpaul if (frag == 0) { 137141502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 137241502Swpaul f->wb_status = 0; 137341502Swpaul } else 137441502Swpaul f->wb_status = WB_TXSTAT_OWN; 137541502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 137641502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 137741502Swpaul frag++; 137841502Swpaul } 1379111119Simp } 138087846Sluigi 138141502Swpaul /* 138241502Swpaul * Handle special case: we used up all 16 fragments, 1383111119Simp * but we have more mbufs left in the chain. Copy the 138441502Swpaul * data into an mbuf cluster. Note that we don't 138541502Swpaul * bother clearing the values in the other fragment 138641502Swpaul * pointers/counters; it wouldn't gain us anything, 138741502Swpaul * and would waste cycles. 138841502Swpaul */ 138941502Swpaul if (m != NULL) { 139041502Swpaul struct mbuf *m_new = NULL; 139141502Swpaul 139241502Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 139341502Swpaul if (m_new == NULL) 139441502Swpaul return(1); 139541502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 139641502Swpaul MCLGET(m_new, M_DONTWAIT); 139741502Swpaul if (!(m_new->m_flags & M_EXT)) { 139841502Swpaul m_freem(m_new); 139941502Swpaul return(1); 140041502Swpaul } 140141502Swpaul } 140241502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 140341502Swpaul mtod(m_new, caddr_t)); 140441502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 140541502Swpaul m_freem(m_head); 140641502Swpaul m_head = m_new; 140741502Swpaul f = &c->wb_ptr->wb_frag[0]; 140841502Swpaul f->wb_status = 0; 140941502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 141041502Swpaul f->wb_ctl = total_len = m_new->m_len; 141141502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 141241502Swpaul frag = 1; 141341502Swpaul } 141441502Swpaul 141541502Swpaul if (total_len < WB_MIN_FRAMELEN) { 141641502Swpaul f = &c->wb_ptr->wb_frag[frag]; 141741502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 141841502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 141941502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 142041502Swpaul f->wb_status = WB_TXSTAT_OWN; 142141502Swpaul frag++; 142241502Swpaul } 142341502Swpaul 142441502Swpaul c->wb_mbuf = m_head; 142541502Swpaul c->wb_lastdesc = frag - 1; 1426102336Salfred WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1427102336Salfred WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 142841502Swpaul 142941502Swpaul return(0); 143041502Swpaul} 1431151774Sjhb 1432151774Sjhb/* 1433151774Sjhb * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1434151774Sjhb * to the mbuf data regions directly in the transmit lists. We also save a 1435151774Sjhb * copy of the pointers since the transmit list fragment pointers are 1436151774Sjhb * physical addresses. 1437151774Sjhb */ 1438151774Sjhb 1439151774Sjhbstatic void 1440151774Sjhbwb_start(ifp) 1441151774Sjhb struct ifnet *ifp; 1442151774Sjhb{ 144341502Swpaul struct wb_softc *sc; 144441502Swpaul 144541502Swpaul sc = ifp->if_softc; 144641502Swpaul WB_LOCK(sc); 1447151774Sjhb wb_start_locked(ifp); 144841502Swpaul WB_UNLOCK(sc); 144941502Swpaul} 145041502Swpaul 145141502Swpaulstatic void 145241502Swpaulwb_start_locked(ifp) 145341502Swpaul struct ifnet *ifp; 1454148887Srwatson{ 145541502Swpaul struct wb_softc *sc; 145641502Swpaul struct mbuf *m_head = NULL; 145741502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 145841502Swpaul 145941502Swpaul sc = ifp->if_softc; 146041502Swpaul WB_LOCK_ASSERT(sc); 146141502Swpaul 146241502Swpaul /* 146341502Swpaul * Check for an available queue slot. If there are none, 146441502Swpaul * punt. 146541502Swpaul */ 146641502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 146741502Swpaul ifp->if_drv_flags |= IFF_DRV_OACTIVE; 146841502Swpaul return; 146941502Swpaul } 147041502Swpaul 147141502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 147241502Swpaul 147341502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 147441502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 147541502Swpaul if (m_head == NULL) 147641502Swpaul break; 147741502Swpaul 147841502Swpaul /* Pick a descriptor off the free list. */ 1479106936Ssam cur_tx = sc->wb_cdata.wb_tx_free; 148041502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 148141502Swpaul 148241502Swpaul /* Pack the data into the descriptor. */ 148341526Swpaul wb_encap(sc, cur_tx, m_head); 148441526Swpaul 1485151774Sjhb if (cur_tx != start_tx) 148641526Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 148741526Swpaul 148841526Swpaul /* 148941502Swpaul * If there's a BPF listener, bounce a copy of this frame 149041502Swpaul * to him. 149141502Swpaul */ 1492172568Skevlo BPF_MTAP(ifp, cur_tx->wb_mbuf); 149341502Swpaul } 149441502Swpaul 149541502Swpaul /* 149642718Swpaul * If there are no packets queued, bail. 149741502Swpaul */ 149841502Swpaul if (cur_tx == NULL) 149941502Swpaul return; 150041502Swpaul 150141502Swpaul /* 150241502Swpaul * Place the request for the upload interrupt 150341502Swpaul * in the last descriptor in the chain. This way, if 150441502Swpaul * we're chaining several packets at once, we'll only 150541502Swpaul * get an interupt once for the whole chain rather than 150641502Swpaul * once for each packet. 150741502Swpaul */ 150841502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 150941502Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 151041502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 151141502Swpaul 151241502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 151341502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 151441502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 151541502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 151641502Swpaul } else { 151741502Swpaul /* 151841502Swpaul * We need to distinguish between the case where 151941502Swpaul * the own bit is clear because the chip cleared it 152041502Swpaul * and where the own bit is clear because we haven't 152141502Swpaul * set it yet. The magic value WB_UNSET is just some 1522199560Sjhb * ramdomly chosen number which doesn't have the own 152341502Swpaul * bit set. When we actually transmit the frame, the 152441502Swpaul * status word will have _only_ the own bit set, so 152541502Swpaul * the txeoc handler will be able to tell if it needs 152641502Swpaul * to initiate another transmission to flush out pending 1527102336Salfred * frames. 1528102336Salfred */ 152941502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 153041502Swpaul } 153141502Swpaul 1532151774Sjhb /* 1533151774Sjhb * Set a timeout in case the chip goes out to lunch. 1534151774Sjhb */ 1535151774Sjhb ifp->if_timer = 5; 1536151774Sjhb 1537151774Sjhb return; 1538151774Sjhb} 1539151774Sjhb 1540151774Sjhbstatic void 1541151774Sjhbwb_init(xsc) 1542147256Sbrooks void *xsc; 154367087Swpaul{ 154450675Swpaul struct wb_softc *sc = xsc; 154541502Swpaul 1546151774Sjhb WB_LOCK(sc); 154750675Swpaul wb_init_locked(sc); 154841502Swpaul WB_UNLOCK(sc); 154941502Swpaul} 155041502Swpaul 155141502Swpaulstatic void 155241502Swpaulwb_init_locked(sc) 155341502Swpaul struct wb_softc *sc; 155441502Swpaul{ 155541502Swpaul struct ifnet *ifp = sc->wb_ifp; 155641502Swpaul int i; 155741502Swpaul struct mii_data *mii; 155841502Swpaul 155941502Swpaul WB_LOCK_ASSERT(sc); 156050675Swpaul mii = device_get_softc(sc->wb_miibus); 156141502Swpaul 156241502Swpaul /* 156341502Swpaul * Cancel pending I/O and free all RX/TX buffers. 156450675Swpaul */ 156541502Swpaul wb_stop(sc); 156650675Swpaul wb_reset(sc); 156750675Swpaul 156850675Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 156950675Swpaul 157050675Swpaul /* 157150675Swpaul * Set cache alignment and burst length. 157250675Swpaul */ 157350675Swpaul#ifdef foo 157450675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 157550675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 157650675Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 157750675Swpaul#endif 157850675Swpaul 157950675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 158050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 158150675Swpaul switch(sc->wb_cachesize) { 158250675Swpaul case 32: 158350675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 158441502Swpaul break; 158541502Swpaul case 16: 158641502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 158741502Swpaul break; 158841502Swpaul case 8: 1589152315Sru WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 159041502Swpaul break; 159141502Swpaul case 0: 159241502Swpaul default: 159341502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1594162315Sglebius break; 1595149677Sjhb } 159641502Swpaul 159741502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 159841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 159941502Swpaul 160041502Swpaul /* Init our MAC address */ 160141502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 160241502Swpaul CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]); 160341502Swpaul } 160441502Swpaul 160541502Swpaul /* Init circular RX list. */ 160641502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 160741502Swpaul device_printf(sc->wb_dev, 160841502Swpaul "initialization failed: no memory for rx buffers\n"); 160941502Swpaul wb_stop(sc); 161041502Swpaul return; 161141502Swpaul } 161241502Swpaul 161341502Swpaul /* Init TX descriptors. */ 161441502Swpaul wb_list_tx_init(sc); 161541502Swpaul 161641502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 161741502Swpaul if (ifp->if_flags & IFF_PROMISC) { 161841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 161941502Swpaul } else { 162041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 162141502Swpaul } 162241502Swpaul 162341502Swpaul /* 162441502Swpaul * Set capture broadcast bit to capture broadcast frames. 162541502Swpaul */ 162641502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 162741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 162841502Swpaul } else { 162941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 163041502Swpaul } 163141502Swpaul 163241502Swpaul /* 163341502Swpaul * Program the multicast filter, if necessary. 163441502Swpaul */ 163541502Swpaul wb_setmulti(sc); 163641502Swpaul 163741502Swpaul /* 163841502Swpaul * Load the address of the RX list. 163941502Swpaul */ 164041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 164141502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 164241502Swpaul 164341502Swpaul /* 164450675Swpaul * Enable interrupts. 164541502Swpaul */ 1646148887Srwatson CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1647148887Srwatson CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 164841502Swpaul 1649151774Sjhb /* Enable receiver and transmitter. */ 165050675Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 165141502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 165241502Swpaul 165341502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 165441502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 165541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 165641502Swpaul 1657102336Salfred mii_mediachg(mii); 1658102336Salfred 165941502Swpaul ifp->if_drv_flags |= IFF_DRV_RUNNING; 166041502Swpaul ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 166141502Swpaul 166241502Swpaul callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 166341502Swpaul 166441502Swpaul return; 1665151774Sjhb} 166650675Swpaul 1667151774Sjhb/* 1668151774Sjhb * Set media options. 166941502Swpaul */ 167041502Swpaulstatic int 167141502Swpaulwb_ifmedia_upd(ifp) 167241502Swpaul struct ifnet *ifp; 167341502Swpaul{ 167441502Swpaul struct wb_softc *sc; 167541502Swpaul 1676102336Salfred sc = ifp->if_softc; 1677102336Salfred 167841502Swpaul WB_LOCK(sc); 167941502Swpaul if (ifp->if_flags & IFF_UP) 168041502Swpaul wb_init_locked(sc); 168141502Swpaul WB_UNLOCK(sc); 168250675Swpaul 168341502Swpaul return(0); 168441502Swpaul} 168541502Swpaul 1686151774Sjhb/* 168750675Swpaul * Report current media status. 168841502Swpaul */ 168950675Swpaulstatic void 169050675Swpaulwb_ifmedia_sts(ifp, ifmr) 169150675Swpaul struct ifnet *ifp; 1692151774Sjhb struct ifmediareq *ifmr; 169341502Swpaul{ 169441502Swpaul struct wb_softc *sc; 169541502Swpaul struct mii_data *mii; 169641502Swpaul 1697102336Salfred sc = ifp->if_softc; 1698102336Salfred 169941502Swpaul WB_LOCK(sc); 170041502Swpaul mii = device_get_softc(sc->wb_miibus); 170141502Swpaul 170241502Swpaul mii_pollstat(mii); 170341502Swpaul ifmr->ifm_active = mii->mii_media_active; 170450675Swpaul ifmr->ifm_status = mii->mii_media_status; 170541502Swpaul WB_UNLOCK(sc); 170667087Swpaul 170741502Swpaul return; 170841502Swpaul} 170941502Swpaul 1710151774Sjhbstatic int 171141502Swpaulwb_ioctl(ifp, command, data) 1712151774Sjhb struct ifnet *ifp; 171341502Swpaul u_long command; 1714148887Srwatson caddr_t data; 171541502Swpaul{ 171641502Swpaul struct wb_softc *sc = ifp->if_softc; 1717151774Sjhb struct mii_data *mii; 171841502Swpaul struct ifreq *ifr = (struct ifreq *) data; 171941502Swpaul int error = 0; 172041502Swpaul 172141502Swpaul switch(command) { 1722151774Sjhb case SIOCSIFFLAGS: 172341502Swpaul WB_LOCK(sc); 1724151774Sjhb if (ifp->if_flags & IFF_UP) { 172541502Swpaul wb_init_locked(sc); 172641502Swpaul } else { 172741502Swpaul if (ifp->if_drv_flags & IFF_DRV_RUNNING) 172841502Swpaul wb_stop(sc); 172950675Swpaul } 173050675Swpaul WB_UNLOCK(sc); 173141502Swpaul error = 0; 173241502Swpaul break; 1733106936Ssam case SIOCADDMULTI: 173441502Swpaul case SIOCDELMULTI: 173541502Swpaul WB_LOCK(sc); 173641502Swpaul wb_setmulti(sc); 173741502Swpaul WB_UNLOCK(sc); 173841502Swpaul error = 0; 173941502Swpaul break; 1740102336Salfred case SIOCGIFMEDIA: 1741199560Sjhb case SIOCSIFMEDIA: 1742199560Sjhb mii = device_get_softc(sc->wb_miibus); 1743199560Sjhb error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 174441502Swpaul break; 174541502Swpaul default: 1746199560Sjhb error = ether_ioctl(ifp, command, data); 1747199560Sjhb break; 174841502Swpaul } 1749149677Sjhb 175050675Swpaul return(error); 175141502Swpaul} 1752149677Sjhb 175350675Swpaulstatic void 175441502Swpaulwb_watchdog(ifp) 175541502Swpaul struct ifnet *ifp; 1756151774Sjhb{ 175741502Swpaul struct wb_softc *sc; 175841502Swpaul 1759151774Sjhb sc = ifp->if_softc; 176041502Swpaul 176141502Swpaul WB_LOCK(sc); 176241502Swpaul ifp->if_oerrors++; 176341502Swpaul if_printf(ifp, "watchdog timeout\n"); 176441502Swpaul#ifdef foo 176541502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 176641502Swpaul if_printf(ifp, "no carrier - transceiver cable problem?\n"); 176741502Swpaul#endif 1768102336Salfred wb_stop(sc); 1769102336Salfred wb_reset(sc); 177041502Swpaul wb_init_locked(sc); 177141502Swpaul 177241502Swpaul if (ifp->if_snd.ifq_head != NULL) 177341502Swpaul wb_start_locked(ifp); 177441502Swpaul WB_UNLOCK(sc); 1775151774Sjhb 1776147256Sbrooks return; 1777199560Sjhb} 177841502Swpaul 1779151774Sjhb/* 178050675Swpaul * Stop the adapter and free any mbufs allocated to the 178141502Swpaul * RX and TX lists. 178241502Swpaul */ 178341502Swpaulstatic void 178441502Swpaulwb_stop(sc) 178541502Swpaul struct wb_softc *sc; 178641502Swpaul{ 178741502Swpaul register int i; 178841502Swpaul struct ifnet *ifp; 178941502Swpaul 179041502Swpaul WB_LOCK_ASSERT(sc); 179141502Swpaul ifp = sc->wb_ifp; 179241502Swpaul ifp->if_timer = 0; 179341502Swpaul 179441502Swpaul callout_stop(&sc->wb_stat_callout); 179541502Swpaul 179641502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 179741502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 179841502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 179941502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 180041502Swpaul 180141502Swpaul /* 180241502Swpaul * Free data in the RX lists. 180341502Swpaul */ 180441502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 180541502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 180641502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 180741502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 180841502Swpaul } 180941502Swpaul } 181041502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 1811148887Srwatson sizeof(sc->wb_ldata->wb_rx_list)); 181241502Swpaul 181341502Swpaul /* 181441502Swpaul * Free the TX list buffers. 181541502Swpaul */ 181641502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 181741502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 181841502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 181941502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1820194023Savg } 1821102336Salfred } 182249611Swpaul 182341502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 182449611Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 182541502Swpaul 182649611Swpaul ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1827151774Sjhb 1828151774Sjhb return; 182941502Swpaul} 1830151774Sjhb 183141502Swpaul/* 1832194023Savg * Stop all chip I/O so that the kernel's probe routines don't 183341502Swpaul * get confused by errant DMAs when rebooting. 1834 */ 1835static void 1836wb_shutdown(dev) 1837 device_t dev; 1838{ 1839 struct wb_softc *sc; 1840 1841 sc = device_get_softc(dev); 1842 1843 WB_LOCK(sc); 1844 wb_stop(sc); 1845 WB_UNLOCK(sc); 1846 1847 return; 1848} 1849