if_wb.c revision 130270
1139825Simp/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 130270 2004-06-09 14:34:04Z naddy $"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * Winbond fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 4041502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 4141502Swpaul * Winbond itself and some made by Linksys. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 4741502Swpaul/* 4841502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4941502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 5041502Swpaul * one major difference which is that while the registers do many of 5141502Swpaul * the same things as a tulip adapter, the offsets are different: where 5241502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5341502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5441502Swpaul * programmed differently. 5541502Swpaul * 5641502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5741502Swpaul * a status word, a control word and 32-bit areas that can either be used 5841502Swpaul * to point to two external data blocks, or to point to a single block 5941502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 6041502Swpaul * together in blocks to form fixed length rings or can be chained 6141502Swpaul * together in linked lists. A single packet may be spread out over 6241502Swpaul * several descriptors if necessary. 6341502Swpaul * 6441502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6541502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6641502Swpaul * to hold an entire packet. The link list is looped back to created a 6741502Swpaul * closed ring. 6841502Swpaul * 6941502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 7041502Swpaul * which each contain several individual descriptors linked toghether. 7141502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7241502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7341502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7441502Swpaul * drivers. 7541502Swpaul * 7641502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7741502Swpaul * The sample boards I have all use a Davicom PHY. 7841502Swpaul * 7941502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 8041502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 8141502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8241502Swpaul * I have no idea what he's on about: transmit performance with all 8341502Swpaul * three of my test boards seems fine. 8441502Swpaul */ 8541502Swpaul 8641502Swpaul#include "opt_bdg.h" 8741502Swpaul 8841502Swpaul#include <sys/param.h> 8941502Swpaul#include <sys/systm.h> 9041502Swpaul#include <sys/sockio.h> 91129878Sphk#include <sys/mbuf.h> 9241502Swpaul#include <sys/malloc.h> 9341502Swpaul#include <sys/module.h> 9450675Swpaul#include <sys/kernel.h> 9541502Swpaul#include <sys/socket.h> 9641502Swpaul#include <sys/queue.h> 9741502Swpaul 9841502Swpaul#include <net/if.h> 9941502Swpaul#include <net/if_arp.h> 10041502Swpaul#include <net/ethernet.h> 101147256Sbrooks#include <net/if_dl.h> 10241502Swpaul#include <net/if_media.h> 10341502Swpaul 10441502Swpaul#include <net/bpf.h> 10541502Swpaul 10641502Swpaul#include <vm/vm.h> /* for vtophys */ 10741502Swpaul#include <vm/pmap.h> /* for vtophys */ 10849611Swpaul#include <machine/bus_memio.h> 10949611Swpaul#include <machine/bus_pio.h> 11049611Swpaul#include <machine/bus.h> 11141502Swpaul#include <machine/resource.h> 112119288Simp#include <sys/bus.h> 113119288Simp#include <sys/rman.h> 11441502Swpaul 11550675Swpaul#include <dev/pci/pcireg.h> 11650675Swpaul#include <dev/pci/pcivar.h> 11750675Swpaul 118151545Simp#include <dev/mii/mii.h> 11950675Swpaul#include <dev/mii/miivar.h> 12050675Swpaul 12141502Swpaul/* "controller miibus0" required. See GENERIC if you get errors here. */ 12241502Swpaul#include "miibus_if.h" 12341502Swpaul 12441502Swpaul#define WB_USEIOSPACE 125113506Smdodd 126113506Smdodd#include <pci/if_wbreg.h> 12759758Speter 12859758SpeterMODULE_DEPEND(wb, pci, 1, 1, 1); 12941502SwpaulMODULE_DEPEND(wb, ether, 1, 1, 1); 13041502SwpaulMODULE_DEPEND(wb, miibus, 1, 1, 1); 13141502Swpaul 13241502Swpaul/* 13341502Swpaul * Various supported device vendors/types and their names. 13441502Swpaul */ 13541502Swpaulstatic struct wb_type wb_devs[] = { 13641502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13741502Swpaul "Winbond W89C840F 10/100BaseTX" }, 13841502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 13941502Swpaul "Compex RL100-ATX 10/100baseTX" }, 140142407Simp { 0, 0, NULL } 141142407Simp}; 142142407Simp 14341502Swpaulstatic int wb_probe (device_t); 144142407Simpstatic int wb_attach (device_t); 145142407Simpstatic int wb_detach (device_t); 146142407Simp 147142407Simpstatic void wb_bfree (void *addr, void *args); 14841502Swpaulstatic int wb_newbuf (struct wb_softc *, 149142407Simp struct wb_chain_onefrag *, 150142407Simp struct mbuf *); 151142407Simpstatic int wb_encap (struct wb_softc *, struct wb_chain *, 152142407Simp struct mbuf *); 153142407Simp 154142407Simpstatic void wb_rxeof (struct wb_softc *); 155142407Simpstatic void wb_rxeoc (struct wb_softc *); 156151774Sjhbstatic void wb_txeof (struct wb_softc *); 157142407Simpstatic void wb_txeoc (struct wb_softc *); 158142407Simpstatic void wb_intr (void *); 159151774Sjhbstatic void wb_tick (void *); 160142407Simpstatic void wb_start (struct ifnet *); 161142407Simpstatic int wb_ioctl (struct ifnet *, u_long, caddr_t); 162142407Simpstatic void wb_init (void *); 163142407Simpstatic void wb_stop (struct wb_softc *); 164142407Simpstatic void wb_watchdog (struct ifnet *); 16541502Swpaulstatic void wb_shutdown (device_t); 166142407Simpstatic int wb_ifmedia_upd (struct ifnet *); 167142407Simpstatic void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 168142407Simp 169142407Simpstatic void wb_eeprom_putbyte (struct wb_softc *, int); 170142407Simpstatic void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 171142407Simpstatic void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 172142407Simpstatic void wb_mii_sync (struct wb_softc *); 17341502Swpaulstatic void wb_mii_send (struct wb_softc *, u_int32_t, int); 174142407Simpstatic int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 175142407Simpstatic int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 176142407Simp 177142407Simpstatic void wb_setcfg (struct wb_softc *, u_int32_t); 178142407Simpstatic void wb_setmulti (struct wb_softc *); 179142407Simpstatic void wb_reset (struct wb_softc *); 18041502Swpaulstatic void wb_fixmedia (struct wb_softc *); 181142407Simpstatic int wb_list_rx_init (struct wb_softc *); 182142407Simpstatic int wb_list_tx_init (struct wb_softc *); 183142407Simp 18450675Swpaulstatic int wb_miibus_readreg (device_t, int, int); 18549611Swpaulstatic int wb_miibus_writereg (device_t, int, int, int); 18649611Swpaulstatic void wb_miibus_statchg (device_t); 18749611Swpaul 18849611Swpaul#ifdef WB_USEIOSPACE 18949611Swpaul#define WB_RES SYS_RES_IOPORT 19049611Swpaul#define WB_RID WB_PCI_LOIO 19149611Swpaul#else 19249611Swpaul#define WB_RES SYS_RES_MEMORY 19349611Swpaul#define WB_RID WB_PCI_LOMEM 19449611Swpaul#endif 19549611Swpaul 19649611Swpaulstatic device_method_t wb_methods[] = { 19749611Swpaul /* Device interface */ 19849611Swpaul DEVMETHOD(device_probe, wb_probe), 19950675Swpaul DEVMETHOD(device_attach, wb_attach), 20050675Swpaul DEVMETHOD(device_detach, wb_detach), 20150675Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 20250675Swpaul 20350675Swpaul /* bus interface, for miibus */ 20450675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20550675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 20650675Swpaul 20750675Swpaul /* MII interface */ 20849611Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 20949611Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 21049611Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 21149611Swpaul { 0, 0 } 21251455Swpaul}; 21349611Swpaul 21449611Swpaulstatic driver_t wb_driver = { 21549611Swpaul "wb", 21649611Swpaul wb_methods, 21749611Swpaul sizeof(struct wb_softc) 21849611Swpaul}; 219113506Smdodd 22051473Swpaulstatic devclass_t wb_devclass; 22149611Swpaul 22241502SwpaulDRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 22341502SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 224105221Sphk 22541502Swpaul#define WB_SETBIT(sc, reg, x) \ 22641502Swpaul CSR_WRITE_4(sc, reg, \ 22741502Swpaul CSR_READ_4(sc, reg) | (x)) 228105221Sphk 22941502Swpaul#define WB_CLRBIT(sc, reg, x) \ 23041502Swpaul CSR_WRITE_4(sc, reg, \ 23141502Swpaul CSR_READ_4(sc, reg) & ~(x)) 232105221Sphk 23341502Swpaul#define SIO_SET(x) \ 23441502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 23541502Swpaul CSR_READ_4(sc, WB_SIO) | (x)) 236105221Sphk 23741502Swpaul#define SIO_CLR(x) \ 23841502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 23941502Swpaul CSR_READ_4(sc, WB_SIO) & ~(x)) 24041502Swpaul 241102336Salfred/* 242102336Salfred * Send a read command and address to the EEPROM, check for ACK. 24341502Swpaul */ 24442718Swpaulstatic void 24541502Swpaulwb_eeprom_putbyte(sc, addr) 24641502Swpaul struct wb_softc *sc; 24741502Swpaul int addr; 24841502Swpaul{ 24941502Swpaul register int d, i; 25041502Swpaul 25141502Swpaul d = addr | WB_EECMD_READ; 25241502Swpaul 25341502Swpaul /* 25441502Swpaul * Feed in each bit and stobe the clock. 25541502Swpaul */ 25641502Swpaul for (i = 0x400; i; i >>= 1) { 25741502Swpaul if (d & i) { 25841502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 25941502Swpaul } else { 26041502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 26141502Swpaul } 26241502Swpaul DELAY(100); 26341502Swpaul SIO_SET(WB_SIO_EE_CLK); 26441502Swpaul DELAY(150); 26541502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26641502Swpaul DELAY(100); 26741502Swpaul } 26841502Swpaul 26941502Swpaul return; 27041502Swpaul} 27141502Swpaul 272102336Salfred/* 273102336Salfred * Read a word of data stored in the EEPROM at address 'addr.' 27441502Swpaul */ 27542718Swpaulstatic void 27641502Swpaulwb_eeprom_getword(sc, addr, dest) 27741502Swpaul struct wb_softc *sc; 27841502Swpaul int addr; 27941502Swpaul u_int16_t *dest; 28041502Swpaul{ 28141502Swpaul register int i; 28241502Swpaul u_int16_t word = 0; 28341502Swpaul 28441502Swpaul /* Enter EEPROM access mode. */ 28541502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28641502Swpaul 28741502Swpaul /* 28841502Swpaul * Send address of word we want to read. 28941502Swpaul */ 29041502Swpaul wb_eeprom_putbyte(sc, addr); 29141502Swpaul 29241502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29341502Swpaul 29441502Swpaul /* 29541502Swpaul * Start reading bits from EEPROM. 29641502Swpaul */ 29741502Swpaul for (i = 0x8000; i; i >>= 1) { 29841502Swpaul SIO_SET(WB_SIO_EE_CLK); 29941502Swpaul DELAY(100); 30041502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 30141502Swpaul word |= i; 30241502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30341502Swpaul DELAY(100); 30441502Swpaul } 30541502Swpaul 30641502Swpaul /* Turn off EEPROM access mode. */ 30741502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 30841502Swpaul 30941502Swpaul *dest = word; 31041502Swpaul 31141502Swpaul return; 31241502Swpaul} 31341502Swpaul 314102336Salfred/* 315102336Salfred * Read a sequence of words from the EEPROM. 31641502Swpaul */ 31741502Swpaulstatic void 31841502Swpaulwb_read_eeprom(sc, dest, off, cnt, swap) 31941502Swpaul struct wb_softc *sc; 32041502Swpaul caddr_t dest; 32141502Swpaul int off; 32241502Swpaul int cnt; 32341502Swpaul int swap; 32441502Swpaul{ 32541502Swpaul int i; 32641502Swpaul u_int16_t word = 0, *ptr; 32741502Swpaul 32841502Swpaul for (i = 0; i < cnt; i++) { 32941502Swpaul wb_eeprom_getword(sc, off + i, &word); 33041502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 33141502Swpaul if (swap) 33241502Swpaul *ptr = ntohs(word); 33341502Swpaul else 33441502Swpaul *ptr = word; 33541502Swpaul } 33641502Swpaul 33741502Swpaul return; 33841502Swpaul} 33941502Swpaul 340102336Salfred/* 341102336Salfred * Sync the PHYs by setting data bit and strobing the clock 32 times. 34241502Swpaul */ 34341502Swpaulstatic void 34441502Swpaulwb_mii_sync(sc) 34541502Swpaul struct wb_softc *sc; 34641502Swpaul{ 34741502Swpaul register int i; 34841502Swpaul 34941502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 35041502Swpaul 35141502Swpaul for (i = 0; i < 32; i++) { 35241502Swpaul SIO_SET(WB_SIO_MII_CLK); 35341502Swpaul DELAY(1); 35441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35541502Swpaul DELAY(1); 35641502Swpaul } 35741502Swpaul 35841502Swpaul return; 35941502Swpaul} 36041502Swpaul 361102336Salfred/* 362102336Salfred * Clock a series of bits through the MII. 36341502Swpaul */ 36441502Swpaulstatic void 36541502Swpaulwb_mii_send(sc, bits, cnt) 36641502Swpaul struct wb_softc *sc; 36741502Swpaul u_int32_t bits; 36841502Swpaul int cnt; 36941502Swpaul{ 37041502Swpaul int i; 37141502Swpaul 37241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37341502Swpaul 37441502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37541502Swpaul if (bits & i) { 37641502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37741502Swpaul } else { 37841502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 37941502Swpaul } 38041502Swpaul DELAY(1); 38141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 38241502Swpaul DELAY(1); 38341502Swpaul SIO_SET(WB_SIO_MII_CLK); 38441502Swpaul } 38541502Swpaul} 38641502Swpaul 387102336Salfred/* 388102336Salfred * Read an PHY register through the MII. 38941502Swpaul */ 39041502Swpaulstatic int 39141502Swpaulwb_mii_readreg(sc, frame) 39241502Swpaul struct wb_softc *sc; 39367087Swpaul struct wb_mii_frame *frame; 39441502Swpaul 39541502Swpaul{ 39641502Swpaul int i, ack; 39741502Swpaul 39841502Swpaul WB_LOCK(sc); 39941502Swpaul 40041502Swpaul /* 40141502Swpaul * Set up frame for RX. 40241502Swpaul */ 40341502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 40441502Swpaul frame->mii_opcode = WB_MII_READOP; 40541502Swpaul frame->mii_turnaround = 0; 40641502Swpaul frame->mii_data = 0; 40741502Swpaul 40841502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 40941502Swpaul 41041502Swpaul /* 41141502Swpaul * Turn on data xmit. 41241502Swpaul */ 41341502Swpaul SIO_SET(WB_SIO_MII_DIR); 41441502Swpaul 41541502Swpaul wb_mii_sync(sc); 41641502Swpaul 41741502Swpaul /* 41841502Swpaul * Send command/address info. 41941502Swpaul */ 42041502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 42141502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 42241502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 42341502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 42441502Swpaul 42541502Swpaul /* Idle bit */ 42641502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42741502Swpaul DELAY(1); 42841502Swpaul SIO_SET(WB_SIO_MII_CLK); 42941502Swpaul DELAY(1); 43041502Swpaul 431109058Smbr /* Turn off xmit. */ 43241502Swpaul SIO_CLR(WB_SIO_MII_DIR); 43341502Swpaul /* Check for ack */ 43441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43541502Swpaul DELAY(1); 43641502Swpaul ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43741502Swpaul SIO_SET(WB_SIO_MII_CLK); 43841502Swpaul DELAY(1); 43941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 44041502Swpaul DELAY(1); 44141502Swpaul SIO_SET(WB_SIO_MII_CLK); 44241502Swpaul DELAY(1); 44341502Swpaul 44441502Swpaul /* 44541502Swpaul * Now try reading data bits. If the ack failed, we still 44641502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44741502Swpaul */ 44841502Swpaul if (ack) { 44941502Swpaul for(i = 0; i < 16; i++) { 45041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45141502Swpaul DELAY(1); 45241502Swpaul SIO_SET(WB_SIO_MII_CLK); 45341502Swpaul DELAY(1); 45441502Swpaul } 45541502Swpaul goto fail; 45641502Swpaul } 45741502Swpaul 45841502Swpaul for (i = 0x8000; i; i >>= 1) { 45941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 46041502Swpaul DELAY(1); 46141502Swpaul if (!ack) { 46241502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 46341502Swpaul frame->mii_data |= i; 46441502Swpaul DELAY(1); 46541502Swpaul } 46641502Swpaul SIO_SET(WB_SIO_MII_CLK); 46741502Swpaul DELAY(1); 46841502Swpaul } 46941502Swpaul 47041502Swpaulfail: 47141502Swpaul 47241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 47341502Swpaul DELAY(1); 47441502Swpaul SIO_SET(WB_SIO_MII_CLK); 47541502Swpaul DELAY(1); 47641502Swpaul 47741502Swpaul WB_UNLOCK(sc); 47841502Swpaul 47941502Swpaul if (ack) 480102336Salfred return(1); 481102336Salfred return(0); 48241502Swpaul} 48341502Swpaul 48441502Swpaul/* 48541502Swpaul * Write to a PHY register through the MII. 48641502Swpaul */ 48741502Swpaulstatic int 48841502Swpaulwb_mii_writereg(sc, frame) 48941502Swpaul struct wb_softc *sc; 49041502Swpaul struct wb_mii_frame *frame; 49141502Swpaul 49241502Swpaul{ 49341502Swpaul WB_LOCK(sc); 49441502Swpaul 49541502Swpaul /* 49641502Swpaul * Set up frame for TX. 49741502Swpaul */ 49841502Swpaul 49941502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 50041502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 50141502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 50241502Swpaul 50341502Swpaul /* 50441502Swpaul * Turn on data output. 50541502Swpaul */ 50641502Swpaul SIO_SET(WB_SIO_MII_DIR); 50741502Swpaul 50841502Swpaul wb_mii_sync(sc); 50941502Swpaul 51041502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 51141502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 51241502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 51341502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 51441502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 51541502Swpaul wb_mii_send(sc, frame->mii_data, 16); 51641502Swpaul 51741502Swpaul /* Idle bit. */ 51841502Swpaul SIO_SET(WB_SIO_MII_CLK); 51941502Swpaul DELAY(1); 52041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 52141502Swpaul DELAY(1); 52241502Swpaul 523102336Salfred /* 524102336Salfred * Turn off xmit. 52550675Swpaul */ 52650675Swpaul SIO_CLR(WB_SIO_MII_DIR); 52750675Swpaul 52841502Swpaul WB_UNLOCK(sc); 52941502Swpaul 53041502Swpaul return(0); 53150675Swpaul} 53250675Swpaul 53341502Swpaulstatic int 53441502Swpaulwb_miibus_readreg(dev, phy, reg) 53550675Swpaul device_t dev; 53641502Swpaul int phy, reg; 53741502Swpaul{ 53841502Swpaul struct wb_softc *sc; 53941502Swpaul struct wb_mii_frame frame; 54041502Swpaul 54141502Swpaul sc = device_get_softc(dev); 542102336Salfred 543102336Salfred bzero((char *)&frame, sizeof(frame)); 54450675Swpaul 54550675Swpaul frame.mii_phyaddr = phy; 54650675Swpaul frame.mii_regaddr = reg; 54741502Swpaul wb_mii_readreg(sc, &frame); 54841502Swpaul 54941502Swpaul return(frame.mii_data); 55050675Swpaul} 55150675Swpaul 55241502Swpaulstatic int 55341502Swpaulwb_miibus_writereg(dev, phy, reg, data) 55450675Swpaul device_t dev; 55541502Swpaul int phy, reg, data; 55641502Swpaul{ 55741502Swpaul struct wb_softc *sc; 55841502Swpaul struct wb_mii_frame frame; 55941502Swpaul 56050675Swpaul sc = device_get_softc(dev); 56150675Swpaul 56250675Swpaul bzero((char *)&frame, sizeof(frame)); 563102336Salfred 564102336Salfred frame.mii_phyaddr = phy; 56550675Swpaul frame.mii_regaddr = reg; 56650675Swpaul frame.mii_data = data; 56750675Swpaul 56850675Swpaul wb_mii_writereg(sc, &frame); 56950675Swpaul 57050675Swpaul return(0); 57150675Swpaul} 57250675Swpaul 57350675Swpaulstatic void 57441502Swpaulwb_miibus_statchg(dev) 57541502Swpaul device_t dev; 57641502Swpaul{ 57741502Swpaul struct wb_softc *sc; 57841502Swpaul struct mii_data *mii; 57941502Swpaul 580102336Salfred sc = device_get_softc(dev); 581102336Salfred WB_LOCK(sc); 58241502Swpaul mii = device_get_softc(sc->wb_miibus); 58341502Swpaul wb_setcfg(sc, mii->mii_media_active); 58441502Swpaul WB_UNLOCK(sc); 58541502Swpaul 58641502Swpaul return; 58741502Swpaul} 58841502Swpaul 58941502Swpaul/* 59041502Swpaul * Program the 64-bit multicast hash filter. 591147256Sbrooks */ 59241502Swpaulstatic void 59341502Swpaulwb_setmulti(sc) 59441502Swpaul struct wb_softc *sc; 59541502Swpaul{ 59641502Swpaul struct ifnet *ifp; 59741502Swpaul int h = 0; 59841502Swpaul u_int32_t hashes[2] = { 0, 0 }; 59941502Swpaul struct ifmultiaddr *ifma; 60041502Swpaul u_int32_t rxfilt; 60141502Swpaul int mcnt = 0; 60241502Swpaul 60341502Swpaul ifp = &sc->arpcom.ac_if; 60441502Swpaul 60541502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 60641502Swpaul 60741502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 608148654Srwatson rxfilt |= WB_NETCFG_RX_MULTI; 60972084Sphk CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 61041502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 61141502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 612130270Snaddy return; 613130270Snaddy } 61441502Swpaul 61541502Swpaul /* first, zot all the existing hash bits */ 61641502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 61741502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 61841502Swpaul 61941502Swpaul /* now program new ones */ 620148654Srwatson TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 62141502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 62241502Swpaul continue; 62341502Swpaul h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 62441502Swpaul ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 62541502Swpaul if (h < 32) 62641502Swpaul hashes[0] |= (1 << h); 62741502Swpaul else 62841502Swpaul hashes[1] |= (1 << (h - 32)); 62941502Swpaul mcnt++; 63041502Swpaul } 63141502Swpaul 63241502Swpaul if (mcnt) 63341502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 63441502Swpaul else 63541502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 63641502Swpaul 63741502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 63841502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 639102336Salfred CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 640102336Salfred 64141502Swpaul return; 64250675Swpaul} 64341502Swpaul 64441502Swpaul/* 64541502Swpaul * The Winbond manual states that in order to fiddle with the 64641502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 64741502Swpaul * first have to put the transmit and/or receive logic in the idle state. 64841502Swpaul */ 64941502Swpaulstatic void 65041502Swpaulwb_setcfg(sc, media) 65141502Swpaul struct wb_softc *sc; 65241502Swpaul u_int32_t media; 65341502Swpaul{ 65441502Swpaul int i, restart = 0; 65541502Swpaul 65641502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 65741502Swpaul restart = 1; 658149677Sjhb WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 659149677Sjhb 66041502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 66141502Swpaul DELAY(10); 66250675Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 66350675Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 66450675Swpaul break; 66541502Swpaul } 66641502Swpaul 66750675Swpaul if (i == WB_TIMEOUT) 66841502Swpaul printf("wb%d: failed to force tx and " 66941502Swpaul "rx to idle state\n", sc->wb_unit); 67041502Swpaul } 67141502Swpaul 67241502Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 67341502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 67441502Swpaul else 67541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 67641502Swpaul 67741502Swpaul if ((media & IFM_GMASK) == IFM_FDX) 678102336Salfred WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 679102336Salfred else 68041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 68141502Swpaul 68241502Swpaul if (restart) 68350675Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 68441502Swpaul 68550675Swpaul return; 68650675Swpaul} 68750675Swpaul 68850675Swpaulstatic void 68950675Swpaulwb_reset(sc) 69041502Swpaul struct wb_softc *sc; 69150675Swpaul{ 69241502Swpaul register int i; 69341502Swpaul struct mii_data *mii; 69441502Swpaul 69541502Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 69641502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 69741502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 69841502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 699149677Sjhb 70041502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 70141502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 70241502Swpaul 70341502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 70450675Swpaul DELAY(10); 70550675Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 70641502Swpaul break; 70750675Swpaul } 70850675Swpaul if (i == WB_TIMEOUT) 70950675Swpaul printf("wb%d: reset never completed!\n", sc->wb_unit); 71050675Swpaul 71150675Swpaul /* Wait a little while for the chip to get its brains in order. */ 71250675Swpaul DELAY(1000); 71372012Sphk 71450675Swpaul if (sc->wb_miibus == NULL) 71550675Swpaul return; 71650675Swpaul 71741502Swpaul mii = device_get_softc(sc->wb_miibus); 71841502Swpaul if (mii == NULL) 71941502Swpaul return; 720102336Salfred 721102336Salfred if (mii->mii_instance) { 72250675Swpaul struct mii_softc *miisc; 72350675Swpaul LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 72450675Swpaul mii_phy_reset(miisc); 72550675Swpaul } 72650675Swpaul 72750675Swpaul return; 72850675Swpaul} 72950675Swpaul 73050675Swpaulstatic void 73150675Swpaulwb_fixmedia(sc) 732147256Sbrooks struct wb_softc *sc; 73350675Swpaul{ 73450675Swpaul struct mii_data *mii = NULL; 73550675Swpaul struct ifnet *ifp; 73650675Swpaul u_int32_t media; 73750675Swpaul 73850675Swpaul if (sc->wb_miibus == NULL) 73950675Swpaul return; 74050675Swpaul 74150675Swpaul mii = device_get_softc(sc->wb_miibus); 74250675Swpaul ifp = &sc->arpcom.ac_if; 74350675Swpaul 74450675Swpaul mii_pollstat(mii); 74550675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 74650675Swpaul media = mii->mii_media_active & ~IFM_10_T; 74750675Swpaul media |= IFM_100_TX; 74850675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 74941502Swpaul media = mii->mii_media_active & ~IFM_100_TX; 75041502Swpaul media |= IFM_10_T; 75141502Swpaul } else 75241502Swpaul return; 753102336Salfred 754102336Salfred ifmedia_set(&mii->mii_media, media); 75549611Swpaul 75641502Swpaul return; 75741502Swpaul} 75841502Swpaul 75941502Swpaul/* 76041502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 76141502Swpaul * IDs against our list and return a device name if we find a match. 76249611Swpaul */ 76349611Swpaulstatic int 76449611Swpaulwb_probe(dev) 765142398Simp device_t dev; 76641502Swpaul{ 76741502Swpaul struct wb_type *t; 76841502Swpaul 76941502Swpaul t = wb_devs; 77049611Swpaul 77141502Swpaul while(t->wb_name != NULL) { 77241502Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 77341502Swpaul (pci_get_device(dev) == t->wb_did)) { 77441502Swpaul device_set_desc(dev, t->wb_name); 77541502Swpaul return(0); 77641502Swpaul } 777102336Salfred t++; 778102336Salfred } 77949611Swpaul 78041502Swpaul return(ENXIO); 78141502Swpaul} 78241502Swpaul 78341502Swpaul/* 784149677Sjhb * Attach the interface. Allocate softc structures, do ifmedia 78541502Swpaul * setup and ethernet/BPF attach. 78649611Swpaul */ 78741502Swpaulstatic int 78893818Sjhbwb_attach(dev) 789151774Sjhb device_t dev; 790151774Sjhb{ 791151774Sjhb u_char eaddr[ETHER_ADDR_LEN]; 79241502Swpaul struct wb_softc *sc; 79341502Swpaul struct ifnet *ifp; 79441502Swpaul int unit, error = 0, rid; 79572813Swpaul 79641502Swpaul sc = device_get_softc(dev); 79749611Swpaul unit = device_get_unit(dev); 798127135Snjl 79949611Swpaul mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 80049611Swpaul MTX_DEF | MTX_RECURSE); 801149677Sjhb#ifndef BURN_BRIDGES 80249611Swpaul /* 80341502Swpaul * Handle power management nonsense. 80441502Swpaul */ 80541502Swpaul 80649611Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 80749611Swpaul u_int32_t iobase, membase, irq; 80849611Swpaul 80941502Swpaul /* Save important PCI config data. */ 81049611Swpaul iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 811127135Snjl membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 81249611Swpaul irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 81349611Swpaul 81449611Swpaul /* Reset the power state. */ 815149677Sjhb printf("wb%d: chip is in D%d power mode " 81649611Swpaul "-- setting to D0\n", unit, 81741502Swpaul pci_get_powerstate(dev)); 81841502Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 81941502Swpaul 82050675Swpaul /* Restore PCI config data. */ 82150675Swpaul pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 82250675Swpaul pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 82341502Swpaul pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 82441502Swpaul } 82541502Swpaul#endif 82641502Swpaul /* 82741502Swpaul * Map control/status registers. 82841502Swpaul */ 82941502Swpaul pci_enable_busmaster(dev); 83041502Swpaul 83150675Swpaul rid = WB_RID; 83251657Swpaul sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 83350675Swpaul 83450675Swpaul if (sc->wb_res == NULL) { 835149677Sjhb printf("wb%d: couldn't map ports/memory\n", unit); 83649611Swpaul error = ENXIO; 83749611Swpaul goto fail; 83841502Swpaul } 83941502Swpaul 84041502Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 84141502Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 842147256Sbrooks 843147256Sbrooks /* Allocate interrupt */ 844149677Sjhb rid = 0; 845147256Sbrooks sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 846147256Sbrooks RF_SHAREABLE | RF_ACTIVE); 847147256Sbrooks 84841502Swpaul if (sc->wb_irq == NULL) { 849121816Sbrooks printf("wb%d: couldn't map interrupt\n", unit); 85041502Swpaul error = ENXIO; 851151774Sjhb goto fail; 85241502Swpaul } 85341502Swpaul 85441502Swpaul /* Save the cache line size. */ 85541502Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 85641502Swpaul 85743515Swpaul /* Reset the adapter. */ 85841502Swpaul wb_reset(sc); 85950675Swpaul 86050675Swpaul /* 86150675Swpaul * Get station address from the EEPROM. 86250675Swpaul */ 86350675Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 86449611Swpaul 86541502Swpaul sc->wb_unit = unit; 86641502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 86741502Swpaul 86841502Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 86963090Sarchie M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 87041502Swpaul 871106936Ssam if (sc->wb_ldata == NULL) { 87241502Swpaul printf("wb%d: no memory for list buffers!\n", unit); 873113609Snjl error = ENXIO; 874151774Sjhb goto fail; 875112872Snjl } 876112872Snjl 877112872Snjl bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 878149677Sjhb 879113609Snjl ifp = &sc->arpcom.ac_if; 880112872Snjl ifp->if_softc = sc; 881112872Snjl if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 882112872Snjl ifp->if_mtu = ETHERMTU; 88341502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 88450675Swpaul ifp->if_ioctl = wb_ioctl; 885112872Snjl ifp->if_start = wb_start; 88650675Swpaul ifp->if_watchdog = wb_watchdog; 88749611Swpaul ifp->if_init = wb_init; 88841502Swpaul ifp->if_baudrate = 10000000; 88941502Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 890113609Snjl 891113609Snjl /* 892113609Snjl * Do MII setup. 893113609Snjl */ 894113609Snjl if (mii_phy_probe(dev, &sc->wb_miibus, 895113609Snjl wb_ifmedia_upd, wb_ifmedia_sts)) { 896113609Snjl error = ENXIO; 897102336Salfred goto fail; 898102336Salfred } 89949611Swpaul 90049611Swpaul /* 90149611Swpaul * Call MI attach routine. 90249611Swpaul */ 90349611Swpaul ether_ifattach(ifp, eaddr); 90449611Swpaul 905112880Sjhb /* Hook interrupt last to avoid having to lock softc */ 906147256Sbrooks error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 90749611Swpaul wb_intr, sc, &sc->wb_intrhand); 908113609Snjl 909113609Snjl if (error) { 910113609Snjl printf("wb%d: couldn't set up irq\n", unit); 911113609Snjl ether_ifdetach(ifp); 912113812Simp goto fail; 913151774Sjhb } 914113609Snjl 915151774Sjhbfail: 916151774Sjhb if (error) 917112872Snjl wb_detach(dev); 918150213Sru 919113609Snjl return(error); 920112872Snjl} 921113609Snjl 92250675Swpaul/* 923112872Snjl * Shutdown hardware and free up resources. This can be called any 924112872Snjl * time after the mutex has been initialized. It is called in both 925112872Snjl * the error case in attach and the normal detach case so it needs 926112872Snjl * to be careful about only freeing resources that have actually been 927112872Snjl * allocated. 928112872Snjl */ 92949611Swpaulstatic int 930151297Sruwb_detach(dev) 931151297Sru device_t dev; 932151297Sru{ 933112872Snjl struct wb_softc *sc; 934112872Snjl struct ifnet *ifp; 935112872Snjl 936112872Snjl sc = device_get_softc(dev); 93749611Swpaul KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 93867087Swpaul WB_LOCK(sc); 93949611Swpaul ifp = &sc->arpcom.ac_if; 94049611Swpaul 94149611Swpaul /* 94249611Swpaul * Delete any miibus and phy devices attached to this interface. 94341502Swpaul * This should only be done if attach succeeded. 94441502Swpaul */ 94541502Swpaul if (device_is_attached(dev)) { 946102336Salfred wb_stop(sc); 947102336Salfred ether_ifdetach(ifp); 94841502Swpaul } 94941502Swpaul if (sc->wb_miibus) 95041502Swpaul device_delete_child(dev, sc->wb_miibus); 95141502Swpaul bus_generic_detach(dev); 95241502Swpaul 95341502Swpaul if (sc->wb_intrhand) 95441502Swpaul bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 95541502Swpaul if (sc->wb_irq) 95641502Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 95741502Swpaul if (sc->wb_res) 95841502Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 95941502Swpaul 96041502Swpaul if (sc->wb_ldata) { 96141502Swpaul contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 96241502Swpaul M_DEVBUF); 96341502Swpaul } 96441502Swpaul 96541502Swpaul WB_UNLOCK(sc); 96641502Swpaul mtx_destroy(&sc->wb_mtx); 96741502Swpaul 96841502Swpaul return(0); 96941502Swpaul} 97041502Swpaul 97141502Swpaul/* 97241502Swpaul * Initialize the transmit descriptors. 97341502Swpaul */ 97441502Swpaulstatic int 97541502Swpaulwb_list_tx_init(sc) 97641502Swpaul struct wb_softc *sc; 97741502Swpaul{ 97841502Swpaul struct wb_chain_data *cd; 97941502Swpaul struct wb_list_data *ld; 980102336Salfred int i; 981102336Salfred 98241502Swpaul cd = &sc->wb_cdata; 98341502Swpaul ld = sc->wb_ldata; 98441502Swpaul 98541502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 98641502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 98741502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 98841502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 98941502Swpaul &cd->wb_tx_chain[0]; 99041502Swpaul } else { 99141502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 99241502Swpaul &cd->wb_tx_chain[i + 1]; 99341502Swpaul } 99450675Swpaul } 99548745Swpaul 99641502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 99741502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 99841502Swpaul 99941502Swpaul return(0); 100041502Swpaul} 100141502Swpaul 100241502Swpaul 100341502Swpaul/* 100441502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 100541502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 100641502Swpaul * points back to the first. 100741502Swpaul */ 100841502Swpaulstatic int 100941502Swpaulwb_list_rx_init(sc) 101041502Swpaul struct wb_softc *sc; 101141502Swpaul{ 101241502Swpaul struct wb_chain_data *cd; 101341502Swpaul struct wb_list_data *ld; 1014102336Salfred int i; 1015102336Salfred 101698995Salfred cd = &sc->wb_cdata; 101764837Sdwmalone ld = sc->wb_ldata; 101850675Swpaul 101950675Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 102050675Swpaul cd->wb_rx_chain[i].wb_ptr = 102150675Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 102241502Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 102341502Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 102441502Swpaul return(ENOBUFS); 1025102336Salfred if (i == (WB_RX_LIST_CNT - 1)) { 1026102336Salfred cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 102741502Swpaul ld->wb_rx_list[i].wb_next = 102841502Swpaul vtophys(&ld->wb_rx_list[0]); 102948745Swpaul } else { 103041502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 103141502Swpaul &cd->wb_rx_chain[i + 1]; 103241502Swpaul ld->wb_rx_list[i].wb_next = 103348745Swpaul vtophys(&ld->wb_rx_list[i + 1]); 1034111119Simp } 103587846Sluigi } 103648745Swpaul 103764837Sdwmalone cd->wb_rx_head = &cd->wb_rx_chain[0]; 103864837Sdwmalone 103968621Sbmilekic return(0); 104068621Sbmilekic} 104148745Swpaul 104248745Swpaulstatic void 104350675Swpaulwb_bfree(buf, args) 104448745Swpaul void *buf; 104541502Swpaul void *args; 104641502Swpaul{ 104748745Swpaul return; 104848745Swpaul} 104941502Swpaul 105041502Swpaul/* 105150675Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 105241502Swpaul */ 105341502Swpaulstatic int 105441502Swpaulwb_newbuf(sc, c, m) 105541502Swpaul struct wb_softc *sc; 105641502Swpaul struct wb_chain_onefrag *c; 105741502Swpaul struct mbuf *m; 105841502Swpaul{ 105941502Swpaul struct mbuf *m_new = NULL; 106041502Swpaul 1061102336Salfred if (m == NULL) { 1062102336Salfred MGETHDR(m_new, M_DONTWAIT, MT_DATA); 106341502Swpaul if (m_new == NULL) 106441502Swpaul return(ENOBUFS); 106550675Swpaul m_new->m_data = c->wb_buf; 106641502Swpaul m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 106741502Swpaul MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 106841502Swpaul EXT_NET_DRV); 106941502Swpaul } else { 107041502Swpaul m_new = m; 1071122689Ssam m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1072122689Ssam m_new->m_data = m_new->m_ext.ext_buf; 1073147256Sbrooks } 107441502Swpaul 107541502Swpaul m_adj(m_new, sizeof(u_int64_t)); 107641502Swpaul 107748745Swpaul c->wb_mbuf = m_new; 107848745Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 107941502Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 108041502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 108150675Swpaul 108248745Swpaul return(0); 108341502Swpaul} 108450675Swpaul 108550675Swpaul/* 108650675Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 108750675Swpaul * the higher level protocols. 108850675Swpaul */ 108941502Swpaulstatic void 109050675Swpaulwb_rxeof(sc) 1091149677Sjhb struct wb_softc *sc; 1092149677Sjhb{ 109350675Swpaul struct mbuf *m = NULL; 109450675Swpaul struct ifnet *ifp; 1095151774Sjhb struct wb_chain_onefrag *cur_rx; 109641502Swpaul int total_len = 0; 109741502Swpaul u_int32_t rxstat; 109841502Swpaul 109942718Swpaul WB_LOCK_ASSERT(sc); 110042718Swpaul 110148745Swpaul ifp = &sc->arpcom.ac_if; 110250675Swpaul 110342718Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 110442718Swpaul WB_RXSTAT_OWN)) { 110541502Swpaul struct mbuf *m0 = NULL; 110641502Swpaul 110741502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 110841502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 110941934Swpaul 111041934Swpaul m = cur_rx->wb_mbuf; 111141934Swpaul 111241934Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 111341934Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 111441934Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 111541934Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 111641934Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 111778508Sbmilekic ifp->if_ierrors++; 111878508Sbmilekic wb_newbuf(sc, cur_rx, m); 111948745Swpaul printf("wb%x: receiver babbling: possible chip " 112048745Swpaul "bug, forcing reset\n", sc->wb_unit); 112148745Swpaul wb_fixmedia(sc); 112250675Swpaul wb_reset(sc); 112341502Swpaul wb_init(sc); 112448745Swpaul return; 112541502Swpaul } 112641502Swpaul 1127122689Ssam if (rxstat & WB_RXSTAT_RXERR) { 1128106936Ssam ifp->if_ierrors++; 1129122689Ssam wb_newbuf(sc, cur_rx, m); 113041502Swpaul break; 113141502Swpaul } 113241502Swpaul 1133105221Sphk /* No errors; receive the packet. */ 1134102336Salfred total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 113541502Swpaul 113641502Swpaul /* 113741502Swpaul * XXX The Winbond chip includes the CRC with every 113841502Swpaul * received frame, and there's no way to turn this 113941502Swpaul * behavior off (at least, I can't find anything in 114041502Swpaul * the manual that explains how to do it) so we have 114141502Swpaul * to trim off the CRC manually. 114241502Swpaul */ 114341502Swpaul total_len -= ETHER_CRC_LEN; 114441502Swpaul 114541502Swpaul m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 114641502Swpaul NULL); 114741502Swpaul wb_newbuf(sc, cur_rx, m); 114841502Swpaul if (m0 == NULL) { 114941502Swpaul ifp->if_ierrors++; 115041502Swpaul break; 115141502Swpaul } 1152102336Salfred m = m0; 1153102336Salfred 115441502Swpaul ifp->if_ipackets++; 115541502Swpaul WB_UNLOCK(sc); 115641502Swpaul (*ifp->if_input)(ifp, m); 115741502Swpaul WB_LOCK(sc); 115841502Swpaul } 1159147256Sbrooks} 116041502Swpaul 116141502Swpaulstatic void 116241502Swpaulwb_rxeoc(sc) 116341502Swpaul struct wb_softc *sc; 116441502Swpaul{ 116541502Swpaul wb_rxeof(sc); 116641502Swpaul 116741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 116841502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 116941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 117041502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 117141502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 117241502Swpaul 117341502Swpaul return; 117441502Swpaul} 117541502Swpaul 117641502Swpaul/* 117741502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 117841502Swpaul * the list buffers. 117941502Swpaul */ 118041502Swpaulstatic void 118141502Swpaulwb_txeof(sc) 118241502Swpaul struct wb_softc *sc; 118341502Swpaul{ 118441502Swpaul struct wb_chain *cur_tx; 118541502Swpaul struct ifnet *ifp; 118641502Swpaul 118741502Swpaul ifp = &sc->arpcom.ac_if; 118841502Swpaul 118941502Swpaul /* Clear the timeout timer. */ 119041502Swpaul ifp->if_timer = 0; 119141502Swpaul 119241502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 119341502Swpaul return; 119441502Swpaul 119541502Swpaul /* 119641502Swpaul * Go through our tx list and free mbufs for those 119741502Swpaul * frames that have been transmitted. 119841502Swpaul */ 119941502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 120041502Swpaul u_int32_t txstat; 120141502Swpaul 120241502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 120341502Swpaul txstat = WB_TXSTATUS(cur_tx); 120441502Swpaul 120541502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 120641502Swpaul break; 120741502Swpaul 120841502Swpaul if (txstat & WB_TXSTAT_TXERR) { 1209102336Salfred ifp->if_oerrors++; 1210102336Salfred if (txstat & WB_TXSTAT_ABORT) 121141502Swpaul ifp->if_collisions++; 121241502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 121341502Swpaul ifp->if_collisions++; 121441502Swpaul } 1215147256Sbrooks 121641502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 121741502Swpaul 121841502Swpaul ifp->if_opackets++; 121941502Swpaul m_freem(cur_tx->wb_mbuf); 1220148887Srwatson cur_tx->wb_mbuf = NULL; 122141502Swpaul 122241502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 122341502Swpaul sc->wb_cdata.wb_tx_head = NULL; 122441502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 122541502Swpaul break; 122641502Swpaul } 122741502Swpaul 122841502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 122941502Swpaul } 123041502Swpaul 123141502Swpaul return; 123241502Swpaul} 1233102336Salfred 1234102336Salfred/* 123541502Swpaul * TX 'end of channel' interrupt handler. 123641502Swpaul */ 123741502Swpaulstatic void 123841502Swpaulwb_txeoc(sc) 123941502Swpaul struct wb_softc *sc; 124041502Swpaul{ 124141502Swpaul struct ifnet *ifp; 124267087Swpaul 1243147256Sbrooks ifp = &sc->arpcom.ac_if; 124441502Swpaul 1245151774Sjhb ifp->if_timer = 0; 124667087Swpaul 124741502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 124867087Swpaul ifp->if_flags &= ~IFF_OACTIVE; 124941502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 125041502Swpaul } else { 125141502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 125241502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 125341502Swpaul ifp->if_timer = 5; 125441502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 125541502Swpaul } 125641502Swpaul } 125741502Swpaul 125841502Swpaul return; 125941502Swpaul} 126041502Swpaul 126141502Swpaulstatic void 126241502Swpaulwb_intr(arg) 126341502Swpaul void *arg; 126441502Swpaul{ 126550675Swpaul struct wb_softc *sc; 126650675Swpaul struct ifnet *ifp; 1267151774Sjhb u_int32_t status; 126850675Swpaul 126941502Swpaul sc = arg; 127041502Swpaul WB_LOCK(sc); 127150675Swpaul ifp = &sc->arpcom.ac_if; 127250675Swpaul 127350675Swpaul if (!(ifp->if_flags & IFF_UP)) { 127450675Swpaul WB_UNLOCK(sc); 127550675Swpaul return; 127650675Swpaul } 127741502Swpaul 127841502Swpaul /* Disable interrupts. */ 127941502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 128041502Swpaul 128141502Swpaul for (;;) { 128241502Swpaul 128341502Swpaul status = CSR_READ_4(sc, WB_ISR); 128441502Swpaul if (status) 128541502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 128641502Swpaul 128741502Swpaul if ((status & WB_INTRS) == 0) 128841502Swpaul break; 128941502Swpaul 129041502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 129141502Swpaul ifp->if_ierrors++; 129241502Swpaul wb_reset(sc); 129341502Swpaul if (status & WB_ISR_RX_ERR) 129441502Swpaul wb_fixmedia(sc); 129541502Swpaul wb_init(sc); 129641502Swpaul continue; 129741502Swpaul } 129841502Swpaul 129941502Swpaul if (status & WB_ISR_RX_OK) 130041502Swpaul wb_rxeof(sc); 130141502Swpaul 130241502Swpaul if (status & WB_ISR_RX_IDLE) 130341502Swpaul wb_rxeoc(sc); 1304151774Sjhb 130541502Swpaul if (status & WB_ISR_TX_OK) 130641502Swpaul wb_txeof(sc); 130741502Swpaul 130841502Swpaul if (status & WB_ISR_TX_NOBUF) 130941502Swpaul wb_txeoc(sc); 131041502Swpaul 131141502Swpaul if (status & WB_ISR_TX_IDLE) { 131241502Swpaul wb_txeof(sc); 1313151774Sjhb if (sc->wb_cdata.wb_tx_head != NULL) { 131441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 131541502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 131667087Swpaul } 131767087Swpaul } 131841502Swpaul 131941502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 132041502Swpaul ifp->if_oerrors++; 1321102336Salfred wb_txeof(sc); 1322102336Salfred WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 132350675Swpaul /* Jack up TX threshold */ 132450675Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 132550675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 132650675Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 132750675Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 132850675Swpaul } 1329151774Sjhb 133050675Swpaul if (status & WB_ISR_BUS_ERR) { 133150675Swpaul wb_reset(sc); 133250675Swpaul wb_init(sc); 133350675Swpaul } 1334151774Sjhb 133550675Swpaul } 133650675Swpaul 133750675Swpaul /* Re-enable interrupts. */ 133850675Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 133941502Swpaul 134041502Swpaul if (ifp->if_snd.ifq_head != NULL) { 134141502Swpaul wb_start(ifp); 134241502Swpaul } 1343102336Salfred 1344102336Salfred WB_UNLOCK(sc); 134541502Swpaul 134641502Swpaul return; 134741502Swpaul} 134841502Swpaul 134941502Swpaulstatic void 135041502Swpaulwb_tick(xsc) 135141502Swpaul void *xsc; 135241502Swpaul{ 135341502Swpaul struct wb_softc *sc; 135441502Swpaul struct mii_data *mii; 135541502Swpaul 135641502Swpaul sc = xsc; 135741502Swpaul WB_LOCK(sc); 135841502Swpaul mii = device_get_softc(sc->wb_miibus); 135941502Swpaul 136041502Swpaul mii_tick(mii); 136141502Swpaul 136241502Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 136341502Swpaul 136441502Swpaul WB_UNLOCK(sc); 136541502Swpaul 136641502Swpaul return; 136741502Swpaul} 136841502Swpaul 136941502Swpaul/* 137041502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 137141502Swpaul * pointers to the fragment pointers. 137241502Swpaul */ 137341502Swpaulstatic int 137441502Swpaulwb_encap(sc, c, m_head) 137541502Swpaul struct wb_softc *sc; 137641502Swpaul struct wb_chain *c; 137741502Swpaul struct mbuf *m_head; 137841502Swpaul{ 137941502Swpaul int frag = 0; 138041502Swpaul struct wb_desc *f = NULL; 138141502Swpaul int total_len; 138241502Swpaul struct mbuf *m; 138341502Swpaul 138441502Swpaul /* 138541502Swpaul * Start packing the mbufs in this chain into 138641502Swpaul * the fragment pointers. Stop when we run out 138741502Swpaul * of fragments or hit the end of the mbuf chain. 138841502Swpaul */ 138941502Swpaul m = m_head; 139041502Swpaul total_len = 0; 1391111119Simp 139287846Sluigi for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 139341502Swpaul if (m->m_len != 0) { 139441502Swpaul if (frag == WB_MAXFRAGS) 1395111119Simp break; 139641502Swpaul total_len += m->m_len; 139741502Swpaul f = &c->wb_ptr->wb_frag[frag]; 139841502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 139941502Swpaul if (frag == 0) { 140041502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 140141502Swpaul f->wb_status = 0; 140241502Swpaul } else 140341502Swpaul f->wb_status = WB_TXSTAT_OWN; 140441502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 140541502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 140641502Swpaul frag++; 140741502Swpaul } 140841502Swpaul } 140941502Swpaul 141041502Swpaul /* 141141502Swpaul * Handle special case: we used up all 16 fragments, 141241502Swpaul * but we have more mbufs left in the chain. Copy the 141341502Swpaul * data into an mbuf cluster. Note that we don't 141441502Swpaul * bother clearing the values in the other fragment 141541502Swpaul * pointers/counters; it wouldn't gain us anything, 141641502Swpaul * and would waste cycles. 141741502Swpaul */ 141841502Swpaul if (m != NULL) { 141941502Swpaul struct mbuf *m_new = NULL; 142041502Swpaul 142141502Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 142241502Swpaul if (m_new == NULL) 142341502Swpaul return(1); 142441502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 142541502Swpaul MCLGET(m_new, M_DONTWAIT); 142641502Swpaul if (!(m_new->m_flags & M_EXT)) { 142741502Swpaul m_freem(m_new); 142841502Swpaul return(1); 142941502Swpaul } 143041502Swpaul } 143141502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 143241502Swpaul mtod(m_new, caddr_t)); 143341502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 143441502Swpaul m_freem(m_head); 143541502Swpaul m_head = m_new; 143641502Swpaul f = &c->wb_ptr->wb_frag[0]; 143741502Swpaul f->wb_status = 0; 1438102336Salfred f->wb_data = vtophys(mtod(m_new, caddr_t)); 1439102336Salfred f->wb_ctl = total_len = m_new->m_len; 144041502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 144141502Swpaul frag = 1; 144241502Swpaul } 1443151774Sjhb 1444151774Sjhb if (total_len < WB_MIN_FRAMELEN) { 1445151774Sjhb f = &c->wb_ptr->wb_frag[frag]; 1446151774Sjhb f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1447151774Sjhb f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1448151774Sjhb f->wb_ctl |= WB_TXCTL_TLINK; 1449151774Sjhb f->wb_status = WB_TXSTAT_OWN; 1450151774Sjhb frag++; 1451151774Sjhb } 1452151774Sjhb 1453151774Sjhb c->wb_mbuf = m_head; 1454151774Sjhb c->wb_lastdesc = frag - 1; 145541502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 145641502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 145741502Swpaul 145841502Swpaul return(0); 1459151774Sjhb} 146041502Swpaul 146141502Swpaul/* 146241502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 146341502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 146441502Swpaul * copy of the pointers since the transmit list fragment pointers are 146541502Swpaul * physical addresses. 1466148887Srwatson */ 146741502Swpaul 146841502Swpaulstatic void 146941502Swpaulwb_start(ifp) 147041502Swpaul struct ifnet *ifp; 147141502Swpaul{ 147241502Swpaul struct wb_softc *sc; 147341502Swpaul struct mbuf *m_head = NULL; 147441502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 147541502Swpaul 147641502Swpaul sc = ifp->if_softc; 147741502Swpaul WB_LOCK(sc); 147841502Swpaul 147941502Swpaul /* 148041502Swpaul * Check for an available queue slot. If there are none, 148141502Swpaul * punt. 148241502Swpaul */ 148341502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 148441502Swpaul ifp->if_flags |= IFF_OACTIVE; 148541502Swpaul WB_UNLOCK(sc); 148641502Swpaul return; 148741502Swpaul } 148841502Swpaul 148941502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 149041502Swpaul 1491106936Ssam while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 149241502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 149341502Swpaul if (m_head == NULL) 149441502Swpaul break; 149541526Swpaul 149641526Swpaul /* Pick a descriptor off the free list. */ 1497151774Sjhb cur_tx = sc->wb_cdata.wb_tx_free; 149841526Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 149941526Swpaul 150041526Swpaul /* Pack the data into the descriptor. */ 150141502Swpaul wb_encap(sc, cur_tx, m_head); 150241502Swpaul 150341502Swpaul if (cur_tx != start_tx) 150441502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 150541502Swpaul 150641502Swpaul /* 150741502Swpaul * If there's a BPF listener, bounce a copy of this frame 150842718Swpaul * to him. 150941502Swpaul */ 151041502Swpaul BPF_MTAP(ifp, cur_tx->wb_mbuf); 151141502Swpaul } 151241502Swpaul 151341502Swpaul /* 151441502Swpaul * If there are no packets queued, bail. 151541502Swpaul */ 151641502Swpaul if (cur_tx == NULL) { 151741502Swpaul WB_UNLOCK(sc); 151841502Swpaul return; 151941502Swpaul } 152041502Swpaul 152141502Swpaul /* 152241502Swpaul * Place the request for the upload interrupt 152341502Swpaul * in the last descriptor in the chain. This way, if 152441502Swpaul * we're chaining several packets at once, we'll only 152541502Swpaul * get an interupt once for the whole chain rather than 152641502Swpaul * once for each packet. 152741502Swpaul */ 152841502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 152941502Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 153041502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 153141502Swpaul 153241502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 153341502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 153441502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 153541502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 153641502Swpaul } else { 153741502Swpaul /* 153841502Swpaul * We need to distinguish between the case where 1539102336Salfred * the own bit is clear because the chip cleared it 1540102336Salfred * and where the own bit is clear because we haven't 154141502Swpaul * set it yet. The magic value WB_UNSET is just some 154241502Swpaul * ramdomly chosen number which doesn't have the own 154341502Swpaul * bit set. When we actually transmit the frame, the 1544151774Sjhb * status word will have _only_ the own bit set, so 1545151774Sjhb * the txeoc handler will be able to tell if it needs 1546151774Sjhb * to initiate another transmission to flush out pending 1547151774Sjhb * frames. 1548151774Sjhb */ 1549151774Sjhb WB_TXOWN(start_tx) = WB_UNSENT; 1550151774Sjhb } 1551151774Sjhb 1552151774Sjhb /* 1553151774Sjhb * Set a timeout in case the chip goes out to lunch. 1554147256Sbrooks */ 155567087Swpaul ifp->if_timer = 5; 155650675Swpaul WB_UNLOCK(sc); 155741502Swpaul 1558151774Sjhb return; 155950675Swpaul} 156041502Swpaul 156141502Swpaulstatic void 156241502Swpaulwb_init(xsc) 156341502Swpaul void *xsc; 156441502Swpaul{ 156541502Swpaul struct wb_softc *sc = xsc; 156641502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 156741502Swpaul int i; 156841502Swpaul struct mii_data *mii; 156941502Swpaul 157041502Swpaul WB_LOCK(sc); 157141502Swpaul mii = device_get_softc(sc->wb_miibus); 157250675Swpaul 157341502Swpaul /* 157441502Swpaul * Cancel pending I/O and free all RX/TX buffers. 157541502Swpaul */ 157650675Swpaul wb_stop(sc); 157741502Swpaul wb_reset(sc); 157850675Swpaul 157950675Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 158050675Swpaul 158150675Swpaul /* 158250675Swpaul * Set cache alignment and burst length. 158350675Swpaul */ 158450675Swpaul#ifdef foo 158550675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 158650675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 158750675Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 158850675Swpaul#endif 158950675Swpaul 159050675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 159150675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 159250675Swpaul switch(sc->wb_cachesize) { 159350675Swpaul case 32: 159450675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 159550675Swpaul break; 159641502Swpaul case 16: 159741502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 159841502Swpaul break; 159941502Swpaul case 8: 160041502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1601152315Sru break; 160241502Swpaul case 0: 160341502Swpaul default: 160441502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 160541502Swpaul break; 1606149677Sjhb } 1607149677Sjhb 160841502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 160941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 161041502Swpaul 161141502Swpaul /* Init our MAC address */ 161241502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 161341502Swpaul CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 161441502Swpaul } 161541502Swpaul 161641502Swpaul /* Init circular RX list. */ 161741502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 161841502Swpaul printf("wb%d: initialization failed: no " 161941502Swpaul "memory for rx buffers\n", sc->wb_unit); 162041502Swpaul wb_stop(sc); 162141502Swpaul WB_UNLOCK(sc); 162241502Swpaul return; 162341502Swpaul } 162441502Swpaul 162541502Swpaul /* Init TX descriptors. */ 162641502Swpaul wb_list_tx_init(sc); 162741502Swpaul 162841502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 162941502Swpaul if (ifp->if_flags & IFF_PROMISC) { 163041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 163141502Swpaul } else { 163241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 163341502Swpaul } 163441502Swpaul 163541502Swpaul /* 163641502Swpaul * Set capture broadcast bit to capture broadcast frames. 163741502Swpaul */ 163841502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 163941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 164041502Swpaul } else { 164141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 164241502Swpaul } 164341502Swpaul 164441502Swpaul /* 164541502Swpaul * Program the multicast filter, if necessary. 164641502Swpaul */ 164741502Swpaul wb_setmulti(sc); 164841502Swpaul 164941502Swpaul /* 165041502Swpaul * Load the address of the RX list. 165141502Swpaul */ 165241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 165341502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 165441502Swpaul 165541502Swpaul /* 165650675Swpaul * Enable interrupts. 165741502Swpaul */ 1658148887Srwatson CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1659148887Srwatson CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 166041502Swpaul 1661151774Sjhb /* Enable receiver and transmitter. */ 166250675Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 166341502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 166441502Swpaul 166541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 166641502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 166741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 166841502Swpaul 1669102336Salfred mii_mediachg(mii); 1670102336Salfred 167141502Swpaul ifp->if_flags |= IFF_RUNNING; 167241502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 167341502Swpaul 167441502Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 167541502Swpaul WB_UNLOCK(sc); 167641502Swpaul 1677151774Sjhb return; 167850675Swpaul} 1679151774Sjhb 1680151774Sjhb/* 168141502Swpaul * Set media options. 168241502Swpaul */ 168341502Swpaulstatic int 168441502Swpaulwb_ifmedia_upd(ifp) 168541502Swpaul struct ifnet *ifp; 168641502Swpaul{ 168741502Swpaul struct wb_softc *sc; 1688102336Salfred 1689102336Salfred sc = ifp->if_softc; 169041502Swpaul 169141502Swpaul if (ifp->if_flags & IFF_UP) 169241502Swpaul wb_init(sc); 169341502Swpaul 169450675Swpaul return(0); 169541502Swpaul} 169641502Swpaul 169741502Swpaul/* 1698151774Sjhb * Report current media status. 169950675Swpaul */ 170041502Swpaulstatic void 170150675Swpaulwb_ifmedia_sts(ifp, ifmr) 170250675Swpaul struct ifnet *ifp; 170350675Swpaul struct ifmediareq *ifmr; 1704151774Sjhb{ 170541502Swpaul struct wb_softc *sc; 170641502Swpaul struct mii_data *mii; 170741502Swpaul 170841502Swpaul sc = ifp->if_softc; 1709102336Salfred 1710102336Salfred mii = device_get_softc(sc->wb_miibus); 171141502Swpaul 171241502Swpaul mii_pollstat(mii); 171341502Swpaul ifmr->ifm_active = mii->mii_media_active; 171441502Swpaul ifmr->ifm_status = mii->mii_media_status; 171541502Swpaul 171650675Swpaul return; 171741502Swpaul} 171867087Swpaul 171941502Swpaulstatic int 172041502Swpaulwb_ioctl(ifp, command, data) 172141502Swpaul struct ifnet *ifp; 1722151774Sjhb u_long command; 172341502Swpaul caddr_t data; 1724151774Sjhb{ 172541502Swpaul struct wb_softc *sc = ifp->if_softc; 1726148887Srwatson struct mii_data *mii; 172741502Swpaul struct ifreq *ifr = (struct ifreq *) data; 172841502Swpaul int error = 0; 1729151774Sjhb 173041502Swpaul WB_LOCK(sc); 173141502Swpaul 173241502Swpaul switch(command) { 173341502Swpaul case SIOCSIFFLAGS: 1734151774Sjhb if (ifp->if_flags & IFF_UP) { 173541502Swpaul wb_init(sc); 1736151774Sjhb } else { 173741502Swpaul if (ifp->if_flags & IFF_RUNNING) 173841502Swpaul wb_stop(sc); 173941502Swpaul } 174041502Swpaul error = 0; 174150675Swpaul break; 174250675Swpaul case SIOCADDMULTI: 174341502Swpaul case SIOCDELMULTI: 174441502Swpaul wb_setmulti(sc); 1745106936Ssam error = 0; 174641502Swpaul break; 174741502Swpaul case SIOCGIFMEDIA: 174841502Swpaul case SIOCSIFMEDIA: 174941502Swpaul mii = device_get_softc(sc->wb_miibus); 175041502Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 175141502Swpaul break; 1752102336Salfred default: 1753102336Salfred error = ether_ioctl(ifp, command, data); 175441502Swpaul break; 175541502Swpaul } 175641502Swpaul 175741502Swpaul WB_UNLOCK(sc); 175841502Swpaul 175941502Swpaul return(error); 176067087Swpaul} 176141502Swpaul 1762149677Sjhbstatic void 176350675Swpaulwb_watchdog(ifp) 176441502Swpaul struct ifnet *ifp; 1765149677Sjhb{ 176650675Swpaul struct wb_softc *sc; 176741502Swpaul 176841502Swpaul sc = ifp->if_softc; 1769151774Sjhb 177041502Swpaul WB_LOCK(sc); 177141502Swpaul ifp->if_oerrors++; 1772151774Sjhb printf("wb%d: watchdog timeout\n", sc->wb_unit); 177367087Swpaul#ifdef foo 177441502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 177541502Swpaul printf("wb%d: no carrier - transceiver cable problem?\n", 177641502Swpaul sc->wb_unit); 177741502Swpaul#endif 177841502Swpaul wb_stop(sc); 177941502Swpaul wb_reset(sc); 178041502Swpaul wb_init(sc); 178141502Swpaul 1782102336Salfred if (ifp->if_snd.ifq_head != NULL) 1783102336Salfred wb_start(ifp); 178441502Swpaul WB_UNLOCK(sc); 178541502Swpaul 178641502Swpaul return; 178741502Swpaul} 178841502Swpaul 1789151774Sjhb/* 1790147256Sbrooks * Stop the adapter and free any mbufs allocated to the 179141502Swpaul * RX and TX lists. 179241502Swpaul */ 1793151774Sjhbstatic void 179450675Swpaulwb_stop(sc) 179541502Swpaul struct wb_softc *sc; 179641502Swpaul{ 179741502Swpaul register int i; 179841502Swpaul struct ifnet *ifp; 179941502Swpaul 180041502Swpaul WB_LOCK(sc); 180141502Swpaul ifp = &sc->arpcom.ac_if; 180241502Swpaul ifp->if_timer = 0; 180341502Swpaul 180441502Swpaul untimeout(wb_tick, sc, sc->wb_stat_ch); 180541502Swpaul 180641502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 180741502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 180841502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 180941502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 181041502Swpaul 181141502Swpaul /* 181241502Swpaul * Free data in the RX lists. 181341502Swpaul */ 181441502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 181541502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 181641502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 181741502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 181841502Swpaul } 181941502Swpaul } 182041502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 182141502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 182241502Swpaul 182341502Swpaul /* 182441502Swpaul * Free the TX list buffers. 1825148887Srwatson */ 182641502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 182741502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 182841502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 182941502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 183041502Swpaul } 183141502Swpaul } 183241502Swpaul 183341502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 1834102336Salfred sizeof(sc->wb_ldata->wb_tx_list)); 1835102336Salfred 183649611Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 183741502Swpaul WB_UNLOCK(sc); 183849611Swpaul 183941502Swpaul return; 184049611Swpaul} 1841151774Sjhb 1842151774Sjhb/* 184341502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 1844151774Sjhb * get confused by errant DMAs when rebooting. 184541502Swpaul */ 184641502Swpaulstatic void 184741502Swpaulwb_shutdown(dev) 1848 device_t dev; 1849{ 1850 struct wb_softc *sc; 1851 1852 sc = device_get_softc(dev); 1853 wb_stop(sc); 1854 1855 return; 1856} 1857